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added 2.6.29.6 aldebaran kernel
[nao-ulib.git] / kernel / 2.6.29.6-aldebaran-rt / drivers / block / cpqarray.c
blob5d39df14ed9032eef70f62f87ec21427f14ad6a1
1 /*
2 * Disk Array driver for Compaq SMART2 Controllers
3 * Copyright 1998 Compaq Computer Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
20 *
21 */
22 #include <linux/module.h>
23 #include <linux/types.h>
24 #include <linux/pci.h>
25 #include <linux/bio.h>
26 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
28 #include <linux/slab.h>
29 #include <linux/delay.h>
30 #include <linux/major.h>
31 #include <linux/fs.h>
32 #include <linux/blkpg.h>
33 #include <linux/timer.h>
34 #include <linux/proc_fs.h>
35 #include <linux/init.h>
36 #include <linux/hdreg.h>
37 #include <linux/spinlock.h>
38 #include <linux/blkdev.h>
39 #include <linux/genhd.h>
40 #include <linux/scatterlist.h>
41 #include <asm/uaccess.h>
42 #include <asm/io.h>
43
44
45 #define SMART2_DRIVER_VERSION(maj,min,submin) ((maj<<16)|(min<<8)|(submin))
46
47 #define DRIVER_NAME "Compaq SMART2 Driver (v 2.6.0)"
48 #define DRIVER_VERSION SMART2_DRIVER_VERSION(2,6,0)
49
50 /* Embedded module documentation macros - see modules.h */
51 /* Original author Chris Frantz - Compaq Computer Corporation */
52 MODULE_AUTHOR("Compaq Computer Corporation");
53 MODULE_DESCRIPTION("Driver for Compaq Smart2 Array Controllers version 2.6.0");
54 MODULE_LICENSE("GPL");
55
56 #include "cpqarray.h"
57 #include "ida_cmd.h"
58 #include "smart1,2.h"
59 #include "ida_ioctl.h"
60
61 #define READ_AHEAD 128
62 #define NR_CMDS 128 /* This could probably go as high as ~400 */
63
64 #define MAX_CTLR 8
65 #define CTLR_SHIFT 8
66
67 #define CPQARRAY_DMA_MASK 0xFFFFFFFF /* 32 bit DMA */
68
69 static int nr_ctlr;
70 static ctlr_info_t *hba[MAX_CTLR];
71
72 static int eisa[8];
73
74 #define NR_PRODUCTS ARRAY_SIZE(products)
75
76 /* board_id = Subsystem Device ID & Vendor ID
77 * product = Marketing Name for the board
78 * access = Address of the struct of function pointers
79 */
80 static struct board_type products[] = {
81 { 0x0040110E, "IDA", &smart1_access },
82 { 0x0140110E, "IDA-2", &smart1_access },
83 { 0x1040110E, "IAES", &smart1_access },
84 { 0x2040110E, "SMART", &smart1_access },
85 { 0x3040110E, "SMART-2/E", &smart2e_access },
86 { 0x40300E11, "SMART-2/P", &smart2_access },
87 { 0x40310E11, "SMART-2SL", &smart2_access },
88 { 0x40320E11, "Smart Array 3200", &smart2_access },
89 { 0x40330E11, "Smart Array 3100ES", &smart2_access },
90 { 0x40340E11, "Smart Array 221", &smart2_access },
91 { 0x40400E11, "Integrated Array", &smart4_access },
92 { 0x40480E11, "Compaq Raid LC2", &smart4_access },
93 { 0x40500E11, "Smart Array 4200", &smart4_access },
94 { 0x40510E11, "Smart Array 4250ES", &smart4_access },
95 { 0x40580E11, "Smart Array 431", &smart4_access },
96 };
97
98 /* define the PCI info for the PCI cards this driver can control */
99 static const struct pci_device_id cpqarray_pci_device_id[] =
100 {
101 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_COMPAQ_42XX,
102 0x0E11, 0x4058, 0, 0, 0}, /* SA431 */
103 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_COMPAQ_42XX,
104 0x0E11, 0x4051, 0, 0, 0}, /* SA4250ES */
105 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_COMPAQ_42XX,
106 0x0E11, 0x4050, 0, 0, 0}, /* SA4200 */
107 { PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C1510,
108 0x0E11, 0x4048, 0, 0, 0}, /* LC2 */
109 { PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C1510,
110 0x0E11, 0x4040, 0, 0, 0}, /* Integrated Array */
111 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
112 0x0E11, 0x4034, 0, 0, 0}, /* SA 221 */
113 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
114 0x0E11, 0x4033, 0, 0, 0}, /* SA 3100ES*/
115 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
116 0x0E11, 0x4032, 0, 0, 0}, /* SA 3200*/
117 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
118 0x0E11, 0x4031, 0, 0, 0}, /* SA 2SL*/
119 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
120 0x0E11, 0x4030, 0, 0, 0}, /* SA 2P */
121 { 0 }
122 };
123
124 MODULE_DEVICE_TABLE(pci, cpqarray_pci_device_id);
125
126 static struct gendisk *ida_gendisk[MAX_CTLR][NWD];
127
128 /* Debug... */
129 #define DBG(s) do { s } while(0)
130 /* Debug (general info)... */
131 #define DBGINFO(s) do { } while(0)
132 /* Debug Paranoid... */
133 #define DBGP(s) do { } while(0)
134 /* Debug Extra Paranoid... */
135 #define DBGPX(s) do { } while(0)
136
137 static int cpqarray_pci_init(ctlr_info_t *c, struct pci_dev *pdev);
138 static void __iomem *remap_pci_mem(ulong base, ulong size);
139 static int cpqarray_eisa_detect(void);
140 static int pollcomplete(int ctlr);
141 static void getgeometry(int ctlr);
142 static void start_fwbk(int ctlr);
143
144 static cmdlist_t * cmd_alloc(ctlr_info_t *h, int get_from_pool);
145 static void cmd_free(ctlr_info_t *h, cmdlist_t *c, int got_from_pool);
146
147 static void free_hba(int i);
148 static int alloc_cpqarray_hba(void);
149
150 static int sendcmd(
151 __u8 cmd,
152 int ctlr,
153 void *buff,
154 size_t size,
155 unsigned int blk,
156 unsigned int blkcnt,
157 unsigned int log_unit );
158
159 static int ida_open(struct block_device *bdev, fmode_t mode);
160 static int ida_release(struct gendisk *disk, fmode_t mode);
161 static int ida_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, unsigned long arg);
162 static int ida_getgeo(struct block_device *bdev, struct hd_geometry *geo);
163 static int ida_ctlr_ioctl(ctlr_info_t *h, int dsk, ida_ioctl_t *io);
164
165 static void do_ida_request(struct request_queue *q);
166 static void start_io(ctlr_info_t *h);
167
168 static inline void addQ(cmdlist_t **Qptr, cmdlist_t *c);
169 static inline cmdlist_t *removeQ(cmdlist_t **Qptr, cmdlist_t *c);
170 static inline void complete_command(cmdlist_t *cmd, int timeout);
171
172 static irqreturn_t do_ida_intr(int irq, void *dev_id);
173 static void ida_timer(unsigned long tdata);
174 static int ida_revalidate(struct gendisk *disk);
175 static int revalidate_allvol(ctlr_info_t *host);
176 static int cpqarray_register_ctlr(int ctlr, struct pci_dev *pdev);
177
178 #ifdef CONFIG_PROC_FS
179 static void ida_procinit(int i);
180 static int ida_proc_get_info(char *buffer, char **start, off_t offset, int length, int *eof, void *data);
181 #else
182 static void ida_procinit(int i) {}
183 #endif
184
185 static inline drv_info_t *get_drv(struct gendisk *disk)
186 {
187 return disk->private_data;
188 }
189
190 static inline ctlr_info_t *get_host(struct gendisk *disk)
191 {
192 return disk->queue->queuedata;
193 }
194
195
196 static struct block_device_operations ida_fops = {
197 .owner = THIS_MODULE,
198 .open = ida_open,
199 .release = ida_release,
200 .locked_ioctl = ida_ioctl,
201 .getgeo = ida_getgeo,
202 .revalidate_disk= ida_revalidate,
203 };
204
205
206 #ifdef CONFIG_PROC_FS
207
208 static struct proc_dir_entry *proc_array;
209
210 /*
211 * Get us a file in /proc/array that says something about each controller.
212 * Create /proc/array if it doesn't exist yet.
213 */
214 static void __init ida_procinit(int i)
215 {
216 if (proc_array == NULL) {
217 proc_array = proc_mkdir("driver/cpqarray", NULL);
218 if (!proc_array) return;
219 }
220
221 create_proc_read_entry(hba[i]->devname, 0, proc_array,
222 ida_proc_get_info, hba[i]);
223 }
224
225 /*
226 * Report information about this controller.
227 */
228 static int ida_proc_get_info(char *buffer, char **start, off_t offset, int length, int *eof, void *data)
229 {
230 off_t pos = 0;
231 off_t len = 0;
232 int size, i, ctlr;
233 ctlr_info_t *h = (ctlr_info_t*)data;
234 drv_info_t *drv;
235 #ifdef CPQ_PROC_PRINT_QUEUES
236 cmdlist_t *c;
237 unsigned long flags;
238 #endif
239
240 ctlr = h->ctlr;
241 size = sprintf(buffer, "%s: Compaq %s Controller\n"
242 " Board ID: 0x%08lx\n"
243 " Firmware Revision: %c%c%c%c\n"
244 " Controller Sig: 0x%08lx\n"
245 " Memory Address: 0x%08lx\n"
246 " I/O Port: 0x%04x\n"
247 " IRQ: %d\n"
248 " Logical drives: %d\n"
249 " Physical drives: %d\n\n"
250 " Current Q depth: %d\n"
251 " Max Q depth since init: %d\n\n",
252 h->devname,
253 h->product_name,
254 (unsigned long)h->board_id,
255 h->firm_rev[0], h->firm_rev[1], h->firm_rev[2], h->firm_rev[3],
256 (unsigned long)h->ctlr_sig, (unsigned long)h->vaddr,
257 (unsigned int) h->io_mem_addr, (unsigned int)h->intr,
258 h->log_drives, h->phys_drives,
259 h->Qdepth, h->maxQsinceinit);
260
261 pos += size; len += size;
262
263 size = sprintf(buffer+len, "Logical Drive Info:\n");
264 pos += size; len += size;
265
266 for(i=0; i<h->log_drives; i++) {
267 drv = &h->drv[i];
268 size = sprintf(buffer+len, "ida/c%dd%d: blksz=%d nr_blks=%d\n",
269 ctlr, i, drv->blk_size, drv->nr_blks);
270 pos += size; len += size;
271 }
272
273 #ifdef CPQ_PROC_PRINT_QUEUES
274 spin_lock_irqsave(IDA_LOCK(h->ctlr), flags);
275 size = sprintf(buffer+len, "\nCurrent Queues:\n");
276 pos += size; len += size;
277
278 c = h->reqQ;
279 size = sprintf(buffer+len, "reqQ = %p", c); pos += size; len += size;
280 if (c) c=c->next;
281 while(c && c != h->reqQ) {
282 size = sprintf(buffer+len, "->%p", c);
283 pos += size; len += size;
284 c=c->next;
285 }
286
287 c = h->cmpQ;
288 size = sprintf(buffer+len, "\ncmpQ = %p", c); pos += size; len += size;
289 if (c) c=c->next;
290 while(c && c != h->cmpQ) {
291 size = sprintf(buffer+len, "->%p", c);
292 pos += size; len += size;
293 c=c->next;
294 }
295
296 size = sprintf(buffer+len, "\n"); pos += size; len += size;
297 spin_unlock_irqrestore(IDA_LOCK(h->ctlr), flags);
298 #endif
299 size = sprintf(buffer+len, "nr_allocs = %d\nnr_frees = %d\n",
300 h->nr_allocs, h->nr_frees);
301 pos += size; len += size;
302
303 *eof = 1;
304 *start = buffer+offset;
305 len -= offset;
306 if (len>length)
307 len = length;
308 return len;
309 }
310 #endif /* CONFIG_PROC_FS */
311
312 module_param_array(eisa, int, NULL, 0);
313
314 static void release_io_mem(ctlr_info_t *c)
315 {
316 /* if IO mem was not protected do nothing */
317 if( c->io_mem_addr == 0)
318 return;
319 release_region(c->io_mem_addr, c->io_mem_length);
320 c->io_mem_addr = 0;
321 c->io_mem_length = 0;
322 }
323
324 static void __devexit cpqarray_remove_one(int i)
325 {
326 int j;
327 char buff[4];
328
329 /* sendcmd will turn off interrupt, and send the flush...
330 * To write all data in the battery backed cache to disks
331 * no data returned, but don't want to send NULL to sendcmd */
332 if( sendcmd(FLUSH_CACHE, i, buff, 4, 0, 0, 0))
333 {
334 printk(KERN_WARNING "Unable to flush cache on controller %d\n",
335 i);
336 }
337 free_irq(hba[i]->intr, hba[i]);
338 iounmap(hba[i]->vaddr);
339 unregister_blkdev(COMPAQ_SMART2_MAJOR+i, hba[i]->devname);
340 del_timer(&hba[i]->timer);
341 remove_proc_entry(hba[i]->devname, proc_array);
342 pci_free_consistent(hba[i]->pci_dev,
343 NR_CMDS * sizeof(cmdlist_t), (hba[i]->cmd_pool),
344 hba[i]->cmd_pool_dhandle);
345 kfree(hba[i]->cmd_pool_bits);
346 for(j = 0; j < NWD; j++) {
347 if (ida_gendisk[i][j]->flags & GENHD_FL_UP)
348 del_gendisk(ida_gendisk[i][j]);
349 put_disk(ida_gendisk[i][j]);
350 }
351 blk_cleanup_queue(hba[i]->queue);
352 release_io_mem(hba[i]);
353 free_hba(i);
354 }
355
356 static void __devexit cpqarray_remove_one_pci (struct pci_dev *pdev)
357 {
358 int i;
359 ctlr_info_t *tmp_ptr;
360
361 if (pci_get_drvdata(pdev) == NULL) {
362 printk( KERN_ERR "cpqarray: Unable to remove device \n");
363 return;
364 }
365
366 tmp_ptr = pci_get_drvdata(pdev);
367 i = tmp_ptr->ctlr;
368 if (hba[i] == NULL) {
369 printk(KERN_ERR "cpqarray: controller %d appears to have"
370 "already been removed \n", i);
371 return;
372 }
373 pci_set_drvdata(pdev, NULL);
374
375 cpqarray_remove_one(i);
376 }
377
378 /* removing an instance that was not removed automatically..
379 * must be an eisa card.
380 */
381 static void __devexit cpqarray_remove_one_eisa (int i)
382 {
383 if (hba[i] == NULL) {
384 printk(KERN_ERR "cpqarray: controller %d appears to have"
385 "already been removed \n", i);
386 return;
387 }
388 cpqarray_remove_one(i);
389 }
390
391 /* pdev is NULL for eisa */
392 static int __init cpqarray_register_ctlr( int i, struct pci_dev *pdev)
393 {
394 struct request_queue *q;
395 int j;
396
397 /*
398 * register block devices
399 * Find disks and fill in structs
400 * Get an interrupt, set the Q depth and get into /proc
401 */
402
403 /* If this successful it should insure that we are the only */
404 /* instance of the driver */
405 if (register_blkdev(COMPAQ_SMART2_MAJOR+i, hba[i]->devname)) {
406 goto Enomem4;
407 }
408 hba[i]->access.set_intr_mask(hba[i], 0);
409 if (request_irq(hba[i]->intr, do_ida_intr,
410 IRQF_DISABLED|IRQF_SHARED, hba[i]->devname, hba[i]))
411 {
412 printk(KERN_ERR "cpqarray: Unable to get irq %d for %s\n",
413 hba[i]->intr, hba[i]->devname);
414 goto Enomem3;
415 }
416
417 for (j=0; j<NWD; j++) {
418 ida_gendisk[i][j] = alloc_disk(1 << NWD_SHIFT);
419 if (!ida_gendisk[i][j])
420 goto Enomem2;
421 }
422
423 hba[i]->cmd_pool = pci_alloc_consistent(
424 hba[i]->pci_dev, NR_CMDS * sizeof(cmdlist_t),
425 &(hba[i]->cmd_pool_dhandle));
426 hba[i]->cmd_pool_bits = kcalloc(
427 DIV_ROUND_UP(NR_CMDS, BITS_PER_LONG), sizeof(unsigned long),
428 GFP_KERNEL);
429
430 if (!hba[i]->cmd_pool_bits || !hba[i]->cmd_pool)
431 goto Enomem1;
432
433 memset(hba[i]->cmd_pool, 0, NR_CMDS * sizeof(cmdlist_t));
434 printk(KERN_INFO "cpqarray: Finding drives on %s",
435 hba[i]->devname);
436
437 spin_lock_init(&hba[i]->lock);
438 q = blk_init_queue(do_ida_request, &hba[i]->lock);
439 if (!q)
440 goto Enomem1;
441
442 hba[i]->queue = q;
443 q->queuedata = hba[i];
444
445 getgeometry(i);
446 start_fwbk(i);
447
448 ida_procinit(i);
449
450 if (pdev)
451 blk_queue_bounce_limit(q, hba[i]->pci_dev->dma_mask);
452
453 /* This is a hardware imposed limit. */
454 blk_queue_max_hw_segments(q, SG_MAX);
455
456 /* This is a driver limit and could be eliminated. */
457 blk_queue_max_phys_segments(q, SG_MAX);
458
459 init_timer(&hba[i]->timer);
460 hba[i]->timer.expires = jiffies + IDA_TIMER;
461 hba[i]->timer.data = (unsigned long)hba[i];
462 hba[i]->timer.function = ida_timer;
463 add_timer(&hba[i]->timer);
464
465 /* Enable IRQ now that spinlock and rate limit timer are set up */
466 hba[i]->access.set_intr_mask(hba[i], FIFO_NOT_EMPTY);
467
468 for(j=0; j<NWD; j++) {
469 struct gendisk *disk = ida_gendisk[i][j];
470 drv_info_t *drv = &hba[i]->drv[j];
471 sprintf(disk->disk_name, "ida/c%dd%d", i, j);
472 disk->major = COMPAQ_SMART2_MAJOR + i;
473 disk->first_minor = j<<NWD_SHIFT;
474 disk->fops = &ida_fops;
475 if (j && !drv->nr_blks)
476 continue;
477 blk_queue_hardsect_size(hba[i]->queue, drv->blk_size);
478 set_capacity(disk, drv->nr_blks);
479 disk->queue = hba[i]->queue;
480 disk->private_data = drv;
481 add_disk(disk);
482 }
483
484 /* done ! */
485 return(i);
486
487 Enomem1:
488 nr_ctlr = i;
489 kfree(hba[i]->cmd_pool_bits);
490 if (hba[i]->cmd_pool)
491 pci_free_consistent(hba[i]->pci_dev, NR_CMDS*sizeof(cmdlist_t),
492 hba[i]->cmd_pool, hba[i]->cmd_pool_dhandle);
493 Enomem2:
494 while (j--) {
495 put_disk(ida_gendisk[i][j]);
496 ida_gendisk[i][j] = NULL;
497 }
498 free_irq(hba[i]->intr, hba[i]);
499 Enomem3:
500 unregister_blkdev(COMPAQ_SMART2_MAJOR+i, hba[i]->devname);
501 Enomem4:
502 if (pdev)
503 pci_set_drvdata(pdev, NULL);
504 release_io_mem(hba[i]);
505 free_hba(i);
506
507 printk( KERN_ERR "cpqarray: out of memory");
508
509 return -1;
510 }
511
512 static int __init cpqarray_init_one( struct pci_dev *pdev,
513 const struct pci_device_id *ent)
514 {
515 int i;
516
517 printk(KERN_DEBUG "cpqarray: Device 0x%x has been found at"
518 " bus %d dev %d func %d\n",
519 pdev->device, pdev->bus->number, PCI_SLOT(pdev->devfn),
520 PCI_FUNC(pdev->devfn));
521 i = alloc_cpqarray_hba();
522 if( i < 0 )
523 return (-1);
524 memset(hba[i], 0, sizeof(ctlr_info_t));
525 sprintf(hba[i]->devname, "ida%d", i);
526 hba[i]->ctlr = i;
527 /* Initialize the pdev driver private data */
528 pci_set_drvdata(pdev, hba[i]);
529
530 if (cpqarray_pci_init(hba[i], pdev) != 0) {
531 pci_set_drvdata(pdev, NULL);
532 release_io_mem(hba[i]);
533 free_hba(i);
534 return -1;
535 }
536
537 return (cpqarray_register_ctlr(i, pdev));
538 }
539
540 static struct pci_driver cpqarray_pci_driver = {
541 .name = "cpqarray",
542 .probe = cpqarray_init_one,
543 .remove = __devexit_p(cpqarray_remove_one_pci),
544 .id_table = cpqarray_pci_device_id,
545 };
546
547 /*
548 * This is it. Find all the controllers and register them.
549 * returns the number of block devices registered.
550 */
551 static int __init cpqarray_init(void)
552 {
553 int num_cntlrs_reg = 0;
554 int i;
555 int rc = 0;
556
557 /* detect controllers */
558 printk(DRIVER_NAME "\n");
559
560 rc = pci_register_driver(&cpqarray_pci_driver);
561 if (rc)
562 return rc;
563 cpqarray_eisa_detect();
564
565 for (i=0; i < MAX_CTLR; i++) {
566 if (hba[i] != NULL)
567 num_cntlrs_reg++;
568 }
569
570 if (num_cntlrs_reg)
571 return 0;
572 else {
573 pci_unregister_driver(&cpqarray_pci_driver);
574 return -ENODEV;
575 }
576 }
577
578 /* Function to find the first free pointer into our hba[] array */
579 /* Returns -1 if no free entries are left. */
580 static int alloc_cpqarray_hba(void)
581 {
582 int i;
583
584 for(i=0; i< MAX_CTLR; i++) {
585 if (hba[i] == NULL) {
586 hba[i] = kmalloc(sizeof(ctlr_info_t), GFP_KERNEL);
587 if(hba[i]==NULL) {
588 printk(KERN_ERR "cpqarray: out of memory.\n");
589 return (-1);
590 }
591 return (i);
592 }
593 }
594 printk(KERN_WARNING "cpqarray: This driver supports a maximum"
595 " of 8 controllers.\n");
596 return(-1);
597 }
598
599 static void free_hba(int i)
600 {
601 kfree(hba[i]);
602 hba[i]=NULL;
603 }
604
605 /*
606 * Find the IO address of the controller, its IRQ and so forth. Fill
607 * in some basic stuff into the ctlr_info_t structure.
608 */
609 static int cpqarray_pci_init(ctlr_info_t *c, struct pci_dev *pdev)
610 {
611 ushort vendor_id, device_id, command;
612 unchar cache_line_size, latency_timer;
613 unchar irq, revision;
614 unsigned long addr[6];
615 __u32 board_id;
616
617 int i;
618
619 c->pci_dev = pdev;
620 if (pci_enable_device(pdev)) {
621 printk(KERN_ERR "cpqarray: Unable to Enable PCI device\n");
622 return -1;
623 }
624 vendor_id = pdev->vendor;
625 device_id = pdev->device;
626 irq = pdev->irq;
627
628 for(i=0; i<6; i++)
629 addr[i] = pci_resource_start(pdev, i);
630
631 if (pci_set_dma_mask(pdev, CPQARRAY_DMA_MASK) != 0)
632 {
633 printk(KERN_ERR "cpqarray: Unable to set DMA mask\n");
634 return -1;
635 }
636
637 pci_read_config_word(pdev, PCI_COMMAND, &command);
638 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision);
639 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line_size);
640 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency_timer);
641
642 pci_read_config_dword(pdev, 0x2c, &board_id);
643
644 /* check to see if controller has been disabled */
645 if(!(command & 0x02)) {
646 printk(KERN_WARNING
647 "cpqarray: controller appears to be disabled\n");
648 return(-1);
649 }
650
651 DBGINFO(
652 printk("vendor_id = %x\n", vendor_id);
653 printk("device_id = %x\n", device_id);
654 printk("command = %x\n", command);
655 for(i=0; i<6; i++)
656 printk("addr[%d] = %lx\n", i, addr[i]);
657 printk("revision = %x\n", revision);
658 printk("irq = %x\n", irq);
659 printk("cache_line_size = %x\n", cache_line_size);
660 printk("latency_timer = %x\n", latency_timer);
661 printk("board_id = %x\n", board_id);
662 );
663
664 c->intr = irq;
665
666 for(i=0; i<6; i++) {
667 if (pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE_IO)
668 { /* IO space */
669 c->io_mem_addr = addr[i];
670 c->io_mem_length = pci_resource_end(pdev, i)
671 - pci_resource_start(pdev, i) + 1;
672 if(!request_region( c->io_mem_addr, c->io_mem_length,
673 "cpqarray"))
674 {
675 printk( KERN_WARNING "cpqarray I/O memory range already in use addr %lx length = %ld\n", c->io_mem_addr, c->io_mem_length);
676 c->io_mem_addr = 0;
677 c->io_mem_length = 0;
678 }
679 break;
680 }
681 }
682
683 c->paddr = 0;
684 for(i=0; i<6; i++)
685 if (!(pci_resource_flags(pdev, i) &
686 PCI_BASE_ADDRESS_SPACE_IO)) {
687 c->paddr = pci_resource_start (pdev, i);
688 break;
689 }
690 if (!c->paddr)
691 return -1;
692 c->vaddr = remap_pci_mem(c->paddr, 128);
693 if (!c->vaddr)
694 return -1;
695 c->board_id = board_id;
696
697 for(i=0; i<NR_PRODUCTS; i++) {
698 if (board_id == products[i].board_id) {
699 c->product_name = products[i].product_name;
700 c->access = *(products[i].access);
701 break;
702 }
703 }
704 if (i == NR_PRODUCTS) {
705 printk(KERN_WARNING "cpqarray: Sorry, I don't know how"
706 " to access the SMART Array controller %08lx\n",
707 (unsigned long)board_id);
708 return -1;
709 }
710
711 return 0;
712 }
713
714 /*
715 * Map (physical) PCI mem into (virtual) kernel space
716 */
717 static void __iomem *remap_pci_mem(ulong base, ulong size)
718 {
719 ulong page_base = ((ulong) base) & PAGE_MASK;
720 ulong page_offs = ((ulong) base) - page_base;
721 void __iomem *page_remapped = ioremap(page_base, page_offs+size);
722
723 return (page_remapped ? (page_remapped + page_offs) : NULL);
724 }
725
726 #ifndef MODULE
727 /*
728 * Config string is a comma separated set of i/o addresses of EISA cards.
729 */
730 static int cpqarray_setup(char *str)
731 {
732 int i, ints[9];
733
734 (void)get_options(str, ARRAY_SIZE(ints), ints);
735
736 for(i=0; i<ints[0] && i<8; i++)
737 eisa[i] = ints[i+1];
738 return 1;
739 }
740
741 __setup("smart2=", cpqarray_setup);
742
743 #endif
744
745 /*
746 * Find an EISA controller's signature. Set up an hba if we find it.
747 */
748 static int __init cpqarray_eisa_detect(void)
749 {
750 int i=0, j;
751 __u32 board_id;
752 int intr;
753 int ctlr;
754 int num_ctlr = 0;
755
756 while(i<8 && eisa[i]) {
757 ctlr = alloc_cpqarray_hba();
758 if(ctlr == -1)
759 break;
760 board_id = inl(eisa[i]+0xC80);
761 for(j=0; j < NR_PRODUCTS; j++)
762 if (board_id == products[j].board_id)
763 break;
764
765 if (j == NR_PRODUCTS) {
766 printk(KERN_WARNING "cpqarray: Sorry, I don't know how"
767 " to access the SMART Array controller %08lx\n", (unsigned long)board_id);
768 continue;
769 }
770
771 memset(hba[ctlr], 0, sizeof(ctlr_info_t));
772 hba[ctlr]->io_mem_addr = eisa[i];
773 hba[ctlr]->io_mem_length = 0x7FF;
774 if(!request_region(hba[ctlr]->io_mem_addr,
775 hba[ctlr]->io_mem_length,
776 "cpqarray"))
777 {
778 printk(KERN_WARNING "cpqarray: I/O range already in "
779 "use addr = %lx length = %ld\n",
780 hba[ctlr]->io_mem_addr,
781 hba[ctlr]->io_mem_length);
782 free_hba(ctlr);
783 continue;
784 }
785
786 /*
787 * Read the config register to find our interrupt
788 */
789 intr = inb(eisa[i]+0xCC0) >> 4;
790 if (intr & 1) intr = 11;
791 else if (intr & 2) intr = 10;
792 else if (intr & 4) intr = 14;
793 else if (intr & 8) intr = 15;
794
795 hba[ctlr]->intr = intr;
796 sprintf(hba[ctlr]->devname, "ida%d", nr_ctlr);
797 hba[ctlr]->product_name = products[j].product_name;
798 hba[ctlr]->access = *(products[j].access);
799 hba[ctlr]->ctlr = ctlr;
800 hba[ctlr]->board_id = board_id;
801 hba[ctlr]->pci_dev = NULL; /* not PCI */
802
803 DBGINFO(
804 printk("i = %d, j = %d\n", i, j);
805 printk("irq = %x\n", intr);
806 printk("product name = %s\n", products[j].product_name);
807 printk("board_id = %x\n", board_id);
808 );
809
810 num_ctlr++;
811 i++;
812
813 if (cpqarray_register_ctlr(ctlr, NULL) == -1)
814 printk(KERN_WARNING
815 "cpqarray: Can't register EISA controller %d\n",
816 ctlr);
817
818 }
819
820 return num_ctlr;
821 }
822
823 /*
824 * Open. Make sure the device is really there.
825 */
826 static int ida_open(struct block_device *bdev, fmode_t mode)
827 {
828 drv_info_t *drv = get_drv(bdev->bd_disk);
829 ctlr_info_t *host = get_host(bdev->bd_disk);
830
831 DBGINFO(printk("ida_open %s\n", bdev->bd_disk->disk_name));
832 /*
833 * Root is allowed to open raw volume zero even if it's not configured
834 * so array config can still work. I don't think I really like this,
835 * but I'm already using way to many device nodes to claim another one
836 * for "raw controller".
837 */
838 if (!drv->nr_blks) {
839 if (!capable(CAP_SYS_RAWIO))
840 return -ENXIO;
841 if (!capable(CAP_SYS_ADMIN) && drv != host->drv)
842 return -ENXIO;
843 }
844 host->usage_count++;
845 return 0;
846 }
847
848 /*
849 * Close. Sync first.
850 */
851 static int ida_release(struct gendisk *disk, fmode_t mode)
852 {
853 ctlr_info_t *host = get_host(disk);
854 host->usage_count--;
855 return 0;
856 }
857
858 /*
859 * Enqueuing and dequeuing functions for cmdlists.
860 */
861 static inline void addQ(cmdlist_t **Qptr, cmdlist_t *c)
862 {
863 if (*Qptr == NULL) {
864 *Qptr = c;
865 c->next = c->prev = c;
866 } else {
867 c->prev = (*Qptr)->prev;
868 c->next = (*Qptr);
869 (*Qptr)->prev->next = c;
870 (*Qptr)->prev = c;
871 }
872 }
873
874 static inline cmdlist_t *removeQ(cmdlist_t **Qptr, cmdlist_t *c)
875 {
876 if (c && c->next != c) {
877 if (*Qptr == c) *Qptr = c->next;
878 c->prev->next = c->next;
879 c->next->prev = c->prev;
880 } else {
881 *Qptr = NULL;
882 }
883 return c;
884 }
885
886 /*
887 * Get a request and submit it to the controller.
888 * This routine needs to grab all the requests it possibly can from the
889 * req Q and submit them. Interrupts are off (and need to be off) when you
890 * are in here (either via the dummy do_ida_request functions or by being
891 * called from the interrupt handler
892 */
893 static void do_ida_request(struct request_queue *q)
894 {
895 ctlr_info_t *h = q->queuedata;
896 cmdlist_t *c;
897 struct request *creq;
898 struct scatterlist tmp_sg[SG_MAX];
899 int i, dir, seg;
900
901 if (blk_queue_plugged(q))
902 goto startio;
903
904 queue_next:
905 creq = elv_next_request(q);
906 if (!creq)
907 goto startio;
908
909 BUG_ON(creq->nr_phys_segments > SG_MAX);
910
911 if ((c = cmd_alloc(h,1)) == NULL)
912 goto startio;
913
914 blkdev_dequeue_request(creq);
915
916 c->ctlr = h->ctlr;
917 c->hdr.unit = (drv_info_t *)(creq->rq_disk->private_data) - h->drv;
918 c->hdr.size = sizeof(rblk_t) >> 2;
919 c->size += sizeof(rblk_t);
920
921 c->req.hdr.blk = creq->sector;
922 c->rq = creq;
923 DBGPX(
924 printk("sector=%d, nr_sectors=%d\n", creq->sector, creq->nr_sectors);
925 );
926 sg_init_table(tmp_sg, SG_MAX);
927 seg = blk_rq_map_sg(q, creq, tmp_sg);
928
929 /* Now do all the DMA Mappings */
930 if (rq_data_dir(creq) == READ)
931 dir = PCI_DMA_FROMDEVICE;
932 else
933 dir = PCI_DMA_TODEVICE;
934 for( i=0; i < seg; i++)
935 {
936 c->req.sg[i].size = tmp_sg[i].length;
937 c->req.sg[i].addr = (__u32) pci_map_page(h->pci_dev,
938 sg_page(&tmp_sg[i]),
939 tmp_sg[i].offset,
940 tmp_sg[i].length, dir);
941 }
942 DBGPX( printk("Submitting %d sectors in %d segments\n", creq->nr_sectors, seg); );
943 c->req.hdr.sg_cnt = seg;
944 c->req.hdr.blk_cnt = creq->nr_sectors;
945 c->req.hdr.cmd = (rq_data_dir(creq) == READ) ? IDA_READ : IDA_WRITE;
946 c->type = CMD_RWREQ;
947
948 /* Put the request on the tail of the request queue */
949 addQ(&h->reqQ, c);
950 h->Qdepth++;
951 if (h->Qdepth > h->maxQsinceinit)
952 h->maxQsinceinit = h->Qdepth;
953
954 goto queue_next;
955
956 startio:
957 start_io(h);
958 }
959
960 /*
961 * start_io submits everything on a controller's request queue
962 * and moves it to the completion queue.
963 *
964 * Interrupts had better be off if you're in here
965 */
966 static void start_io(ctlr_info_t *h)
967 {
968 cmdlist_t *c;
969
970 while((c = h->reqQ) != NULL) {
971 /* Can't do anything if we're busy */
972 if (h->access.fifo_full(h) == 0)
973 return;
974
975 /* Get the first entry from the request Q */
976 removeQ(&h->reqQ, c);
977 h->Qdepth--;
978
979 /* Tell the controller to do our bidding */
980 h->access.submit_command(h, c);
981
982 /* Get onto the completion Q */
983 addQ(&h->cmpQ, c);
984 }
985 }
986
987 /*
988 * Mark all buffers that cmd was responsible for
989 */
990 static inline void complete_command(cmdlist_t *cmd, int timeout)
991 {
992 struct request *rq = cmd->rq;
993 int error = 0;
994 int i, ddir;
995
996 if (cmd->req.hdr.rcode & RCODE_NONFATAL &&
997 (hba[cmd->ctlr]->misc_tflags & MISC_NONFATAL_WARN) == 0) {
998 printk(KERN_NOTICE "Non Fatal error on ida/c%dd%d\n",
999 cmd->ctlr, cmd->hdr.unit);
1000 hba[cmd->ctlr]->misc_tflags |= MISC_NONFATAL_WARN;
1001 }
1002 if (cmd->req.hdr.rcode & RCODE_FATAL) {
1003 printk(KERN_WARNING "Fatal error on ida/c%dd%d\n",
1004 cmd->ctlr, cmd->hdr.unit);
1005 error = -EIO;
1006 }
1007 if (cmd->req.hdr.rcode & RCODE_INVREQ) {
1008 printk(KERN_WARNING "Invalid request on ida/c%dd%d = (cmd=%x sect=%d cnt=%d sg=%d ret=%x)\n",
1009 cmd->ctlr, cmd->hdr.unit, cmd->req.hdr.cmd,
1010 cmd->req.hdr.blk, cmd->req.hdr.blk_cnt,
1011 cmd->req.hdr.sg_cnt, cmd->req.hdr.rcode);
1012 error = -EIO;
1013 }
1014 if (timeout)
1015 error = -EIO;
1016 /* unmap the DMA mapping for all the scatter gather elements */
1017 if (cmd->req.hdr.cmd == IDA_READ)
1018 ddir = PCI_DMA_FROMDEVICE;
1019 else
1020 ddir = PCI_DMA_TODEVICE;
1021 for(i=0; i<cmd->req.hdr.sg_cnt; i++)
1022 pci_unmap_page(hba[cmd->ctlr]->pci_dev, cmd->req.sg[i].addr,
1023 cmd->req.sg[i].size, ddir);
1024
1025 DBGPX(printk("Done with %p\n", rq););
1026 if (__blk_end_request(rq, error, blk_rq_bytes(rq)))
1027 BUG();
1028 }
1029
1030 /*
1031 * The controller will interrupt us upon completion of commands.
1032 * Find the command on the completion queue, remove it, tell the OS and
1033 * try to queue up more IO
1034 */
1035 static irqreturn_t do_ida_intr(int irq, void *dev_id)
1036 {
1037 ctlr_info_t *h = dev_id;
1038 cmdlist_t *c;
1039 unsigned long istat;
1040 unsigned long flags;
1041 __u32 a,a1;
1042
1043 istat = h->access.intr_pending(h);
1044 /* Is this interrupt for us? */
1045 if (istat == 0)
1046 return IRQ_NONE;
1047
1048 /*
1049 * If there are completed commands in the completion queue,
1050 * we had better do something about it.
1051 */
1052 spin_lock_irqsave(IDA_LOCK(h->ctlr), flags);
1053 if (istat & FIFO_NOT_EMPTY) {
1054 while((a = h->access.command_completed(h))) {
1055 a1 = a; a &= ~3;
1056 if ((c = h->cmpQ) == NULL)
1057 {
1058 printk(KERN_WARNING "cpqarray: Completion of %08lx ignored\n", (unsigned long)a1);
1059 continue;
1060 }
1061 while(c->busaddr != a) {
1062 c = c->next;
1063 if (c == h->cmpQ)
1064 break;
1065 }
1066 /*
1067 * If we've found the command, take it off the
1068 * completion Q and free it
1069 */
1070 if (c->busaddr == a) {
1071 removeQ(&h->cmpQ, c);
1072 /* Check for invalid command.
1073 * Controller returns command error,
1074 * But rcode = 0.
1075 */
1076
1077 if((a1 & 0x03) && (c->req.hdr.rcode == 0))
1078 {
1079 c->req.hdr.rcode = RCODE_INVREQ;
1080 }
1081 if (c->type == CMD_RWREQ) {
1082 complete_command(c, 0);
1083 cmd_free(h, c, 1);
1084 } else if (c->type == CMD_IOCTL_PEND) {
1085 c->type = CMD_IOCTL_DONE;
1086 }
1087 continue;
1088 }
1089 }
1090 }
1091
1092 /*
1093 * See if we can queue up some more IO
1094 */
1095 do_ida_request(h->queue);
1096 spin_unlock_irqrestore(IDA_LOCK(h->ctlr), flags);
1097 return IRQ_HANDLED;
1098 }
1099
1100 /*
1101 * This timer was for timing out requests that haven't happened after
1102 * IDA_TIMEOUT. That wasn't such a good idea. This timer is used to
1103 * reset a flags structure so we don't flood the user with
1104 * "Non-Fatal error" messages.
1105 */
1106 static void ida_timer(unsigned long tdata)
1107 {
1108 ctlr_info_t *h = (ctlr_info_t*)tdata;
1109
1110 h->timer.expires = jiffies + IDA_TIMER;
1111 add_timer(&h->timer);
1112 h->misc_tflags = 0;
1113 }
1114
1115 static int ida_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1116 {
1117 drv_info_t *drv = get_drv(bdev->bd_disk);
1118
1119 if (drv->cylinders) {
1120 geo->heads = drv->heads;
1121 geo->sectors = drv->sectors;
1122 geo->cylinders = drv->cylinders;
1123 } else {
1124 geo->heads = 0xff;
1125 geo->sectors = 0x3f;
1126 geo->cylinders = drv->nr_blks / (0xff*0x3f);
1127 }
1128
1129 return 0;
1130 }
1131
1132 /*
1133 * ida_ioctl does some miscellaneous stuff like reporting drive geometry,
1134 * setting readahead and submitting commands from userspace to the controller.
1135 */
1136 static int ida_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, unsigned long arg)
1137 {
1138 drv_info_t *drv = get_drv(bdev->bd_disk);
1139 ctlr_info_t *host = get_host(bdev->bd_disk);
1140 int error;
1141 ida_ioctl_t __user *io = (ida_ioctl_t __user *)arg;
1142 ida_ioctl_t *my_io;
1143
1144 switch(cmd) {
1145 case IDAGETDRVINFO:
1146 if (copy_to_user(&io->c.drv, drv, sizeof(drv_info_t)))
1147 return -EFAULT;
1148 return 0;
1149 case IDAPASSTHRU:
1150 if (!capable(CAP_SYS_RAWIO))
1151 return -EPERM;
1152 my_io = kmalloc(sizeof(ida_ioctl_t), GFP_KERNEL);
1153 if (!my_io)
1154 return -ENOMEM;
1155 error = -EFAULT;
1156 if (copy_from_user(my_io, io, sizeof(*my_io)))
1157 goto out_passthru;
1158 error = ida_ctlr_ioctl(host, drv - host->drv, my_io);
1159 if (error)
1160 goto out_passthru;
1161 error = -EFAULT;
1162 if (copy_to_user(io, my_io, sizeof(*my_io)))
1163 goto out_passthru;
1164 error = 0;
1165 out_passthru:
1166 kfree(my_io);
1167 return error;
1168 case IDAGETCTLRSIG:
1169 if (!arg) return -EINVAL;
1170 put_user(host->ctlr_sig, (int __user *)arg);
1171 return 0;
1172 case IDAREVALIDATEVOLS:
1173 if (MINOR(bdev->bd_dev) != 0)
1174 return -ENXIO;
1175 return revalidate_allvol(host);
1176 case IDADRIVERVERSION:
1177 if (!arg) return -EINVAL;
1178 put_user(DRIVER_VERSION, (unsigned long __user *)arg);
1179 return 0;
1180 case IDAGETPCIINFO:
1181 {
1182
1183 ida_pci_info_struct pciinfo;
1184
1185 if (!arg) return -EINVAL;
1186 pciinfo.bus = host->pci_dev->bus->number;
1187 pciinfo.dev_fn = host->pci_dev->devfn;
1188 pciinfo.board_id = host->board_id;
1189 if(copy_to_user((void __user *) arg, &pciinfo,
1190 sizeof( ida_pci_info_struct)))
1191 return -EFAULT;
1192 return(0);
1193 }
1194
1195 default:
1196 return -EINVAL;
1197 }
1198
1199 }
1200 /*
1201 * ida_ctlr_ioctl is for passing commands to the controller from userspace.
1202 * The command block (io) has already been copied to kernel space for us,
1203 * however, any elements in the sglist need to be copied to kernel space
1204 * or copied back to userspace.
1205 *
1206 * Only root may perform a controller passthru command, however I'm not doing
1207 * any serious sanity checking on the arguments. Doing an IDA_WRITE_MEDIA and
1208 * putting a 64M buffer in the sglist is probably a *bad* idea.
1209 */
1210 static int ida_ctlr_ioctl(ctlr_info_t *h, int dsk, ida_ioctl_t *io)
1211 {
1212 int ctlr = h->ctlr;
1213 cmdlist_t *c;
1214 void *p = NULL;
1215 unsigned long flags;
1216 int error;
1217
1218 if ((c = cmd_alloc(h, 0)) == NULL)
1219 return -ENOMEM;
1220 c->ctlr = ctlr;
1221 c->hdr.unit = (io->unit & UNITVALID) ? (io->unit & ~UNITVALID) : dsk;
1222 c->hdr.size = sizeof(rblk_t) >> 2;
1223 c->size += sizeof(rblk_t);
1224
1225 c->req.hdr.cmd = io->cmd;
1226 c->req.hdr.blk = io->blk;
1227 c->req.hdr.blk_cnt = io->blk_cnt;
1228 c->type = CMD_IOCTL_PEND;
1229
1230 /* Pre submit processing */
1231 switch(io->cmd) {
1232 case PASSTHRU_A:
1233 p = kmalloc(io->sg[0].size, GFP_KERNEL);
1234 if (!p)
1235 {
1236 error = -ENOMEM;
1237 cmd_free(h, c, 0);
1238 return(error);
1239 }
1240 if (copy_from_user(p, io->sg[0].addr, io->sg[0].size)) {
1241 kfree(p);
1242 cmd_free(h, c, 0);
1243 return -EFAULT;
1244 }
1245 c->req.hdr.blk = pci_map_single(h->pci_dev, &(io->c),
1246 sizeof(ida_ioctl_t),
1247 PCI_DMA_BIDIRECTIONAL);
1248 c->req.sg[0].size = io->sg[0].size;
1249 c->req.sg[0].addr = pci_map_single(h->pci_dev, p,
1250 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1251 c->req.hdr.sg_cnt = 1;
1252 break;
1253 case IDA_READ:
1254 case READ_FLASH_ROM:
1255 case SENSE_CONTROLLER_PERFORMANCE:
1256 p = kmalloc(io->sg[0].size, GFP_KERNEL);
1257 if (!p)
1258 {
1259 error = -ENOMEM;
1260 cmd_free(h, c, 0);
1261 return(error);
1262 }
1263
1264 c->req.sg[0].size = io->sg[0].size;
1265 c->req.sg[0].addr = pci_map_single(h->pci_dev, p,
1266 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1267 c->req.hdr.sg_cnt = 1;
1268 break;
1269 case IDA_WRITE:
1270 case IDA_WRITE_MEDIA:
1271 case DIAG_PASS_THRU:
1272 case COLLECT_BUFFER:
1273 case WRITE_FLASH_ROM:
1274 p = kmalloc(io->sg[0].size, GFP_KERNEL);
1275 if (!p)
1276 {
1277 error = -ENOMEM;
1278 cmd_free(h, c, 0);
1279 return(error);
1280 }
1281 if (copy_from_user(p, io->sg[0].addr, io->sg[0].size)) {
1282 kfree(p);
1283 cmd_free(h, c, 0);
1284 return -EFAULT;
1285 }
1286 c->req.sg[0].size = io->sg[0].size;
1287 c->req.sg[0].addr = pci_map_single(h->pci_dev, p,
1288 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1289 c->req.hdr.sg_cnt = 1;
1290 break;
1291 default:
1292 c->req.sg[0].size = sizeof(io->c);
1293 c->req.sg[0].addr = pci_map_single(h->pci_dev,&io->c,
1294 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1295 c->req.hdr.sg_cnt = 1;
1296 }
1297
1298 /* Put the request on the tail of the request queue */
1299 spin_lock_irqsave(IDA_LOCK(ctlr), flags);
1300 addQ(&h->reqQ, c);
1301 h->Qdepth++;
1302 start_io(h);
1303 spin_unlock_irqrestore(IDA_LOCK(ctlr), flags);
1304
1305 /* Wait for completion */
1306 while(c->type != CMD_IOCTL_DONE)
1307 schedule();
1308
1309 /* Unmap the DMA */
1310 pci_unmap_single(h->pci_dev, c->req.sg[0].addr, c->req.sg[0].size,
1311 PCI_DMA_BIDIRECTIONAL);
1312 /* Post submit processing */
1313 switch(io->cmd) {
1314 case PASSTHRU_A:
1315 pci_unmap_single(h->pci_dev, c->req.hdr.blk,
1316 sizeof(ida_ioctl_t),
1317 PCI_DMA_BIDIRECTIONAL);
1318 case IDA_READ:
1319 case DIAG_PASS_THRU:
1320 case SENSE_CONTROLLER_PERFORMANCE:
1321 case READ_FLASH_ROM:
1322 if (copy_to_user(io->sg[0].addr, p, io->sg[0].size)) {
1323 kfree(p);
1324 return -EFAULT;
1325 }
1326 /* fall through and free p */
1327 case IDA_WRITE:
1328 case IDA_WRITE_MEDIA:
1329 case COLLECT_BUFFER:
1330 case WRITE_FLASH_ROM:
1331 kfree(p);
1332 break;
1333 default:;
1334 /* Nothing to do */
1335 }
1336
1337 io->rcode = c->req.hdr.rcode;
1338 cmd_free(h, c, 0);
1339 return(0);
1340 }
1341
1342 /*
1343 * Commands are pre-allocated in a large block. Here we use a simple bitmap
1344 * scheme to suballocte them to the driver. Operations that are not time
1345 * critical (and can wait for kmalloc and possibly sleep) can pass in NULL
1346 * as the first argument to get a new command.
1347 */
1348 static cmdlist_t * cmd_alloc(ctlr_info_t *h, int get_from_pool)
1349 {
1350 cmdlist_t * c;
1351 int i;
1352 dma_addr_t cmd_dhandle;
1353
1354 if (!get_from_pool) {
1355 c = (cmdlist_t*)pci_alloc_consistent(h->pci_dev,
1356 sizeof(cmdlist_t), &cmd_dhandle);
1357 if(c==NULL)
1358 return NULL;
1359 } else {
1360 do {
1361 i = find_first_zero_bit(h->cmd_pool_bits, NR_CMDS);
1362 if (i == NR_CMDS)
1363 return NULL;
1364 } while(test_and_set_bit(i&(BITS_PER_LONG-1), h->cmd_pool_bits+(i/BITS_PER_LONG)) != 0);
1365 c = h->cmd_pool + i;
1366 cmd_dhandle = h->cmd_pool_dhandle + i*sizeof(cmdlist_t);
1367 h->nr_allocs++;
1368 }
1369
1370 memset(c, 0, sizeof(cmdlist_t));
1371 c->busaddr = cmd_dhandle;
1372 return c;
1373 }
1374
1375 static void cmd_free(ctlr_info_t *h, cmdlist_t *c, int got_from_pool)
1376 {
1377 int i;
1378
1379 if (!got_from_pool) {
1380 pci_free_consistent(h->pci_dev, sizeof(cmdlist_t), c,
1381 c->busaddr);
1382 } else {
1383 i = c - h->cmd_pool;
1384 clear_bit(i&(BITS_PER_LONG-1), h->cmd_pool_bits+(i/BITS_PER_LONG));
1385 h->nr_frees++;
1386 }
1387 }
1388
1389 /***********************************************************************
1390 name: sendcmd
1391 Send a command to an IDA using the memory mapped FIFO interface
1392 and wait for it to complete.
1393 This routine should only be called at init time.
1394 ***********************************************************************/
1395 static int sendcmd(
1396 __u8 cmd,
1397 int ctlr,
1398 void *buff,
1399 size_t size,
1400 unsigned int blk,
1401 unsigned int blkcnt,
1402 unsigned int log_unit )
1403 {
1404 cmdlist_t *c;
1405 int complete;
1406 unsigned long temp;
1407 unsigned long i;
1408 ctlr_info_t *info_p = hba[ctlr];
1409
1410 c = cmd_alloc(info_p, 1);
1411 if(!c)
1412 return IO_ERROR;
1413 c->ctlr = ctlr;
1414 c->hdr.unit = log_unit;
1415 c->hdr.prio = 0;
1416 c->hdr.size = sizeof(rblk_t) >> 2;
1417 c->size += sizeof(rblk_t);
1418
1419 /* The request information. */
1420 c->req.hdr.next = 0;
1421 c->req.hdr.rcode = 0;
1422 c->req.bp = 0;
1423 c->req.hdr.sg_cnt = 1;
1424 c->req.hdr.reserved = 0;
1425
1426 if (size == 0)
1427 c->req.sg[0].size = 512;
1428 else
1429 c->req.sg[0].size = size;
1430
1431 c->req.hdr.blk = blk;
1432 c->req.hdr.blk_cnt = blkcnt;
1433 c->req.hdr.cmd = (unsigned char) cmd;
1434 c->req.sg[0].addr = (__u32) pci_map_single(info_p->pci_dev,
1435 buff, c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1436 /*
1437 * Disable interrupt
1438 */
1439 info_p->access.set_intr_mask(info_p, 0);
1440 /* Make sure there is room in the command FIFO */
1441 /* Actually it should be completely empty at this time. */
1442 for (i = 200000; i > 0; i--) {
1443 temp = info_p->access.fifo_full(info_p);
1444 if (temp != 0) {
1445 break;
1446 }
1447 udelay(10);
1448 DBG(
1449 printk(KERN_WARNING "cpqarray ida%d: idaSendPciCmd FIFO full,"
1450 " waiting!\n", ctlr);
1451 );
1452 }
1453 /*
1454 * Send the cmd
1455 */
1456 info_p->access.submit_command(info_p, c);
1457 complete = pollcomplete(ctlr);
1458
1459 pci_unmap_single(info_p->pci_dev, (dma_addr_t) c->req.sg[0].addr,
1460 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1461 if (complete != 1) {
1462 if (complete != c->busaddr) {
1463 printk( KERN_WARNING
1464 "cpqarray ida%d: idaSendPciCmd "
1465 "Invalid command list address returned! (%08lx)\n",
1466 ctlr, (unsigned long)complete);
1467 cmd_free(info_p, c, 1);
1468 return (IO_ERROR);
1469 }
1470 } else {
1471 printk( KERN_WARNING
1472 "cpqarray ida%d: idaSendPciCmd Timeout out, "
1473 "No command list address returned!\n",
1474 ctlr);
1475 cmd_free(info_p, c, 1);
1476 return (IO_ERROR);
1477 }
1478
1479 if (c->req.hdr.rcode & 0x00FE) {
1480 if (!(c->req.hdr.rcode & BIG_PROBLEM)) {
1481 printk( KERN_WARNING
1482 "cpqarray ida%d: idaSendPciCmd, error: "
1483 "Controller failed at init time "
1484 "cmd: 0x%x, return code = 0x%x\n",
1485 ctlr, c->req.hdr.cmd, c->req.hdr.rcode);
1486
1487 cmd_free(info_p, c, 1);
1488 return (IO_ERROR);
1489 }
1490 }
1491 cmd_free(info_p, c, 1);
1492 return (IO_OK);
1493 }
1494
1495 /*
1496 * revalidate_allvol is for online array config utilities. After a
1497 * utility reconfigures the drives in the array, it can use this function
1498 * (through an ioctl) to make the driver zap any previous disk structs for
1499 * that controller and get new ones.
1500 *
1501 * Right now I'm using the getgeometry() function to do this, but this
1502 * function should probably be finer grained and allow you to revalidate one
1503 * particualar logical volume (instead of all of them on a particular
1504 * controller).
1505 */
1506 static int revalidate_allvol(ctlr_info_t *host)
1507 {
1508 int ctlr = host->ctlr;
1509 int i;
1510 unsigned long flags;
1511
1512 spin_lock_irqsave(IDA_LOCK(ctlr), flags);
1513 if (host->usage_count > 1) {
1514 spin_unlock_irqrestore(IDA_LOCK(ctlr), flags);
1515 printk(KERN_WARNING "cpqarray: Device busy for volume"
1516 " revalidation (usage=%d)\n", host->usage_count);
1517 return -EBUSY;
1518 }
1519 host->usage_count++;
1520 spin_unlock_irqrestore(IDA_LOCK(ctlr), flags);
1521
1522 /*
1523 * Set the partition and block size structures for all volumes
1524 * on this controller to zero. We will reread all of this data
1525 */
1526 set_capacity(ida_gendisk[ctlr][0], 0);
1527 for (i = 1; i < NWD; i++) {
1528 struct gendisk *disk = ida_gendisk[ctlr][i];
1529 if (disk->flags & GENHD_FL_UP)
1530 del_gendisk(disk);
1531 }
1532 memset(host->drv, 0, sizeof(drv_info_t)*NWD);
1533
1534 /*
1535 * Tell the array controller not to give us any interrupts while
1536 * we check the new geometry. Then turn interrupts back on when
1537 * we're done.
1538 */
1539 host->access.set_intr_mask(host, 0);
1540 getgeometry(ctlr);
1541 host->access.set_intr_mask(host, FIFO_NOT_EMPTY);
1542
1543 for(i=0; i<NWD; i++) {
1544 struct gendisk *disk = ida_gendisk[ctlr][i];
1545 drv_info_t *drv = &host->drv[i];
1546 if (i && !drv->nr_blks)
1547 continue;
1548 blk_queue_hardsect_size(host->queue, drv->blk_size);
1549 set_capacity(disk, drv->nr_blks);
1550 disk->queue = host->queue;
1551 disk->private_data = drv;
1552 if (i)
1553 add_disk(disk);
1554 }
1555
1556 host->usage_count--;
1557 return 0;
1558 }
1559
1560 static int ida_revalidate(struct gendisk *disk)
1561 {
1562 drv_info_t *drv = disk->private_data;
1563 set_capacity(disk, drv->nr_blks);
1564 return 0;
1565 }
1566
1567 /********************************************************************
1568 name: pollcomplete
1569 Wait polling for a command to complete.
1570 The memory mapped FIFO is polled for the completion.
1571 Used only at init time, interrupts disabled.
1572 ********************************************************************/
1573 static int pollcomplete(int ctlr)
1574 {
1575 int done;
1576 int i;
1577
1578 /* Wait (up to 2 seconds) for a command to complete */
1579
1580 for (i = 200000; i > 0; i--) {
1581 done = hba[ctlr]->access.command_completed(hba[ctlr]);
1582 if (done == 0) {
1583 udelay(10); /* a short fixed delay */
1584 } else
1585 return (done);
1586 }
1587 /* Invalid address to tell caller we ran out of time */
1588 return 1;
1589 }
1590 /*****************************************************************
1591 start_fwbk
1592 Starts controller firmwares background processing.
1593 Currently only the Integrated Raid controller needs this done.
1594 If the PCI mem address registers are written to after this,
1595 data corruption may occur
1596 *****************************************************************/
1597 static void start_fwbk(int ctlr)
1598 {
1599 id_ctlr_t *id_ctlr_buf;
1600 int ret_code;
1601
1602 if( (hba[ctlr]->board_id != 0x40400E11)
1603 && (hba[ctlr]->board_id != 0x40480E11) )
1604
1605 /* Not a Integrated Raid, so there is nothing for us to do */
1606 return;
1607 printk(KERN_DEBUG "cpqarray: Starting firmware's background"
1608 " processing\n");
1609 /* Command does not return anything, but idasend command needs a
1610 buffer */
1611 id_ctlr_buf = kmalloc(sizeof(id_ctlr_t), GFP_KERNEL);
1612 if(id_ctlr_buf==NULL)
1613 {
1614 printk(KERN_WARNING "cpqarray: Out of memory. "
1615 "Unable to start background processing.\n");
1616 return;
1617 }
1618 ret_code = sendcmd(RESUME_BACKGROUND_ACTIVITY, ctlr,
1619 id_ctlr_buf, 0, 0, 0, 0);
1620 if(ret_code != IO_OK)
1621 printk(KERN_WARNING "cpqarray: Unable to start"
1622 " background processing\n");
1623
1624 kfree(id_ctlr_buf);
1625 }
1626 /*****************************************************************
1627 getgeometry
1628 Get ida logical volume geometry from the controller
1629 This is a large bit of code which once existed in two flavors,
1630 It is used only at init time.
1631 *****************************************************************/
1632 static void getgeometry(int ctlr)
1633 {
1634 id_log_drv_t *id_ldrive;
1635 id_ctlr_t *id_ctlr_buf;
1636 sense_log_drv_stat_t *id_lstatus_buf;
1637 config_t *sense_config_buf;
1638 unsigned int log_unit, log_index;
1639 int ret_code, size;
1640 drv_info_t *drv;
1641 ctlr_info_t *info_p = hba[ctlr];
1642 int i;
1643
1644 info_p->log_drv_map = 0;
1645
1646 id_ldrive = kzalloc(sizeof(id_log_drv_t), GFP_KERNEL);
1647 if (!id_ldrive) {
1648 printk( KERN_ERR "cpqarray: out of memory.\n");
1649 goto err_0;
1650 }
1651
1652 id_ctlr_buf = kzalloc(sizeof(id_ctlr_t), GFP_KERNEL);
1653 if (!id_ctlr_buf) {
1654 printk( KERN_ERR "cpqarray: out of memory.\n");
1655 goto err_1;
1656 }
1657
1658 id_lstatus_buf = kzalloc(sizeof(sense_log_drv_stat_t), GFP_KERNEL);
1659 if (!id_lstatus_buf) {
1660 printk( KERN_ERR "cpqarray: out of memory.\n");
1661 goto err_2;
1662 }
1663
1664 sense_config_buf = kzalloc(sizeof(config_t), GFP_KERNEL);
1665 if (!sense_config_buf) {
1666 printk( KERN_ERR "cpqarray: out of memory.\n");
1667 goto err_3;
1668 }
1669
1670 info_p->phys_drives = 0;
1671 info_p->log_drv_map = 0;
1672 info_p->drv_assign_map = 0;
1673 info_p->drv_spare_map = 0;
1674 info_p->mp_failed_drv_map = 0; /* only initialized here */
1675 /* Get controllers info for this logical drive */
1676 ret_code = sendcmd(ID_CTLR, ctlr, id_ctlr_buf, 0, 0, 0, 0);
1677 if (ret_code == IO_ERROR) {
1678 /*
1679 * If can't get controller info, set the logical drive map to 0,
1680 * so the idastubopen will fail on all logical drives
1681 * on the controller.
1682 */
1683 printk(KERN_ERR "cpqarray: error sending ID controller\n");
1684 goto err_4;
1685 }
1686
1687 info_p->log_drives = id_ctlr_buf->nr_drvs;
1688 for(i=0;i<4;i++)
1689 info_p->firm_rev[i] = id_ctlr_buf->firm_rev[i];
1690 info_p->ctlr_sig = id_ctlr_buf->cfg_sig;
1691
1692 printk(" (%s)\n", info_p->product_name);
1693 /*
1694 * Initialize logical drive map to zero
1695 */
1696 log_index = 0;
1697 /*
1698 * Get drive geometry for all logical drives
1699 */
1700 if (id_ctlr_buf->nr_drvs > 16)
1701 printk(KERN_WARNING "cpqarray ida%d: This driver supports "
1702 "16 logical drives per controller.\n. "
1703 " Additional drives will not be "
1704 "detected\n", ctlr);
1705
1706 for (log_unit = 0;
1707 (log_index < id_ctlr_buf->nr_drvs)
1708 && (log_unit < NWD);
1709 log_unit++) {
1710 size = sizeof(sense_log_drv_stat_t);
1711
1712 /*
1713 Send "Identify logical drive status" cmd
1714 */
1715 ret_code = sendcmd(SENSE_LOG_DRV_STAT,
1716 ctlr, id_lstatus_buf, size, 0, 0, log_unit);
1717 if (ret_code == IO_ERROR) {
1718 /*
1719 If can't get logical drive status, set
1720 the logical drive map to 0, so the
1721 idastubopen will fail for all logical drives
1722 on the controller.
1723 */
1724 info_p->log_drv_map = 0;
1725 printk( KERN_WARNING
1726 "cpqarray ida%d: idaGetGeometry - Controller"
1727 " failed to report status of logical drive %d\n"
1728 "Access to this controller has been disabled\n",
1729 ctlr, log_unit);
1730 goto err_4;
1731 }
1732 /*
1733 Make sure the logical drive is configured
1734 */
1735 if (id_lstatus_buf->status != LOG_NOT_CONF) {
1736 ret_code = sendcmd(ID_LOG_DRV, ctlr, id_ldrive,
1737 sizeof(id_log_drv_t), 0, 0, log_unit);
1738 /*
1739 If error, the bit for this
1740 logical drive won't be set and
1741 idastubopen will return error.
1742 */
1743 if (ret_code != IO_ERROR) {
1744 drv = &info_p->drv[log_unit];
1745 drv->blk_size = id_ldrive->blk_size;
1746 drv->nr_blks = id_ldrive->nr_blks;
1747 drv->cylinders = id_ldrive->drv.cyl;
1748 drv->heads = id_ldrive->drv.heads;
1749 drv->sectors = id_ldrive->drv.sect_per_track;
1750 info_p->log_drv_map |= (1 << log_unit);
1751
1752 printk(KERN_INFO "cpqarray ida/c%dd%d: blksz=%d nr_blks=%d\n",
1753 ctlr, log_unit, drv->blk_size, drv->nr_blks);
1754 ret_code = sendcmd(SENSE_CONFIG,
1755 ctlr, sense_config_buf,
1756 sizeof(config_t), 0, 0, log_unit);
1757 if (ret_code == IO_ERROR) {
1758 info_p->log_drv_map = 0;
1759 printk(KERN_ERR "cpqarray: error sending sense config\n");
1760 goto err_4;
1761 }
1762
1763 info_p->phys_drives =
1764 sense_config_buf->ctlr_phys_drv;
1765 info_p->drv_assign_map
1766 |= sense_config_buf->drv_asgn_map;
1767 info_p->drv_assign_map
1768 |= sense_config_buf->spare_asgn_map;
1769 info_p->drv_spare_map
1770 |= sense_config_buf->spare_asgn_map;
1771 } /* end of if no error on id_ldrive */
1772 log_index = log_index + 1;
1773 } /* end of if logical drive configured */
1774 } /* end of for log_unit */
1775
1776 /* Free all the buffers and return */
1777 err_4:
1778 kfree(sense_config_buf);
1779 err_3:
1780 kfree(id_lstatus_buf);
1781 err_2:
1782 kfree(id_ctlr_buf);
1783 err_1:
1784 kfree(id_ldrive);
1785 err_0:
1786 return;
1787 }
1788
1789 static void __exit cpqarray_exit(void)
1790 {
1791 int i;
1792
1793 pci_unregister_driver(&cpqarray_pci_driver);
1794
1795 /* Double check that all controller entries have been removed */
1796 for(i=0; i<MAX_CTLR; i++) {
1797 if (hba[i] != NULL) {
1798 printk(KERN_WARNING "cpqarray: Removing EISA "
1799 "controller %d\n", i);
1800 cpqarray_remove_one_eisa(i);
1801 }
1802 }
1803
1804 remove_proc_entry("driver/cpqarray", NULL);
1805 }
1806
1807 module_init(cpqarray_init)
1808 module_exit(cpqarray_exit)
Nao low-level kernelspace/userspace library that runs on our robots, Nao-Team HTWK