kernel/2.6.29.6-aldebaran-rt/drivers/ata/pata_at32.c

   1 /*
   2  * AVR32 SMC/CFC PATA Driver
   3  *
   4  * Copyright (C) 2007 Atmel Norway
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License version
   8  * 2 as published by the Free Software Foundation.
   9  */
  10
  11 #define DEBUG
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/init.h>
  16 #include <linux/device.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/delay.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/irq.h>
  21 #include <scsi/scsi_host.h>
  22 #include <linux/ata.h>
  23 #include <linux/libata.h>
  24 #include <linux/err.h>
  25 #include <linux/io.h>
  26
  27 #include <mach/board.h>
  28 #include <mach/smc.h>
  29
  30 #define DRV_NAME "pata_at32"
  31 #define DRV_VERSION "0.0.3"
  32
  33 /*
  34  * CompactFlash controller memory layout relative to the base address:
  35  *
  36  *      Attribute memory:  0000 0000 -> 003f ffff
  37  *      Common memory:     0040 0000 -> 007f ffff
  38  *      I/O memory:        0080 0000 -> 00bf ffff
  39  *      True IDE Mode:     00c0 0000 -> 00df ffff
  40  *      Alt IDE Mode:      00e0 0000 -> 00ff ffff
  41  *
  42  * Only True IDE and Alt True IDE mode are needed for this driver.
  43  *
  44  *      True IDE mode     => CS0 = 0, CS1 = 1 (cmd, error, stat, etc)
  45  *      Alt True IDE mode => CS0 = 1, CS1 = 0 (ctl, alt_stat)
  46  */
  47 #define CF_IDE_OFFSET     0x00c00000
  48 #define CF_ALT_IDE_OFFSET 0x00e00000
  49 #define CF_RES_SIZE       2048
  50
  51 /*
  52  * Define DEBUG_BUS if you are doing debugging of your own EBI -> PATA
  53  * adaptor with a logic analyzer or similar.
  54  */
  55 #undef DEBUG_BUS
  56
  57 /*
  58  * ATA PIO modes
  59  *
  60  *      Name    | Mb/s  | Min cycle time | Mask
  61  *      --------+-------+----------------+--------
  62  *      Mode 0  | 3.3   | 600 ns         | 0x01
  63  *      Mode 1  | 5.2   | 383 ns         | 0x03
  64  *      Mode 2  | 8.3   | 240 ns         | 0x07
  65  *      Mode 3  | 11.1  | 180 ns         | 0x0f
  66  *      Mode 4  | 16.7  | 120 ns         | 0x1f
  67  *
  68  * Alter PIO_MASK below according to table to set maximal PIO mode.
  69  */
  70 #define PIO_MASK (0x1f)
  71
  72 /*
  73  * Struct containing private information about device.
  74  */
  75 struct at32_ide_info {
  76         unsigned int            irq;
  77         struct resource         res_ide;
  78         struct resource         res_alt;
  79         void __iomem            *ide_addr;
  80         void __iomem            *alt_addr;
  81         unsigned int            cs;
  82         struct smc_config       smc;
  83 };
  84
  85 /*
  86  * Setup SMC for the given ATA timing.
  87  */
  88 static int pata_at32_setup_timing(struct device *dev,
  89                                   struct at32_ide_info *info,
  90                                   const struct ata_timing *ata)
  91 {
  92         struct smc_config *smc = &info->smc;
  93         struct smc_timing timing;
  94
  95         int active;
  96         int recover;
  97
  98         memset(&timing, 0, sizeof(struct smc_timing));
  99
 100         /* Total cycle time */
 101         timing.read_cycle  = ata->cyc8b;
 102
 103         /* DIOR <= CFIOR timings */
 104         timing.nrd_setup   = ata->setup;
 105         timing.nrd_pulse   = ata->act8b;
 106         timing.nrd_recover = ata->rec8b;
 107
 108         /* Convert nanosecond timing to clock cycles */
 109         smc_set_timing(smc, &timing);
 110
 111         /* Add one extra cycle setup due to signal ring */
 112         smc->nrd_setup = smc->nrd_setup + 1;
 113
 114         active  = smc->nrd_setup + smc->nrd_pulse;
 115         recover = smc->read_cycle - active;
 116
 117         /* Need at least two cycles recovery */
 118         if (recover < 2)
 119           smc->read_cycle = active + 2;
 120
 121         /* (CS0, CS1, DIR, OE) <= (CFCE1, CFCE2, CFRNW, NCSX) timings */
 122         smc->ncs_read_setup = 1;
 123         smc->ncs_read_pulse = smc->read_cycle - 2;
 124
 125         /* Write timings same as read timings */
 126         smc->write_cycle = smc->read_cycle;
 127         smc->nwe_setup = smc->nrd_setup;
 128         smc->nwe_pulse = smc->nrd_pulse;
 129         smc->ncs_write_setup = smc->ncs_read_setup;
 130         smc->ncs_write_pulse = smc->ncs_read_pulse;
 131
 132         /* Do some debugging output of ATA and SMC timings */
 133         dev_dbg(dev, "ATA: C=%d S=%d P=%d R=%d\n",
 134                 ata->cyc8b, ata->setup, ata->act8b, ata->rec8b);
 135
 136         dev_dbg(dev, "SMC: C=%d S=%d P=%d NS=%d NP=%d\n",
 137                 smc->read_cycle, smc->nrd_setup, smc->nrd_pulse,
 138                 smc->ncs_read_setup, smc->ncs_read_pulse);
 139
 140         /* Finally, configure the SMC */
 141         return smc_set_configuration(info->cs, smc);
 142 }
 143
 144 /*
 145  * Procedures for libATA.
 146  */
 147 static void pata_at32_set_piomode(struct ata_port *ap, struct ata_device *adev)
 148 {
 149         struct ata_timing timing;
 150         struct at32_ide_info *info = ap->host->private_data;
 151
 152         int ret;
 153
 154         /* Compute ATA timing */
 155         ret = ata_timing_compute(adev, adev->pio_mode, &timing, 1000, 0);
 156         if (ret) {
 157                 dev_warn(ap->dev, "Failed to compute ATA timing %d\n", ret);
 158                 return;
 159         }
 160
 161         /* Setup SMC to ATA timing */
 162         ret = pata_at32_setup_timing(ap->dev, info, &timing);
 163         if (ret) {
 164                 dev_warn(ap->dev, "Failed to setup ATA timing %d\n", ret);
 165                 return;
 166         }
 167 }
 168
 169 static struct scsi_host_template at32_sht = {
 170         ATA_PIO_SHT(DRV_NAME),
 171 };
 172
 173 static struct ata_port_operations at32_port_ops = {
 174         .inherits               = &ata_sff_port_ops,
 175         .cable_detect           = ata_cable_40wire,
 176         .set_piomode            = pata_at32_set_piomode,
 177 };
 178
 179 static int __init pata_at32_init_one(struct device *dev,
 180                                      struct at32_ide_info *info)
 181 {
 182         struct ata_host *host;
 183         struct ata_port *ap;
 184
 185         host = ata_host_alloc(dev, 1);
 186         if (!host)
 187                 return -ENOMEM;
 188
 189         ap = host->ports[0];
 190
 191         /* Setup ATA bindings */
 192         ap->ops      = &at32_port_ops;
 193         ap->pio_mask = PIO_MASK;
 194         ap->flags   |= ATA_FLAG_MMIO | ATA_FLAG_SLAVE_POSS;
 195
 196         /*
 197          * Since all 8-bit taskfile transfers has to go on the lower
 198          * byte of the data bus and there is a bug in the SMC that
 199          * makes it impossible to alter the bus width during runtime,
 200          * we need to hardwire the address signals as follows:
 201          *
 202          *      A_IDE(2:0) <= A_EBI(3:1)
 203          *
 204          * This makes all addresses on the EBI even, thus all data
 205          * will be on the lower byte of the data bus.  All addresses
 206          * used by libATA need to be altered according to this.
 207          */
 208         ap->ioaddr.altstatus_addr = info->alt_addr + (0x06 << 1);
 209         ap->ioaddr.ctl_addr       = info->alt_addr + (0x06 << 1);
 210
 211         ap->ioaddr.data_addr      = info->ide_addr + (ATA_REG_DATA << 1);
 212         ap->ioaddr.error_addr     = info->ide_addr + (ATA_REG_ERR << 1);
 213         ap->ioaddr.feature_addr   = info->ide_addr + (ATA_REG_FEATURE << 1);
 214         ap->ioaddr.nsect_addr     = info->ide_addr + (ATA_REG_NSECT << 1);
 215         ap->ioaddr.lbal_addr      = info->ide_addr + (ATA_REG_LBAL << 1);
 216         ap->ioaddr.lbam_addr      = info->ide_addr + (ATA_REG_LBAM << 1);
 217         ap->ioaddr.lbah_addr      = info->ide_addr + (ATA_REG_LBAH << 1);
 218         ap->ioaddr.device_addr    = info->ide_addr + (ATA_REG_DEVICE << 1);
 219         ap->ioaddr.status_addr    = info->ide_addr + (ATA_REG_STATUS << 1);
 220         ap->ioaddr.command_addr   = info->ide_addr + (ATA_REG_CMD << 1);
 221
 222         /* Set info as private data of ATA host */
 223         host->private_data = info;
 224
 225         /* Register ATA device and return */
 226         return ata_host_activate(host, info->irq, ata_sff_interrupt,
 227                                  IRQF_SHARED | IRQF_TRIGGER_RISING,
 228                                  &at32_sht);
 229 }
 230
 231 /*
 232  * This function may come in handy for people analyzing their own
 233  * EBI -> PATA adaptors.
 234  */
 235 #ifdef DEBUG_BUS
 236
 237 static void __init pata_at32_debug_bus(struct device *dev,
 238                                        struct at32_ide_info *info)
 239 {
 240         const int d1 = 0xff;
 241         const int d2 = 0x00;
 242
 243         int i;
 244
 245         /* Write 8-bit values (registers) */
 246         iowrite8(d1, info->alt_addr + (0x06 << 1));
 247         iowrite8(d2, info->alt_addr + (0x06 << 1));
 248
 249         for (i = 0; i < 8; i++) {
 250                 iowrite8(d1, info->ide_addr + (i << 1));
 251                 iowrite8(d2, info->ide_addr + (i << 1));
 252         }
 253
 254         /* Write 16 bit values (data) */
 255         iowrite16(d1,      info->ide_addr);
 256         iowrite16(d1 << 8, info->ide_addr);
 257
 258         iowrite16(d1,      info->ide_addr);
 259         iowrite16(d1 << 8, info->ide_addr);
 260 }
 261
 262 #endif
 263
 264 static int __init pata_at32_probe(struct platform_device *pdev)
 265 {
 266         const struct ata_timing initial_timing =
 267                 {XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0};
 268
 269         struct device            *dev = &pdev->dev;
 270         struct at32_ide_info     *info;
 271         struct ide_platform_data *board = pdev->dev.platform_data;
 272         struct resource          *res;
 273
 274         int irq;
 275         int ret;
 276
 277         if (!board)
 278                 return -ENXIO;
 279
 280         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 281         if (!res)
 282                 return -ENXIO;
 283
 284         /* Retrive IRQ */
 285         irq = platform_get_irq(pdev, 0);
 286         if (irq < 0)
 287                 return irq;
 288
 289         /* Setup struct containing private information */
 290         info = kzalloc(sizeof(struct at32_ide_info), GFP_KERNEL);
 291         if (!info)
 292                 return -ENOMEM;
 293
 294         info->irq = irq;
 295         info->cs  = board->cs;
 296
 297         /* Request memory resources */
 298         info->res_ide.start = res->start + CF_IDE_OFFSET;
 299         info->res_ide.end   = info->res_ide.start + CF_RES_SIZE - 1;
 300         info->res_ide.name  = "ide";
 301         info->res_ide.flags = IORESOURCE_MEM;
 302
 303         ret = request_resource(res, &info->res_ide);
 304         if (ret)
 305                 goto err_req_res_ide;
 306
 307         info->res_alt.start = res->start + CF_ALT_IDE_OFFSET;
 308         info->res_alt.end   = info->res_alt.start + CF_RES_SIZE - 1;
 309         info->res_alt.name  = "alt";
 310         info->res_alt.flags = IORESOURCE_MEM;
 311
 312         ret = request_resource(res, &info->res_alt);
 313         if (ret)
 314                 goto err_req_res_alt;
 315
 316         /* Setup non-timing elements of SMC */
 317         info->smc.bus_width      = 2; /* 16 bit data bus */
 318         info->smc.nrd_controlled = 1; /* Sample data on rising edge of NRD */
 319         info->smc.nwe_controlled = 0; /* Drive data on falling edge of NCS */
 320         info->smc.nwait_mode     = 3; /* NWAIT is in READY mode */
 321         info->smc.byte_write     = 0; /* Byte select access type */
 322         info->smc.tdf_mode       = 0; /* TDF optimization disabled */
 323         info->smc.tdf_cycles     = 0; /* No TDF wait cycles */
 324
 325         /* Setup SMC to ATA timing */
 326         ret = pata_at32_setup_timing(dev, info, &initial_timing);
 327         if (ret)
 328                 goto err_setup_timing;
 329
 330         /* Map ATA address space */
 331         ret = -ENOMEM;
 332         info->ide_addr = devm_ioremap(dev, info->res_ide.start, 16);
 333         info->alt_addr = devm_ioremap(dev, info->res_alt.start, 16);
 334         if (!info->ide_addr || !info->alt_addr)
 335                 goto err_ioremap;
 336
 337 #ifdef DEBUG_BUS
 338         pata_at32_debug_bus(dev, info);
 339 #endif
 340
 341         /* Setup and register ATA device */
 342         ret = pata_at32_init_one(dev, info);
 343         if (ret)
 344                 goto err_ata_device;
 345
 346         return 0;
 347
 348  err_ata_device:
 349  err_ioremap:
 350  err_setup_timing:
 351         release_resource(&info->res_alt);
 352  err_req_res_alt:
 353         release_resource(&info->res_ide);
 354  err_req_res_ide:
 355         kfree(info);
 356
 357         return ret;
 358 }
 359
 360 static int __exit pata_at32_remove(struct platform_device *pdev)
 361 {
 362         struct ata_host *host = platform_get_drvdata(pdev);
 363         struct at32_ide_info *info;
 364
 365         if (!host)
 366                 return 0;
 367
 368         info = host->private_data;
 369         ata_host_detach(host);
 370
 371         if (!info)
 372                 return 0;
 373
 374         release_resource(&info->res_ide);
 375         release_resource(&info->res_alt);
 376
 377         kfree(info);
 378
 379         return 0;
 380 }
 381
 382 /* work with hotplug and coldplug */
 383 MODULE_ALIAS("platform:at32_ide");
 384
 385 static struct platform_driver pata_at32_driver = {
 386         .remove        = __exit_p(pata_at32_remove),
 387         .driver        = {
 388                 .name  = "at32_ide",
 389                 .owner = THIS_MODULE,
 390         },
 391 };
 392
 393 static int __init pata_at32_init(void)
 394 {
 395         return platform_driver_probe(&pata_at32_driver, pata_at32_probe);
 396 }
 397
 398 static void __exit pata_at32_exit(void)
 399 {
 400         platform_driver_unregister(&pata_at32_driver);
 401 }
 402
 403 module_init(pata_at32_init);
 404 module_exit(pata_at32_exit);
 405
 406 MODULE_LICENSE("GPL");
 407 MODULE_DESCRIPTION("AVR32 SMC/CFC PATA Driver");
 408 MODULE_AUTHOR("Kristoffer Nyborg Gregertsen <kngregertsen@norway.atmel.com>");
 409 MODULE_VERSION(DRV_VERSION);