kernel/2.6.29.6-aldebaran-rt/arch/x86/oprofile/nmi_int.c

   1 /**
   2  * @file nmi_int.c
   3  *
   4  * @remark Copyright 2002-2008 OProfile authors
   5  * @remark Read the file COPYING
   6  *
   7  * @author John Levon <levon@movementarian.org>
   8  * @author Robert Richter <robert.richter@amd.com>
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/notifier.h>
  13 #include <linux/smp.h>
  14 #include <linux/oprofile.h>
  15 #include <linux/sysdev.h>
  16 #include <linux/slab.h>
  17 #include <linux/moduleparam.h>
  18 #include <linux/kdebug.h>
  19 #include <linux/cpu.h>
  20 #include <asm/nmi.h>
  21 #include <asm/msr.h>
  22 #include <asm/apic.h>
  23
  24 #include "op_counter.h"
  25 #include "op_x86_model.h"
  26
  27 static struct op_x86_model_spec const *model;
  28 static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
  29 static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
  30
  31 /* 0 == registered but off, 1 == registered and on */
  32 static int nmi_enabled = 0;
  33
  34 static int profile_exceptions_notify(struct notifier_block *self,
  35                                      unsigned long val, void *data)
  36 {
  37         struct die_args *args = (struct die_args *)data;
  38         int ret = NOTIFY_DONE;
  39         int cpu = smp_processor_id();
  40
  41         switch (val) {
  42         case DIE_NMI:
  43         case DIE_NMI_IPI:
  44                 model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu));
  45                 ret = NOTIFY_STOP;
  46                 break;
  47         default:
  48                 break;
  49         }
  50         return ret;
  51 }
  52
  53 static void nmi_cpu_save_registers(struct op_msrs *msrs)
  54 {
  55         unsigned int const nr_ctrs = model->num_counters;
  56         unsigned int const nr_ctrls = model->num_controls;
  57         struct op_msr *counters = msrs->counters;
  58         struct op_msr *controls = msrs->controls;
  59         unsigned int i;
  60
  61         for (i = 0; i < nr_ctrs; ++i) {
  62                 if (counters[i].addr) {
  63                         rdmsr(counters[i].addr,
  64                                 counters[i].saved.low,
  65                                 counters[i].saved.high);
  66                 }
  67         }
  68
  69         for (i = 0; i < nr_ctrls; ++i) {
  70                 if (controls[i].addr) {
  71                         rdmsr(controls[i].addr,
  72                                 controls[i].saved.low,
  73                                 controls[i].saved.high);
  74                 }
  75         }
  76 }
  77
  78 static void nmi_save_registers(void *dummy)
  79 {
  80         int cpu = smp_processor_id();
  81         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
  82         nmi_cpu_save_registers(msrs);
  83 }
  84
  85 static void free_msrs(void)
  86 {
  87         int i;
  88         for_each_possible_cpu(i) {
  89                 kfree(per_cpu(cpu_msrs, i).counters);
  90                 per_cpu(cpu_msrs, i).counters = NULL;
  91                 kfree(per_cpu(cpu_msrs, i).controls);
  92                 per_cpu(cpu_msrs, i).controls = NULL;
  93         }
  94 }
  95
  96 static int allocate_msrs(void)
  97 {
  98         int success = 1;
  99         size_t controls_size = sizeof(struct op_msr) * model->num_controls;
 100         size_t counters_size = sizeof(struct op_msr) * model->num_counters;
 101
 102         int i;
 103         for_each_possible_cpu(i) {
 104                 per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
 105                                                                 GFP_KERNEL);
 106                 if (!per_cpu(cpu_msrs, i).counters) {
 107                         success = 0;
 108                         break;
 109                 }
 110                 per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
 111                                                                 GFP_KERNEL);
 112                 if (!per_cpu(cpu_msrs, i).controls) {
 113                         success = 0;
 114                         break;
 115                 }
 116         }
 117
 118         if (!success)
 119                 free_msrs();
 120
 121         return success;
 122 }
 123
 124 static void nmi_cpu_setup(void *dummy)
 125 {
 126         int cpu = smp_processor_id();
 127         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 128         spin_lock(&oprofilefs_lock);
 129         model->setup_ctrs(msrs);
 130         spin_unlock(&oprofilefs_lock);
 131         per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
 132         apic_write(APIC_LVTPC, APIC_DM_NMI);
 133 }
 134
 135 static struct notifier_block profile_exceptions_nb = {
 136         .notifier_call = profile_exceptions_notify,
 137         .next = NULL,
 138         .priority = 2
 139 };
 140
 141 static int nmi_setup(void)
 142 {
 143         int err = 0;
 144         int cpu;
 145
 146         if (!allocate_msrs())
 147                 return -ENOMEM;
 148
 149         err = register_die_notifier(&profile_exceptions_nb);
 150         if (err) {
 151                 free_msrs();
 152                 return err;
 153         }
 154
 155         /* We need to serialize save and setup for HT because the subset
 156          * of msrs are distinct for save and setup operations
 157          */
 158
 159         /* Assume saved/restored counters are the same on all CPUs */
 160         model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
 161         for_each_possible_cpu(cpu) {
 162                 if (cpu != 0) {
 163                         memcpy(per_cpu(cpu_msrs, cpu).counters,
 164                                 per_cpu(cpu_msrs, 0).counters,
 165                                 sizeof(struct op_msr) * model->num_counters);
 166
 167                         memcpy(per_cpu(cpu_msrs, cpu).controls,
 168                                 per_cpu(cpu_msrs, 0).controls,
 169                                 sizeof(struct op_msr) * model->num_controls);
 170                 }
 171
 172         }
 173         on_each_cpu(nmi_save_registers, NULL, 1);
 174         on_each_cpu(nmi_cpu_setup, NULL, 1);
 175         nmi_enabled = 1;
 176         return 0;
 177 }
 178
 179 static void nmi_restore_registers(struct op_msrs *msrs)
 180 {
 181         unsigned int const nr_ctrs = model->num_counters;
 182         unsigned int const nr_ctrls = model->num_controls;
 183         struct op_msr *counters = msrs->counters;
 184         struct op_msr *controls = msrs->controls;
 185         unsigned int i;
 186
 187         for (i = 0; i < nr_ctrls; ++i) {
 188                 if (controls[i].addr) {
 189                         wrmsr(controls[i].addr,
 190                                 controls[i].saved.low,
 191                                 controls[i].saved.high);
 192                 }
 193         }
 194
 195         for (i = 0; i < nr_ctrs; ++i) {
 196                 if (counters[i].addr) {
 197                         wrmsr(counters[i].addr,
 198                                 counters[i].saved.low,
 199                                 counters[i].saved.high);
 200                 }
 201         }
 202 }
 203
 204 static void nmi_cpu_shutdown(void *dummy)
 205 {
 206         unsigned int v;
 207         int cpu = smp_processor_id();
 208         struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);
 209
 210         /* restoring APIC_LVTPC can trigger an apic error because the delivery
 211          * mode and vector nr combination can be illegal. That's by design: on
 212          * power on apic lvt contain a zero vector nr which are legal only for
 213          * NMI delivery mode. So inhibit apic err before restoring lvtpc
 214          */
 215         v = apic_read(APIC_LVTERR);
 216         apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
 217         apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
 218         apic_write(APIC_LVTERR, v);
 219         nmi_restore_registers(msrs);
 220 }
 221
 222 static void nmi_shutdown(void)
 223 {
 224         struct op_msrs *msrs;
 225
 226         nmi_enabled = 0;
 227         on_each_cpu(nmi_cpu_shutdown, NULL, 1);
 228         unregister_die_notifier(&profile_exceptions_nb);
 229         msrs = &get_cpu_var(cpu_msrs);
 230         model->shutdown(msrs);
 231         free_msrs();
 232         put_cpu_var(cpu_msrs);
 233 }
 234
 235 static void nmi_cpu_start(void *dummy)
 236 {
 237         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
 238         model->start(msrs);
 239 }
 240
 241 static int nmi_start(void)
 242 {
 243         on_each_cpu(nmi_cpu_start, NULL, 1);
 244         return 0;
 245 }
 246
 247 static void nmi_cpu_stop(void *dummy)
 248 {
 249         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
 250         model->stop(msrs);
 251 }
 252
 253 static void nmi_stop(void)
 254 {
 255         on_each_cpu(nmi_cpu_stop, NULL, 1);
 256 }
 257
 258 struct op_counter_config counter_config[OP_MAX_COUNTER];
 259
 260 static int nmi_create_files(struct super_block *sb, struct dentry *root)
 261 {
 262         unsigned int i;
 263
 264         for (i = 0; i < model->num_counters; ++i) {
 265                 struct dentry *dir;
 266                 char buf[4];
 267
 268                 /* quick little hack to _not_ expose a counter if it is not
 269                  * available for use.  This should protect userspace app.
 270                  * NOTE:  assumes 1:1 mapping here (that counters are organized
 271                  *        sequentially in their struct assignment).
 272                  */
 273                 if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
 274                         continue;
 275
 276                 snprintf(buf,  sizeof(buf), "%d", i);
 277                 dir = oprofilefs_mkdir(sb, root, buf);
 278                 oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
 279                 oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
 280                 oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
 281                 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
 282                 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
 283                 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
 284         }
 285
 286         return 0;
 287 }
 288
 289 #ifdef CONFIG_SMP
 290 static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
 291                                  void *data)
 292 {
 293         int cpu = (unsigned long)data;
 294         switch (action) {
 295         case CPU_DOWN_FAILED:
 296         case CPU_ONLINE:
 297                 smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
 298                 break;
 299         case CPU_DOWN_PREPARE:
 300                 smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
 301                 break;
 302         }
 303         return NOTIFY_DONE;
 304 }
 305
 306 static struct notifier_block oprofile_cpu_nb = {
 307         .notifier_call = oprofile_cpu_notifier
 308 };
 309 #endif
 310
 311 #ifdef CONFIG_PM
 312
 313 static int nmi_suspend(struct sys_device *dev, pm_message_t state)
 314 {
 315         /* Only one CPU left, just stop that one */
 316         if (nmi_enabled == 1)
 317                 nmi_cpu_stop(NULL);
 318         return 0;
 319 }
 320
 321 static int nmi_resume(struct sys_device *dev)
 322 {
 323         if (nmi_enabled == 1)
 324                 nmi_cpu_start(NULL);
 325         return 0;
 326 }
 327
 328 static struct sysdev_class oprofile_sysclass = {
 329         .name           = "oprofile",
 330         .resume         = nmi_resume,
 331         .suspend        = nmi_suspend,
 332 };
 333
 334 static struct sys_device device_oprofile = {
 335         .id     = 0,
 336         .cls    = &oprofile_sysclass,
 337 };
 338
 339 static int __init init_sysfs(void)
 340 {
 341         int error;
 342
 343         error = sysdev_class_register(&oprofile_sysclass);
 344         if (!error)
 345                 error = sysdev_register(&device_oprofile);
 346         return error;
 347 }
 348
 349 static void exit_sysfs(void)
 350 {
 351         sysdev_unregister(&device_oprofile);
 352         sysdev_class_unregister(&oprofile_sysclass);
 353 }
 354
 355 #else
 356 #define init_sysfs() do { } while (0)
 357 #define exit_sysfs() do { } while (0)
 358 #endif /* CONFIG_PM */
 359
 360 static int p4force;
 361 module_param(p4force, int, 0);
 362
 363 static int __init p4_init(char **cpu_type)
 364 {
 365         __u8 cpu_model = boot_cpu_data.x86_model;
 366
 367         if (!p4force && (cpu_model > 6 || cpu_model == 5))
 368                 return 0;
 369
 370 #ifndef CONFIG_SMP
 371         *cpu_type = "i386/p4";
 372         model = &op_p4_spec;
 373         return 1;
 374 #else
 375         switch (smp_num_siblings) {
 376         case 1:
 377                 *cpu_type = "i386/p4";
 378                 model = &op_p4_spec;
 379                 return 1;
 380
 381         case 2:
 382                 *cpu_type = "i386/p4-ht";
 383                 model = &op_p4_ht2_spec;
 384                 return 1;
 385         }
 386 #endif
 387
 388         printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
 389         printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
 390         return 0;
 391 }
 392
 393 static int __init ppro_init(char **cpu_type)
 394 {
 395         __u8 cpu_model = boot_cpu_data.x86_model;
 396
 397         switch (cpu_model) {
 398         case 0 ... 2:
 399                 *cpu_type = "i386/ppro";
 400                 break;
 401         case 3 ... 5:
 402                 *cpu_type = "i386/pii";
 403                 break;
 404         case 6 ... 8:
 405         case 10 ... 11:
 406                 *cpu_type = "i386/piii";
 407                 break;
 408         case 9:
 409         case 13:
 410                 *cpu_type = "i386/p6_mobile";
 411                 break;
 412         case 14:
 413                 *cpu_type = "i386/core";
 414                 break;
 415         case 15: case 23:
 416                 *cpu_type = "i386/core_2";
 417                 break;
 418         default:
 419                 /* Unknown */
 420                 return 0;
 421         }
 422
 423         model = &op_ppro_spec;
 424         return 1;
 425 }
 426
 427 static int __init arch_perfmon_init(char **cpu_type)
 428 {
 429         if (!cpu_has_arch_perfmon)
 430                 return 0;
 431         *cpu_type = "i386/arch_perfmon";
 432         model = &op_arch_perfmon_spec;
 433         arch_perfmon_setup_counters();
 434         return 1;
 435 }
 436
 437 /* in order to get sysfs right */
 438 static int using_nmi;
 439
 440 int __init op_nmi_init(struct oprofile_operations *ops)
 441 {
 442         __u8 vendor = boot_cpu_data.x86_vendor;
 443         __u8 family = boot_cpu_data.x86;
 444         char *cpu_type = NULL;
 445         int ret = 0;
 446
 447         if (!cpu_has_apic)
 448                 return -ENODEV;
 449
 450         switch (vendor) {
 451         case X86_VENDOR_AMD:
 452                 /* Needs to be at least an Athlon (or hammer in 32bit mode) */
 453
 454                 switch (family) {
 455                 default:
 456                         return -ENODEV;
 457                 case 6:
 458                         model = &op_amd_spec;
 459                         cpu_type = "i386/athlon";
 460                         break;
 461                 case 0xf:
 462                         model = &op_amd_spec;
 463                         /* Actually it could be i386/hammer too, but give
 464                          user space an consistent name. */
 465                         cpu_type = "x86-64/hammer";
 466                         break;
 467                 case 0x10:
 468                         model = &op_amd_spec;
 469                         cpu_type = "x86-64/family10";
 470                         break;
 471                 case 0x11:
 472                         model = &op_amd_spec;
 473                         cpu_type = "x86-64/family11h";
 474                         break;
 475                 }
 476                 break;
 477
 478         case X86_VENDOR_INTEL:
 479                 switch (family) {
 480                         /* Pentium IV */
 481                 case 0xf:
 482                         p4_init(&cpu_type);
 483                         break;
 484
 485                         /* A P6-class processor */
 486                 case 6:
 487                         ppro_init(&cpu_type);
 488                         break;
 489
 490                 default:
 491                         break;
 492                 }
 493
 494                 if (!cpu_type && !arch_perfmon_init(&cpu_type))
 495                         return -ENODEV;
 496                 break;
 497
 498         default:
 499                 return -ENODEV;
 500         }
 501
 502 #ifdef CONFIG_SMP
 503         register_cpu_notifier(&oprofile_cpu_nb);
 504 #endif
 505         /* default values, can be overwritten by model */
 506         ops->create_files = nmi_create_files;
 507         ops->setup = nmi_setup;
 508         ops->shutdown = nmi_shutdown;
 509         ops->start = nmi_start;
 510         ops->stop = nmi_stop;
 511         ops->cpu_type = cpu_type;
 512
 513         if (model->init)
 514                 ret = model->init(ops);
 515         if (ret)
 516                 return ret;
 517
 518         init_sysfs();
 519         using_nmi = 1;
 520         printk(KERN_INFO "oprofile: using NMI interrupt.\n");
 521         return 0;
 522 }
 523
 524 void op_nmi_exit(void)
 525 {
 526         if (using_nmi) {
 527                 exit_sysfs();
 528 #ifdef CONFIG_SMP
 529                 unregister_cpu_notifier(&oprofile_cpu_nb);
 530 #endif
 531         }
 532         if (model->exit)
 533                 model->exit();
 534 }