kernel/2.6.29.6-aldebaran-rt/arch/sh/kernel/cpu/sh4/probe.c

   1 /*
   2  * arch/sh/kernel/cpu/sh4/probe.c
   3  *
   4  * CPU Subtype Probing for SH-4.
   5  *
   6  * Copyright (C) 2001 - 2007  Paul Mundt
   7  * Copyright (C) 2003  Richard Curnow
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License.  See the file "COPYING" in the main directory of this archive
  11  * for more details.
  12  */
  13 #include <linux/init.h>
  14 #include <linux/io.h>
  15 #include <asm/processor.h>
  16 #include <asm/cache.h>
  17
  18 int __init detect_cpu_and_cache_system(void)
  19 {
  20         unsigned long pvr, prr, cvr;
  21         unsigned long size;
  22
  23         static unsigned long sizes[16] = {
  24                 [1] = (1 << 12),
  25                 [2] = (1 << 13),
  26                 [4] = (1 << 14),
  27                 [8] = (1 << 15),
  28                 [9] = (1 << 16)
  29         };
  30
  31         pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffffff;
  32         prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff;
  33         cvr = (ctrl_inl(CCN_CVR));
  34
  35         /*
  36          * Setup some sane SH-4 defaults for the icache
  37          */
  38         boot_cpu_data.icache.way_incr           = (1 << 13);
  39         boot_cpu_data.icache.entry_shift        = 5;
  40         boot_cpu_data.icache.sets               = 256;
  41         boot_cpu_data.icache.ways               = 1;
  42         boot_cpu_data.icache.linesz             = L1_CACHE_BYTES;
  43
  44         /*
  45          * And again for the dcache ..
  46          */
  47         boot_cpu_data.dcache.way_incr           = (1 << 14);
  48         boot_cpu_data.dcache.entry_shift        = 5;
  49         boot_cpu_data.dcache.sets               = 512;
  50         boot_cpu_data.dcache.ways               = 1;
  51         boot_cpu_data.dcache.linesz             = L1_CACHE_BYTES;
  52
  53         /* We don't know the chip cut */
  54         boot_cpu_data.cut_major = boot_cpu_data.cut_minor = -1;
  55
  56         /*
  57          * Setup some generic flags we can probe on SH-4A parts
  58          */
  59         if (((pvr >> 16) & 0xff) == 0x10) {
  60                 if ((cvr & 0x10000000) == 0)
  61                         boot_cpu_data.flags |= CPU_HAS_DSP;
  62
  63                 boot_cpu_data.flags |= CPU_HAS_LLSC;
  64                 boot_cpu_data.cut_major = pvr & 0x7f;
  65         }
  66
  67         /* FPU detection works for everyone */
  68         if ((cvr & 0x20000000) == 1)
  69                 boot_cpu_data.flags |= CPU_HAS_FPU;
  70
  71         /* Mask off the upper chip ID */
  72         pvr &= 0xffff;
  73
  74         /*
  75          * Probe the underlying processor version/revision and
  76          * adjust cpu_data setup accordingly.
  77          */
  78         switch (pvr) {
  79         case 0x205:
  80                 boot_cpu_data.type = CPU_SH7750;
  81                 boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
  82                                    CPU_HAS_PERF_COUNTER;
  83                 break;
  84         case 0x206:
  85                 boot_cpu_data.type = CPU_SH7750S;
  86                 boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
  87                                    CPU_HAS_PERF_COUNTER;
  88                 break;
  89         case 0x1100:
  90                 boot_cpu_data.type = CPU_SH7751;
  91                 boot_cpu_data.flags |= CPU_HAS_FPU;
  92                 break;
  93         case 0x2001:
  94         case 0x2004:
  95                 boot_cpu_data.type = CPU_SH7770;
  96                 boot_cpu_data.icache.ways = 4;
  97                 boot_cpu_data.dcache.ways = 4;
  98
  99                 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
 100                 break;
 101         case 0x2006:
 102         case 0x200A:
 103                 if (prr == 0x61)
 104                         boot_cpu_data.type = CPU_SH7781;
 105                 else if (prr == 0xa1)
 106                         boot_cpu_data.type = CPU_SH7763;
 107                 else
 108                         boot_cpu_data.type = CPU_SH7780;
 109
 110                 boot_cpu_data.icache.ways = 4;
 111                 boot_cpu_data.dcache.ways = 4;
 112
 113                 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
 114                                    CPU_HAS_LLSC;
 115                 break;
 116         case 0x3000:
 117         case 0x3003:
 118         case 0x3009:
 119                 boot_cpu_data.type = CPU_SH7343;
 120                 boot_cpu_data.icache.ways = 4;
 121                 boot_cpu_data.dcache.ways = 4;
 122                 boot_cpu_data.flags |= CPU_HAS_LLSC;
 123                 break;
 124         case 0x3004:
 125         case 0x3007:
 126                 boot_cpu_data.type = CPU_SH7785;
 127                 boot_cpu_data.icache.ways = 4;
 128                 boot_cpu_data.dcache.ways = 4;
 129                 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
 130                                           CPU_HAS_LLSC;
 131                 break;
 132         case 0x3008:
 133                 boot_cpu_data.icache.ways = 4;
 134                 boot_cpu_data.dcache.ways = 4;
 135                 boot_cpu_data.flags |= CPU_HAS_LLSC;
 136
 137                 switch (prr) {
 138                 case 0x50:
 139                 case 0x51:
 140                         boot_cpu_data.type = CPU_SH7723;
 141                         boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_L2_CACHE;
 142                         break;
 143                 case 0x70:
 144                         boot_cpu_data.type = CPU_SH7366;
 145                         break;
 146                 case 0xa0:
 147                 case 0xa1:
 148                         boot_cpu_data.type = CPU_SH7722;
 149                         break;
 150                 }
 151                 break;
 152         case 0x4000:    /* 1st cut */
 153         case 0x4001:    /* 2nd cut */
 154                 boot_cpu_data.type = CPU_SHX3;
 155                 boot_cpu_data.icache.ways = 4;
 156                 boot_cpu_data.dcache.ways = 4;
 157                 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
 158                                           CPU_HAS_LLSC;
 159                 break;
 160         case 0x700:
 161                 boot_cpu_data.type = CPU_SH4_501;
 162                 boot_cpu_data.icache.ways = 2;
 163                 boot_cpu_data.dcache.ways = 2;
 164                 break;
 165         case 0x600:
 166                 boot_cpu_data.type = CPU_SH4_202;
 167                 boot_cpu_data.icache.ways = 2;
 168                 boot_cpu_data.dcache.ways = 2;
 169                 boot_cpu_data.flags |= CPU_HAS_FPU;
 170                 break;
 171         case 0x500 ... 0x501:
 172                 switch (prr) {
 173                 case 0x10:
 174                         boot_cpu_data.type = CPU_SH7750R;
 175                         break;
 176                 case 0x11:
 177                         boot_cpu_data.type = CPU_SH7751R;
 178                         break;
 179                 case 0x50 ... 0x5f:
 180                         boot_cpu_data.type = CPU_SH7760;
 181                         break;
 182                 }
 183
 184                 boot_cpu_data.icache.ways = 2;
 185                 boot_cpu_data.dcache.ways = 2;
 186
 187                 boot_cpu_data.flags |= CPU_HAS_FPU;
 188
 189                 break;
 190         default:
 191                 boot_cpu_data.type = CPU_SH_NONE;
 192                 break;
 193         }
 194
 195 #ifdef CONFIG_SH_DIRECT_MAPPED
 196         boot_cpu_data.icache.ways = 1;
 197         boot_cpu_data.dcache.ways = 1;
 198 #endif
 199
 200 #ifdef CONFIG_CPU_HAS_PTEA
 201         boot_cpu_data.flags |= CPU_HAS_PTEA;
 202 #endif
 203
 204         /*
 205          * On anything that's not a direct-mapped cache, look to the CVR
 206          * for I/D-cache specifics.
 207          */
 208         if (boot_cpu_data.icache.ways > 1) {
 209                 size = sizes[(cvr >> 20) & 0xf];
 210                 boot_cpu_data.icache.way_incr   = (size >> 1);
 211                 boot_cpu_data.icache.sets       = (size >> 6);
 212
 213         }
 214
 215         /* And the rest of the D-cache */
 216         if (boot_cpu_data.dcache.ways > 1) {
 217                 size = sizes[(cvr >> 16) & 0xf];
 218                 boot_cpu_data.dcache.way_incr   = (size >> 1);
 219                 boot_cpu_data.dcache.sets       = (size >> 6);
 220         }
 221
 222         /*
 223          * Setup the L2 cache desc
 224          *
 225          * SH-4A's have an optional PIPT L2.
 226          */
 227         if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
 228                 /* Bug if we can't decode the L2 info */
 229                 BUG_ON(!(cvr & 0xf));
 230
 231                 /* Silicon and specifications have clearly never met.. */
 232                 cvr ^= 0xf;
 233
 234                 /*
 235                  * Size calculation is much more sensible
 236                  * than it is for the L1.
 237                  *
 238                  * Sizes are 128KB, 258KB, 512KB, and 1MB.
 239                  */
 240                 size = (cvr & 0xf) << 17;
 241
 242                 BUG_ON(!size);
 243
 244                 boot_cpu_data.scache.way_incr           = (1 << 16);
 245                 boot_cpu_data.scache.entry_shift        = 5;
 246                 boot_cpu_data.scache.ways               = 4;
 247                 boot_cpu_data.scache.linesz             = L1_CACHE_BYTES;
 248
 249                 boot_cpu_data.scache.entry_mask =
 250                         (boot_cpu_data.scache.way_incr -
 251                          boot_cpu_data.scache.linesz);
 252
 253                 boot_cpu_data.scache.sets       = size /
 254                         (boot_cpu_data.scache.linesz *
 255                          boot_cpu_data.scache.ways);
 256
 257                 boot_cpu_data.scache.way_size   =
 258                         (boot_cpu_data.scache.sets *
 259                          boot_cpu_data.scache.linesz);
 260         }
 261
 262         return 0;
 263 }