kernel/2.6.29.6-aldebaran-rt/arch/sh/drivers/pci/pci-sh7780.c

   1 /*
   2  *      Low-Level PCI Support for the SH7780
   3  *
   4  *  Dustin McIntire (dustin@sensoria.com)
   5  *      Derived from arch/i386/kernel/pci-*.c which bore the message:
   6  *      (c) 1999--2000 Martin Mares <mj@ucw.cz>
   7  *
   8  *  Ported to the new API by Paul Mundt <lethal@linux-sh.org>
   9  *  With cleanup by Paul van Gool <pvangool@mimotech.com>
  10  *
  11  *  May be copied or modified under the terms of the GNU General Public
  12  *  License.  See linux/COPYING for more information.
  13  *
  14  */
  15 #undef DEBUG
  16
  17 #include <linux/types.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/pci.h>
  21 #include <linux/errno.h>
  22 #include <linux/delay.h>
  23 #include "pci-sh4.h"
  24
  25 #define INTC_BASE       0xffd00000
  26 #define INTC_ICR0       (INTC_BASE+0x0)
  27 #define INTC_ICR1       (INTC_BASE+0x1c)
  28 #define INTC_INTPRI     (INTC_BASE+0x10)
  29 #define INTC_INTREQ     (INTC_BASE+0x24)
  30 #define INTC_INTMSK0    (INTC_BASE+0x44)
  31 #define INTC_INTMSK1    (INTC_BASE+0x48)
  32 #define INTC_INTMSK2    (INTC_BASE+0x40080)
  33 #define INTC_INTMSKCLR0 (INTC_BASE+0x64)
  34 #define INTC_INTMSKCLR1 (INTC_BASE+0x68)
  35 #define INTC_INTMSKCLR2 (INTC_BASE+0x40084)
  36 #define INTC_INT2MSKR   (INTC_BASE+0x40038)
  37 #define INTC_INT2MSKCR  (INTC_BASE+0x4003c)
  38
  39 /*
  40  * Initialization. Try all known PCI access methods. Note that we support
  41  * using both PCI BIOS and direct access: in such cases, we use I/O ports
  42  * to access config space.
  43  *
  44  * Note that the platform specific initialization (BSC registers, and memory
  45  * space mapping) will be called via the platform defined function
  46  * pcibios_init_platform().
  47  */
  48 static int __init sh7780_pci_init(void)
  49 {
  50         unsigned int id;
  51         int ret, match = 0;
  52
  53         pr_debug("PCI: Starting intialization.\n");
  54
  55         ctrl_outl(0x00000001, SH7780_PCI_VCR2); /* Enable PCIC */
  56
  57         /* check for SH7780/SH7780R hardware */
  58         id = pci_read_reg(SH7780_PCIVID);
  59         if ((id & 0xffff) == SH7780_VENDOR_ID) {
  60                 switch ((id >> 16) & 0xffff) {
  61                 case SH7763_DEVICE_ID:
  62                 case SH7780_DEVICE_ID:
  63                 case SH7781_DEVICE_ID:
  64                 case SH7785_DEVICE_ID:
  65                         match = 1;
  66                         break;
  67                 }
  68         }
  69
  70         if (unlikely(!match)) {
  71                 printk(KERN_ERR "PCI: This is not an SH7780 (%x)\n", id);
  72                 return -ENODEV;
  73         }
  74
  75         /* Setup the INTC */
  76         if (mach_is_7780se()) {
  77                 /* ICR0: IRL=use separately */
  78                 ctrl_outl(0x00C00020, INTC_ICR0);
  79                 /* ICR1: detect low level(for 2ndcut) */
  80                 ctrl_outl(0xAAAA0000, INTC_ICR1);
  81                 /* INTPRI: priority=3(all) */
  82                 ctrl_outl(0x33333333, INTC_INTPRI);
  83         }
  84
  85         if ((ret = sh4_pci_check_direct()) != 0)
  86                 return ret;
  87
  88         return pcibios_init_platform();
  89 }
  90 core_initcall(sh7780_pci_init);
  91
  92 int __init sh7780_pcic_init(struct sh4_pci_address_map *map)
  93 {
  94         u32 word;
  95
  96         /*
  97          * This code is unused for some boards as it is done in the
  98          * bootloader and doing it here means the MAC addresses loaded
  99          * by the bootloader get lost.
 100          */
 101         if (!(map->flags & SH4_PCIC_NO_RESET)) {
 102                 /* toggle PCI reset pin */
 103                 word = SH4_PCICR_PREFIX | SH4_PCICR_PRST;
 104                 pci_write_reg(word, SH4_PCICR);
 105                 /* Wait for a long time... not 1 sec. but long enough */
 106                 mdelay(100);
 107                 word = SH4_PCICR_PREFIX;
 108                 pci_write_reg(word, SH4_PCICR);
 109         }
 110
 111         /* set the command/status bits to:
 112          * Wait Cycle Control + Parity Enable + Bus Master +
 113          * Mem space enable
 114          */
 115         pci_write_reg(0x00000046, SH7780_PCICMD);
 116
 117         /* define this host as the host bridge */
 118         word = PCI_BASE_CLASS_BRIDGE << 24;
 119         pci_write_reg(word, SH7780_PCIRID);
 120
 121         /* Set IO and Mem windows to local address
 122          * Make PCI and local address the same for easy 1 to 1 mapping
 123          * Window0 = map->window0.size @ non-cached area base = SDRAM
 124          * Window1 = map->window1.size @ cached area base = SDRAM
 125          */
 126         word = (CONFIG_MEMORY_SIZE - 0x00100000) | 0x00000001;
 127         pci_write_reg(word, SH4_PCILSR0);
 128         pci_write_reg(0x00000001, SH4_PCILSR1);
 129         /* Set the values on window 0 PCI config registers */
 130         word = (CONFIG_MEMORY_SIZE > 0x08000000) ? 0x10000000 : 0x08000000;
 131         pci_write_reg(word | 0xa0000000, SH4_PCILAR0);
 132         pci_write_reg(word, SH7780_PCIMBAR0);
 133         /* Set the values on window 1 PCI config registers */
 134         pci_write_reg(0x00000000, SH4_PCILAR1);
 135         pci_write_reg(0x00000000, SH7780_PCIMBAR1);
 136
 137         /* Map IO space into PCI IO window
 138          * The IO window is 64K-PCIBIOS_MIN_IO in size
 139          * IO addresses will be translated to the
 140          * PCI IO window base address
 141          */
 142         pr_debug("PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n",
 143                  PCIBIOS_MIN_IO, (64 << 10),
 144                  SH7780_PCI_IO_BASE + PCIBIOS_MIN_IO);
 145
 146         /* NOTE: I'm ignoring the PCI error IRQs for now..
 147          * TODO: add support for the internal error interrupts and
 148          * DMA interrupts...
 149          */
 150
 151         /* Apply any last-minute PCIC fixups */
 152         pci_fixup_pcic();
 153
 154         /* SH7780 init done, set central function init complete */
 155         /* use round robin mode to stop a device starving/overruning */
 156         word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO;
 157         pci_write_reg(word, SH4_PCICR);
 158
 159         return 1;
 160 }