kernel/2.6.29.6-aldebaran-rt/arch/powerpc/platforms/cell/celleb_pci.c

   1 /*
   2  * Support for PCI on Celleb platform.
   3  *
   4  * (C) Copyright 2006-2007 TOSHIBA CORPORATION
   5  *
   6  * This code is based on arch/powerpc/kernel/rtas_pci.c:
   7  *  Copyright (C) 2001 Dave Engebretsen, IBM Corporation
   8  *  Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along
  21  * with this program; if not, write to the Free Software Foundation, Inc.,
  22  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  23  */
  24
  25 #undef DEBUG
  26
  27 #include <linux/kernel.h>
  28 #include <linux/threads.h>
  29 #include <linux/pci.h>
  30 #include <linux/string.h>
  31 #include <linux/init.h>
  32 #include <linux/bootmem.h>
  33 #include <linux/pci_regs.h>
  34 #include <linux/of.h>
  35 #include <linux/of_device.h>
  36
  37 #include <asm/io.h>
  38 #include <asm/irq.h>
  39 #include <asm/prom.h>
  40 #include <asm/pci-bridge.h>
  41 #include <asm/ppc-pci.h>
  42
  43 #include "io-workarounds.h"
  44 #include "celleb_pci.h"
  45
  46 #define MAX_PCI_DEVICES    32
  47 #define MAX_PCI_FUNCTIONS   8
  48 #define MAX_PCI_BASE_ADDRS  3 /* use 64 bit address */
  49
  50 /* definition for fake pci configuration area for GbE, .... ,and etc. */
  51
  52 struct celleb_pci_resource {
  53         struct resource r[MAX_PCI_BASE_ADDRS];
  54 };
  55
  56 struct celleb_pci_private {
  57         unsigned char *fake_config[MAX_PCI_DEVICES][MAX_PCI_FUNCTIONS];
  58         struct celleb_pci_resource *res[MAX_PCI_DEVICES][MAX_PCI_FUNCTIONS];
  59 };
  60
  61 static inline u8 celleb_fake_config_readb(void *addr)
  62 {
  63         u8 *p = addr;
  64         return *p;
  65 }
  66
  67 static inline u16 celleb_fake_config_readw(void *addr)
  68 {
  69         __le16 *p = addr;
  70         return le16_to_cpu(*p);
  71 }
  72
  73 static inline u32 celleb_fake_config_readl(void *addr)
  74 {
  75         __le32 *p = addr;
  76         return le32_to_cpu(*p);
  77 }
  78
  79 static inline void celleb_fake_config_writeb(u32 val, void *addr)
  80 {
  81         u8 *p = addr;
  82         *p = val;
  83 }
  84
  85 static inline void celleb_fake_config_writew(u32 val, void *addr)
  86 {
  87         __le16 val16;
  88         __le16 *p = addr;
  89         val16 = cpu_to_le16(val);
  90         *p = val16;
  91 }
  92
  93 static inline void celleb_fake_config_writel(u32 val, void *addr)
  94 {
  95         __le32 val32;
  96         __le32 *p = addr;
  97         val32 = cpu_to_le32(val);
  98         *p = val32;
  99 }
 100
 101 static unsigned char *get_fake_config_start(struct pci_controller *hose,
 102                                             int devno, int fn)
 103 {
 104         struct celleb_pci_private *private = hose->private_data;
 105
 106         if (private == NULL)
 107                 return NULL;
 108
 109         return private->fake_config[devno][fn];
 110 }
 111
 112 static struct celleb_pci_resource *get_resource_start(
 113                                 struct pci_controller *hose,
 114                                 int devno, int fn)
 115 {
 116         struct celleb_pci_private *private = hose->private_data;
 117
 118         if (private == NULL)
 119                 return NULL;
 120
 121         return private->res[devno][fn];
 122 }
 123
 124
 125 static void celleb_config_read_fake(unsigned char *config, int where,
 126                                     int size, u32 *val)
 127 {
 128         char *p = config + where;
 129
 130         switch (size) {
 131         case 1:
 132                 *val = celleb_fake_config_readb(p);
 133                 break;
 134         case 2:
 135                 *val = celleb_fake_config_readw(p);
 136                 break;
 137         case 4:
 138                 *val = celleb_fake_config_readl(p);
 139                 break;
 140         }
 141 }
 142
 143 static void celleb_config_write_fake(unsigned char *config, int where,
 144                                      int size, u32 val)
 145 {
 146         char *p = config + where;
 147
 148         switch (size) {
 149         case 1:
 150                 celleb_fake_config_writeb(val, p);
 151                 break;
 152         case 2:
 153                 celleb_fake_config_writew(val, p);
 154                 break;
 155         case 4:
 156                 celleb_fake_config_writel(val, p);
 157                 break;
 158         }
 159 }
 160
 161 static int celleb_fake_pci_read_config(struct pci_bus *bus,
 162                 unsigned int devfn, int where, int size, u32 *val)
 163 {
 164         char *config;
 165         struct device_node *node;
 166         struct pci_controller *hose;
 167         unsigned int devno = devfn >> 3;
 168         unsigned int fn = devfn & 0x7;
 169
 170         /* allignment check */
 171         BUG_ON(where % size);
 172
 173         pr_debug("    fake read: bus=0x%x, ", bus->number);
 174         node = (struct device_node *)bus->sysdata;
 175         hose = pci_find_hose_for_OF_device(node);
 176         config = get_fake_config_start(hose, devno, fn);
 177
 178         pr_debug("devno=0x%x, where=0x%x, size=0x%x, ", devno, where, size);
 179         if (!config) {
 180                 pr_debug("failed\n");
 181                 return PCIBIOS_DEVICE_NOT_FOUND;
 182         }
 183
 184         celleb_config_read_fake(config, where, size, val);
 185         pr_debug("val=0x%x\n", *val);
 186
 187         return PCIBIOS_SUCCESSFUL;
 188 }
 189
 190
 191 static int celleb_fake_pci_write_config(struct pci_bus *bus,
 192                 unsigned int devfn, int where, int size, u32 val)
 193 {
 194         char *config;
 195         struct device_node *node;
 196         struct pci_controller *hose;
 197         struct celleb_pci_resource *res;
 198         unsigned int devno = devfn >> 3;
 199         unsigned int fn = devfn & 0x7;
 200
 201         /* allignment check */
 202         BUG_ON(where % size);
 203
 204         node = (struct device_node *)bus->sysdata;
 205         hose = pci_find_hose_for_OF_device(node);
 206         config = get_fake_config_start(hose, devno, fn);
 207
 208         if (!config)
 209                 return PCIBIOS_DEVICE_NOT_FOUND;
 210
 211         if (val == ~0) {
 212                 int i = (where - PCI_BASE_ADDRESS_0) >> 3;
 213
 214                 switch (where) {
 215                 case PCI_BASE_ADDRESS_0:
 216                 case PCI_BASE_ADDRESS_2:
 217                         if (size != 4)
 218                                 return PCIBIOS_DEVICE_NOT_FOUND;
 219                         res = get_resource_start(hose, devno, fn);
 220                         if (!res)
 221                                 return PCIBIOS_DEVICE_NOT_FOUND;
 222                         celleb_config_write_fake(config, where, size,
 223                                         (res->r[i].end - res->r[i].start));
 224                         return PCIBIOS_SUCCESSFUL;
 225                 case PCI_BASE_ADDRESS_1:
 226                 case PCI_BASE_ADDRESS_3:
 227                 case PCI_BASE_ADDRESS_4:
 228                 case PCI_BASE_ADDRESS_5:
 229                         break;
 230                 default:
 231                         break;
 232                 }
 233         }
 234
 235         celleb_config_write_fake(config, where, size, val);
 236         pr_debug("    fake write: where=%x, size=%d, val=%x\n",
 237                  where, size, val);
 238
 239         return PCIBIOS_SUCCESSFUL;
 240 }
 241
 242 static struct pci_ops celleb_fake_pci_ops = {
 243         .read = celleb_fake_pci_read_config,
 244         .write = celleb_fake_pci_write_config,
 245 };
 246
 247 static inline void celleb_setup_pci_base_addrs(struct pci_controller *hose,
 248                                         unsigned int devno, unsigned int fn,
 249                                         unsigned int num_base_addr)
 250 {
 251         u32 val;
 252         unsigned char *config;
 253         struct celleb_pci_resource *res;
 254
 255         config = get_fake_config_start(hose, devno, fn);
 256         res = get_resource_start(hose, devno, fn);
 257
 258         if (!config || !res)
 259                 return;
 260
 261         switch (num_base_addr) {
 262         case 3:
 263                 val = (res->r[2].start & 0xfffffff0)
 264                     | PCI_BASE_ADDRESS_MEM_TYPE_64;
 265                 celleb_config_write_fake(config, PCI_BASE_ADDRESS_4, 4, val);
 266                 val = res->r[2].start >> 32;
 267                 celleb_config_write_fake(config, PCI_BASE_ADDRESS_5, 4, val);
 268                 /* FALLTHROUGH */
 269         case 2:
 270                 val = (res->r[1].start & 0xfffffff0)
 271                     | PCI_BASE_ADDRESS_MEM_TYPE_64;
 272                 celleb_config_write_fake(config, PCI_BASE_ADDRESS_2, 4, val);
 273                 val = res->r[1].start >> 32;
 274                 celleb_config_write_fake(config, PCI_BASE_ADDRESS_3, 4, val);
 275                 /* FALLTHROUGH */
 276         case 1:
 277                 val = (res->r[0].start & 0xfffffff0)
 278                     | PCI_BASE_ADDRESS_MEM_TYPE_64;
 279                 celleb_config_write_fake(config, PCI_BASE_ADDRESS_0, 4, val);
 280                 val = res->r[0].start >> 32;
 281                 celleb_config_write_fake(config, PCI_BASE_ADDRESS_1, 4, val);
 282                 break;
 283         }
 284
 285         val = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 286         celleb_config_write_fake(config, PCI_COMMAND, 2, val);
 287 }
 288
 289 static int __init celleb_setup_fake_pci_device(struct device_node *node,
 290                                                struct pci_controller *hose)
 291 {
 292         unsigned int rlen;
 293         int num_base_addr = 0;
 294         u32 val;
 295         const u32 *wi0, *wi1, *wi2, *wi3, *wi4;
 296         unsigned int devno, fn;
 297         struct celleb_pci_private *private = hose->private_data;
 298         unsigned char **config = NULL;
 299         struct celleb_pci_resource **res = NULL;
 300         const char *name;
 301         const unsigned long *li;
 302         int size, result;
 303
 304         if (private == NULL) {
 305                 printk(KERN_ERR "PCI: "
 306                        "memory space for pci controller is not assigned\n");
 307                 goto error;
 308         }
 309
 310         name = of_get_property(node, "model", &rlen);
 311         if (!name) {
 312                 printk(KERN_ERR "PCI: model property not found.\n");
 313                 goto error;
 314         }
 315
 316         wi4 = of_get_property(node, "reg", &rlen);
 317         if (wi4 == NULL)
 318                 goto error;
 319
 320         devno = ((wi4[0] >> 8) & 0xff) >> 3;
 321         fn = (wi4[0] >> 8) & 0x7;
 322
 323         pr_debug("PCI: celleb_setup_fake_pci() %s devno=%x fn=%x\n", name,
 324                  devno, fn);
 325
 326         size = 256;
 327         config = &private->fake_config[devno][fn];
 328         *config = alloc_maybe_bootmem(size, GFP_KERNEL);
 329         if (*config == NULL) {
 330                 printk(KERN_ERR "PCI: "
 331                        "not enough memory for fake configuration space\n");
 332                 goto error;
 333         }
 334         pr_debug("PCI: fake config area assigned 0x%016lx\n",
 335                  (unsigned long)*config);
 336
 337         size = sizeof(struct celleb_pci_resource);
 338         res = &private->res[devno][fn];
 339         *res = alloc_maybe_bootmem(size, GFP_KERNEL);
 340         if (*res == NULL) {
 341                 printk(KERN_ERR
 342                        "PCI: not enough memory for resource data space\n");
 343                 goto error;
 344         }
 345         pr_debug("PCI: res assigned 0x%016lx\n", (unsigned long)*res);
 346
 347         wi0 = of_get_property(node, "device-id", NULL);
 348         wi1 = of_get_property(node, "vendor-id", NULL);
 349         wi2 = of_get_property(node, "class-code", NULL);
 350         wi3 = of_get_property(node, "revision-id", NULL);
 351         if (!wi0 || !wi1 || !wi2 || !wi3) {
 352                 printk(KERN_ERR "PCI: Missing device tree properties.\n");
 353                 goto error;
 354         }
 355
 356         celleb_config_write_fake(*config, PCI_DEVICE_ID, 2, wi0[0] & 0xffff);
 357         celleb_config_write_fake(*config, PCI_VENDOR_ID, 2, wi1[0] & 0xffff);
 358         pr_debug("class-code = 0x%08x\n", wi2[0]);
 359
 360         celleb_config_write_fake(*config, PCI_CLASS_PROG, 1, wi2[0] & 0xff);
 361         celleb_config_write_fake(*config, PCI_CLASS_DEVICE, 2,
 362                                  (wi2[0] >> 8) & 0xffff);
 363         celleb_config_write_fake(*config, PCI_REVISION_ID, 1, wi3[0]);
 364
 365         while (num_base_addr < MAX_PCI_BASE_ADDRS) {
 366                 result = of_address_to_resource(node,
 367                                 num_base_addr, &(*res)->r[num_base_addr]);
 368                 if (result)
 369                         break;
 370                 num_base_addr++;
 371         }
 372
 373         celleb_setup_pci_base_addrs(hose, devno, fn, num_base_addr);
 374
 375         li = of_get_property(node, "interrupts", &rlen);
 376         if (!li) {
 377                 printk(KERN_ERR "PCI: interrupts not found.\n");
 378                 goto error;
 379         }
 380         val = li[0];
 381         celleb_config_write_fake(*config, PCI_INTERRUPT_PIN, 1, 1);
 382         celleb_config_write_fake(*config, PCI_INTERRUPT_LINE, 1, val);
 383
 384 #ifdef DEBUG
 385         pr_debug("PCI: %s irq=%ld\n", name, li[0]);
 386         for (i = 0; i < 6; i++) {
 387                 celleb_config_read_fake(*config,
 388                                         PCI_BASE_ADDRESS_0 + 0x4 * i, 4,
 389                                         &val);
 390                 pr_debug("PCI: %s fn=%d base_address_%d=0x%x\n",
 391                          name, fn, i, val);
 392         }
 393 #endif
 394
 395         celleb_config_write_fake(*config, PCI_HEADER_TYPE, 1,
 396                                  PCI_HEADER_TYPE_NORMAL);
 397
 398         return 0;
 399
 400 error:
 401         if (mem_init_done) {
 402                 if (config && *config)
 403                         kfree(*config);
 404                 if (res && *res)
 405                         kfree(*res);
 406
 407         } else {
 408                 if (config && *config) {
 409                         size = 256;
 410                         free_bootmem((unsigned long)(*config), size);
 411                 }
 412                 if (res && *res) {
 413                         size = sizeof(struct celleb_pci_resource);
 414                         free_bootmem((unsigned long)(*res), size);
 415                 }
 416         }
 417
 418         return 1;
 419 }
 420
 421 static int __init phb_set_bus_ranges(struct device_node *dev,
 422                                      struct pci_controller *phb)
 423 {
 424         const int *bus_range;
 425         unsigned int len;
 426
 427         bus_range = of_get_property(dev, "bus-range", &len);
 428         if (bus_range == NULL || len < 2 * sizeof(int))
 429                 return 1;
 430
 431         phb->first_busno = bus_range[0];
 432         phb->last_busno = bus_range[1];
 433
 434         return 0;
 435 }
 436
 437 static void __init celleb_alloc_private_mem(struct pci_controller *hose)
 438 {
 439         hose->private_data =
 440                 alloc_maybe_bootmem(sizeof(struct celleb_pci_private),
 441                         GFP_KERNEL);
 442 }
 443
 444 static int __init celleb_setup_fake_pci(struct device_node *dev,
 445                                         struct pci_controller *phb)
 446 {
 447         struct device_node *node;
 448
 449         phb->ops = &celleb_fake_pci_ops;
 450         celleb_alloc_private_mem(phb);
 451
 452         for (node = of_get_next_child(dev, NULL);
 453              node != NULL; node = of_get_next_child(dev, node))
 454                 celleb_setup_fake_pci_device(node, phb);
 455
 456         return 0;
 457 }
 458
 459 static struct celleb_phb_spec celleb_fake_pci_spec __initdata = {
 460         .setup = celleb_setup_fake_pci,
 461 };
 462
 463 static struct of_device_id celleb_phb_match[] __initdata = {
 464         {
 465                 .name = "pci-pseudo",
 466                 .data = &celleb_fake_pci_spec,
 467         }, {
 468                 .name = "epci",
 469                 .data = &celleb_epci_spec,
 470         }, {
 471                 .name = "pcie",
 472                 .data = &celleb_pciex_spec,
 473         }, {
 474         },
 475 };
 476
 477 static int __init celleb_io_workaround_init(struct pci_controller *phb,
 478                                             struct celleb_phb_spec *phb_spec)
 479 {
 480         if (phb_spec->ops) {
 481                 iowa_register_bus(phb, phb_spec->ops, phb_spec->iowa_init,
 482                                   phb_spec->iowa_data);
 483                 io_workaround_init();
 484         }
 485
 486         return 0;
 487 }
 488
 489 int __init celleb_setup_phb(struct pci_controller *phb)
 490 {
 491         struct device_node *dev = phb->dn;
 492         const struct of_device_id *match;
 493         struct celleb_phb_spec *phb_spec;
 494         int rc;
 495
 496         match = of_match_node(celleb_phb_match, dev);
 497         if (!match)
 498                 return 1;
 499
 500         phb_set_bus_ranges(dev, phb);
 501         phb->buid = 1;
 502
 503         phb_spec = match->data;
 504         rc = (*phb_spec->setup)(dev, phb);
 505         if (rc)
 506                 return 1;
 507
 508         return celleb_io_workaround_init(phb, phb_spec);
 509 }
 510
 511 int celleb_pci_probe_mode(struct pci_bus *bus)
 512 {
 513         return PCI_PROBE_DEVTREE;
 514 }