2 * Performance counter support for POWER5 (not POWER5++) processors.
4 * Copyright 2009 Paul Mackerras, IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 #include <linux/kernel.h>
12 #include <linux/perf_counter.h>
16 * Bits in event code for POWER5+ (POWER5 GS) and POWER5++ (POWER5 GS DD3)
18 #define PM_PMC_SH 20 /* PMC number (1-based) for direct events */
19 #define PM_PMC_MSK 0xf
20 #define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH)
21 #define PM_UNIT_SH 16 /* TTMMUX number and setting - unit select */
22 #define PM_UNIT_MSK 0xf
23 #define PM_BYTE_SH 12 /* Byte number of event bus to use */
25 #define PM_GRS_SH 8 /* Storage subsystem mux select */
27 #define PM_BUSEVENT_MSK 0x80 /* Set if event uses event bus */
28 #define PM_PMCSEL_MSK 0x7f
30 /* Values in PM_UNIT field */
40 #define PM_LASTUNIT 0xc
43 * Bits in MMCR1 for POWER5+
45 #define MMCR1_TTM0SEL_SH 62
46 #define MMCR1_TTM1SEL_SH 60
47 #define MMCR1_TTM2SEL_SH 58
48 #define MMCR1_TTM3SEL_SH 56
49 #define MMCR1_TTMSEL_MSK 3
50 #define MMCR1_TD_CP_DBG0SEL_SH 54
51 #define MMCR1_TD_CP_DBG1SEL_SH 52
52 #define MMCR1_TD_CP_DBG2SEL_SH 50
53 #define MMCR1_TD_CP_DBG3SEL_SH 48
54 #define MMCR1_GRS_L2SEL_SH 46
55 #define MMCR1_GRS_L2SEL_MSK 3
56 #define MMCR1_GRS_L3SEL_SH 44
57 #define MMCR1_GRS_L3SEL_MSK 3
58 #define MMCR1_GRS_MCSEL_SH 41
59 #define MMCR1_GRS_MCSEL_MSK 7
60 #define MMCR1_GRS_FABSEL_SH 39
61 #define MMCR1_GRS_FABSEL_MSK 3
62 #define MMCR1_PMC1_ADDER_SEL_SH 35
63 #define MMCR1_PMC2_ADDER_SEL_SH 34
64 #define MMCR1_PMC3_ADDER_SEL_SH 33
65 #define MMCR1_PMC4_ADDER_SEL_SH 32
66 #define MMCR1_PMC1SEL_SH 25
67 #define MMCR1_PMC2SEL_SH 17
68 #define MMCR1_PMC3SEL_SH 9
69 #define MMCR1_PMC4SEL_SH 1
70 #define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8)
71 #define MMCR1_PMCSEL_MSK 0x7f
78 * Layout of constraint bits:
79 * 6666555555555544444444443333333333222222222211111111110000000000
80 * 3210987654321098765432109876543210987654321098765432109876543210
81 * [ ><><>< ><> <><>[ > < >< >< >< ><><><><>
82 * NC G0G1G2 G3 T0T1 UC B0 B1 B2 B3 P4P3P2P1
84 * NC - number of counters
85 * 51: NC error 0x0008_0000_0000_0000
86 * 48-50: number of events needing PMC1-4 0x0007_0000_0000_0000
88 * G0..G3 - GRS mux constraints
89 * 46-47: GRS_L2SEL value
90 * 44-45: GRS_L3SEL value
91 * 41-44: GRS_MCSEL value
92 * 39-40: GRS_FABSEL value
93 * Note that these match up with their bit positions in MMCR1
95 * T0 - TTM0 constraint
96 * 36-37: TTM0SEL value (0=FPU, 2=IFU, 3=ISU1) 0x30_0000_0000
98 * T1 - TTM1 constraint
99 * 34-35: TTM1SEL value (0=IDU, 3=GRS) 0x0c_0000_0000
101 * UC - unit constraint: can't have all three of FPU|IFU|ISU1, ISU0, IDU|GRS
102 * 33: UC3 error 0x02_0000_0000
103 * 32: FPU|IFU|ISU1 events needed 0x01_0000_0000
104 * 31: ISU0 events needed 0x01_8000_0000
105 * 30: IDU|GRS events needed 0x00_4000_0000
108 * 20-23: Byte 0 event source 0x00f0_0000
109 * Encoding as for the event code
112 * 16-19, 12-15, 8-11: Byte 1, 2, 3 event sources
116 * 6-7: Count of events needing PMC4
119 * 0-6: Count of events needing PMC1..PMC3
122 static const int grsel_shift
[8] = {
123 MMCR1_GRS_L2SEL_SH
, MMCR1_GRS_L2SEL_SH
, MMCR1_GRS_L2SEL_SH
,
124 MMCR1_GRS_L3SEL_SH
, MMCR1_GRS_L3SEL_SH
, MMCR1_GRS_L3SEL_SH
,
125 MMCR1_GRS_MCSEL_SH
, MMCR1_GRS_FABSEL_SH
128 /* Masks and values for using events from the various units */
129 static u64 unit_cons
[PM_LASTUNIT
+1][2] = {
130 [PM_FPU
] = { 0x3200000000ull
, 0x0100000000ull
},
131 [PM_ISU0
] = { 0x0200000000ull
, 0x0080000000ull
},
132 [PM_ISU1
] = { 0x3200000000ull
, 0x3100000000ull
},
133 [PM_IFU
] = { 0x3200000000ull
, 0x2100000000ull
},
134 [PM_IDU
] = { 0x0e00000000ull
, 0x0040000000ull
},
135 [PM_GRS
] = { 0x0e00000000ull
, 0x0c40000000ull
},
138 static int power5p_get_constraint(unsigned int event
, u64
*maskp
, u64
*valp
)
140 int pmc
, byte
, unit
, sh
;
142 u64 mask
= 0, value
= 0;
144 pmc
= (event
>> PM_PMC_SH
) & PM_PMC_MSK
;
152 if (event
& PM_BUSEVENT_MSK
) {
153 unit
= (event
>> PM_UNIT_SH
) & PM_UNIT_MSK
;
154 if (unit
> PM_LASTUNIT
)
156 if (unit
== PM_ISU0_ALT
)
158 mask
|= unit_cons
[unit
][0];
159 value
|= unit_cons
[unit
][1];
160 byte
= (event
>> PM_BYTE_SH
) & PM_BYTE_MSK
;
164 /* Map LSU1 low word (bytes 4-7) to unit LSU1+1 */
168 if (unit
== PM_GRS
) {
170 fmask
= (bit
== 6)? 7: 3;
171 sh
= grsel_shift
[bit
];
172 mask
|= (u64
)fmask
<< sh
;
173 value
|= (u64
)((event
>> PM_GRS_SH
) & fmask
) << sh
;
175 /* Set byte lane select field */
176 mask
|= 0xfULL
<< (20 - 4 * byte
);
177 value
|= (u64
)unit
<< (20 - 4 * byte
);
179 mask
|= 0x8000000000000ull
;
180 value
|= 0x1000000000000ull
;
186 #define MAX_ALT 3 /* at most 3 alternatives for any event */
188 static const unsigned int event_alternatives
[][MAX_ALT
] = {
189 { 0x100c0, 0x40001f }, /* PM_GCT_FULL_CYC */
190 { 0x120e4, 0x400002 }, /* PM_GRP_DISP_REJECT */
191 { 0x230e2, 0x323087 }, /* PM_BR_PRED_CR */
192 { 0x230e3, 0x223087, 0x3230a0 }, /* PM_BR_PRED_TA */
193 { 0x410c7, 0x441084 }, /* PM_THRD_L2MISS_BOTH_CYC */
194 { 0x800c4, 0xc20e0 }, /* PM_DTLB_MISS */
195 { 0xc50c6, 0xc60e0 }, /* PM_MRK_DTLB_MISS */
196 { 0x100009, 0x200009 }, /* PM_INST_CMPL */
197 { 0x200015, 0x300015 }, /* PM_LSU_LMQ_SRQ_EMPTY_CYC */
198 { 0x300009, 0x400009 }, /* PM_INST_DISP */
202 * Scan the alternatives table for a match and return the
203 * index into the alternatives table if found, else -1.
205 static int find_alternative(unsigned int event
)
209 for (i
= 0; i
< ARRAY_SIZE(event_alternatives
); ++i
) {
210 if (event
< event_alternatives
[i
][0])
212 for (j
= 0; j
< MAX_ALT
&& event_alternatives
[i
][j
]; ++j
)
213 if (event
== event_alternatives
[i
][j
])
219 static const unsigned char bytedecode_alternatives
[4][4] = {
220 /* PMC 1 */ { 0x21, 0x23, 0x25, 0x27 },
221 /* PMC 2 */ { 0x07, 0x17, 0x0e, 0x1e },
222 /* PMC 3 */ { 0x20, 0x22, 0x24, 0x26 },
223 /* PMC 4 */ { 0x07, 0x17, 0x0e, 0x1e }
227 * Some direct events for decodes of event bus byte 3 have alternative
228 * PMCSEL values on other counters. This returns the alternative
229 * event code for those that do, or -1 otherwise. This also handles
230 * alternative PCMSEL values for add events.
232 static int find_alternative_bdecode(unsigned int event
)
234 int pmc
, altpmc
, pp
, j
;
236 pmc
= (event
>> PM_PMC_SH
) & PM_PMC_MSK
;
237 if (pmc
== 0 || pmc
> 4)
239 altpmc
= 5 - pmc
; /* 1 <-> 4, 2 <-> 3 */
240 pp
= event
& PM_PMCSEL_MSK
;
241 for (j
= 0; j
< 4; ++j
) {
242 if (bytedecode_alternatives
[pmc
- 1][j
] == pp
) {
243 return (event
& ~(PM_PMC_MSKS
| PM_PMCSEL_MSK
)) |
244 (altpmc
<< PM_PMC_SH
) |
245 bytedecode_alternatives
[altpmc
- 1][j
];
249 /* new decode alternatives for power5+ */
250 if (pmc
== 1 && (pp
== 0x0d || pp
== 0x0e))
251 return event
+ (2 << PM_PMC_SH
) + (0x2e - 0x0d);
252 if (pmc
== 3 && (pp
== 0x2e || pp
== 0x2f))
253 return event
- (2 << PM_PMC_SH
) - (0x2e - 0x0d);
255 /* alternative add event encodings */
256 if (pp
== 0x10 || pp
== 0x28)
257 return ((event
^ (0x10 ^ 0x28)) & ~PM_PMC_MSKS
) |
258 (altpmc
<< PM_PMC_SH
);
263 static int power5p_get_alternatives(unsigned int event
, unsigned int alt
[])
265 int i
, j
, ae
, nalt
= 1;
269 i
= find_alternative(event
);
271 for (j
= 0; j
< MAX_ALT
; ++j
) {
272 ae
= event_alternatives
[i
][j
];
273 if (ae
&& ae
!= event
)
277 ae
= find_alternative_bdecode(event
);
284 static int power5p_compute_mmcr(unsigned int event
[], int n_ev
,
285 unsigned int hwc
[], u64 mmcr
[])
288 unsigned int pmc
, unit
, byte
, psel
;
290 int i
, isbus
, bit
, grsel
;
291 unsigned int pmc_inuse
= 0;
292 unsigned char busbyte
[4];
293 unsigned char unituse
[16];
299 /* First pass to count resource use */
300 memset(busbyte
, 0, sizeof(busbyte
));
301 memset(unituse
, 0, sizeof(unituse
));
302 for (i
= 0; i
< n_ev
; ++i
) {
303 pmc
= (event
[i
] >> PM_PMC_SH
) & PM_PMC_MSK
;
307 if (pmc_inuse
& (1 << (pmc
- 1)))
309 pmc_inuse
|= 1 << (pmc
- 1);
311 if (event
[i
] & PM_BUSEVENT_MSK
) {
312 unit
= (event
[i
] >> PM_UNIT_SH
) & PM_UNIT_MSK
;
313 byte
= (event
[i
] >> PM_BYTE_SH
) & PM_BYTE_MSK
;
314 if (unit
> PM_LASTUNIT
)
316 if (unit
== PM_ISU0_ALT
)
324 if (busbyte
[byte
] && busbyte
[byte
] != unit
)
326 busbyte
[byte
] = unit
;
332 * Assign resources and set multiplexer selects.
334 * PM_ISU0 can go either on TTM0 or TTM1, but that's the only
335 * choice we have to deal with.
337 if (unituse
[PM_ISU0
] &
338 (unituse
[PM_FPU
] | unituse
[PM_IFU
] | unituse
[PM_ISU1
])) {
339 unituse
[PM_ISU0_ALT
] = 1; /* move ISU to TTM1 */
340 unituse
[PM_ISU0
] = 0;
342 /* Set TTM[01]SEL fields. */
344 for (i
= PM_FPU
; i
<= PM_ISU1
; ++i
) {
349 mmcr1
|= (u64
)i
<< MMCR1_TTM0SEL_SH
;
352 for (; i
<= PM_GRS
; ++i
) {
357 mmcr1
|= (u64
)(i
& 3) << MMCR1_TTM1SEL_SH
;
362 /* Set byte lane select fields, TTM[23]SEL and GRS_*SEL. */
363 for (byte
= 0; byte
< 4; ++byte
) {
364 unit
= busbyte
[byte
];
367 if (unit
== PM_ISU0
&& unituse
[PM_ISU0_ALT
]) {
368 /* get ISU0 through TTM1 rather than TTM0 */
370 } else if (unit
== PM_LSU1
+ 1) {
371 /* select lower word of LSU1 for this byte */
372 mmcr1
|= 1ull << (MMCR1_TTM3SEL_SH
+ 3 - byte
);
375 mmcr1
|= (u64
)ttm
<< (MMCR1_TD_CP_DBG0SEL_SH
- 2 * byte
);
378 /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
379 for (i
= 0; i
< n_ev
; ++i
) {
380 pmc
= (event
[i
] >> PM_PMC_SH
) & PM_PMC_MSK
;
381 unit
= (event
[i
] >> PM_UNIT_SH
) & PM_UNIT_MSK
;
382 byte
= (event
[i
] >> PM_BYTE_SH
) & PM_BYTE_MSK
;
383 psel
= event
[i
] & PM_PMCSEL_MSK
;
384 isbus
= event
[i
] & PM_BUSEVENT_MSK
;
386 /* Bus event or any-PMC direct event */
387 for (pmc
= 0; pmc
< 4; ++pmc
) {
388 if (!(pmc_inuse
& (1 << pmc
)))
393 pmc_inuse
|= 1 << pmc
;
397 if (isbus
&& (byte
& 2) &&
398 (psel
== 8 || psel
== 0x10 || psel
== 0x28))
399 /* add events on higher-numbered bus */
400 mmcr1
|= 1ull << (MMCR1_PMC1_ADDER_SEL_SH
- pmc
);
402 if (isbus
&& unit
== PM_GRS
) {
404 grsel
= (event
[i
] >> PM_GRS_SH
) & PM_GRS_MSK
;
405 mmcr1
|= (u64
)grsel
<< grsel_shift
[bit
];
407 if ((psel
& 0x58) == 0x40 && (byte
& 1) != ((pmc
>> 1) & 1))
408 /* select alternate byte lane */
411 mmcr1
|= psel
<< MMCR1_PMCSEL_SH(pmc
);
415 /* Return MMCRx values */
418 mmcr
[0] = MMCR0_PMC1CE
;
419 if (pmc_inuse
& 0x3e)
420 mmcr
[0] |= MMCR0_PMCjCE
;
426 static void power5p_disable_pmc(unsigned int pmc
, u64 mmcr
[])
429 mmcr
[1] &= ~(0x7fUL
<< MMCR1_PMCSEL_SH(pmc
));
432 static int power5p_generic_events
[] = {
433 [PERF_COUNT_CPU_CYCLES
] = 0xf,
434 [PERF_COUNT_INSTRUCTIONS
] = 0x100009,
435 [PERF_COUNT_CACHE_REFERENCES
] = 0x1c10a8, /* LD_REF_L1 */
436 [PERF_COUNT_CACHE_MISSES
] = 0x3c1088, /* LD_MISS_L1 */
437 [PERF_COUNT_BRANCH_INSTRUCTIONS
] = 0x230e4, /* BR_ISSUED */
438 [PERF_COUNT_BRANCH_MISSES
] = 0x230e5, /* BR_MPRED_CR */
441 struct power_pmu power5p_pmu
= {
443 .max_alternatives
= MAX_ALT
,
444 .add_fields
= 0x7000000000055ull
,
445 .test_adder
= 0x3000040000000ull
,
446 .compute_mmcr
= power5p_compute_mmcr
,
447 .get_constraint
= power5p_get_constraint
,
448 .get_alternatives
= power5p_get_alternatives
,
449 .disable_pmc
= power5p_disable_pmc
,
450 .n_generic
= ARRAY_SIZE(power5p_generic_events
),
451 .generic_events
= power5p_generic_events
,