kernel/2.6.29.6-aldebaran-rt/arch/mips/nxp/pnx833x/stb22x/board.c

   1 /*
   2  *  board.c: STB225 board support.
   3  *
   4  *  Copyright 2008 NXP Semiconductors
   5  *        Chris Steel <chris.steel@nxp.com>
   6  *    Daniel Laird <daniel.j.laird@nxp.com>
   7  *
   8  *  Based on software written by:
   9  *      Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
  10  *
  11  *  This program is free software; you can redistribute it and/or modify
  12  *  it under the terms of the GNU General Public License as published by
  13  *  the Free Software Foundation; either version 2 of the License, or
  14  *  (at your option) any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful,
  17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *  GNU General Public License for more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License
  22  *  along with this program; if not, write to the Free Software
  23  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  */
  25 #include <linux/init.h>
  26 #include <asm/bootinfo.h>
  27 #include <linux/mm.h>
  28 #include <pnx833x.h>
  29 #include <gpio.h>
  30
  31 /* endianess twiddlers */
  32 #define PNX8335_DEBUG0 0x4400
  33 #define PNX8335_DEBUG1 0x4404
  34 #define PNX8335_DEBUG2 0x4408
  35 #define PNX8335_DEBUG3 0x440c
  36 #define PNX8335_DEBUG4 0x4410
  37 #define PNX8335_DEBUG5 0x4414
  38 #define PNX8335_DEBUG6 0x4418
  39 #define PNX8335_DEBUG7 0x441c
  40
  41 int prom_argc;
  42 char **prom_argv = 0, **prom_envp = 0;
  43
  44 extern void prom_init_cmdline(void);
  45 extern char *prom_getenv(char *envname);
  46
  47 const char *get_system_type(void)
  48 {
  49         return "NXP STB22x";
  50 }
  51
  52 static inline unsigned long env_or_default(char *env, unsigned long dfl)
  53 {
  54         char *str = prom_getenv(env);
  55         return str ? simple_strtol(str, 0, 0) : dfl;
  56 }
  57
  58 void __init prom_init(void)
  59 {
  60         unsigned long memsize;
  61
  62         prom_argc = fw_arg0;
  63         prom_argv = (char **)fw_arg1;
  64         prom_envp = (char **)fw_arg2;
  65
  66         prom_init_cmdline();
  67
  68         memsize = env_or_default("memsize", 0x02000000);
  69         add_memory_region(0, memsize, BOOT_MEM_RAM);
  70 }
  71
  72 void __init pnx833x_board_setup(void)
  73 {
  74         pnx833x_gpio_select_function_alt(4);
  75         pnx833x_gpio_select_output(4);
  76         pnx833x_gpio_select_function_alt(5);
  77         pnx833x_gpio_select_input(5);
  78         pnx833x_gpio_select_function_alt(6);
  79         pnx833x_gpio_select_input(6);
  80         pnx833x_gpio_select_function_alt(7);
  81         pnx833x_gpio_select_output(7);
  82
  83         pnx833x_gpio_select_function_alt(25);
  84         pnx833x_gpio_select_function_alt(26);
  85
  86         pnx833x_gpio_select_function_alt(27);
  87         pnx833x_gpio_select_function_alt(28);
  88         pnx833x_gpio_select_function_alt(29);
  89         pnx833x_gpio_select_function_alt(30);
  90         pnx833x_gpio_select_function_alt(31);
  91         pnx833x_gpio_select_function_alt(32);
  92         pnx833x_gpio_select_function_alt(33);
  93
  94 #if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
  95         /* Setup MIU for NAND access on CS0...
  96          *
  97          * (it seems that we must also configure CS1 for reliable operation,
  98          * otherwise the first read ID command will fail if it's read as 4 bytes
  99          * but pass if it's read as 1 word.)
 100          */
 101
 102         /* Setup MIU CS0 & CS1 timing */
 103         PNX833X_MIU_SEL0 = 0;
 104         PNX833X_MIU_SEL1 = 0;
 105         PNX833X_MIU_SEL0_TIMING = 0x50003081;
 106         PNX833X_MIU_SEL1_TIMING = 0x50003081;
 107
 108         /* Setup GPIO 00 for use as MIU CS1 (CS0 is not multiplexed, so does not need this) */
 109         pnx833x_gpio_select_function_alt(0);
 110
 111         /* Setup GPIO 04 to input NAND read/busy signal */
 112         pnx833x_gpio_select_function_io(4);
 113         pnx833x_gpio_select_input(4);
 114
 115         /* Setup GPIO 05 to disable NAND write protect */
 116         pnx833x_gpio_select_function_io(5);
 117         pnx833x_gpio_select_output(5);
 118         pnx833x_gpio_write(1, 5);
 119
 120 #elif defined(CONFIG_MTD_CFI) || defined(CONFIG_MTD_CFI_MODULE)
 121
 122         /* Set up MIU for 16-bit NOR access on CS0 and CS1... */
 123
 124         /* Setup MIU CS0 & CS1 timing */
 125         PNX833X_MIU_SEL0 = 1;
 126         PNX833X_MIU_SEL1 = 1;
 127         PNX833X_MIU_SEL0_TIMING = 0x6A08D082;
 128         PNX833X_MIU_SEL1_TIMING = 0x6A08D082;
 129
 130         /* Setup GPIO 00 for use as MIU CS1 (CS0 is not multiplexed, so does not need this) */
 131         pnx833x_gpio_select_function_alt(0);
 132 #endif
 133 }