kernel/2.6.29.6-aldebaran-rt/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h

   1 /*
   2  *
   3  * BRIEF MODULE DESCRIPTION
   4  *      Include file for Alchemy Semiconductor's Au1550 Descriptor
   5  *      Based DMA Controller.
   6  *
   7  * Copyright 2004 Embedded Edge, LLC
   8  *      dan@embeddededge.com
   9  *
  10  *  This program is free software; you can redistribute  it and/or modify it
  11  *  under  the terms of  the GNU General  Public License as published by the
  12  *  Free Software Foundation;  either version 2 of the  License, or (at your
  13  *  option) any later version.
  14  *
  15  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  16  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  17  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  18  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  19  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  21  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  22  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  23  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  24  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  *  You should have received a copy of the  GNU General Public License along
  27  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  28  *  675 Mass Ave, Cambridge, MA 02139, USA.
  29  */
  30
  31 /*
  32  * Specifics for the Au1xxx Descriptor-Based DMA Controller,
  33  * first seen in the AU1550 part.
  34  */
  35 #ifndef _AU1000_DBDMA_H_
  36 #define _AU1000_DBDMA_H_
  37
  38 #ifndef _LANGUAGE_ASSEMBLY
  39
  40 /*
  41  * The DMA base addresses.
  42  * The channels are every 256 bytes (0x0100) from the channel 0 base.
  43  * Interrupt status/enable is bits 15:0 for channels 15 to zero.
  44  */
  45 #define DDMA_GLOBAL_BASE        0xb4003000
  46 #define DDMA_CHANNEL_BASE       0xb4002000
  47
  48 typedef volatile struct dbdma_global {
  49         u32     ddma_config;
  50         u32     ddma_intstat;
  51         u32     ddma_throttle;
  52         u32     ddma_inten;
  53 } dbdma_global_t;
  54
  55 /* General Configuration. */
  56 #define DDMA_CONFIG_AF          (1 << 2)
  57 #define DDMA_CONFIG_AH          (1 << 1)
  58 #define DDMA_CONFIG_AL          (1 << 0)
  59
  60 #define DDMA_THROTTLE_EN        (1 << 31)
  61
  62 /* The structure of a DMA Channel. */
  63 typedef volatile struct au1xxx_dma_channel {
  64         u32     ddma_cfg;       /* See below */
  65         u32     ddma_desptr;    /* 32-byte aligned pointer to descriptor */
  66         u32     ddma_statptr;   /* word aligned pointer to status word */
  67         u32     ddma_dbell;     /* A write activates channel operation */
  68         u32     ddma_irq;       /* If bit 0 set, interrupt pending */
  69         u32     ddma_stat;      /* See below */
  70         u32     ddma_bytecnt;   /* Byte count, valid only when chan idle */
  71         /* Remainder, up to the 256 byte boundary, is reserved. */
  72 } au1x_dma_chan_t;
  73
  74 #define DDMA_CFG_SED    (1 << 9)        /* source DMA level/edge detect */
  75 #define DDMA_CFG_SP     (1 << 8)        /* source DMA polarity */
  76 #define DDMA_CFG_DED    (1 << 7)        /* destination DMA level/edge detect */
  77 #define DDMA_CFG_DP     (1 << 6)        /* destination DMA polarity */
  78 #define DDMA_CFG_SYNC   (1 << 5)        /* Sync static bus controller */
  79 #define DDMA_CFG_PPR    (1 << 4)        /* PCI posted read/write control */
  80 #define DDMA_CFG_DFN    (1 << 3)        /* Descriptor fetch non-coherent */
  81 #define DDMA_CFG_SBE    (1 << 2)        /* Source big endian */
  82 #define DDMA_CFG_DBE    (1 << 1)        /* Destination big endian */
  83 #define DDMA_CFG_EN     (1 << 0)        /* Channel enable */
  84
  85 /*
  86  * Always set when descriptor processing done, regardless of
  87  * interrupt enable state.  Reflected in global intstat, don't
  88  * clear this until global intstat is read/used.
  89  */
  90 #define DDMA_IRQ_IN     (1 << 0)
  91
  92 #define DDMA_STAT_DB    (1 << 2)        /* Doorbell pushed */
  93 #define DDMA_STAT_V     (1 << 1)        /* Descriptor valid */
  94 #define DDMA_STAT_H     (1 << 0)        /* Channel Halted */
  95
  96 /*
  97  * "Standard" DDMA Descriptor.
  98  * Must be 32-byte aligned.
  99  */
 100 typedef volatile struct au1xxx_ddma_desc {
 101         u32     dscr_cmd0;              /* See below */
 102         u32     dscr_cmd1;              /* See below */
 103         u32     dscr_source0;           /* source phys address */
 104         u32     dscr_source1;           /* See below */
 105         u32     dscr_dest0;             /* Destination address */
 106         u32     dscr_dest1;             /* See below */
 107         u32     dscr_stat;              /* completion status */
 108         u32     dscr_nxtptr;            /* Next descriptor pointer (mostly) */
 109         /*
 110          * First 32 bytes are HW specific!!!
 111          * Lets have some SW data following -- make sure it's 32 bytes.
 112          */
 113         u32     sw_status;
 114         u32     sw_context;
 115         u32     sw_reserved[6];
 116 } au1x_ddma_desc_t;
 117
 118 #define DSCR_CMD0_V             (1 << 31)       /* Descriptor valid */
 119 #define DSCR_CMD0_MEM           (1 << 30)       /* mem-mem transfer */
 120 #define DSCR_CMD0_SID_MASK      (0x1f << 25)    /* Source ID */
 121 #define DSCR_CMD0_DID_MASK      (0x1f << 20)    /* Destination ID */
 122 #define DSCR_CMD0_SW_MASK       (0x3 << 18)     /* Source Width */
 123 #define DSCR_CMD0_DW_MASK       (0x3 << 16)     /* Destination Width */
 124 #define DSCR_CMD0_ARB           (0x1 << 15)     /* Set for Hi Pri */
 125 #define DSCR_CMD0_DT_MASK       (0x3 << 13)     /* Descriptor Type */
 126 #define DSCR_CMD0_SN            (0x1 << 12)     /* Source non-coherent */
 127 #define DSCR_CMD0_DN            (0x1 << 11)     /* Destination non-coherent */
 128 #define DSCR_CMD0_SM            (0x1 << 10)     /* Stride mode */
 129 #define DSCR_CMD0_IE            (0x1 << 8)      /* Interrupt Enable */
 130 #define DSCR_CMD0_SP            (0x1 << 4)      /* Status pointer select */
 131 #define DSCR_CMD0_CV            (0x1 << 2)      /* Clear Valid when done */
 132 #define DSCR_CMD0_ST_MASK       (0x3 << 0)      /* Status instruction */
 133
 134 #define SW_STATUS_INUSE         (1 << 0)
 135
 136 /* Command 0 device IDs. */
 137 #ifdef CONFIG_SOC_AU1550
 138 #define DSCR_CMD0_UART0_TX      0
 139 #define DSCR_CMD0_UART0_RX      1
 140 #define DSCR_CMD0_UART3_TX      2
 141 #define DSCR_CMD0_UART3_RX      3
 142 #define DSCR_CMD0_DMA_REQ0      4
 143 #define DSCR_CMD0_DMA_REQ1      5
 144 #define DSCR_CMD0_DMA_REQ2      6
 145 #define DSCR_CMD0_DMA_REQ3      7
 146 #define DSCR_CMD0_USBDEV_RX0    8
 147 #define DSCR_CMD0_USBDEV_TX0    9
 148 #define DSCR_CMD0_USBDEV_TX1    10
 149 #define DSCR_CMD0_USBDEV_TX2    11
 150 #define DSCR_CMD0_USBDEV_RX3    12
 151 #define DSCR_CMD0_USBDEV_RX4    13
 152 #define DSCR_CMD0_PSC0_TX       14
 153 #define DSCR_CMD0_PSC0_RX       15
 154 #define DSCR_CMD0_PSC1_TX       16
 155 #define DSCR_CMD0_PSC1_RX       17
 156 #define DSCR_CMD0_PSC2_TX       18
 157 #define DSCR_CMD0_PSC2_RX       19
 158 #define DSCR_CMD0_PSC3_TX       20
 159 #define DSCR_CMD0_PSC3_RX       21
 160 #define DSCR_CMD0_PCI_WRITE     22
 161 #define DSCR_CMD0_NAND_FLASH    23
 162 #define DSCR_CMD0_MAC0_RX       24
 163 #define DSCR_CMD0_MAC0_TX       25
 164 #define DSCR_CMD0_MAC1_RX       26
 165 #define DSCR_CMD0_MAC1_TX       27
 166 #endif /* CONFIG_SOC_AU1550 */
 167
 168 #ifdef CONFIG_SOC_AU1200
 169 #define DSCR_CMD0_UART0_TX      0
 170 #define DSCR_CMD0_UART0_RX      1
 171 #define DSCR_CMD0_UART1_TX      2
 172 #define DSCR_CMD0_UART1_RX      3
 173 #define DSCR_CMD0_DMA_REQ0      4
 174 #define DSCR_CMD0_DMA_REQ1      5
 175 #define DSCR_CMD0_MAE_BE        6
 176 #define DSCR_CMD0_MAE_FE        7
 177 #define DSCR_CMD0_SDMS_TX0      8
 178 #define DSCR_CMD0_SDMS_RX0      9
 179 #define DSCR_CMD0_SDMS_TX1      10
 180 #define DSCR_CMD0_SDMS_RX1      11
 181 #define DSCR_CMD0_AES_TX        13
 182 #define DSCR_CMD0_AES_RX        12
 183 #define DSCR_CMD0_PSC0_TX       14
 184 #define DSCR_CMD0_PSC0_RX       15
 185 #define DSCR_CMD0_PSC1_TX       16
 186 #define DSCR_CMD0_PSC1_RX       17
 187 #define DSCR_CMD0_CIM_RXA       18
 188 #define DSCR_CMD0_CIM_RXB       19
 189 #define DSCR_CMD0_CIM_RXC       20
 190 #define DSCR_CMD0_MAE_BOTH      21
 191 #define DSCR_CMD0_LCD           22
 192 #define DSCR_CMD0_NAND_FLASH    23
 193 #define DSCR_CMD0_PSC0_SYNC     24
 194 #define DSCR_CMD0_PSC1_SYNC     25
 195 #define DSCR_CMD0_CIM_SYNC      26
 196 #endif /* CONFIG_SOC_AU1200 */
 197
 198 #define DSCR_CMD0_THROTTLE      30
 199 #define DSCR_CMD0_ALWAYS        31
 200 #define DSCR_NDEV_IDS           32
 201 /* This macro is used to find/create custom device types */
 202 #define DSCR_DEV2CUSTOM_ID(x, d) (((((x) & 0xFFFF) << 8) | 0x32000000) | \
 203                                   ((d) & 0xFF))
 204 #define DSCR_CUSTOM2DEV_ID(x)   ((x) & 0xFF)
 205
 206 #define DSCR_CMD0_SID(x)        (((x) & 0x1f) << 25)
 207 #define DSCR_CMD0_DID(x)        (((x) & 0x1f) << 20)
 208
 209 /* Source/Destination transfer width. */
 210 #define DSCR_CMD0_BYTE          0
 211 #define DSCR_CMD0_HALFWORD      1
 212 #define DSCR_CMD0_WORD          2
 213
 214 #define DSCR_CMD0_SW(x)         (((x) & 0x3) << 18)
 215 #define DSCR_CMD0_DW(x)         (((x) & 0x3) << 16)
 216
 217 /* DDMA Descriptor Type. */
 218 #define DSCR_CMD0_STANDARD      0
 219 #define DSCR_CMD0_LITERAL       1
 220 #define DSCR_CMD0_CMP_BRANCH    2
 221
 222 #define DSCR_CMD0_DT(x)         (((x) & 0x3) << 13)
 223
 224 /* Status Instruction. */
 225 #define DSCR_CMD0_ST_NOCHANGE   0       /* Don't change */
 226 #define DSCR_CMD0_ST_CURRENT    1       /* Write current status */
 227 #define DSCR_CMD0_ST_CMD0       2       /* Write cmd0 with V cleared */
 228 #define DSCR_CMD0_ST_BYTECNT    3       /* Write remaining byte count */
 229
 230 #define DSCR_CMD0_ST(x)         (((x) & 0x3) << 0)
 231
 232 /* Descriptor Command 1. */
 233 #define DSCR_CMD1_SUPTR_MASK    (0xf << 28)     /* upper 4 bits of src addr */
 234 #define DSCR_CMD1_DUPTR_MASK    (0xf << 24)     /* upper 4 bits of dest addr */
 235 #define DSCR_CMD1_FL_MASK       (0x3 << 22)     /* Flag bits */
 236 #define DSCR_CMD1_BC_MASK       (0x3fffff)      /* Byte count */
 237
 238 /* Flag description. */
 239 #define DSCR_CMD1_FL_MEM_STRIDE0        0
 240 #define DSCR_CMD1_FL_MEM_STRIDE1        1
 241 #define DSCR_CMD1_FL_MEM_STRIDE2        2
 242
 243 #define DSCR_CMD1_FL(x)         (((x) & 0x3) << 22)
 244
 245 /* Source1, 1-dimensional stride. */
 246 #define DSCR_SRC1_STS_MASK      (3 << 30)       /* Src xfer size */
 247 #define DSCR_SRC1_SAM_MASK      (3 << 28)       /* Src xfer movement */
 248 #define DSCR_SRC1_SB_MASK       (0x3fff << 14)  /* Block size */
 249 #define DSCR_SRC1_SB(x)         (((x) & 0x3fff) << 14)
 250 #define DSCR_SRC1_SS_MASK       (0x3fff << 0)   /* Stride */
 251 #define DSCR_SRC1_SS(x)         (((x) & 0x3fff) << 0)
 252
 253 /* Dest1, 1-dimensional stride. */
 254 #define DSCR_DEST1_DTS_MASK     (3 << 30)       /* Dest xfer size */
 255 #define DSCR_DEST1_DAM_MASK     (3 << 28)       /* Dest xfer movement */
 256 #define DSCR_DEST1_DB_MASK      (0x3fff << 14)  /* Block size */
 257 #define DSCR_DEST1_DB(x)        (((x) & 0x3fff) << 14)
 258 #define DSCR_DEST1_DS_MASK      (0x3fff << 0)   /* Stride */
 259 #define DSCR_DEST1_DS(x)        (((x) & 0x3fff) << 0)
 260
 261 #define DSCR_xTS_SIZE1          0
 262 #define DSCR_xTS_SIZE2          1
 263 #define DSCR_xTS_SIZE4          2
 264 #define DSCR_xTS_SIZE8          3
 265 #define DSCR_SRC1_STS(x)        (((x) & 3) << 30)
 266 #define DSCR_DEST1_DTS(x)       (((x) & 3) << 30)
 267
 268 #define DSCR_xAM_INCREMENT      0
 269 #define DSCR_xAM_DECREMENT      1
 270 #define DSCR_xAM_STATIC         2
 271 #define DSCR_xAM_BURST          3
 272 #define DSCR_SRC1_SAM(x)        (((x) & 3) << 28)
 273 #define DSCR_DEST1_DAM(x)       (((x) & 3) << 28)
 274
 275 /* The next descriptor pointer. */
 276 #define DSCR_NXTPTR_MASK        (0x07ffffff)
 277 #define DSCR_NXTPTR(x)          ((x) >> 5)
 278 #define DSCR_GET_NXTPTR(x)      ((x) << 5)
 279 #define DSCR_NXTPTR_MS          (1 << 27)
 280
 281 /* The number of DBDMA channels. */
 282 #define NUM_DBDMA_CHANS 16
 283
 284 /*
 285  * DDMA API definitions
 286  * FIXME: may not fit to this header file
 287  */
 288 typedef struct dbdma_device_table {
 289         u32     dev_id;
 290         u32     dev_flags;
 291         u32     dev_tsize;
 292         u32     dev_devwidth;
 293         u32     dev_physaddr;           /* If FIFO */
 294         u32     dev_intlevel;
 295         u32     dev_intpolarity;
 296 } dbdev_tab_t;
 297
 298
 299 typedef struct dbdma_chan_config {
 300         spinlock_t      lock;
 301
 302         u32                     chan_flags;
 303         u32                     chan_index;
 304         dbdev_tab_t             *chan_src;
 305         dbdev_tab_t             *chan_dest;
 306         au1x_dma_chan_t         *chan_ptr;
 307         au1x_ddma_desc_t        *chan_desc_base;
 308         au1x_ddma_desc_t        *get_ptr, *put_ptr, *cur_ptr;
 309         void                    *chan_callparam;
 310         void                    (*chan_callback)(int, void *);
 311 } chan_tab_t;
 312
 313 #define DEV_FLAGS_INUSE         (1 << 0)
 314 #define DEV_FLAGS_ANYUSE        (1 << 1)
 315 #define DEV_FLAGS_OUT           (1 << 2)
 316 #define DEV_FLAGS_IN            (1 << 3)
 317 #define DEV_FLAGS_BURSTABLE     (1 << 4)
 318 #define DEV_FLAGS_SYNC          (1 << 5)
 319 /* end DDMA API definitions */
 320
 321 /*
 322  * External functions for drivers to use.
 323  * Use this to allocate a DBDMA channel.  The device IDs are one of
 324  * the DSCR_CMD0 devices IDs, which is usually redefined to a more
 325  * meaningful name.  The 'callback' is called during DMA completion
 326  * interrupt.
 327  */
 328 extern u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
 329                                    void (*callback)(int, void *),
 330                                    void *callparam);
 331
 332 #define DBDMA_MEM_CHAN  DSCR_CMD0_ALWAYS
 333
 334 /* Set the device width of an in/out FIFO. */
 335 u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
 336
 337 /* Allocate a ring of descriptors for DBDMA. */
 338 u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
 339
 340 /* Put buffers on source/destination descriptors. */
 341 u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags);
 342 u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags);
 343
 344 /* Get a buffer from the destination descriptor. */
 345 u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes);
 346
 347 void au1xxx_dbdma_stop(u32 chanid);
 348 void au1xxx_dbdma_start(u32 chanid);
 349 void au1xxx_dbdma_reset(u32 chanid);
 350 u32 au1xxx_get_dma_residue(u32 chanid);
 351
 352 void au1xxx_dbdma_chan_free(u32 chanid);
 353 void au1xxx_dbdma_dump(u32 chanid);
 354
 355 u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr);
 356
 357 u32 au1xxx_ddma_add_device(dbdev_tab_t *dev);
 358 extern void au1xxx_ddma_del_device(u32 devid);
 359 void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
 360 #ifdef CONFIG_PM
 361 void au1xxx_dbdma_suspend(void);
 362 void au1xxx_dbdma_resume(void);
 363 #endif
 364
 365
 366 /*
 367  * Some compatibilty macros -- needed to make changes to API
 368  * without breaking existing drivers.
 369  */
 370 #define au1xxx_dbdma_put_source(chanid, buf, nbytes)                    \
 371         _au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
 372 #define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags)       \
 373         _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
 374 #define put_source_flags(chanid, buf, nbytes, flags)                    \
 375         au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags)
 376
 377 #define au1xxx_dbdma_put_dest(chanid, buf, nbytes)                      \
 378         _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
 379 #define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags)         \
 380         _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
 381 #define put_dest_flags(chanid, buf, nbytes, flags)                      \
 382         au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags)
 383
 384 /*
 385  *      Flags for the put_source/put_dest functions.
 386  */
 387 #define DDMA_FLAGS_IE   (1 << 0)
 388 #define DDMA_FLAGS_NOIE (1 << 1)
 389
 390 #endif /* _LANGUAGE_ASSEMBLY */
 391 #endif /* _AU1000_DBDMA_H_ */