kernel/2.6.29.6-aldebaran-rt/arch/ia64/include/asm/pci.h

   1 #ifndef _ASM_IA64_PCI_H
   2 #define _ASM_IA64_PCI_H
   3
   4 #include <linux/mm.h>
   5 #include <linux/slab.h>
   6 #include <linux/spinlock.h>
   7 #include <linux/string.h>
   8 #include <linux/types.h>
   9
  10 #include <asm/io.h>
  11 #include <asm/scatterlist.h>
  12 #include <asm/hw_irq.h>
  13
  14 /*
  15  * Can be used to override the logic in pci_scan_bus for skipping already-configured bus
  16  * numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the
  17  * loader.
  18  */
  19 #define pcibios_assign_all_busses()     0
  20 #define pcibios_scan_all_fns(a, b)      0
  21
  22 #define PCIBIOS_MIN_IO          0x1000
  23 #define PCIBIOS_MIN_MEM         0x10000000
  24
  25 void pcibios_config_init(void);
  26
  27 struct pci_dev;
  28
  29 /*
  30  * PCI_DMA_BUS_IS_PHYS should be set to 1 if there is _necessarily_ a direct
  31  * correspondence between device bus addresses and CPU physical addresses.
  32  * Platforms with a hardware I/O MMU _must_ turn this off to suppress the
  33  * bounce buffer handling code in the block and network device layers.
  34  * Platforms with separate bus address spaces _must_ turn this off and provide
  35  * a device DMA mapping implementation that takes care of the necessary
  36  * address translation.
  37  *
  38  * For now, the ia64 platforms which may have separate/multiple bus address
  39  * spaces all have I/O MMUs which support the merging of physically
  40  * discontiguous buffers, so we can use that as the sole factor to determine
  41  * the setting of PCI_DMA_BUS_IS_PHYS.
  42  */
  43 extern unsigned long ia64_max_iommu_merge_mask;
  44 #define PCI_DMA_BUS_IS_PHYS     (ia64_max_iommu_merge_mask == ~0UL)
  45
  46 static inline void
  47 pcibios_set_master (struct pci_dev *dev)
  48 {
  49         /* No special bus mastering setup handling */
  50 }
  51
  52 static inline void
  53 pcibios_penalize_isa_irq (int irq, int active)
  54 {
  55         /* We don't do dynamic PCI IRQ allocation */
  56 }
  57
  58 #include <asm-generic/pci-dma-compat.h>
  59
  60 /* pci_unmap_{single,page} is not a nop, thus... */
  61 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       \
  62         dma_addr_t ADDR_NAME;
  63 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME)         \
  64         __u32 LEN_NAME;
  65 #define pci_unmap_addr(PTR, ADDR_NAME)                  \
  66         ((PTR)->ADDR_NAME)
  67 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)         \
  68         (((PTR)->ADDR_NAME) = (VAL))
  69 #define pci_unmap_len(PTR, LEN_NAME)                    \
  70         ((PTR)->LEN_NAME)
  71 #define pci_unmap_len_set(PTR, LEN_NAME, VAL)           \
  72         (((PTR)->LEN_NAME) = (VAL))
  73
  74 #ifdef CONFIG_PCI
  75 static inline void pci_dma_burst_advice(struct pci_dev *pdev,
  76                                         enum pci_dma_burst_strategy *strat,
  77                                         unsigned long *strategy_parameter)
  78 {
  79         unsigned long cacheline_size;
  80         u8 byte;
  81
  82         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
  83         if (byte == 0)
  84                 cacheline_size = 1024;
  85         else
  86                 cacheline_size = (int) byte * 4;
  87
  88         *strat = PCI_DMA_BURST_MULTIPLE;
  89         *strategy_parameter = cacheline_size;
  90 }
  91 #endif
  92
  93 #define HAVE_PCI_MMAP
  94 extern int pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
  95                                 enum pci_mmap_state mmap_state, int write_combine);
  96 #define HAVE_PCI_LEGACY
  97 extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
  98                                       struct vm_area_struct *vma,
  99                                       enum pci_mmap_state mmap_state);
 100
 101 #define pci_get_legacy_mem platform_pci_get_legacy_mem
 102 #define pci_legacy_read platform_pci_legacy_read
 103 #define pci_legacy_write platform_pci_legacy_write
 104
 105 struct pci_window {
 106         struct resource resource;
 107         u64 offset;
 108 };
 109
 110 struct pci_controller {
 111         void *acpi_handle;
 112         void *iommu;
 113         int segment;
 114         int node;               /* nearest node with memory or -1 for global allocation */
 115
 116         unsigned int windows;
 117         struct pci_window *window;
 118
 119         void *platform_data;
 120 };
 121
 122 #define PCI_CONTROLLER(busdev) ((struct pci_controller *) busdev->sysdata)
 123 #define pci_domain_nr(busdev)    (PCI_CONTROLLER(busdev)->segment)
 124
 125 extern struct pci_ops pci_root_ops;
 126
 127 static inline int pci_proc_domain(struct pci_bus *bus)
 128 {
 129         return (pci_domain_nr(bus) != 0);
 130 }
 131
 132 extern void pcibios_resource_to_bus(struct pci_dev *dev,
 133                 struct pci_bus_region *region, struct resource *res);
 134
 135 extern void pcibios_bus_to_resource(struct pci_dev *dev,
 136                 struct resource *res, struct pci_bus_region *region);
 137
 138 static inline struct resource *
 139 pcibios_select_root(struct pci_dev *pdev, struct resource *res)
 140 {
 141         struct resource *root = NULL;
 142
 143         if (res->flags & IORESOURCE_IO)
 144                 root = &ioport_resource;
 145         if (res->flags & IORESOURCE_MEM)
 146                 root = &iomem_resource;
 147
 148         return root;
 149 }
 150
 151 #define pcibios_scan_all_fns(a, b)      0
 152
 153 #define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
 154 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 155 {
 156         return channel ? isa_irq_to_vector(15) : isa_irq_to_vector(14);
 157 }
 158
 159 #ifdef CONFIG_DMAR
 160 extern void pci_iommu_alloc(void);
 161 #endif
 162 #endif /* _ASM_IA64_PCI_H */