kernel/2.6.29.6-aldebaran-rt/arch/blackfin/mach-bf548/dma.c

   1 /*
   2  * File:         arch/blackfin/mach-bf548/dma.c
   3  * Based on:
   4  * Author:
   5  *
   6  * Created:
   7  * Description:  This file contains the simple DMA Implementation for Blackfin
   8  *
   9  * Modified:
  10  *               Copyright 2004-2008 Analog Devices Inc.
  11  *
  12  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, see the file COPYING, or write
  26  * to the Free Software Foundation, Inc.,
  27  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  28  */
  29
  30 #include <linux/module.h>
  31
  32 #include <asm/blackfin.h>
  33 #include <asm/dma.h>
  34
  35 struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
  36         (struct dma_register *) DMA0_NEXT_DESC_PTR,
  37         (struct dma_register *) DMA1_NEXT_DESC_PTR,
  38         (struct dma_register *) DMA2_NEXT_DESC_PTR,
  39         (struct dma_register *) DMA3_NEXT_DESC_PTR,
  40         (struct dma_register *) DMA4_NEXT_DESC_PTR,
  41         (struct dma_register *) DMA5_NEXT_DESC_PTR,
  42         (struct dma_register *) DMA6_NEXT_DESC_PTR,
  43         (struct dma_register *) DMA7_NEXT_DESC_PTR,
  44         (struct dma_register *) DMA8_NEXT_DESC_PTR,
  45         (struct dma_register *) DMA9_NEXT_DESC_PTR,
  46         (struct dma_register *) DMA10_NEXT_DESC_PTR,
  47         (struct dma_register *) DMA11_NEXT_DESC_PTR,
  48         (struct dma_register *) DMA12_NEXT_DESC_PTR,
  49         (struct dma_register *) DMA13_NEXT_DESC_PTR,
  50         (struct dma_register *) DMA14_NEXT_DESC_PTR,
  51         (struct dma_register *) DMA15_NEXT_DESC_PTR,
  52         (struct dma_register *) DMA16_NEXT_DESC_PTR,
  53         (struct dma_register *) DMA17_NEXT_DESC_PTR,
  54         (struct dma_register *) DMA18_NEXT_DESC_PTR,
  55         (struct dma_register *) DMA19_NEXT_DESC_PTR,
  56         (struct dma_register *) DMA20_NEXT_DESC_PTR,
  57         (struct dma_register *) DMA21_NEXT_DESC_PTR,
  58         (struct dma_register *) DMA22_NEXT_DESC_PTR,
  59         (struct dma_register *) DMA23_NEXT_DESC_PTR,
  60         (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
  61         (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
  62         (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
  63         (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
  64         (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
  65         (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
  66         (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
  67         (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
  68 };
  69 EXPORT_SYMBOL(dma_io_base_addr);
  70
  71 int channel2irq(unsigned int channel)
  72 {
  73         int ret_irq = -1;
  74
  75         switch (channel) {
  76         case CH_SPORT0_RX:
  77                 ret_irq = IRQ_SPORT0_RX;
  78                 break;
  79         case CH_SPORT0_TX:
  80                 ret_irq = IRQ_SPORT0_TX;
  81                 break;
  82         case CH_SPORT1_RX:
  83                 ret_irq = IRQ_SPORT1_RX;
  84                 break;
  85         case CH_SPORT1_TX:
  86                 ret_irq = IRQ_SPORT1_TX;
  87         case CH_SPI0:
  88                 ret_irq = IRQ_SPI0;
  89                 break;
  90         case CH_SPI1:
  91                 ret_irq = IRQ_SPI1;
  92                 break;
  93         case CH_UART0_RX:
  94                 ret_irq = IRQ_UART_RX;
  95                 break;
  96         case CH_UART0_TX:
  97                 ret_irq = IRQ_UART_TX;
  98                 break;
  99         case CH_UART1_RX:
 100                 ret_irq = IRQ_UART_RX;
 101                 break;
 102         case CH_UART1_TX:
 103                 ret_irq = IRQ_UART_TX;
 104                 break;
 105         case CH_EPPI0:
 106                 ret_irq = IRQ_EPPI0;
 107                 break;
 108         case CH_EPPI1:
 109                 ret_irq = IRQ_EPPI1;
 110                 break;
 111         case CH_EPPI2:
 112                 ret_irq = IRQ_EPPI2;
 113                 break;
 114         case CH_PIXC_IMAGE:
 115                 ret_irq = IRQ_PIXC_IN0;
 116                 break;
 117         case CH_PIXC_OVERLAY:
 118                 ret_irq = IRQ_PIXC_IN1;
 119                 break;
 120         case CH_PIXC_OUTPUT:
 121                 ret_irq = IRQ_PIXC_OUT;
 122                 break;
 123         case CH_SPORT2_RX:
 124                 ret_irq = IRQ_SPORT2_RX;
 125                 break;
 126         case CH_SPORT2_TX:
 127                 ret_irq = IRQ_SPORT2_TX;
 128                 break;
 129         case CH_SPORT3_RX:
 130                 ret_irq = IRQ_SPORT3_RX;
 131                 break;
 132         case CH_SPORT3_TX:
 133                 ret_irq = IRQ_SPORT3_TX;
 134                 break;
 135         case CH_SDH:
 136                 ret_irq = IRQ_SDH;
 137                 break;
 138         case CH_SPI2:
 139                 ret_irq = IRQ_SPI2;
 140                 break;
 141         case CH_MEM_STREAM0_SRC:
 142         case CH_MEM_STREAM0_DEST:
 143                 ret_irq = IRQ_MDMAS0;
 144                 break;
 145         case CH_MEM_STREAM1_SRC:
 146         case CH_MEM_STREAM1_DEST:
 147                 ret_irq = IRQ_MDMAS1;
 148                 break;
 149         case CH_MEM_STREAM2_SRC:
 150         case CH_MEM_STREAM2_DEST:
 151                 ret_irq = IRQ_MDMAS2;
 152                 break;
 153         case CH_MEM_STREAM3_SRC:
 154         case CH_MEM_STREAM3_DEST:
 155                 ret_irq = IRQ_MDMAS3;
 156                 break;
 157         }
 158         return ret_irq;
 159 }