kernel/2.6.29.6-aldebaran-rt/arch/blackfin/mach-bf533/include/mach/blackfin.h

   1 /*
   2  * File:         include/asm-blackfin/mach-bf533/blackfin.h
   3  * Based on:
   4  * Author:
   5  *
   6  * Created:
   7  * Description:
   8  *
   9  * Rev:
  10  *
  11  * Modified:
  12  *
  13  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2, or (at your option)
  18  * any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; see the file COPYING.
  27  * If not, write to the Free Software Foundation,
  28  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  29  */
  30
  31 #ifndef _MACH_BLACKFIN_H_
  32 #define _MACH_BLACKFIN_H_
  33
  34 #define BF533_FAMILY
  35
  36 #include "bf533.h"
  37 #include "mem_map.h"
  38 #include "defBF532.h"
  39 #include "anomaly.h"
  40
  41 #if !defined(__ASSEMBLY__)
  42 #include "cdefBF532.h"
  43 #endif
  44
  45 #define BFIN_UART_NR_PORTS      1
  46
  47 #define CH_UART_RX CH_UART0_RX
  48 #define CH_UART_TX CH_UART0_TX
  49
  50 #define IRQ_UART_ERROR IRQ_UART0_ERROR
  51 #define IRQ_UART_RX    IRQ_UART0_RX
  52 #define IRQ_UART_TX    IRQ_UART0_TX
  53
  54 #define OFFSET_THR              0x00    /* Transmit Holding register            */
  55 #define OFFSET_RBR              0x00    /* Receive Buffer register              */
  56 #define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
  57 #define OFFSET_IER              0x04    /* Interrupt Enable Register            */
  58 #define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
  59 #define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
  60 #define OFFSET_LCR              0x0C    /* Line Control Register                */
  61 #define OFFSET_MCR              0x10    /* Modem Control Register               */
  62 #define OFFSET_LSR              0x14    /* Line Status Register                 */
  63 #define OFFSET_MSR              0x18    /* Modem Status Register                */
  64 #define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
  65 #define OFFSET_GCTL             0x24    /* Global Control Register              */
  66
  67 #endif                          /* _MACH_BLACKFIN_H_ */