kernel/2.6.29.6-aldebaran-rt/arch/blackfin/mach-bf518/ints-priority.c

   1 /*
   2  * File:         arch/blackfin/mach-bf518/ints-priority.c
   3  * Based on:     arch/blackfin/mach-bf527/ints-priority.c
   4  * Author:       Bryan Wu <cooloney@kernel.org>
   5  *
   6  * Created:
   7  * Description:  Set up the interrupt priorities
   8  *
   9  * Modified:
  10  *               Copyright 2004-2007 Analog Devices Inc.
  11  *
  12  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, see the file COPYING, or write
  26  * to the Free Software Foundation, Inc.,
  27  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  28  */
  29
  30 #include <linux/module.h>
  31 #include <linux/irq.h>
  32 #include <asm/blackfin.h>
  33
  34 void __init program_IAR(void)
  35 {
  36         /* Program the IAR0 Register with the configured priority */
  37         bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
  38                         ((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) |
  39                         ((CONFIG_IRQ_DMAR0_BLK - 7) << IRQ_DMAR0_BLK_POS) |
  40                         ((CONFIG_IRQ_DMAR1_BLK - 7) << IRQ_DMAR1_BLK_POS) |
  41                         ((CONFIG_IRQ_DMAR0_OVR - 7) << IRQ_DMAR0_OVR_POS) |
  42                         ((CONFIG_IRQ_DMAR1_OVR - 7) << IRQ_DMAR1_OVR_POS) |
  43                         ((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) |
  44                         ((CONFIG_IRQ_MAC_ERROR - 7) << IRQ_MAC_ERROR_POS));
  45
  46
  47         bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
  48                         ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) |
  49                         ((CONFIG_IRQ_PTP_ERROR - 7) << IRQ_PTP_ERROR_POS) |
  50                         ((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) |
  51                         ((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) |
  52                         ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) |
  53                         ((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS));
  54
  55         bfin_write_SIC_IAR2(((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
  56                         ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
  57                         ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
  58                         ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
  59                         ((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) |
  60                         ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
  61                         ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
  62                         ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
  63
  64         bfin_write_SIC_IAR3(((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
  65                         ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
  66                         ((CONFIG_IRQ_OPTSEC - 7) << IRQ_OPTSEC_POS) |
  67                         ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
  68                         ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
  69                         ((CONFIG_IRQ_PORTH_INTA - 7) << IRQ_PORTH_INTA_POS) |
  70                         ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
  71                         ((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS));
  72
  73         bfin_write_SIC_IAR4(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
  74                         ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
  75                         ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
  76                         ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
  77                         ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) |
  78                         ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
  79                         ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
  80                         ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS));
  81
  82         bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) |
  83                         ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
  84                         ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
  85                         ((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) |
  86                         ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS) |
  87                         ((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) |
  88                         ((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) |
  89                         ((CONFIG_IRQ_SPI0_ERROR - 7) << IRQ_SPI0_ERROR_POS));
  90
  91         bfin_write_SIC_IAR6(((CONFIG_IRQ_SPI1_ERROR - 7) << IRQ_SPI1_ERROR_POS) |
  92                         ((CONFIG_IRQ_RSI_INT0 - 7) << IRQ_RSI_INT0_POS) |
  93                         ((CONFIG_IRQ_RSI_INT1 - 7) << IRQ_RSI_INT1_POS) |
  94                         ((CONFIG_IRQ_PWM_TRIP - 7) << IRQ_PWM_TRIP_POS) |
  95                         ((CONFIG_IRQ_PWM_SYNC - 7) << IRQ_PWM_SYNC_POS) |
  96                         ((CONFIG_IRQ_PTP_STAT - 7) << IRQ_PTP_STAT_POS));
  97
  98         SSYNC();
  99 }