kernel/2.6.29.6-aldebaran-rt/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h

   1 /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h
   2  *
   3  * Copyright 2008 Openmoko, Inc.
   4  * Copyright 2008 Simtec Electronics
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *      http://armlinux.simtec.co.uk/
   7  *
   8  * GPIO Bank A register and configuration definitions
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13 */
  14
  15 #define S3C64XX_GPACON                  (S3C64XX_GPA_BASE + 0x00)
  16 #define S3C64XX_GPADAT                  (S3C64XX_GPA_BASE + 0x04)
  17 #define S3C64XX_GPAPUD                  (S3C64XX_GPA_BASE + 0x08)
  18 #define S3C64XX_GPACONSLP               (S3C64XX_GPA_BASE + 0x0c)
  19 #define S3C64XX_GPAPUDSLP               (S3C64XX_GPA_BASE + 0x10)
  20
  21 #define S3C64XX_GPA_CONMASK(__gpio)     (0xf << ((__gpio) * 4))
  22 #define S3C64XX_GPA_INPUT(__gpio)       (0x0 << ((__gpio) * 4))
  23 #define S3C64XX_GPA_OUTPUT(__gpio)      (0x1 << ((__gpio) * 4))
  24
  25 #define S3C64XX_GPA0_UART_RXD0          (0x02 << 0)
  26 #define S3C64XX_GPA0_EINT_G1_0          (0x07 << 0)
  27
  28 #define S3C64XX_GPA1_UART_TXD0          (0x02 << 4)
  29 #define S3C64XX_GPA1_EINT_G1_1          (0x07 << 4)
  30
  31 #define S3C64XX_GPA2_UART_nCTS0         (0x02 << 8)
  32 #define S3C64XX_GPA2_EINT_G1_2          (0x07 << 8)
  33
  34 #define S3C64XX_GPA3_UART_nRTS0         (0x02 << 12)
  35 #define S3C64XX_GPA3_EINT_G1_3          (0x07 << 12)
  36
  37 #define S3C64XX_GPA4_UART_RXD1          (0x02 << 16)
  38 #define S3C64XX_GPA4_EINT_G1_4          (0x07 << 16)
  39
  40 #define S3C64XX_GPA5_UART_TXD1          (0x02 << 20)
  41 #define S3C64XX_GPA5_EINT_G1_5          (0x07 << 20)
  42
  43 #define S3C64XX_GPA6_UART_nCTS1         (0x02 << 24)
  44 #define S3C64XX_GPA6_EINT_G1_6          (0x07 << 24)
  45
  46 #define S3C64XX_GPA7_UART_nRTS1         (0x02 << 28)
  47 #define S3C64XX_GPA7_EINT_G1_7          (0x07 << 28)
  48