1 /* linux/arch/arm/plat-s3c64xx/clock.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C64XX Base clock support
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/ioport.h>
21 #include <mach/hardware.h>
24 #include <plat/regs-sys.h>
25 #include <plat/regs-clock.h>
27 #include <plat/devs.h>
28 #include <plat/clock.h>
30 struct clk clk_27m
= {
36 static int clk_48m_ctrl(struct clk
*clk
, int enable
)
41 /* can't rely on clock lock, this register has other usages */
42 local_irq_save(flags
);
44 val
= __raw_readl(S3C64XX_OTHERS
);
46 val
|= S3C64XX_OTHERS_USBMASK
;
48 val
&= ~S3C64XX_OTHERS_USBMASK
;
50 __raw_writel(val
, S3C64XX_OTHERS
);
51 local_irq_restore(flags
);
56 struct clk clk_48m
= {
60 .enable
= clk_48m_ctrl
,
63 static int inline s3c64xx_gate(void __iomem
*reg
,
67 unsigned int ctrlbit
= clk
->ctrlbit
;
70 con
= __raw_readl(reg
);
77 __raw_writel(con
, reg
);
81 static int s3c64xx_pclk_ctrl(struct clk
*clk
, int enable
)
83 return s3c64xx_gate(S3C_PCLK_GATE
, clk
, enable
);
86 static int s3c64xx_hclk_ctrl(struct clk
*clk
, int enable
)
88 return s3c64xx_gate(S3C_HCLK_GATE
, clk
, enable
);
91 int s3c64xx_sclk_ctrl(struct clk
*clk
, int enable
)
93 return s3c64xx_gate(S3C_SCLK_GATE
, clk
, enable
);
96 static struct clk init_clocks_disable
[] = {
105 .enable
= s3c64xx_pclk_ctrl
,
106 .ctrlbit
= S3C_CLKCON_PCLK_TSADC
,
111 .enable
= s3c64xx_pclk_ctrl
,
112 .ctrlbit
= S3C_CLKCON_PCLK_IIC
,
117 .enable
= s3c64xx_pclk_ctrl
,
118 .ctrlbit
= S3C_CLKCON_PCLK_IIS0
,
123 .enable
= s3c64xx_pclk_ctrl
,
124 .ctrlbit
= S3C_CLKCON_PCLK_IIS1
,
129 .enable
= s3c64xx_pclk_ctrl
,
130 .ctrlbit
= S3C_CLKCON_PCLK_SPI0
,
135 .enable
= s3c64xx_pclk_ctrl
,
136 .ctrlbit
= S3C_CLKCON_PCLK_SPI1
,
141 .enable
= s3c64xx_sclk_ctrl
,
142 .ctrlbit
= S3C_CLKCON_SCLK_MMC0_48
,
147 .enable
= s3c64xx_sclk_ctrl
,
148 .ctrlbit
= S3C_CLKCON_SCLK_MMC1_48
,
153 .enable
= s3c64xx_sclk_ctrl
,
154 .ctrlbit
= S3C_CLKCON_SCLK_MMC2_48
,
158 static struct clk init_clocks
[] = {
163 .enable
= s3c64xx_hclk_ctrl
,
164 .ctrlbit
= S3C_CLKCON_HCLK_LCD
,
169 .enable
= s3c64xx_pclk_ctrl
,
170 .ctrlbit
= S3C_CLKCON_PCLK_GPIO
,
175 .enable
= s3c64xx_hclk_ctrl
,
176 .ctrlbit
= S3C_CLKCON_SCLK_UHOST
,
181 .enable
= s3c64xx_hclk_ctrl
,
182 .ctrlbit
= S3C_CLKCON_HCLK_HSMMC0
,
187 .enable
= s3c64xx_hclk_ctrl
,
188 .ctrlbit
= S3C_CLKCON_HCLK_HSMMC1
,
193 .enable
= s3c64xx_hclk_ctrl
,
194 .ctrlbit
= S3C_CLKCON_HCLK_HSMMC2
,
199 .enable
= s3c64xx_pclk_ctrl
,
200 .ctrlbit
= S3C_CLKCON_PCLK_PWM
,
205 .enable
= s3c64xx_pclk_ctrl
,
206 .ctrlbit
= S3C_CLKCON_PCLK_UART0
,
211 .enable
= s3c64xx_pclk_ctrl
,
212 .ctrlbit
= S3C_CLKCON_PCLK_UART1
,
217 .enable
= s3c64xx_pclk_ctrl
,
218 .ctrlbit
= S3C_CLKCON_PCLK_UART2
,
223 .enable
= s3c64xx_pclk_ctrl
,
224 .ctrlbit
= S3C_CLKCON_PCLK_UART3
,
229 .enable
= s3c64xx_pclk_ctrl
,
230 .ctrlbit
= S3C_CLKCON_PCLK_RTC
,
235 .ctrlbit
= S3C_CLKCON_PCLK_WDT
,
240 .ctrlbit
= S3C_CLKCON_PCLK_AC97
,
244 static struct clk
*clks
[] __initdata
= {
251 void __init
s3c64xx_register_clocks(void)
257 s3c24xx_register_clocks(clks
, ARRAY_SIZE(clks
));
260 for (ptr
= 0; ptr
< ARRAY_SIZE(init_clocks
); ptr
++, clkp
++) {
261 ret
= s3c24xx_register_clock(clkp
);
263 printk(KERN_ERR
"Failed to register clock %s (%d)\n",
268 clkp
= init_clocks_disable
;
269 for (ptr
= 0; ptr
< ARRAY_SIZE(init_clocks_disable
); ptr
++, clkp
++) {
271 ret
= s3c24xx_register_clock(clkp
);
273 printk(KERN_ERR
"Failed to register clock %s (%d)\n",
277 (clkp
->enable
)(clkp
, 0);