added 2.6.29.6 aldebaran kernel
[nao-ulib.git] / kernel / 2.6.29.6-aldebaran-rt / arch / arm / mach-s3c2412 / dma.c
blob919856c9433f013fb81678a485a32abc8290859c
1 /* linux/arch/arm/mach-s3c2412/dma.c
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2412 DMA selection
8 * http://armlinux.simtec.co.uk/
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/sysdev.h>
18 #include <linux/serial_core.h>
19 #include <linux/io.h>
21 #include <mach/dma.h>
23 #include <plat/dma.h>
24 #include <plat/cpu.h>
26 #include <plat/regs-serial.h>
27 #include <mach/regs-gpio.h>
28 #include <plat/regs-ac97.h>
29 #include <mach/regs-mem.h>
30 #include <mach/regs-lcd.h>
31 #include <mach/regs-sdi.h>
32 #include <asm/plat-s3c24xx/regs-s3c2412-iis.h>
33 #include <asm/plat-s3c24xx/regs-iis.h>
34 #include <plat/regs-spi.h>
36 #define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID }
38 static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
39 [DMACH_XD0] = {
40 .name = "xdreq0",
41 .channels = MAP(S3C2412_DMAREQSEL_XDREQ0),
42 .channels_rx = MAP(S3C2412_DMAREQSEL_XDREQ0),
44 [DMACH_XD1] = {
45 .name = "xdreq1",
46 .channels = MAP(S3C2412_DMAREQSEL_XDREQ1),
47 .channels_rx = MAP(S3C2412_DMAREQSEL_XDREQ1),
49 [DMACH_SDI] = {
50 .name = "sdi",
51 .channels = MAP(S3C2412_DMAREQSEL_SDI),
52 .channels_rx = MAP(S3C2412_DMAREQSEL_SDI),
53 .hw_addr.to = S3C2410_PA_SDI + S3C2410_SDIDATA,
54 .hw_addr.from = S3C2410_PA_SDI + S3C2410_SDIDATA,
56 [DMACH_SPI0] = {
57 .name = "spi0",
58 .channels = MAP(S3C2412_DMAREQSEL_SPI0TX),
59 .channels_rx = MAP(S3C2412_DMAREQSEL_SPI0RX),
60 .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
61 .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
63 [DMACH_SPI1] = {
64 .name = "spi1",
65 .channels = MAP(S3C2412_DMAREQSEL_SPI1TX),
66 .channels_rx = MAP(S3C2412_DMAREQSEL_SPI1RX),
67 .hw_addr.to = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPTDAT,
68 .hw_addr.from = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPRDAT,
70 [DMACH_UART0] = {
71 .name = "uart0",
72 .channels = MAP(S3C2412_DMAREQSEL_UART0_0),
73 .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_0),
74 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
75 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
77 [DMACH_UART1] = {
78 .name = "uart1",
79 .channels = MAP(S3C2412_DMAREQSEL_UART1_0),
80 .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_0),
81 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
82 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
84 [DMACH_UART2] = {
85 .name = "uart2",
86 .channels = MAP(S3C2412_DMAREQSEL_UART2_0),
87 .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_0),
88 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
89 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
91 [DMACH_UART0_SRC2] = {
92 .name = "uart0",
93 .channels = MAP(S3C2412_DMAREQSEL_UART0_1),
94 .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_1),
95 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
96 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
98 [DMACH_UART1_SRC2] = {
99 .name = "uart1",
100 .channels = MAP(S3C2412_DMAREQSEL_UART1_1),
101 .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_1),
102 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
103 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
105 [DMACH_UART2_SRC2] = {
106 .name = "uart2",
107 .channels = MAP(S3C2412_DMAREQSEL_UART2_1),
108 .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_1),
109 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
110 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
112 [DMACH_TIMER] = {
113 .name = "timer",
114 .channels = MAP(S3C2412_DMAREQSEL_TIMER),
115 .channels_rx = MAP(S3C2412_DMAREQSEL_TIMER),
117 [DMACH_I2S_IN] = {
118 .name = "i2s-sdi",
119 .channels = MAP(S3C2412_DMAREQSEL_I2SRX),
120 .channels_rx = MAP(S3C2412_DMAREQSEL_I2SRX),
121 .hw_addr.from = S3C2410_PA_IIS + S3C2412_IISRXD,
123 [DMACH_I2S_OUT] = {
124 .name = "i2s-sdo",
125 .channels = MAP(S3C2412_DMAREQSEL_I2STX),
126 .channels_rx = MAP(S3C2412_DMAREQSEL_I2STX),
127 .hw_addr.to = S3C2410_PA_IIS + S3C2412_IISTXD,
129 [DMACH_USB_EP1] = {
130 .name = "usb-ep1",
131 .channels = MAP(S3C2412_DMAREQSEL_USBEP1),
132 .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP1),
134 [DMACH_USB_EP2] = {
135 .name = "usb-ep2",
136 .channels = MAP(S3C2412_DMAREQSEL_USBEP2),
137 .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP2),
139 [DMACH_USB_EP3] = {
140 .name = "usb-ep3",
141 .channels = MAP(S3C2412_DMAREQSEL_USBEP3),
142 .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP3),
144 [DMACH_USB_EP4] = {
145 .name = "usb-ep4",
146 .channels = MAP(S3C2412_DMAREQSEL_USBEP4),
147 .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP4),
151 static void s3c2412_dma_direction(struct s3c2410_dma_chan *chan,
152 struct s3c24xx_dma_map *map,
153 enum s3c2410_dmasrc dir)
155 unsigned long chsel;
157 if (dir == S3C2410_DMASRC_HW)
158 chsel = map->channels_rx[0];
159 else
160 chsel = map->channels[0];
162 chsel &= ~DMA_CH_VALID;
163 chsel |= S3C2412_DMAREQSEL_HW;
165 writel(chsel, chan->regs + S3C2412_DMA_DMAREQSEL);
168 static void s3c2412_dma_select(struct s3c2410_dma_chan *chan,
169 struct s3c24xx_dma_map *map)
171 s3c2412_dma_direction(chan, map, chan->source);
174 static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = {
175 .select = s3c2412_dma_select,
176 .direction = s3c2412_dma_direction,
177 .dcon_mask = 0,
178 .map = s3c2412_dma_mappings,
179 .map_size = ARRAY_SIZE(s3c2412_dma_mappings),
182 static int __init s3c2412_dma_add(struct sys_device *sysdev)
184 s3c2410_dma_init();
185 return s3c24xx_dma_init_map(&s3c2412_dma_sel);
188 static struct sysdev_driver s3c2412_dma_driver = {
189 .add = s3c2412_dma_add,
192 static int __init s3c2412_dma_init(void)
194 return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_dma_driver);
197 arch_initcall(s3c2412_dma_init);