kernel/2.6.29.6-aldebaran-rt/arch/arm/mach-orion5x/pci.c

   1 /*
   2  * arch/arm/mach-orion5x/pci.c
   3  *
   4  * PCI and PCIe functions for Marvell Orion System On Chip
   5  *
   6  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/pci.h>
  15 #include <linux/mbus.h>
  16 #include <asm/irq.h>
  17 #include <asm/mach/pci.h>
  18 #include <plat/pcie.h>
  19 #include "common.h"
  20
  21 /*****************************************************************************
  22  * Orion has one PCIe controller and one PCI controller.
  23  *
  24  * Note1: The local PCIe bus number is '0'. The local PCI bus number
  25  * follows the scanned PCIe bridged busses, if any.
  26  *
  27  * Note2: It is possible for PCI/PCIe agents to access many subsystem's
  28  * space, by configuring BARs and Address Decode Windows, e.g. flashes on
  29  * device bus, Orion registers, etc. However this code only enable the
  30  * access to DDR banks.
  31  ****************************************************************************/
  32
  33
  34 /*****************************************************************************
  35  * PCIe controller
  36  ****************************************************************************/
  37 #define PCIE_BASE       ((void __iomem *)ORION5X_PCIE_VIRT_BASE)
  38
  39 void __init orion5x_pcie_id(u32 *dev, u32 *rev)
  40 {
  41         *dev = orion_pcie_dev_id(PCIE_BASE);
  42         *rev = orion_pcie_rev(PCIE_BASE);
  43 }
  44
  45 static int pcie_valid_config(int bus, int dev)
  46 {
  47         /*
  48          * Don't go out when trying to access --
  49          * 1. nonexisting device on local bus
  50          * 2. where there's no device connected (no link)
  51          */
  52         if (bus == 0 && dev == 0)
  53                 return 1;
  54
  55         if (!orion_pcie_link_up(PCIE_BASE))
  56                 return 0;
  57
  58         if (bus == 0 && dev != 1)
  59                 return 0;
  60
  61         return 1;
  62 }
  63
  64
  65 /*
  66  * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
  67  * and then reading the PCIE_CONF_DATA register. Need to make sure these
  68  * transactions are atomic.
  69  */
  70 static DEFINE_SPINLOCK(orion5x_pcie_lock);
  71
  72 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
  73                         int size, u32 *val)
  74 {
  75         unsigned long flags;
  76         int ret;
  77
  78         if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
  79                 *val = 0xffffffff;
  80                 return PCIBIOS_DEVICE_NOT_FOUND;
  81         }
  82
  83         spin_lock_irqsave(&orion5x_pcie_lock, flags);
  84         ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
  85         spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
  86
  87         return ret;
  88 }
  89
  90 static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
  91                            int where, int size, u32 *val)
  92 {
  93         int ret;
  94
  95         if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
  96                 *val = 0xffffffff;
  97                 return PCIBIOS_DEVICE_NOT_FOUND;
  98         }
  99
 100         /*
 101          * We only support access to the non-extended configuration
 102          * space when using the WA access method (or we would have to
 103          * sacrifice 256M of CPU virtual address space.)
 104          */
 105         if (where >= 0x100) {
 106                 *val = 0xffffffff;
 107                 return PCIBIOS_DEVICE_NOT_FOUND;
 108         }
 109
 110         ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE,
 111                                     bus, devfn, where, size, val);
 112
 113         return ret;
 114 }
 115
 116 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 117                         int where, int size, u32 val)
 118 {
 119         unsigned long flags;
 120         int ret;
 121
 122         if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
 123                 return PCIBIOS_DEVICE_NOT_FOUND;
 124
 125         spin_lock_irqsave(&orion5x_pcie_lock, flags);
 126         ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
 127         spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
 128
 129         return ret;
 130 }
 131
 132 static struct pci_ops pcie_ops = {
 133         .read = pcie_rd_conf,
 134         .write = pcie_wr_conf,
 135 };
 136
 137
 138 static int __init pcie_setup(struct pci_sys_data *sys)
 139 {
 140         struct resource *res;
 141         int dev;
 142
 143         /*
 144          * Generic PCIe unit setup.
 145          */
 146         orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info);
 147
 148         /*
 149          * Check whether to apply Orion-1/Orion-NAS PCIe config
 150          * read transaction workaround.
 151          */
 152         dev = orion_pcie_dev_id(PCIE_BASE);
 153         if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
 154                 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
 155                                    "read transaction workaround\n");
 156                 orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
 157                                           ORION5X_PCIE_WA_SIZE);
 158                 pcie_ops.read = pcie_rd_conf_wa;
 159         }
 160
 161         /*
 162          * Request resources.
 163          */
 164         res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
 165         if (!res)
 166                 panic("pcie_setup unable to alloc resources");
 167
 168         /*
 169          * IORESOURCE_IO
 170          */
 171         res[0].name = "PCIe I/O Space";
 172         res[0].flags = IORESOURCE_IO;
 173         res[0].start = ORION5X_PCIE_IO_BUS_BASE;
 174         res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1;
 175         if (request_resource(&ioport_resource, &res[0]))
 176                 panic("Request PCIe IO resource failed\n");
 177         sys->resource[0] = &res[0];
 178
 179         /*
 180          * IORESOURCE_MEM
 181          */
 182         res[1].name = "PCIe Memory Space";
 183         res[1].flags = IORESOURCE_MEM;
 184         res[1].start = ORION5X_PCIE_MEM_PHYS_BASE;
 185         res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1;
 186         if (request_resource(&iomem_resource, &res[1]))
 187                 panic("Request PCIe Memory resource failed\n");
 188         sys->resource[1] = &res[1];
 189
 190         sys->resource[2] = NULL;
 191         sys->io_offset = 0;
 192
 193         return 1;
 194 }
 195
 196 /*****************************************************************************
 197  * PCI controller
 198  ****************************************************************************/
 199 #define PCI_MODE                ORION5X_PCI_REG(0xd00)
 200 #define PCI_CMD                 ORION5X_PCI_REG(0xc00)
 201 #define PCI_P2P_CONF            ORION5X_PCI_REG(0x1d14)
 202 #define PCI_CONF_ADDR           ORION5X_PCI_REG(0xc78)
 203 #define PCI_CONF_DATA           ORION5X_PCI_REG(0xc7c)
 204
 205 /*
 206  * PCI_MODE bits
 207  */
 208 #define PCI_MODE_64BIT                  (1 << 2)
 209 #define PCI_MODE_PCIX                   ((1 << 4) | (1 << 5))
 210
 211 /*
 212  * PCI_CMD bits
 213  */
 214 #define PCI_CMD_HOST_REORDER            (1 << 29)
 215
 216 /*
 217  * PCI_P2P_CONF bits
 218  */
 219 #define PCI_P2P_BUS_OFFS                16
 220 #define PCI_P2P_BUS_MASK                (0xff << PCI_P2P_BUS_OFFS)
 221 #define PCI_P2P_DEV_OFFS                24
 222 #define PCI_P2P_DEV_MASK                (0x1f << PCI_P2P_DEV_OFFS)
 223
 224 /*
 225  * PCI_CONF_ADDR bits
 226  */
 227 #define PCI_CONF_REG(reg)               ((reg) & 0xfc)
 228 #define PCI_CONF_FUNC(func)             (((func) & 0x3) << 8)
 229 #define PCI_CONF_DEV(dev)               (((dev) & 0x1f) << 11)
 230 #define PCI_CONF_BUS(bus)               (((bus) & 0xff) << 16)
 231 #define PCI_CONF_ADDR_EN                (1 << 31)
 232
 233 /*
 234  * Internal configuration space
 235  */
 236 #define PCI_CONF_FUNC_STAT_CMD          0
 237 #define PCI_CONF_REG_STAT_CMD           4
 238 #define PCIX_STAT                       0x64
 239 #define PCIX_STAT_BUS_OFFS              8
 240 #define PCIX_STAT_BUS_MASK              (0xff << PCIX_STAT_BUS_OFFS)
 241
 242 /*
 243  * PCI Address Decode Windows registers
 244  */
 245 #define PCI_BAR_SIZE_DDR_CS(n)  (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
 246                                  ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
 247                                  ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
 248                                  ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
 249 #define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
 250                                  ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
 251                                  ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
 252                                  ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
 253 #define PCI_BAR_ENABLE          ORION5X_PCI_REG(0xc3c)
 254 #define PCI_ADDR_DECODE_CTRL    ORION5X_PCI_REG(0xd3c)
 255
 256 /*
 257  * PCI configuration helpers for BAR settings
 258  */
 259 #define PCI_CONF_FUNC_BAR_CS(n)         ((n) >> 1)
 260 #define PCI_CONF_REG_BAR_LO_CS(n)       (((n) & 1) ? 0x18 : 0x10)
 261 #define PCI_CONF_REG_BAR_HI_CS(n)       (((n) & 1) ? 0x1c : 0x14)
 262
 263 /*
 264  * PCI config cycles are done by programming the PCI_CONF_ADDR register
 265  * and then reading the PCI_CONF_DATA register. Need to make sure these
 266  * transactions are atomic.
 267  */
 268 static DEFINE_SPINLOCK(orion5x_pci_lock);
 269
 270 static int orion5x_pci_cardbus_mode;
 271
 272 static int orion5x_pci_local_bus_nr(void)
 273 {
 274         u32 conf = readl(PCI_P2P_CONF);
 275         return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
 276 }
 277
 278 static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
 279                                         u32 where, u32 size, u32 *val)
 280 {
 281         unsigned long flags;
 282         spin_lock_irqsave(&orion5x_pci_lock, flags);
 283
 284         writel(PCI_CONF_BUS(bus) |
 285                 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
 286                 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
 287
 288         *val = readl(PCI_CONF_DATA);
 289
 290         if (size == 1)
 291                 *val = (*val >> (8*(where & 0x3))) & 0xff;
 292         else if (size == 2)
 293                 *val = (*val >> (8*(where & 0x3))) & 0xffff;
 294
 295         spin_unlock_irqrestore(&orion5x_pci_lock, flags);
 296
 297         return PCIBIOS_SUCCESSFUL;
 298 }
 299
 300 static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
 301                                         u32 where, u32 size, u32 val)
 302 {
 303         unsigned long flags;
 304         int ret = PCIBIOS_SUCCESSFUL;
 305
 306         spin_lock_irqsave(&orion5x_pci_lock, flags);
 307
 308         writel(PCI_CONF_BUS(bus) |
 309                 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
 310                 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
 311
 312         if (size == 4) {
 313                 __raw_writel(val, PCI_CONF_DATA);
 314         } else if (size == 2) {
 315                 __raw_writew(val, PCI_CONF_DATA + (where & 0x3));
 316         } else if (size == 1) {
 317                 __raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
 318         } else {
 319                 ret = PCIBIOS_BAD_REGISTER_NUMBER;
 320         }
 321
 322         spin_unlock_irqrestore(&orion5x_pci_lock, flags);
 323
 324         return ret;
 325 }
 326
 327 static int orion5x_pci_valid_config(int bus, u32 devfn)
 328 {
 329         if (bus == orion5x_pci_local_bus_nr()) {
 330                 /*
 331                  * Don't go out for local device
 332                  */
 333                 if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
 334                         return 0;
 335
 336                 /*
 337                  * When the PCI signals are directly connected to a
 338                  * Cardbus slot, ignore all but device IDs 0 and 1.
 339                  */
 340                 if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1)
 341                         return 0;
 342         }
 343
 344         return 1;
 345 }
 346
 347 static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
 348                                 int where, int size, u32 *val)
 349 {
 350         if (!orion5x_pci_valid_config(bus->number, devfn)) {
 351                 *val = 0xffffffff;
 352                 return PCIBIOS_DEVICE_NOT_FOUND;
 353         }
 354
 355         return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
 356                                         PCI_FUNC(devfn), where, size, val);
 357 }
 358
 359 static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
 360                                 int where, int size, u32 val)
 361 {
 362         if (!orion5x_pci_valid_config(bus->number, devfn))
 363                 return PCIBIOS_DEVICE_NOT_FOUND;
 364
 365         return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
 366                                         PCI_FUNC(devfn), where, size, val);
 367 }
 368
 369 static struct pci_ops pci_ops = {
 370         .read = orion5x_pci_rd_conf,
 371         .write = orion5x_pci_wr_conf,
 372 };
 373
 374 static void __init orion5x_pci_set_bus_nr(int nr)
 375 {
 376         u32 p2p = readl(PCI_P2P_CONF);
 377
 378         if (readl(PCI_MODE) & PCI_MODE_PCIX) {
 379                 /*
 380                  * PCI-X mode
 381                  */
 382                 u32 pcix_status, bus, dev;
 383                 bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
 384                 dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
 385                 orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
 386                 pcix_status &= ~PCIX_STAT_BUS_MASK;
 387                 pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
 388                 orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
 389         } else {
 390                 /*
 391                  * PCI Conventional mode
 392                  */
 393                 p2p &= ~PCI_P2P_BUS_MASK;
 394                 p2p |= (nr << PCI_P2P_BUS_OFFS);
 395                 writel(p2p, PCI_P2P_CONF);
 396         }
 397 }
 398
 399 static void __init orion5x_pci_master_slave_enable(void)
 400 {
 401         int bus_nr, func, reg;
 402         u32 val;
 403
 404         bus_nr = orion5x_pci_local_bus_nr();
 405         func = PCI_CONF_FUNC_STAT_CMD;
 406         reg = PCI_CONF_REG_STAT_CMD;
 407         orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
 408         val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 409         orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
 410 }
 411
 412 static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
 413 {
 414         u32 win_enable;
 415         int bus;
 416         int i;
 417
 418         /*
 419          * First, disable windows.
 420          */
 421         win_enable = 0xffffffff;
 422         writel(win_enable, PCI_BAR_ENABLE);
 423
 424         /*
 425          * Setup windows for DDR banks.
 426          */
 427         bus = orion5x_pci_local_bus_nr();
 428
 429         for (i = 0; i < dram->num_cs; i++) {
 430                 struct mbus_dram_window *cs = dram->cs + i;
 431                 u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
 432                 u32 reg;
 433                 u32 val;
 434
 435                 /*
 436                  * Write DRAM bank base address register.
 437                  */
 438                 reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
 439                 orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
 440                 val = (cs->base & 0xfffff000) | (val & 0xfff);
 441                 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val);
 442
 443                 /*
 444                  * Write DRAM bank size register.
 445                  */
 446                 reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
 447                 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
 448                 writel((cs->size - 1) & 0xfffff000,
 449                         PCI_BAR_SIZE_DDR_CS(cs->cs_index));
 450                 writel(cs->base & 0xfffff000,
 451                         PCI_BAR_REMAP_DDR_CS(cs->cs_index));
 452
 453                 /*
 454                  * Enable decode window for this chip select.
 455                  */
 456                 win_enable &= ~(1 << cs->cs_index);
 457         }
 458
 459         /*
 460          * Re-enable decode windows.
 461          */
 462         writel(win_enable, PCI_BAR_ENABLE);
 463
 464         /*
 465          * Disable automatic update of address remaping when writing to BARs.
 466          */
 467         orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
 468 }
 469
 470 static int __init pci_setup(struct pci_sys_data *sys)
 471 {
 472         struct resource *res;
 473
 474         /*
 475          * Point PCI unit MBUS decode windows to DRAM space.
 476          */
 477         orion5x_setup_pci_wins(&orion5x_mbus_dram_info);
 478
 479         /*
 480          * Master + Slave enable
 481          */
 482         orion5x_pci_master_slave_enable();
 483
 484         /*
 485          * Force ordering
 486          */
 487         orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
 488
 489         /*
 490          * Request resources
 491          */
 492         res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
 493         if (!res)
 494                 panic("pci_setup unable to alloc resources");
 495
 496         /*
 497          * IORESOURCE_IO
 498          */
 499         res[0].name = "PCI I/O Space";
 500         res[0].flags = IORESOURCE_IO;
 501         res[0].start = ORION5X_PCI_IO_BUS_BASE;
 502         res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1;
 503         if (request_resource(&ioport_resource, &res[0]))
 504                 panic("Request PCI IO resource failed\n");
 505         sys->resource[0] = &res[0];
 506
 507         /*
 508          * IORESOURCE_MEM
 509          */
 510         res[1].name = "PCI Memory Space";
 511         res[1].flags = IORESOURCE_MEM;
 512         res[1].start = ORION5X_PCI_MEM_PHYS_BASE;
 513         res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1;
 514         if (request_resource(&iomem_resource, &res[1]))
 515                 panic("Request PCI Memory resource failed\n");
 516         sys->resource[1] = &res[1];
 517
 518         sys->resource[2] = NULL;
 519         sys->io_offset = 0;
 520
 521         return 1;
 522 }
 523
 524
 525 /*****************************************************************************
 526  * General PCIe + PCI
 527  ****************************************************************************/
 528 static void __devinit rc_pci_fixup(struct pci_dev *dev)
 529 {
 530         /*
 531          * Prevent enumeration of root complex.
 532          */
 533         if (dev->bus->parent == NULL && dev->devfn == 0) {
 534                 int i;
 535
 536                 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
 537                         dev->resource[i].start = 0;
 538                         dev->resource[i].end   = 0;
 539                         dev->resource[i].flags = 0;
 540                 }
 541         }
 542 }
 543 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
 544
 545 static int orion5x_pci_disabled __initdata;
 546
 547 void __init orion5x_pci_disable(void)
 548 {
 549         orion5x_pci_disabled = 1;
 550 }
 551
 552 void __init orion5x_pci_set_cardbus_mode(void)
 553 {
 554         orion5x_pci_cardbus_mode = 1;
 555 }
 556
 557 int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
 558 {
 559         int ret = 0;
 560
 561         if (nr == 0) {
 562                 orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
 563                 ret = pcie_setup(sys);
 564         } else if (nr == 1 && !orion5x_pci_disabled) {
 565                 orion5x_pci_set_bus_nr(sys->busnr);
 566                 ret = pci_setup(sys);
 567         }
 568
 569         return ret;
 570 }
 571
 572 struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
 573 {
 574         struct pci_bus *bus;
 575
 576         if (nr == 0) {
 577                 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
 578         } else if (nr == 1 && !orion5x_pci_disabled) {
 579                 bus = pci_scan_bus(sys->busnr, &pci_ops, sys);
 580         } else {
 581                 bus = NULL;
 582                 BUG();
 583         }
 584
 585         return bus;
 586 }
 587
 588 int __init orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 589 {
 590         int bus = dev->bus->number;
 591
 592         /*
 593          * PCIe endpoint?
 594          */
 595         if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr())
 596                 return IRQ_ORION5X_PCIE0_INT;
 597
 598         return -1;
 599 }