kernel/2.6.29.6-aldebaran-rt/arch/arm/mach-kirkwood/pcie.c

   1 /*
   2  * arch/arm/mach-kirkwood/pcie.c
   3  *
   4  * PCIe functions for Marvell Kirkwood SoCs
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/pci.h>
  13 #include <linux/mbus.h>
  14 #include <asm/irq.h>
  15 #include <asm/mach/pci.h>
  16 #include <plat/pcie.h>
  17 #include "common.h"
  18
  19
  20 #define PCIE_BASE       ((void __iomem *)PCIE_VIRT_BASE)
  21
  22 void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
  23 {
  24         *dev = orion_pcie_dev_id(PCIE_BASE);
  25         *rev = orion_pcie_rev(PCIE_BASE);
  26 }
  27
  28 static int pcie_valid_config(int bus, int dev)
  29 {
  30         /*
  31          * Don't go out when trying to access --
  32          * 1. nonexisting device on local bus
  33          * 2. where there's no device connected (no link)
  34          */
  35         if (bus == 0 && dev == 0)
  36                 return 1;
  37
  38         if (!orion_pcie_link_up(PCIE_BASE))
  39                 return 0;
  40
  41         if (bus == 0 && dev != 1)
  42                 return 0;
  43
  44         return 1;
  45 }
  46
  47
  48 /*
  49  * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
  50  * and then reading the PCIE_CONF_DATA register. Need to make sure these
  51  * transactions are atomic.
  52  */
  53 static DEFINE_SPINLOCK(kirkwood_pcie_lock);
  54
  55 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
  56                         int size, u32 *val)
  57 {
  58         unsigned long flags;
  59         int ret;
  60
  61         if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
  62                 *val = 0xffffffff;
  63                 return PCIBIOS_DEVICE_NOT_FOUND;
  64         }
  65
  66         spin_lock_irqsave(&kirkwood_pcie_lock, flags);
  67         ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
  68         spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
  69
  70         return ret;
  71 }
  72
  73 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
  74                         int where, int size, u32 val)
  75 {
  76         unsigned long flags;
  77         int ret;
  78
  79         if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
  80                 return PCIBIOS_DEVICE_NOT_FOUND;
  81
  82         spin_lock_irqsave(&kirkwood_pcie_lock, flags);
  83         ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
  84         spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
  85
  86         return ret;
  87 }
  88
  89 static struct pci_ops pcie_ops = {
  90         .read = pcie_rd_conf,
  91         .write = pcie_wr_conf,
  92 };
  93
  94
  95 static int kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
  96 {
  97         struct resource *res;
  98
  99         /*
 100          * Generic PCIe unit setup.
 101          */
 102         orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info);
 103
 104         /*
 105          * Request resources.
 106          */
 107         res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
 108         if (!res)
 109                 panic("pcie_setup unable to alloc resources");
 110
 111         /*
 112          * IORESOURCE_IO
 113          */
 114         res[0].name = "PCIe I/O Space";
 115         res[0].flags = IORESOURCE_IO;
 116         res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
 117         res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
 118         if (request_resource(&ioport_resource, &res[0]))
 119                 panic("Request PCIe IO resource failed\n");
 120         sys->resource[0] = &res[0];
 121
 122         /*
 123          * IORESOURCE_MEM
 124          */
 125         res[1].name = "PCIe Memory Space";
 126         res[1].flags = IORESOURCE_MEM;
 127         res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
 128         res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
 129         if (request_resource(&iomem_resource, &res[1]))
 130                 panic("Request PCIe Memory resource failed\n");
 131         sys->resource[1] = &res[1];
 132
 133         sys->resource[2] = NULL;
 134         sys->io_offset = 0;
 135
 136         return 1;
 137 }
 138
 139 static void __devinit rc_pci_fixup(struct pci_dev *dev)
 140 {
 141         /*
 142          * Prevent enumeration of root complex.
 143          */
 144         if (dev->bus->parent == NULL && dev->devfn == 0) {
 145                 int i;
 146
 147                 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
 148                         dev->resource[i].start = 0;
 149                         dev->resource[i].end   = 0;
 150                         dev->resource[i].flags = 0;
 151                 }
 152         }
 153 }
 154 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
 155
 156 static struct pci_bus __init *
 157 kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 158 {
 159         struct pci_bus *bus;
 160
 161         if (nr == 0) {
 162                 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
 163         } else {
 164                 bus = NULL;
 165                 BUG();
 166         }
 167
 168         return bus;
 169 }
 170
 171 static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 172 {
 173         return IRQ_KIRKWOOD_PCIE;
 174 }
 175
 176 static struct hw_pci kirkwood_pci __initdata = {
 177         .nr_controllers = 1,
 178         .swizzle        = pci_std_swizzle,
 179         .setup          = kirkwood_pcie_setup,
 180         .scan           = kirkwood_pcie_scan_bus,
 181         .map_irq        = kirkwood_pcie_map_irq,
 182 };
 183
 184 void __init kirkwood_pcie_init(void)
 185 {
 186         pci_common_init(&kirkwood_pci);
 187 }