kernel/2.6.29.6-aldebaran-rt/arch/arm/mach-imx/cpufreq.c

   1 /*
   2  * cpu.c: clock scaling for the iMX
   3  *
   4  * Copyright (C) 2000 2001, The Delft University of Technology
   5  * Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de>
   6  * Copyright (C) 2006 Inky Lung <ilung@cwlinux.com>
   7  * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
   8  *
   9  * Based on SA1100 version written by:
  10  * - Johan Pouwelse (J.A.Pouwelse@its.tudelft.nl): initial version
  11  * - Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  26  *
  27  */
  28
  29 /*#define DEBUG*/
  30
  31 #include <linux/kernel.h>
  32 #include <linux/types.h>
  33 #include <linux/init.h>
  34 #include <linux/cpufreq.h>
  35 #include <linux/clk.h>
  36 #include <linux/err.h>
  37 #include <asm/system.h>
  38
  39 #include <mach/hardware.h>
  40
  41 #include "generic.h"
  42
  43 #ifndef __val2mfld
  44 #define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask))
  45 #endif
  46 #ifndef __mfld2val
  47 #define __mfld2val(mask,val) (((val)&(mask))/((mask)&~((mask)<<1)))
  48 #endif
  49
  50 #define CR_920T_CLOCK_MODE      0xC0000000
  51 #define CR_920T_FASTBUS_MODE    0x00000000
  52 #define CR_920T_ASYNC_MODE      0xC0000000
  53
  54 static u32 mpctl0_at_boot;
  55 static u32 bclk_div_at_boot;
  56
  57 static struct clk *system_clk, *mcu_clk;
  58
  59 static void imx_set_async_mode(void)
  60 {
  61         adjust_cr(CR_920T_CLOCK_MODE, CR_920T_ASYNC_MODE);
  62 }
  63
  64 static void imx_set_fastbus_mode(void)
  65 {
  66         adjust_cr(CR_920T_CLOCK_MODE, CR_920T_FASTBUS_MODE);
  67 }
  68
  69 static void imx_set_mpctl0(u32 mpctl0)
  70 {
  71         unsigned long flags;
  72
  73         if (mpctl0 == 0) {
  74                 local_irq_save(flags);
  75                 CSCR &= ~CSCR_MPEN;
  76                 local_irq_restore(flags);
  77                 return;
  78         }
  79
  80         local_irq_save(flags);
  81         MPCTL0 = mpctl0;
  82         CSCR |= CSCR_MPEN;
  83         local_irq_restore(flags);
  84 }
  85
  86 /**
  87  * imx_compute_mpctl - compute new PLL parameters
  88  * @new_mpctl:  pointer to location assigned by new PLL control register value
  89  * @cur_mpctl:  current PLL control register parameters
  90  * @f_ref:      reference source frequency Hz
  91  * @freq:       required frequency in Hz
  92  * @relation:   is one of %CPUFREQ_RELATION_L (supremum)
  93  *              and %CPUFREQ_RELATION_H (infimum)
  94  */
  95 long imx_compute_mpctl(u32 *new_mpctl, u32 cur_mpctl, u32 f_ref, unsigned long freq, int relation)
  96 {
  97         u32 mfi;
  98         u32 mfn;
  99         u32 mfd;
 100         u32 pd;
 101         unsigned long long ll;
 102         long l;
 103         long quot;
 104
 105         /* Fdppl=2*Fref*(MFI+MFN/(MFD+1))/(PD+1) */
 106         /*  PD=<0,15>, MFD=<1,1023>, MFI=<5,15> MFN=<0,1022> */
 107
 108         if (cur_mpctl) {
 109                 mfd = ((cur_mpctl >> 16) & 0x3ff) + 1;
 110                 pd =  ((cur_mpctl >> 26) & 0xf) + 1;
 111         } else {
 112                 pd=2; mfd=313;
 113         }
 114
 115         /* pd=2; mfd=313; mfi=8; mfn=183; */
 116         /* (MFI+MFN/(MFD)) = Fdppl / (2*Fref) * (PD); */
 117
 118         quot = (f_ref + (1 << 9)) >> 10;
 119         l = (freq * pd + quot) / (2 * quot);
 120         mfi = l >> 10;
 121         mfn = ((l & ((1 << 10) - 1)) * mfd + (1 << 9)) >> 10;
 122
 123         mfd -= 1;
 124         pd -= 1;
 125
 126         *new_mpctl = ((mfi & 0xf) << 10) | (mfn & 0x3ff) | ((mfd & 0x3ff) << 16)
 127                 | ((pd & 0xf) << 26);
 128
 129         ll = 2 * (unsigned long long)f_ref * ( (mfi<<16) + (mfn<<16) / (mfd+1) );
 130         quot = (pd+1) * (1<<16);
 131         ll += quot / 2;
 132         do_div(ll, quot);
 133         freq = ll;
 134
 135         pr_debug(KERN_DEBUG "imx: new PLL parameters pd=%d mfd=%d mfi=%d mfn=%d, freq=%ld\n",
 136                 pd, mfd, mfi, mfn, freq);
 137
 138         return freq;
 139 }
 140
 141
 142 static int imx_verify_speed(struct cpufreq_policy *policy)
 143 {
 144         if (policy->cpu != 0)
 145                 return -EINVAL;
 146
 147         cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
 148
 149         return 0;
 150 }
 151
 152 static unsigned int imx_get_speed(unsigned int cpu)
 153 {
 154         unsigned int freq;
 155         unsigned int cr;
 156         unsigned int cscr;
 157         unsigned int bclk_div;
 158
 159         if (cpu)
 160                 return 0;
 161
 162         cscr = CSCR;
 163         bclk_div = __mfld2val(CSCR_BCLK_DIV, cscr) + 1;
 164         cr = get_cr();
 165
 166         if((cr & CR_920T_CLOCK_MODE) == CR_920T_FASTBUS_MODE) {
 167                 freq = clk_get_rate(system_clk);
 168                 freq = (freq + bclk_div/2) / bclk_div;
 169         } else {
 170                 freq = clk_get_rate(mcu_clk);
 171                 if (cscr & CSCR_MPU_PRESC)
 172                         freq /= 2;
 173         }
 174
 175         freq = (freq + 500) / 1000;
 176
 177         return freq;
 178 }
 179
 180 static int imx_set_target(struct cpufreq_policy *policy,
 181                           unsigned int target_freq,
 182                           unsigned int relation)
 183 {
 184         struct cpufreq_freqs freqs;
 185         u32 mpctl0 = 0;
 186         u32 cscr;
 187         unsigned long flags;
 188         long freq;
 189         long sysclk;
 190         unsigned int bclk_div = bclk_div_at_boot;
 191
 192         /*
 193          * Some governors do not respects CPU and policy lower limits
 194          * which leads to bad things (division by zero etc), ensure
 195          * that such things do not happen.
 196          */
 197         if(target_freq < policy->cpuinfo.min_freq)
 198                 target_freq = policy->cpuinfo.min_freq;
 199
 200         if(target_freq < policy->min)
 201                 target_freq = policy->min;
 202
 203         freq = target_freq * 1000;
 204
 205         pr_debug(KERN_DEBUG "imx: requested frequency %ld Hz, mpctl0 at boot 0x%08x\n",
 206                         freq, mpctl0_at_boot);
 207
 208         sysclk = clk_get_rate(system_clk);
 209
 210         if (freq > sysclk / bclk_div_at_boot + 1000000) {
 211                 freq = imx_compute_mpctl(&mpctl0, mpctl0_at_boot, CLK32 * 512, freq, relation);
 212                 if (freq < 0) {
 213                         printk(KERN_WARNING "imx: target frequency %ld Hz cannot be set\n", freq);
 214                         return -EINVAL;
 215                 }
 216         } else {
 217                 if(freq + 1000 < sysclk) {
 218                         if (relation == CPUFREQ_RELATION_L)
 219                                 bclk_div = (sysclk - 1000) / freq;
 220                         else
 221                                 bclk_div = (sysclk + freq + 1000) / freq;
 222
 223                         if(bclk_div > 16)
 224                                 bclk_div = 16;
 225                         if(bclk_div < bclk_div_at_boot)
 226                                 bclk_div = bclk_div_at_boot;
 227                 }
 228                 freq = (sysclk + bclk_div / 2) / bclk_div;
 229         }
 230
 231         freqs.old = imx_get_speed(0);
 232         freqs.new = (freq + 500) / 1000;
 233         freqs.cpu = 0;
 234         freqs.flags = 0;
 235
 236         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 237
 238         local_irq_save(flags);
 239
 240         imx_set_fastbus_mode();
 241
 242         imx_set_mpctl0(mpctl0);
 243
 244         cscr = CSCR;
 245         cscr &= ~CSCR_BCLK_DIV;
 246         cscr |= __val2mfld(CSCR_BCLK_DIV, bclk_div - 1);
 247         CSCR = cscr;
 248
 249         if(mpctl0) {
 250                 CSCR |= CSCR_MPLL_RESTART;
 251
 252                 /* Wait until MPLL is stabilized */
 253                 while( CSCR & CSCR_MPLL_RESTART );
 254
 255                 imx_set_async_mode();
 256         }
 257
 258         local_irq_restore(flags);
 259
 260         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 261
 262         pr_debug(KERN_INFO "imx: set frequency %ld Hz, running from %s\n",
 263                         freq, mpctl0? "MPLL": "SPLL");
 264
 265         return 0;
 266 }
 267
 268 static int __init imx_cpufreq_driver_init(struct cpufreq_policy *policy)
 269 {
 270         printk(KERN_INFO "i.MX cpu freq change driver v1.0\n");
 271
 272         if (policy->cpu != 0)
 273                 return -EINVAL;
 274
 275         policy->cur = policy->min = policy->max = imx_get_speed(0);
 276         policy->cpuinfo.min_freq = 8000;
 277         policy->cpuinfo.max_freq = 200000;
 278          /* Manual states, that PLL stabilizes in two CLK32 periods */
 279         policy->cpuinfo.transition_latency = 4 * 1000000000LL / CLK32;
 280         return 0;
 281 }
 282
 283 static struct cpufreq_driver imx_driver = {
 284         .flags          = CPUFREQ_STICKY,
 285         .verify         = imx_verify_speed,
 286         .target         = imx_set_target,
 287         .get            = imx_get_speed,
 288         .init           = imx_cpufreq_driver_init,
 289         .name           = "imx",
 290 };
 291
 292 static int __init imx_cpufreq_init(void)
 293 {
 294         bclk_div_at_boot = __mfld2val(CSCR_BCLK_DIV, CSCR) + 1;
 295         mpctl0_at_boot = 0;
 296
 297         system_clk = clk_get(NULL, "system_clk");
 298         if (IS_ERR(system_clk))
 299                 return PTR_ERR(system_clk);
 300
 301         mcu_clk = clk_get(NULL, "mcu_clk");
 302         if (IS_ERR(mcu_clk)) {
 303                 clk_put(system_clk);
 304                 return PTR_ERR(mcu_clk);
 305         }
 306
 307         if((CSCR & CSCR_MPEN) &&
 308            ((get_cr() & CR_920T_CLOCK_MODE) != CR_920T_FASTBUS_MODE))
 309                 mpctl0_at_boot = MPCTL0;
 310
 311         return cpufreq_register_driver(&imx_driver);
 312 }
 313
 314 arch_initcall(imx_cpufreq_init);
 315