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.\" ======================================================================
.\"
.IX Title "GCC 1"
.TH GCC 1 "gcc-3.4.2" "2004-09-20" "GNU"
.UC
.SH "NAME"
gcc \- \s-1GNU\s0 project C and \*(C+ compiler
.SH "SYNOPSIS"
.IX Header "SYNOPSIS"
gcc [\fB\-c\fR|\fB\-S\fR|\fB\-E\fR] [\fB\-std=\fR\fIstandard\fR]
    [\fB\-g\fR] [\fB\-pg\fR] [\fB\-O\fR\fIlevel\fR]
    [\fB\-W\fR\fIwarn\fR...] [\fB\-pedantic\fR]
    [\fB\-I\fR\fIdir\fR...] [\fB\-L\fR\fIdir\fR...]
    [\fB\-D\fR\fImacro\fR[=\fIdefn\fR]...] [\fB\-U\fR\fImacro\fR]
    [\fB\-f\fR\fIoption\fR...] [\fB\-m\fR\fImachine-option\fR...]
    [\fB\-o\fR \fIoutfile\fR] \fIinfile\fR...
.PP
Only the most useful options are listed here; see below for the
remainder.  \fBg++\fR accepts mostly the same options as \fBgcc\fR.
.SH "DESCRIPTION"
.IX Header "DESCRIPTION"
When you invoke \s-1GCC\s0, it normally does preprocessing, compilation,
assembly and linking.  The ``overall options'' allow you to stop this
process at an intermediate stage.  For example, the \fB\-c\fR option
says not to run the linker.  Then the output consists of object files
output by the assembler.
.PP
Other options are passed on to one stage of processing.  Some options
control the preprocessor and others the compiler itself.  Yet other
options control the assembler and linker; most of these are not
documented here, since you rarely need to use any of them.
.PP
Most of the command line options that you can use with \s-1GCC\s0 are useful
for C programs; when an option is only useful with another language
(usually \*(C+), the explanation says so explicitly.  If the description
for a particular option does not mention a source language, you can use
that option with all supported languages.
.PP
The \fBgcc\fR program accepts options and file names as operands.  Many
options have multi-letter names; therefore multiple single-letter options
may \fInot\fR be grouped: \fB\-dr\fR is very different from \fB\-d\ \-r\fR.
.PP
You can mix options and other arguments.  For the most part, the order
you use doesn't matter.  Order does matter when you use several options
of the same kind; for example, if you specify \fB\-L\fR more than once,
the directories are searched in the order specified.
.PP
Many options have long names starting with \fB\-f\fR or with
\&\fB\-W\fR\-\-\-for example, \fB\-fforce-mem\fR,
\&\fB\-fstrength-reduce\fR, \fB\-Wformat\fR and so on.  Most of
these have both positive and negative forms; the negative form of
\&\fB\-ffoo\fR would be \fB\-fno-foo\fR.  This manual documents
only one of these two forms, whichever one is not the default.
.SH "OPTIONS"
.IX Header "OPTIONS"
.Sh "Option Summary"
.IX Subsection "Option Summary"
Here is a summary of all the options, grouped by type.  Explanations are
in the following sections.
.Ip "\fIOverall Options\fR" 4
.IX Item "Overall Options"
\&\fB\-c  \-S  \-E  \-o\fR \fIfile\fR  \fB\-pipe  \-pass-exit-codes  
\&\-x\fR \fIlanguage\fR  \fB\-v  \-###  \-\-help  \-\-target-help  \-\-version\fR
.Ip "\fIC Language Options\fR" 4
.IX Item "C Language Options"
\&\fB\-ansi  \-std=\fR\fIstandard\fR  \fB\-aux-info\fR \fIfilename\fR 
\&\fB\-fno-asm  \-fno-builtin  \-fno-builtin-\fR\fIfunction\fR 
\&\fB\-fhosted  \-ffreestanding  \-fms-extensions 
\&\-trigraphs  \-no-integrated-cpp  \-traditional  \-traditional-cpp 
\&\-fallow-single-precision  \-fcond-mismatch 
\&\-fsigned-bitfields  \-fsigned-char 
\&\-funsigned-bitfields  \-funsigned-char 
\&\-fwritable-strings\fR
.Ip "\fI\*(C+ Language Options\fR" 4
.IX Item " Language Options"
\&\fB\-fabi-version=\fR\fIn\fR  \fB\-fno-access-control  \-fcheck-new 
\&\-fconserve-space  \-fno-const-strings 
\&\-fno-elide-constructors 
\&\-fno-enforce-eh-specs 
\&\-ffor-scope  \-fno-for-scope  \-fno-gnu-keywords 
\&\-fno-implicit-templates 
\&\-fno-implicit-inline-templates 
\&\-fno-implement-inlines  \-fms-extensions 
\&\-fno-nonansi-builtins  \-fno-operator-names 
\&\-fno-optional-diags  \-fpermissive 
\&\-frepo  \-fno-rtti  \-fstats  \-ftemplate-depth-\fR\fIn\fR 
\&\fB\-fuse-cxa-atexit  \-fno-weak  \-nostdinc++ 
\&\-fno-default-inline  \-Wabi  \-Wctor-dtor-privacy 
\&\-Wnon-virtual-dtor  \-Wreorder 
\&\-Weffc++  \-Wno-deprecated 
\&\-Wno-non-template-friend  \-Wold-style-cast 
\&\-Woverloaded-virtual  \-Wno-pmf-conversions 
\&\-Wsign-promo  \-Wsynth\fR
.Ip "\fIObjective-C Language Options\fR" 4
.IX Item "Objective-C Language Options"
\&\fB\-fconstant-string-class=\fR\fIclass-name\fR 
\&\fB\-fgnu-runtime  \-fnext-runtime 
\&\-fno-nil-receivers 
\&\-fobjc-exceptions 
\&\-freplace-objc-classes 
\&\-fzero-link 
\&\-gen-decls 
\&\-Wno-protocol  \-Wselector \-Wundeclared-selector\fR
.Ip "\fILanguage Independent Options\fR" 4
.IX Item "Language Independent Options"
\&\fB\-fmessage-length=\fR\fIn\fR  
\&\fB\-fdiagnostics-show-location=\fR[\fBonce\fR|\fBevery-line\fR]
.Ip "\fIWarning Options\fR" 4
.IX Item "Warning Options"
\&\fB\-fsyntax-only  \-pedantic  \-pedantic-errors 
\&\-w  \-Wextra  \-Wall  \-Waggregate-return 
\&\-Wcast-align  \-Wcast-qual  \-Wchar-subscripts  \-Wcomment 
\&\-Wconversion  \-Wno-deprecated-declarations 
\&\-Wdisabled-optimization  \-Wno-div-by-zero  \-Wendif-labels 
\&\-Werror  \-Werror-implicit-function-declaration 
\&\-Wfloat-equal  \-Wformat  \-Wformat=2 
\&\-Wno-format-extra-args \-Wformat-nonliteral 
\&\-Wformat-security  \-Wformat-y2k 
\&\-Wimplicit  \-Wimplicit-function-declaration  \-Wimplicit-int 
\&\-Wimport  \-Wno-import  \-Winit-self  \-Winline 
\&\-Wno-invalid-offsetof  \-Winvalid-pch 
\&\-Wlarger-than-\fR\fIlen\fR  \fB\-Wlong-long 
\&\-Wmain  \-Wmissing-braces 
\&\-Wmissing-format-attribute  \-Wmissing-noreturn 
\&\-Wno-multichar  \-Wnonnull  \-Wpacked  \-Wpadded 
\&\-Wparentheses  \-Wpointer-arith  \-Wredundant-decls 
\&\-Wreturn-type  \-Wsequence-point  \-Wshadow 
\&\-Wsign-compare  \-Wstrict-aliasing 
\&\-Wswitch  \-Wswitch-default  \-Wswitch-enum 
\&\-Wsystem-headers  \-Wtrigraphs  \-Wundef  \-Wuninitialized 
\&\-Wunknown-pragmas  \-Wunreachable-code 
\&\-Wunused  \-Wunused-function  \-Wunused-label  \-Wunused-parameter 
\&\-Wunused-value  \-Wunused-variable  \-Wwrite-strings\fR
.Ip "\fIC-only Warning Options\fR" 4
.IX Item "C-only Warning Options"
\&\fB\-Wbad-function-cast  \-Wmissing-declarations 
\&\-Wmissing-prototypes  \-Wnested-externs  \-Wold-style-definition 
\&\-Wstrict-prototypes  \-Wtraditional 
\&\-Wdeclaration-after-statement\fR
.Ip "\fIDebugging Options\fR" 4
.IX Item "Debugging Options"
\&\fB\-d\fR\fIletters\fR  \fB\-dumpspecs  \-dumpmachine  \-dumpversion 
\&\-fdump-unnumbered  \-fdump-translation-unit\fR[\fB-\fR\fIn\fR] 
\&\fB\-fdump-class-hierarchy\fR[\fB-\fR\fIn\fR] 
\&\fB\-fdump-tree-original\fR[\fB-\fR\fIn\fR]  
\&\fB\-fdump-tree-optimized\fR[\fB-\fR\fIn\fR] 
\&\fB\-fdump-tree-inlined\fR[\fB-\fR\fIn\fR] 
\&\fB\-feliminate-dwarf2\-dups \-feliminate-unused-debug-types 
\&\-feliminate-unused-debug-symbols \-fmem-report \-fprofile-arcs 
\&\-frandom-seed=\fR\fIstring\fR \fB\-fsched-verbose=\fR\fIn\fR 
\&\fB\-ftest-coverage  \-ftime-report 
\&\-g  \-g\fR\fIlevel\fR  \fB\-gcoff \-gdwarf-2 
\&\-ggdb  \-gstabs  \-gstabs+  \-gvms  \-gxcoff  \-gxcoff+ 
\&\-p  \-pg  \-print-file-name=\fR\fIlibrary\fR  \fB\-print-libgcc-file-name 
\&\-print-multi-directory  \-print-multi-lib 
\&\-print-prog-name=\fR\fIprogram\fR  \fB\-print-search-dirs  \-Q 
\&\-save-temps  \-time\fR
.Ip "\fIOptimization Options\fR" 4
.IX Item "Optimization Options"
\&\fB\-falign-functions=\fR\fIn\fR  \fB\-falign-jumps=\fR\fIn\fR 
\&\fB\-falign-labels=\fR\fIn\fR  \fB\-falign-loops=\fR\fIn\fR  
\&\fB\-fbranch-probabilities \-fprofile-values \-fvpt \-fbranch-target-load-optimize 
\&\-fbranch-target-load-optimize2 \-fcaller-saves  \-fcprop-registers 
\&\-fcse-follow-jumps  \-fcse-skip-blocks  \-fdata-sections 
\&\-fdelayed-branch  \-fdelete-null-pointer-checks 
\&\-fexpensive-optimizations  \-ffast-math  \-ffloat-store 
\&\-fforce-addr  \-fforce-mem  \-ffunction-sections 
\&\-fgcse  \-fgcse-lm  \-fgcse-sm  \-fgcse-las  \-floop-optimize 
\&\-fcrossjumping  \-fif-conversion  \-fif-conversion2 
\&\-finline-functions  \-finline-limit=\fR\fIn\fR  \fB\-fkeep-inline-functions 
\&\-fkeep-static-consts  \-fmerge-constants  \-fmerge-all-constants 
\&\-fmove-all-movables  \-fnew-ra  \-fno-branch-count-reg 
\&\-fno-default-inline  \-fno-defer-pop 
\&\-fno-function-cse  \-fno-guess-branch-probability 
\&\-fno-inline  \-fno-math-errno  \-fno-peephole  \-fno-peephole2 
\&\-funsafe-math-optimizations  \-ffinite-math-only 
\&\-fno-trapping-math  \-fno-zero-initialized-in-bss 
\&\-fomit-frame-pointer  \-foptimize-register-move 
\&\-foptimize-sibling-calls  \-fprefetch-loop-arrays 
\&\-fprofile-generate \-fprofile-use 
\&\-freduce-all-givs  \-fregmove  \-frename-registers 
\&\-freorder-blocks  \-freorder-functions 
\&\-frerun-cse-after-loop  \-frerun-loop-opt 
\&\-frounding-math \-fschedule-insns  \-fschedule-insns2 
\&\-fno-sched-interblock  \-fno-sched-spec  \-fsched-spec-load 
\&\-fsched-spec-load-dangerous  
\&\-fsched-stalled-insns=\fR\fIn\fR \fB\-sched-stalled-insns-dep=\fR\fIn\fR 
\&\fB\-fsched2\-use-superblocks 
\&\-fsched2\-use-traces  \-fsignaling-nans 
\&\-fsingle-precision-constant  
\&\-fstrength-reduce  \-fstrict-aliasing  \-ftracer  \-fthread-jumps 
\&\-funroll-all-loops  \-funroll-loops  \-fpeel-loops 
\&\-funswitch-loops  \-fold-unroll-loops  \-fold-unroll-all-loops 
\&\-\-param\fR \fIname\fR\fB=\fR\fIvalue\fR
\&\fB\-O  \-O0  \-O1  \-O2  \-O3  \-Os\fR
.Ip "\fIPreprocessor Options\fR" 4
.IX Item "Preprocessor Options"
\&\fB\-A\fR\fIquestion\fR\fB=\fR\fIanswer\fR 
\&\fB\-A-\fR\fIquestion\fR[\fB=\fR\fIanswer\fR] 
\&\fB\-C  \-dD  \-dI  \-dM  \-dN 
\&\-D\fR\fImacro\fR[\fB=\fR\fIdefn\fR]  \fB\-E  \-H 
\&\-idirafter\fR \fIdir\fR 
\&\fB\-include\fR \fIfile\fR  \fB\-imacros\fR \fIfile\fR 
\&\fB\-iprefix\fR \fIfile\fR  \fB\-iwithprefix\fR \fIdir\fR 
\&\fB\-iwithprefixbefore\fR \fIdir\fR  \fB\-isystem\fR \fIdir\fR 
\&\fB\-M  \-MM  \-MF  \-MG  \-MP  \-MQ  \-MT  \-nostdinc  
\&\-P  \-fworking-directory  \-remap 
\&\-trigraphs  \-undef  \-U\fR\fImacro\fR  \fB\-Wp,\fR\fIoption\fR 
\&\fB\-Xpreprocessor\fR \fIoption\fR
.Ip "\fIAssembler Option\fR" 4
.IX Item "Assembler Option"
\&\fB\-Wa,\fR\fIoption\fR  \fB\-Xassembler\fR \fIoption\fR
.Ip "\fILinker Options\fR" 4
.IX Item "Linker Options"
\&\fIobject-file-name\fR  \fB\-l\fR\fIlibrary\fR 
\&\fB\-nostartfiles  \-nodefaultlibs  \-nostdlib \-pie 
\&\-s  \-static  \-static-libgcc  \-shared  \-shared-libgcc  \-symbolic 
\&\-Wl,\fR\fIoption\fR  \fB\-Xlinker\fR \fIoption\fR 
\&\fB\-u\fR \fIsymbol\fR
.Ip "\fIDirectory Options\fR" 4
.IX Item "Directory Options"
\&\fB\-B\fR\fIprefix\fR  \fB\-I\fR\fIdir\fR  \fB\-I-  \-L\fR\fIdir\fR  \fB\-specs=\fR\fIfile\fR
.Ip "\fITarget Options\fR" 4
.IX Item "Target Options"
\&\fB\-V\fR \fIversion\fR  \fB\-b\fR \fImachine\fR
.Ip "\fIMachine Dependent Options\fR" 4
.IX Item "Machine Dependent Options"
\&\fIM680x0 Options\fR
\&\fB\-m68000  \-m68020  \-m68020\-40  \-m68020\-60  \-m68030  \-m68040 
\&\-m68060  \-mcpu32  \-m5200  \-m68881  \-mbitfield  \-mc68000  \-mc68020   
\&\-mnobitfield  \-mrtd  \-mshort  \-msoft-float  \-mpcrel 
\&\-malign-int  \-mstrict-align  \-msep-data  \-mno-sep-data 
\&\-mshared-library-id=n  \-mid-shared-library  \-mno-id-shared-library\fR
.Sp
\&\fIM68hc1x Options\fR
\&\fB\-m6811  \-m6812  \-m68hc11  \-m68hc12   \-m68hcs12 
\&\-mauto-incdec  \-minmax  \-mlong-calls  \-mshort 
\&\-msoft-reg-count=\fR\fIcount\fR
.Sp
\&\fI\s-1VAX\s0 Options\fR
\&\fB\-mg  \-mgnu  \-munix\fR
.Sp
\&\fI\s-1SPARC\s0 Options\fR
\&\fB\-mcpu=\fR\fIcpu-type\fR 
\&\fB\-mtune=\fR\fIcpu-type\fR 
\&\fB\-mcmodel=\fR\fIcode-model\fR 
\&\fB\-m32  \-m64  \-mapp-regs  \-mno-app-regs 
\&\-mfaster-structs  \-mno-faster-structs 
\&\-mflat  \-mno-flat  \-mfpu  \-mno-fpu 
\&\-mhard-float  \-msoft-float 
\&\-mhard-quad-float  \-msoft-quad-float 
\&\-mimpure-text  \-mno-impure-text  \-mlittle-endian 
\&\-mstack-bias  \-mno-stack-bias 
\&\-munaligned-doubles  \-mno-unaligned-doubles 
\&\-mv8plus  \-mno-v8plus  \-mvis  \-mno-vis 
\&\-mcypress  \-mf930  \-mf934 
\&\-msparclite  \-msupersparc  \-mv8
\&\-threads \-pthreads\fR
.Sp
\&\fI\s-1ARM\s0 Options\fR
\&\fB\-mapcs-frame  \-mno-apcs-frame 
\&\-mapcs-26  \-mapcs-32 
\&\-mapcs-stack-check  \-mno-apcs-stack-check 
\&\-mapcs-float  \-mno-apcs-float 
\&\-mapcs-reentrant  \-mno-apcs-reentrant 
\&\-msched-prolog  \-mno-sched-prolog 
\&\-mlittle-endian  \-mbig-endian  \-mwords-little-endian 
\&\-malignment-traps  \-mno-alignment-traps 
\&\-msoft-float  \-mhard-float  \-mfpe 
\&\-mthumb-interwork  \-mno-thumb-interwork 
\&\-mcpu=\fR\fIname\fR  \fB\-march=\fR\fIname\fR  \fB\-mfpe=\fR\fIname\fR  
\&\fB\-mstructure-size-boundary=\fR\fIn\fR 
\&\fB\-mabort-on-noreturn 
\&\-mlong-calls  \-mno-long-calls 
\&\-msingle-pic-base  \-mno-single-pic-base 
\&\-mpic-register=\fR\fIreg\fR 
\&\fB\-mnop-fun-dllimport 
\&\-mcirrus-fix-invalid-insns \-mno-cirrus-fix-invalid-insns 
\&\-mpoke-function-name 
\&\-mthumb  \-marm 
\&\-mtpcs-frame  \-mtpcs-leaf-frame 
\&\-mcaller-super-interworking  \-mcallee-super-interworking\fR
.Sp
\&\fI\s-1MN10300\s0 Options\fR
\&\fB\-mmult-bug  \-mno-mult-bug 
\&\-mam33  \-mno-am33 
\&\-mam33\-2  \-mno-am33\-2 
\&\-mno-crt0  \-mrelax\fR
.Sp
\&\fIM32R/D Options\fR
\&\fB\-m32r2 \-m32rx \-m32r 
\&\-mdebug 
\&\-malign-loops \-mno-align-loops 
\&\-missue-rate=\fR\fInumber\fR 
\&\fB\-mbranch-cost=\fR\fInumber\fR 
\&\fB\-mmodel=\fR\fIcode-size-model-type\fR 
\&\fB\-msdata=\fR\fIsdata-type\fR 
\&\fB\-mno-flush-func \-mflush-func=\fR\fIname\fR 
\&\fB\-mno-flush-trap \-mflush-trap=\fR\fInumber\fR 
\&\fB\-G\fR \fInum\fR
.Sp
\&\fI\s-1RS/6000\s0 and PowerPC Options\fR
\&\fB\-mcpu=\fR\fIcpu-type\fR 
\&\fB\-mtune=\fR\fIcpu-type\fR 
\&\fB\-mpower  \-mno-power  \-mpower2  \-mno-power2 
\&\-mpowerpc  \-mpowerpc64  \-mno-powerpc 
\&\-maltivec  \-mno-altivec 
\&\-mpowerpc-gpopt  \-mno-powerpc-gpopt 
\&\-mpowerpc-gfxopt  \-mno-powerpc-gfxopt 
\&\-mnew-mnemonics  \-mold-mnemonics 
\&\-mfull-toc   \-mminimal-toc  \-mno-fp-in-toc  \-mno-sum-in-toc 
\&\-m64  \-m32  \-mxl-call  \-mno-xl-call  \-mpe 
\&\-malign-power  \-malign-natural 
\&\-msoft-float  \-mhard-float  \-mmultiple  \-mno-multiple 
\&\-mstring  \-mno-string  \-mupdate  \-mno-update 
\&\-mfused-madd  \-mno-fused-madd  \-mbit-align  \-mno-bit-align 
\&\-mstrict-align  \-mno-strict-align  \-mrelocatable 
\&\-mno-relocatable  \-mrelocatable-lib  \-mno-relocatable-lib 
\&\-mtoc  \-mno-toc  \-mlittle  \-mlittle-endian  \-mbig  \-mbig-endian 
\&\-mdynamic-no-pic 
\&\-mprioritize-restricted-insns=\fR\fIpriority\fR 
\&\fB\-msched-costly-dep=\fR\fIdependence_type\fR 
\&\fB\-minsert-sched-nops=\fR\fIscheme\fR 
\&\fB\-mcall-sysv  \-mcall-netbsd 
\&\-maix-struct-return  \-msvr4\-struct-return 
\&\-mabi=altivec  \-mabi=no-altivec 
\&\-mabi=spe  \-mabi=no-spe 
\&\-misel=yes  \-misel=no 
\&\-mspe=yes  \-mspe=no 
\&\-mfloat-gprs=yes  \-mfloat-gprs=no 
\&\-mprototype  \-mno-prototype 
\&\-msim  \-mmvme  \-mads  \-myellowknife  \-memb  \-msdata 
\&\-msdata=\fR\fIopt\fR  \fB\-mvxworks  \-mwindiss  \-G\fR \fInum\fR  \fB\-pthread\fR
.Sp
\&\fIDarwin Options\fR
\&\fB\-all_load  \-allowable_client  \-arch  \-arch_errors_fatal 
\&\-arch_only  \-bind_at_load  \-bundle  \-bundle_loader 
\&\-client_name  \-compatibility_version  \-current_version 
\&\-dependency-file  \-dylib_file  \-dylinker_install_name 
\&\-dynamic  \-dynamiclib  \-exported_symbols_list 
\&\-filelist  \-flat_namespace  \-force_cpusubtype_ALL 
\&\-force_flat_namespace  \-headerpad_max_install_names 
\&\-image_base  \-init  \-install_name  \-keep_private_externs 
\&\-multi_module  \-multiply_defined  \-multiply_defined_unused 
\&\-noall_load  \-nofixprebinding \-nomultidefs  \-noprebind  \-noseglinkedit 
\&\-pagezero_size  \-prebind  \-prebind_all_twolevel_modules 
\&\-private_bundle  \-read_only_relocs  \-sectalign 
\&\-sectobjectsymbols  \-whyload  \-seg1addr 
\&\-sectcreate  \-sectobjectsymbols  \-sectorder 
\&\-seg_addr_table  \-seg_addr_table_filename  \-seglinkedit 
\&\-segprot  \-segs_read_only_addr  \-segs_read_write_addr 
\&\-single_module  \-static  \-sub_library  \-sub_umbrella 
\&\-twolevel_namespace  \-umbrella  \-undefined 
\&\-unexported_symbols_list  \-weak_reference_mismatches 
\&\-whatsloaded\fR
.Sp
\&\fI\s-1MIPS\s0 Options\fR
\&\fB\-EL  \-EB  \-march=\fR\fIarch\fR  \fB\-mtune=\fR\fIarch\fR 
\&\fB\-mips1  \-mips2  \-mips3  \-mips4  \-mips32  \-mips32r2  \-mips64 
\&\-mips16  \-mno-mips16  \-mabi=\fR\fIabi\fR  \fB\-mabicalls  \-mno-abicalls 
\&\-mxgot  \-mno-xgot  \-membedded-pic  \-mno-embedded-pic 
\&\-mgp32  \-mgp64  \-mfp32  \-mfp64  \-mhard-float  \-msoft-float 
\&\-msingle-float  \-mdouble-float  \-mint64  \-mlong64  \-mlong32 
\&\-G\fR\fInum\fR  \fB\-membedded-data  \-mno-embedded-data 
\&\-muninit-const-in-rodata  \-mno-uninit-const-in-rodata 
\&\-msplit-addresses  \-mno-split-addresses  
\&\-mexplicit-relocs  \-mno-explicit-relocs  
\&\-mrnames  \-mno-rnames 
\&\-mcheck-zero-division  \-mno-check-zero-division 
\&\-mmemcpy  \-mno-memcpy  \-mlong-calls  \-mno-long-calls 
\&\-mmad  \-mno-mad  \-mfused-madd  \-mno-fused-madd  \-nocpp 
\&\-mfix-sb1  \-mno-fix-sb1  \-mflush-func=\fR\fIfunc\fR 
\&\fB\-mno-flush-func  \-mbranch-likely  \-mno-branch-likely\fR
.Sp
\&\fIi386 and x86\-64 Options\fR
\&\fB\-mtune=\fR\fIcpu-type\fR  \fB\-march=\fR\fIcpu-type\fR 
\&\fB\-mfpmath=\fR\fIunit\fR 
\&\fB\-masm=\fR\fIdialect\fR  \fB\-mno-fancy-math-387 
\&\-mno-fp-ret-in-387  \-msoft-float  \-msvr3\-shlib 
\&\-mno-wide-multiply  \-mrtd  \-malign-double 
\&\-mpreferred-stack-boundary=\fR\fInum\fR 
\&\fB\-mmmx  \-msse  \-msse2 \-msse3 \-m3dnow 
\&\-mthreads  \-mno-align-stringops  \-minline-all-stringops 
\&\-mpush-args  \-maccumulate-outgoing-args  \-m128bit-long-double 
\&\-m96bit-long-double  \-mregparm=\fR\fInum\fR  \fB\-momit-leaf-frame-pointer 
\&\-mno-red-zone \-mno-tls-direct-seg-refs 
\&\-mcmodel=\fR\fIcode-model\fR 
\&\fB\-m32  \-m64 \-mstack-arg-probe\fR
.Sp
\&\fI\s-1HPPA\s0 Options\fR
\&\fB\-march=\fR\fIarchitecture-type\fR 
\&\fB\-mbig-switch  \-mdisable-fpregs  \-mdisable-indexing 
\&\-mfast-indirect-calls  \-mgas  \-mgnu-ld   \-mhp-ld 
\&\-mjump-in-delay \-mlinker-opt \-mlong-calls 
\&\-mlong-load-store  \-mno-big-switch  \-mno-disable-fpregs 
\&\-mno-disable-indexing  \-mno-fast-indirect-calls  \-mno-gas 
\&\-mno-jump-in-delay  \-mno-long-load-store 
\&\-mno-portable-runtime  \-mno-soft-float 
\&\-mno-space-regs  \-msoft-float  \-mpa-risc-1\-0 
\&\-mpa-risc-1\-1  \-mpa-risc-2\-0  \-mportable-runtime 
\&\-mschedule=\fR\fIcpu-type\fR  \fB\-mspace-regs  \-msio  \-mwsio 
\&\-nolibdld  \-static  \-threads\fR
.Sp
\&\fIIntel 960 Options\fR
\&\fB\-m\fR\fIcpu-type\fR  \fB\-masm-compat  \-mclean-linkage 
\&\-mcode-align  \-mcomplex-addr  \-mleaf-procedures 
\&\-mic-compat  \-mic2.0\-compat  \-mic3.0\-compat 
\&\-mintel-asm  \-mno-clean-linkage  \-mno-code-align 
\&\-mno-complex-addr  \-mno-leaf-procedures 
\&\-mno-old-align  \-mno-strict-align  \-mno-tail-call 
\&\-mnumerics  \-mold-align  \-msoft-float  \-mstrict-align 
\&\-mtail-call\fR
.Sp
\&\fI\s-1DEC\s0 Alpha Options\fR
\&\fB\-mno-fp-regs  \-msoft-float  \-malpha-as  \-mgas 
\&\-mieee  \-mieee-with-inexact  \-mieee-conformant 
\&\-mfp-trap-mode=\fR\fImode\fR  \fB\-mfp-rounding-mode=\fR\fImode\fR 
\&\fB\-mtrap-precision=\fR\fImode\fR  \fB\-mbuild-constants 
\&\-mcpu=\fR\fIcpu-type\fR  \fB\-mtune=\fR\fIcpu-type\fR 
\&\fB\-mbwx  \-mmax  \-mfix  \-mcix 
\&\-mfloat-vax  \-mfloat-ieee 
\&\-mexplicit-relocs  \-msmall-data  \-mlarge-data 
\&\-msmall-text  \-mlarge-text 
\&\-mmemory-latency=\fR\fItime\fR
.Sp
\&\fI\s-1DEC\s0 Alpha/VMS Options\fR
\&\fB\-mvms-return-codes\fR
.Sp
\&\fIH8/300 Options\fR
\&\fB\-mrelax  \-mh  \-ms  \-mn  \-mint32  \-malign-300\fR
.Sp
\&\fI\s-1SH\s0 Options\fR
\&\fB\-m1  \-m2  \-m2e  \-m3  \-m3e 
\&\-m4\-nofpu  \-m4\-single-only  \-m4\-single  \-m4 
\&\-m5\-64media  \-m5\-64media-nofpu 
\&\-m5\-32media  \-m5\-32media-nofpu 
\&\-m5\-compact  \-m5\-compact-nofpu 
\&\-mb  \-ml  \-mdalign  \-mrelax 
\&\-mbigtable  \-mfmovd  \-mhitachi  \-mnomacsave 
\&\-mieee  \-misize  \-mpadstruct  \-mspace 
\&\-mprefergot  \-musermode\fR
.Sp
\&\fISystem V Options\fR
\&\fB\-Qy  \-Qn  \-YP,\fR\fIpaths\fR  \fB\-Ym,\fR\fIdir\fR
.Sp
\&\fI\s-1ARC\s0 Options\fR
\&\fB\-EB  \-EL 
\&\-mmangle-cpu  \-mcpu=\fR\fIcpu\fR  \fB\-mtext=\fR\fItext-section\fR 
\&\fB\-mdata=\fR\fIdata-section\fR  \fB\-mrodata=\fR\fIreadonly-data-section\fR
.Sp
\&\fITMS320C3x/C4x Options\fR
\&\fB\-mcpu=\fR\fIcpu\fR  \fB\-mbig  \-msmall  \-mregparm  \-mmemparm 
\&\-mfast-fix  \-mmpyi  \-mbk  \-mti  \-mdp-isr-reload 
\&\-mrpts=\fR\fIcount\fR  \fB\-mrptb  \-mdb  \-mloop-unsigned 
\&\-mparallel-insns  \-mparallel-mpy  \-mpreserve-float\fR
.Sp
\&\fIV850 Options\fR
\&\fB\-mlong-calls  \-mno-long-calls  \-mep  \-mno-ep 
\&\-mprolog-function  \-mno-prolog-function  \-mspace 
\&\-mtda=\fR\fIn\fR  \fB\-msda=\fR\fIn\fR  \fB\-mzda=\fR\fIn\fR 
\&\fB\-mapp-regs  \-mno-app-regs 
\&\-mdisable-callt  \-mno-disable-callt 
\&\-mv850e1 
\&\-mv850e 
\&\-mv850  \-mbig-switch\fR
.Sp
\&\fI\s-1NS32K\s0 Options\fR
\&\fB\-m32032  \-m32332  \-m32532  \-m32081  \-m32381 
\&\-mmult-add  \-mnomult-add  \-msoft-float  \-mrtd  \-mnortd 
\&\-mregparam  \-mnoregparam  \-msb  \-mnosb 
\&\-mbitfield  \-mnobitfield  \-mhimem  \-mnohimem\fR
.Sp
\&\fI\s-1AVR\s0 Options\fR
\&\fB\-mmcu=\fR\fImcu\fR  \fB\-msize  \-minit-stack=\fR\fIn\fR  \fB\-mno-interrupts 
\&\-mcall-prologues  \-mno-tablejump  \-mtiny-stack\fR
.Sp
\&\fIMCore Options\fR
\&\fB\-mhardlit  \-mno-hardlit  \-mdiv  \-mno-div  \-mrelax-immediates 
\&\-mno-relax-immediates  \-mwide-bitfields  \-mno-wide-bitfields 
\&\-m4byte-functions  \-mno-4byte-functions  \-mcallgraph-data 
\&\-mno-callgraph-data  \-mslow-bytes  \-mno-slow-bytes  \-mno-lsim 
\&\-mlittle-endian  \-mbig-endian  \-m210  \-m340  \-mstack-increment\fR
.Sp
\&\fI\s-1MMIX\s0 Options\fR
\&\fB\-mlibfuncs  \-mno-libfuncs  \-mepsilon  \-mno-epsilon  \-mabi=gnu 
\&\-mabi=mmixware  \-mzero-extend  \-mknuthdiv  \-mtoplevel-symbols 
\&\-melf  \-mbranch-predict  \-mno-branch-predict  \-mbase-addresses 
\&\-mno-base-addresses  \-msingle-exit  \-mno-single-exit\fR
.Sp
\&\fI\s-1IA-64\s0 Options\fR
\&\fB\-mbig-endian  \-mlittle-endian  \-mgnu-as  \-mgnu-ld  \-mno-pic 
\&\-mvolatile-asm-stop  \-mb-step  \-mregister-names  \-mno-sdata 
\&\-mconstant-gp  \-mauto-pic  \-minline-float-divide-min-latency 
\&\-minline-float-divide-max-throughput 
\&\-minline-int-divide-min-latency 
\&\-minline-int-divide-max-throughput  \-mno-dwarf2\-asm 
\&\-mfixed-range=\fR\fIregister-range\fR
.Sp
\&\fID30V Options\fR
\&\fB\-mextmem  \-mextmemory  \-monchip  \-mno-asm-optimize 
\&\-masm-optimize  \-mbranch-cost=\fR\fIn\fR  \fB\-mcond-exec=\fR\fIn\fR
.Sp
\&\fIS/390 and zSeries Options\fR
\&\fB\-mtune=\fR\fIcpu-type\fR  \fB\-march=\fR\fIcpu-type\fR 
\&\fB\-mhard-float  \-msoft-float  \-mbackchain  \-mno-backchain 
\&\-msmall-exec  \-mno-small-exec  \-mmvcle \-mno-mvcle 
\&\-m64  \-m31  \-mdebug  \-mno-debug  \-mesa  \-mzarch  \-mfused-madd  \-mno-fused-madd\fR
.Sp
\&\fI\s-1CRIS\s0 Options\fR
\&\fB\-mcpu=\fR\fIcpu\fR  \fB\-march=\fR\fIcpu\fR  \fB\-mtune=\fR\fIcpu\fR 
\&\fB\-mmax-stack-frame=\fR\fIn\fR  \fB\-melinux-stacksize=\fR\fIn\fR 
\&\fB\-metrax4  \-metrax100  \-mpdebug  \-mcc-init  \-mno-side-effects 
\&\-mstack-align  \-mdata-align  \-mconst-align 
\&\-m32\-bit  \-m16\-bit  \-m8\-bit  \-mno-prologue-epilogue  \-mno-gotplt 
\&\-melf  \-maout  \-melinux  \-mlinux  \-sim  \-sim2 
\&\-mmul-bug-workaround  \-mno-mul-bug-workaround\fR
.Sp
\&\fI\s-1PDP-11\s0 Options\fR
\&\fB\-mfpu  \-msoft-float  \-mac0  \-mno-ac0  \-m40  \-m45  \-m10 
\&\-mbcopy  \-mbcopy-builtin  \-mint32  \-mno-int16 
\&\-mint16  \-mno-int32  \-mfloat32  \-mno-float64 
\&\-mfloat64  \-mno-float32  \-mabshi  \-mno-abshi 
\&\-mbranch-expensive  \-mbranch-cheap 
\&\-msplit  \-mno-split  \-munix-asm  \-mdec-asm\fR
.Sp
\&\fIXstormy16 Options\fR
\&\fB\-msim\fR
.Sp
\&\fIXtensa Options\fR
\&\fB\-mconst16 \-mno-const16 
\&\-mfused-madd  \-mno-fused-madd 
\&\-mtext-section-literals  \-mno-text-section-literals 
\&\-mtarget-align  \-mno-target-align 
\&\-mlongcalls  \-mno-longcalls\fR
.Sp
\&\fI\s-1FRV\s0 Options\fR
\&\fB\-mgpr-32  \-mgpr-64  \-mfpr-32  \-mfpr-64 
\&\-mhard-float  \-msoft-float 
\&\-malloc-cc  \-mfixed-cc  \-mdword  \-mno-dword 
\&\-mdouble  \-mno-double 
\&\-mmedia  \-mno-media  \-mmuladd  \-mno-muladd 
\&\-mlibrary-pic  \-macc-4 \-macc-8 
\&\-mpack  \-mno-pack  \-mno-eflags  \-mcond-move  \-mno-cond-move 
\&\-mscc  \-mno-scc  \-mcond-exec  \-mno-cond-exec 
\&\-mvliw-branch  \-mno-vliw-branch 
\&\-mmulti-cond-exec  \-mno-multi-cond-exec  \-mnested-cond-exec 
\&\-mno-nested-cond-exec  \-mtomcat-stats 
\&\-mcpu=\fR\fIcpu\fR
.Ip "\fICode Generation Options\fR" 4
.IX Item "Code Generation Options"
\&\fB\-fcall-saved-\fR\fIreg\fR  \fB\-fcall-used-\fR\fIreg\fR 
\&\fB\-ffixed-\fR\fIreg\fR  \fB\-fexceptions 
\&\-fnon-call-exceptions  \-funwind-tables 
\&\-fasynchronous-unwind-tables 
\&\-finhibit-size-directive  \-finstrument-functions 
\&\-fno-common  \-fno-ident 
\&\-fpcc-struct-return  \-fpic  \-fPIC \-fpie \-fPIE 
\&\-freg-struct-return  \-fshared-data  \-fshort-enums 
\&\-fshort-double  \-fshort-wchar 
\&\-fverbose-asm  \-fpack-struct  \-fstack-check 
\&\-fstack-limit-register=\fR\fIreg\fR  \fB\-fstack-limit-symbol=\fR\fIsym\fR 
\&\fB\-fargument-alias  \-fargument-noalias 
\&\-fargument-noalias-global  \-fleading-underscore 
\&\-ftls-model=\fR\fImodel\fR 
\&\fB\-ftrapv  \-fwrapv  \-fbounds-check\fR
.Sh "Options Controlling the Kind of Output"
.IX Subsection "Options Controlling the Kind of Output"
Compilation can involve up to four stages: preprocessing, compilation
proper, assembly and linking, always in that order.  \s-1GCC\s0 is capable of
preprocessing and compiling several files either into several
assembler input files, or into one assembler input file; then each
assembler input file produces an object file, and linking combines all
the object files (those newly compiled, and those specified as input)
into an executable file.
.PP
For any given input file, the file name suffix determines what kind of
compilation is done:
.Ip "\fIfile\fR\fB.c\fR" 4
.IX Item "file.c"
C source code which must be preprocessed.
.Ip "\fIfile\fR\fB.i\fR" 4
.IX Item "file.i"
C source code which should not be preprocessed.
.Ip "\fIfile\fR\fB.ii\fR" 4
.IX Item "file.ii"
\&\*(C+ source code which should not be preprocessed.
.Ip "\fIfile\fR\fB.m\fR" 4
.IX Item "file.m"
Objective-C source code.  Note that you must link with the library
\&\fIlibobjc.a\fR to make an Objective-C program work.
.Ip "\fIfile\fR\fB.mi\fR" 4
.IX Item "file.mi"
Objective-C source code which should not be preprocessed.
.Ip "\fIfile\fR\fB.h\fR" 4
.IX Item "file.h"
C or \*(C+ header file to be turned into a precompiled header.
.Ip "\fIfile\fR\fB.cc\fR" 4
.IX Item "file.cc"
.PD 0
.Ip "\fIfile\fR\fB.cp\fR" 4
.IX Item "file.cp"
.Ip "\fIfile\fR\fB.cxx\fR" 4
.IX Item "file.cxx"
.Ip "\fIfile\fR\fB.cpp\fR" 4
.IX Item "file.cpp"
.Ip "\fIfile\fR\fB.CPP\fR" 4
.IX Item "file.CPP"
.Ip "\fIfile\fR\fB.c++\fR" 4
.IX Item "file.c++"
.Ip "\fIfile\fR\fB.C\fR" 4
.IX Item "file.C"
.PD
\&\*(C+ source code which must be preprocessed.  Note that in \fB.cxx\fR,
the last two letters must both be literally \fBx\fR.  Likewise,
\&\fB.C\fR refers to a literal capital C.
.Ip "\fIfile\fR\fB.hh\fR" 4
.IX Item "file.hh"
.PD 0
.Ip "\fIfile\fR\fB.H\fR" 4
.IX Item "file.H"
.PD
\&\*(C+ header file to be turned into a precompiled header.
.Ip "\fIfile\fR\fB.f\fR" 4
.IX Item "file.f"
.PD 0
.Ip "\fIfile\fR\fB.for\fR" 4
.IX Item "file.for"
.Ip "\fIfile\fR\fB.FOR\fR" 4
.IX Item "file.FOR"
.PD
Fortran source code which should not be preprocessed.
.Ip "\fIfile\fR\fB.F\fR" 4
.IX Item "file.F"
.PD 0
.Ip "\fIfile\fR\fB.fpp\fR" 4
.IX Item "file.fpp"
.Ip "\fIfile\fR\fB.FPP\fR" 4
.IX Item "file.FPP"
.PD
Fortran source code which must be preprocessed (with the traditional
preprocessor).
.Ip "\fIfile\fR\fB.r\fR" 4
.IX Item "file.r"
Fortran source code which must be preprocessed with a \s-1RATFOR\s0
preprocessor (not included with \s-1GCC\s0).
.Ip "\fIfile\fR\fB.ads\fR" 4
.IX Item "file.ads"
Ada source code file which contains a library unit declaration (a
declaration of a package, subprogram, or generic, or a generic
instantiation), or a library unit renaming declaration (a package,
generic, or subprogram renaming declaration).  Such files are also
called \fIspecs\fR.
.Ip "\fIfile\fR\fB.adb\fR" 4
.IX Item "file.adb"
Ada source code file containing a library unit body (a subprogram or
package body).  Such files are also called \fIbodies\fR.
.Ip "\fIfile\fR\fB.s\fR" 4
.IX Item "file.s"
Assembler code.
.Ip "\fIfile\fR\fB.S\fR" 4
.IX Item "file.S"
Assembler code which must be preprocessed.
.Ip "\fIother\fR" 4
.IX Item "other"
An object file to be fed straight into linking.
Any file name with no recognized suffix is treated this way.
.PP
You can specify the input language explicitly with the \fB\-x\fR option:
.Ip "\fB\-x\fR \fIlanguage\fR" 4
.IX Item "-x language"
Specify explicitly the \fIlanguage\fR for the following input files
(rather than letting the compiler choose a default based on the file
name suffix).  This option applies to all following input files until
the next \fB\-x\fR option.  Possible values for \fIlanguage\fR are:
.Sp
.Vb 8
\&        c  c-header  cpp-output
\&        c++  c++-header  c++-cpp-output
\&        objective-c  objective-c-header  objc-cpp-output
\&        assembler  assembler-with-cpp
\&        ada
\&        f77  f77-cpp-input  ratfor
\&        java
\&        treelang
.Ve
.Ip "\fB\-x none\fR" 4
.IX Item "-x none"
Turn off any specification of a language, so that subsequent files are
handled according to their file name suffixes (as they are if \fB\-x\fR
has not been used at all).
.Ip "\fB\-pass-exit-codes\fR" 4
.IX Item "-pass-exit-codes"
Normally the \fBgcc\fR program will exit with the code of 1 if any
phase of the compiler returns a non-success return code.  If you specify
\&\fB\-pass-exit-codes\fR, the \fBgcc\fR program will instead return with
numerically highest error produced by any phase that returned an error
indication.
.PP
If you only want some of the stages of compilation, you can use
\&\fB\-x\fR (or filename suffixes) to tell \fBgcc\fR where to start, and
one of the options \fB\-c\fR, \fB\-S\fR, or \fB\-E\fR to say where
\&\fBgcc\fR is to stop.  Note that some combinations (for example,
\&\fB\-x cpp-output \-E\fR) instruct \fBgcc\fR to do nothing at all.
.Ip "\fB\-c\fR" 4
.IX Item "-c"
Compile or assemble the source files, but do not link.  The linking
stage simply is not done.  The ultimate output is in the form of an
object file for each source file.
.Sp
By default, the object file name for a source file is made by replacing
the suffix \fB.c\fR, \fB.i\fR, \fB.s\fR, etc., with \fB.o\fR.
.Sp
Unrecognized input files, not requiring compilation or assembly, are
ignored.
.Ip "\fB\-S\fR" 4
.IX Item "-S"
Stop after the stage of compilation proper; do not assemble.  The output
is in the form of an assembler code file for each non-assembler input
file specified.
.Sp
By default, the assembler file name for a source file is made by
replacing the suffix \fB.c\fR, \fB.i\fR, etc., with \fB.s\fR.
.Sp
Input files that don't require compilation are ignored.
.Ip "\fB\-E\fR" 4
.IX Item "-E"
Stop after the preprocessing stage; do not run the compiler proper.  The
output is in the form of preprocessed source code, which is sent to the
standard output.
.Sp
Input files which don't require preprocessing are ignored.
.Ip "\fB\-o\fR \fIfile\fR" 4
.IX Item "-o file"
Place output in file \fIfile\fR.  This applies regardless to whatever
sort of output is being produced, whether it be an executable file,
an object file, an assembler file or preprocessed C code.
.Sp
If you specify \fB\-o\fR when compiling more than one input file, or
you are producing an executable file as output, all the source files
on the command line will be compiled at once.
.Sp
If \fB\-o\fR is not specified, the default is to put an executable file
in \fIa.out\fR, the object file for \fI\fIsource\fI.\fIsuffix\fI\fR in
\&\fI\fIsource\fI.o\fR, its assembler file in \fI\fIsource\fI.s\fR, and
all preprocessed C source on standard output.
.Ip "\fB\-v\fR" 4
.IX Item "-v"
Print (on standard error output) the commands executed to run the stages
of compilation.  Also print the version number of the compiler driver
program and of the preprocessor and the compiler proper.
.Ip "\fB\-###\fR" 4
.IX Item "-###"
Like \fB\-v\fR except the commands are not executed and all command
arguments are quoted.  This is useful for shell scripts to capture the
driver-generated command lines.
.Ip "\fB\-pipe\fR" 4
.IX Item "-pipe"
Use pipes rather than temporary files for communication between the
various stages of compilation.  This fails to work on some systems where
the assembler is unable to read from a pipe; but the \s-1GNU\s0 assembler has
no trouble.
.Ip "\fB\*(--help\fR" 4
.IX Item "help"
Print (on the standard output) a description of the command line options
understood by \fBgcc\fR.  If the \fB\-v\fR option is also specified
then \fB\*(--help\fR will also be passed on to the various processes
invoked by \fBgcc\fR, so that they can display the command line options
they accept.  If the \fB\-Wextra\fR option is also specified then command
line options which have no documentation associated with them will also
be displayed.
.Ip "\fB\*(--target-help\fR" 4
.IX Item "target-help"
Print (on the standard output) a description of target specific command
line options for each tool.
.Ip "\fB\*(--version\fR" 4
.IX Item "version"
Display the version number and copyrights of the invoked \s-1GCC\s0.
.Sh "Compiling \*(C+ Programs"
.IX Subsection "Compiling  Programs"
\&\*(C+ source files conventionally use one of the suffixes \fB.C\fR,
\&\fB.cc\fR, \fB.cpp\fR, \fB.CPP\fR, \fB.c++\fR, \fB.cp\fR, or
\&\fB.cxx\fR; \*(C+ header files often use \fB.hh\fR or \fB.H\fR; and
preprocessed \*(C+ files use the suffix \fB.ii\fR.  \s-1GCC\s0 recognizes
files with these names and compiles them as \*(C+ programs even if you
call the compiler the same way as for compiling C programs (usually
with the name \fBgcc\fR).
.PP
However, \*(C+ programs often require class libraries as well as a
compiler that understands the \*(C+ language\-\-\-and under some
circumstances, you might want to compile programs or header files from
standard input, or otherwise without a suffix that flags them as \*(C+
programs.  You might also like to precompile a C header file with a
\&\fB.h\fR extension to be used in \*(C+ compilations.  \fBg++\fR is a
program that calls \s-1GCC\s0 with the default language set to \*(C+, and
automatically specifies linking against the \*(C+ library.  On many
systems, \fBg++\fR is also installed with the name \fBc++\fR.
.PP
When you compile \*(C+ programs, you may specify many of the same
command-line options that you use for compiling programs in any
language; or command-line options meaningful for C and related
languages; or options that are meaningful only for \*(C+ programs.
.Sh "Options Controlling C Dialect"
.IX Subsection "Options Controlling C Dialect"
The following options control the dialect of C (or languages derived
from C, such as \*(C+ and Objective-C) that the compiler accepts:
.Ip "\fB\-ansi\fR" 4
.IX Item "-ansi"
In C mode, support all \s-1ISO\s0 C90 programs.  In \*(C+ mode,
remove \s-1GNU\s0 extensions that conflict with \s-1ISO\s0 \*(C+.
.Sp
This turns off certain features of \s-1GCC\s0 that are incompatible with \s-1ISO\s0
C90 (when compiling C code), or of standard \*(C+ (when compiling \*(C+ code),
such as the \f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`typeof\*(C'\fR keywords, and
predefined macros such as \f(CW\*(C`unix\*(C'\fR and \f(CW\*(C`vax\*(C'\fR that identify the
type of system you are using.  It also enables the undesirable and
rarely used \s-1ISO\s0 trigraph feature.  For the C compiler,
it disables recognition of \*(C+ style \fB//\fR comments as well as
the \f(CW\*(C`inline\*(C'\fR keyword.
.Sp
The alternate keywords \f(CW\*(C`_\|_asm_\|_\*(C'\fR, \f(CW\*(C`_\|_extension_\|_\*(C'\fR,
\&\f(CW\*(C`_\|_inline_\|_\*(C'\fR and \f(CW\*(C`_\|_typeof_\|_\*(C'\fR continue to work despite
\&\fB\-ansi\fR.  You would not want to use them in an \s-1ISO\s0 C program, of
course, but it is useful to put them in header files that might be included
in compilations done with \fB\-ansi\fR.  Alternate predefined macros
such as \f(CW\*(C`_\|_unix_\|_\*(C'\fR and \f(CW\*(C`_\|_vax_\|_\*(C'\fR are also available, with or
without \fB\-ansi\fR.
.Sp
The \fB\-ansi\fR option does not cause non-ISO programs to be
rejected gratuitously.  For that, \fB\-pedantic\fR is required in
addition to \fB\-ansi\fR.  
.Sp
The macro \f(CW\*(C`_\|_STRICT_ANSI_\|_\*(C'\fR is predefined when the \fB\-ansi\fR
option is used.  Some header files may notice this macro and refrain
from declaring certain functions or defining certain macros that the
\&\s-1ISO\s0 standard doesn't call for; this is to avoid interfering with any
programs that might use these names for other things.
.Sp
Functions which would normally be built in but do not have semantics
defined by \s-1ISO\s0 C (such as \f(CW\*(C`alloca\*(C'\fR and \f(CW\*(C`ffs\*(C'\fR) are not built-in
functions with \fB\-ansi\fR is used.  
.Ip "\fB\-std=\fR" 4
.IX Item "-std="
Determine the language standard.  This option is currently only
supported when compiling C or \*(C+.  A value for this option must be
provided; possible values are
.RS 4
.Ip "\fBc89\fR" 4
.IX Item "c89"
.PD 0
.Ip "\fBiso9899:1990\fR" 4
.IX Item "iso9899:1990"
.PD
\&\s-1ISO\s0 C90 (same as \fB\-ansi\fR).
.Ip "\fBiso9899:199409\fR" 4
.IX Item "iso9899:199409"
\&\s-1ISO\s0 C90 as modified in amendment 1.
.Ip "\fBc99\fR" 4
.IX Item "c99"
.PD 0
.Ip "\fBc9x\fR" 4
.IX Item "c9x"
.Ip "\fBiso9899:1999\fR" 4
.IX Item "iso9899:1999"
.Ip "\fBiso9899:199x\fR" 4
.IX Item "iso9899:199x"
.PD
\&\s-1ISO\s0 C99.  Note that this standard is not yet fully supported; see
<\fBhttp://gcc.gnu.org/gcc-3.4/c99status.html\fR> for more information.  The
names \fBc9x\fR and \fBiso9899:199x\fR are deprecated.
.Ip "\fBgnu89\fR" 4
.IX Item "gnu89"
Default, \s-1ISO\s0 C90 plus \s-1GNU\s0 extensions (including some C99 features).
.Ip "\fBgnu99\fR" 4
.IX Item "gnu99"
.PD 0
.Ip "\fBgnu9x\fR" 4
.IX Item "gnu9x"
.PD
\&\s-1ISO\s0 C99 plus \s-1GNU\s0 extensions.  When \s-1ISO\s0 C99 is fully implemented in \s-1GCC\s0,
this will become the default.  The name \fBgnu9x\fR is deprecated.
.Ip "\fBc++98\fR" 4
.IX Item "c++98"
The 1998 \s-1ISO\s0 \*(C+ standard plus amendments.
.Ip "\fBgnu++98\fR" 4
.IX Item "gnu++98"
The same as \fB\-std=c++98\fR plus \s-1GNU\s0 extensions.  This is the
default for \*(C+ code.
.RE
.RS 4
.Sp
Even when this option is not specified, you can still use some of the
features of newer standards in so far as they do not conflict with
previous C standards.  For example, you may use \f(CW\*(C`_\|_restrict_\|_\*(C'\fR even
when \fB\-std=c99\fR is not specified.
.Sp
The \fB\-std\fR options specifying some version of \s-1ISO\s0 C have the same
effects as \fB\-ansi\fR, except that features that were not in \s-1ISO\s0 C90
but are in the specified version (for example, \fB//\fR comments and
the \f(CW\*(C`inline\*(C'\fR keyword in \s-1ISO\s0 C99) are not disabled.
.RE
.Ip "\fB\-aux-info\fR \fIfilename\fR" 4
.IX Item "-aux-info filename"
Output to the given filename prototyped declarations for all functions
declared and/or defined in a translation unit, including those in header
files.  This option is silently ignored in any language other than C.
.Sp
Besides declarations, the file indicates, in comments, the origin of
each declaration (source file and line), whether the declaration was
implicit, prototyped or unprototyped (\fBI\fR, \fBN\fR for new or
\&\fBO\fR for old, respectively, in the first character after the line
number and the colon), and whether it came from a declaration or a
definition (\fBC\fR or \fBF\fR, respectively, in the following
character).  In the case of function definitions, a K&R-style list of
arguments followed by their declarations is also provided, inside
comments, after the declaration.
.Ip "\fB\-fno-asm\fR" 4
.IX Item "-fno-asm"
Do not recognize \f(CW\*(C`asm\*(C'\fR, \f(CW\*(C`inline\*(C'\fR or \f(CW\*(C`typeof\*(C'\fR as a
keyword, so that code can use these words as identifiers.  You can use
the keywords \f(CW\*(C`_\|_asm_\|_\*(C'\fR, \f(CW\*(C`_\|_inline_\|_\*(C'\fR and \f(CW\*(C`_\|_typeof_\|_\*(C'\fR
instead.  \fB\-ansi\fR implies \fB\-fno-asm\fR.
.Sp
In \*(C+, this switch only affects the \f(CW\*(C`typeof\*(C'\fR keyword, since
\&\f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`inline\*(C'\fR are standard keywords.  You may want to
use the \fB\-fno-gnu-keywords\fR flag instead, which has the same
effect.  In C99 mode (\fB\-std=c99\fR or \fB\-std=gnu99\fR), this
switch only affects the \f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`typeof\*(C'\fR keywords, since
\&\f(CW\*(C`inline\*(C'\fR is a standard keyword in \s-1ISO\s0 C99.
.Ip "\fB\-fno-builtin\fR" 4
.IX Item "-fno-builtin"
.PD 0
.Ip "\fB\-fno-builtin-\fR\fIfunction\fR" 4
.IX Item "-fno-builtin-function"
.PD
Don't recognize built-in functions that do not begin with
\&\fB_\|_builtin_\fR as prefix.  
.Sp
\&\s-1GCC\s0 normally generates special code to handle certain built-in functions
more efficiently; for instance, calls to \f(CW\*(C`alloca\*(C'\fR may become single
instructions that adjust the stack directly, and calls to \f(CW\*(C`memcpy\*(C'\fR
may become inline copy loops.  The resulting code is often both smaller
and faster, but since the function calls no longer appear as such, you
cannot set a breakpoint on those calls, nor can you change the behavior
of the functions by linking with a different library.
.Sp
With the \fB\-fno-builtin-\fR\fIfunction\fR option
only the built-in function \fIfunction\fR is
disabled.  \fIfunction\fR must not begin with \fB_\|_builtin_\fR.  If a
function is named this is not built-in in this version of \s-1GCC\s0, this
option is ignored.  There is no corresponding
\&\fB\-fbuiltin-\fR\fIfunction\fR option; if you wish to enable
built-in functions selectively when using \fB\-fno-builtin\fR or
\&\fB\-ffreestanding\fR, you may define macros such as:
.Sp
.Vb 2
\&        #define abs(n)          __builtin_abs ((n))
\&        #define strcpy(d, s)    __builtin_strcpy ((d), (s))
.Ve
.Ip "\fB\-fhosted\fR" 4
.IX Item "-fhosted"
Assert that compilation takes place in a hosted environment.  This implies
\&\fB\-fbuiltin\fR.  A hosted environment is one in which the
entire standard library is available, and in which \f(CW\*(C`main\*(C'\fR has a return
type of \f(CW\*(C`int\*(C'\fR.  Examples are nearly everything except a kernel.
This is equivalent to \fB\-fno-freestanding\fR.
.Ip "\fB\-ffreestanding\fR" 4
.IX Item "-ffreestanding"
Assert that compilation takes place in a freestanding environment.  This
implies \fB\-fno-builtin\fR.  A freestanding environment
is one in which the standard library may not exist, and program startup may
not necessarily be at \f(CW\*(C`main\*(C'\fR.  The most obvious example is an \s-1OS\s0 kernel.
This is equivalent to \fB\-fno-hosted\fR.
.Ip "\fB\-fms-extensions\fR" 4
.IX Item "-fms-extensions"
Accept some non-standard constructs used in Microsoft header files.
.Ip "\fB\-trigraphs\fR" 4
.IX Item "-trigraphs"
Support \s-1ISO\s0 C trigraphs.  The \fB\-ansi\fR option (and \fB\-std\fR
options for strict \s-1ISO\s0 C conformance) implies \fB\-trigraphs\fR.
.Ip "\fB\-no-integrated-cpp\fR" 4
.IX Item "-no-integrated-cpp"
Performs a compilation in two passes: preprocessing and compiling.  This
option allows a user supplied \*(L"cc1\*(R", \*(L"cc1plus\*(R", or \*(L"cc1obj\*(R" via the
\&\fB\-B\fR option. The user supplied compilation step can then add in
an additional preprocessing step after normal preprocessing but before
compiling. The default is to use the integrated cpp (internal cpp)
.Sp
The semantics of this option will change if \*(L"cc1\*(R", \*(L"cc1plus\*(R", and
\&\*(L"cc1obj\*(R" are merged.
.Ip "\fB\-traditional\fR" 4
.IX Item "-traditional"
.PD 0
.Ip "\fB\-traditional-cpp\fR" 4
.IX Item "-traditional-cpp"
.PD
Formerly, these options caused \s-1GCC\s0 to attempt to emulate a pre-standard
C compiler.  They are now only supported with the \fB\-E\fR switch.
The preprocessor continues to support a pre-standard mode.  See the \s-1GNU\s0
\&\s-1CPP\s0 manual for details.
.Ip "\fB\-fcond-mismatch\fR" 4
.IX Item "-fcond-mismatch"
Allow conditional expressions with mismatched types in the second and
third arguments.  The value of such an expression is void.  This option
is not supported for \*(C+.
.Ip "\fB\-funsigned-char\fR" 4
.IX Item "-funsigned-char"
Let the type \f(CW\*(C`char\*(C'\fR be unsigned, like \f(CW\*(C`unsigned char\*(C'\fR.
.Sp
Each kind of machine has a default for what \f(CW\*(C`char\*(C'\fR should
be.  It is either like \f(CW\*(C`unsigned char\*(C'\fR by default or like
\&\f(CW\*(C`signed char\*(C'\fR by default.
.Sp
Ideally, a portable program should always use \f(CW\*(C`signed char\*(C'\fR or
\&\f(CW\*(C`unsigned char\*(C'\fR when it depends on the signedness of an object.
But many programs have been written to use plain \f(CW\*(C`char\*(C'\fR and
expect it to be signed, or expect it to be unsigned, depending on the
machines they were written for.  This option, and its inverse, let you
make such a program work with the opposite default.
.Sp
The type \f(CW\*(C`char\*(C'\fR is always a distinct type from each of
\&\f(CW\*(C`signed char\*(C'\fR or \f(CW\*(C`unsigned char\*(C'\fR, even though its behavior
is always just like one of those two.
.Ip "\fB\-fsigned-char\fR" 4
.IX Item "-fsigned-char"
Let the type \f(CW\*(C`char\*(C'\fR be signed, like \f(CW\*(C`signed char\*(C'\fR.
.Sp
Note that this is equivalent to \fB\-fno-unsigned-char\fR, which is
the negative form of \fB\-funsigned-char\fR.  Likewise, the option
\&\fB\-fno-signed-char\fR is equivalent to \fB\-funsigned-char\fR.
.Ip "\fB\-fsigned-bitfields\fR" 4
.IX Item "-fsigned-bitfields"
.PD 0
.Ip "\fB\-funsigned-bitfields\fR" 4
.IX Item "-funsigned-bitfields"
.Ip "\fB\-fno-signed-bitfields\fR" 4
.IX Item "-fno-signed-bitfields"
.Ip "\fB\-fno-unsigned-bitfields\fR" 4
.IX Item "-fno-unsigned-bitfields"
.PD
These options control whether a bit-field is signed or unsigned, when the
declaration does not use either \f(CW\*(C`signed\*(C'\fR or \f(CW\*(C`unsigned\*(C'\fR.  By
default, such a bit-field is signed, because this is consistent: the
basic integer types such as \f(CW\*(C`int\*(C'\fR are signed types.
.Ip "\fB\-fwritable-strings\fR" 4
.IX Item "-fwritable-strings"
Store string constants in the writable data segment and don't uniquize
them.  This is for compatibility with old programs which assume they can
write into string constants.
.Sp
Writing into string constants is a very bad idea; ``constants'' should
be constant.
.Sp
This option is deprecated.
.Sh "Options Controlling \*(C+ Dialect"
.IX Subsection "Options Controlling  Dialect"
This section describes the command-line options that are only meaningful
for \*(C+ programs; but you can also use most of the \s-1GNU\s0 compiler options
regardless of what language your program is in.  For example, you
might compile a file \f(CW\*(C`firstClass.C\*(C'\fR like this:
.PP
.Vb 1
\&        g++ -g -frepo -O -c firstClass.C
.Ve
In this example, only \fB\-frepo\fR is an option meant
only for \*(C+ programs; you can use the other options with any
language supported by \s-1GCC\s0.
.PP
Here is a list of options that are \fIonly\fR for compiling \*(C+ programs:
.Ip "\fB\-fabi-version=\fR\fIn\fR" 4
.IX Item "-fabi-version=n"
Use version \fIn\fR of the \*(C+ \s-1ABI\s0.  Version 2 is the version of the
\&\*(C+ \s-1ABI\s0 that first appeared in G++ 3.4.  Version 1 is the version of
the \*(C+ \s-1ABI\s0 that first appeared in G++ 3.2.  Version 0 will always be
the version that conforms most closely to the \*(C+ \s-1ABI\s0 specification.
Therefore, the \s-1ABI\s0 obtained using version 0 will change as \s-1ABI\s0 bugs
are fixed.
.Sp
The default is version 2.
.Ip "\fB\-fno-access-control\fR" 4
.IX Item "-fno-access-control"
Turn off all access checking.  This switch is mainly useful for working
around bugs in the access control code.
.Ip "\fB\-fcheck-new\fR" 4
.IX Item "-fcheck-new"
Check that the pointer returned by \f(CW\*(C`operator new\*(C'\fR is non-null
before attempting to modify the storage allocated.  This check is
normally unnecessary because the \*(C+ standard specifies that
\&\f(CW\*(C`operator new\*(C'\fR will only return \f(CW\*(C`0\*(C'\fR if it is declared
\&\fB\f(BIthrow()\fB\fR, in which case the compiler will always check the
return value even without this option.  In all other cases, when
\&\f(CW\*(C`operator new\*(C'\fR has a non-empty exception specification, memory
exhaustion is signalled by throwing \f(CW\*(C`std::bad_alloc\*(C'\fR.  See also
\&\fBnew (nothrow)\fR.
.Ip "\fB\-fconserve-space\fR" 4
.IX Item "-fconserve-space"
Put uninitialized or runtime-initialized global variables into the
common segment, as C does.  This saves space in the executable at the
cost of not diagnosing duplicate definitions.  If you compile with this
flag and your program mysteriously crashes after \f(CW\*(C`main()\*(C'\fR has
completed, you may have an object that is being destroyed twice because
two definitions were merged.
.Sp
This option is no longer useful on most targets, now that support has
been added for putting variables into \s-1BSS\s0 without making them common.
.Ip "\fB\-fno-const-strings\fR" 4
.IX Item "-fno-const-strings"
Give string constants type \f(CW\*(C`char *\*(C'\fR instead of type \f(CW\*(C`const
char *\*(C'\fR.  By default, G++ uses type \f(CW\*(C`const char *\*(C'\fR as required by
the standard.  Even if you use \fB\-fno-const-strings\fR, you cannot
actually modify the value of a string constant, unless you also use
\&\fB\-fwritable-strings\fR.
.Sp
This option might be removed in a future release of G++.  For maximum
portability, you should structure your code so that it works with
string constants that have type \f(CW\*(C`const char *\*(C'\fR.
.Ip "\fB\-fno-elide-constructors\fR" 4
.IX Item "-fno-elide-constructors"
The \*(C+ standard allows an implementation to omit creating a temporary
which is only used to initialize another object of the same type.
Specifying this option disables that optimization, and forces G++ to
call the copy constructor in all cases.
.Ip "\fB\-fno-enforce-eh-specs\fR" 4
.IX Item "-fno-enforce-eh-specs"
Don't check for violation of exception specifications at runtime.  This
option violates the \*(C+ standard, but may be useful for reducing code
size in production builds, much like defining \fB\s-1NDEBUG\s0\fR.  The compiler
will still optimize based on the exception specifications.
.Ip "\fB\-ffor-scope\fR" 4
.IX Item "-ffor-scope"
.PD 0
.Ip "\fB\-fno-for-scope\fR" 4
.IX Item "-fno-for-scope"
.PD
If \fB\-ffor-scope\fR is specified, the scope of variables declared in
a \fIfor-init-statement\fR is limited to the \fBfor\fR loop itself,
as specified by the \*(C+ standard.
If \fB\-fno-for-scope\fR is specified, the scope of variables declared in
a \fIfor-init-statement\fR extends to the end of the enclosing scope,
as was the case in old versions of G++, and other (traditional)
implementations of \*(C+.
.Sp
The default if neither flag is given to follow the standard,
but to allow and give a warning for old-style code that would
otherwise be invalid, or have different behavior.
.Ip "\fB\-fno-gnu-keywords\fR" 4
.IX Item "-fno-gnu-keywords"
Do not recognize \f(CW\*(C`typeof\*(C'\fR as a keyword, so that code can use this
word as an identifier.  You can use the keyword \f(CW\*(C`_\|_typeof_\|_\*(C'\fR instead.
\&\fB\-ansi\fR implies \fB\-fno-gnu-keywords\fR.
.Ip "\fB\-fno-implicit-templates\fR" 4
.IX Item "-fno-implicit-templates"
Never emit code for non-inline templates which are instantiated
implicitly (i.e. by use); only emit code for explicit instantiations.
.Ip "\fB\-fno-implicit-inline-templates\fR" 4
.IX Item "-fno-implicit-inline-templates"
Don't emit code for implicit instantiations of inline templates, either.
The default is to handle inlines differently so that compiles with and
without optimization will need the same set of explicit instantiations.
.Ip "\fB\-fno-implement-inlines\fR" 4
.IX Item "-fno-implement-inlines"
To save space, do not emit out-of-line copies of inline functions
controlled by \fB#pragma implementation\fR.  This will cause linker
errors if these functions are not inlined everywhere they are called.
.Ip "\fB\-fms-extensions\fR" 4
.IX Item "-fms-extensions"
Disable pedantic warnings about constructs used in \s-1MFC\s0, such as implicit
int and getting a pointer to member function via non-standard syntax.
.Ip "\fB\-fno-nonansi-builtins\fR" 4
.IX Item "-fno-nonansi-builtins"
Disable built-in declarations of functions that are not mandated by
\&\s-1ANSI/ISO\s0 C.  These include \f(CW\*(C`ffs\*(C'\fR, \f(CW\*(C`alloca\*(C'\fR, \f(CW\*(C`_exit\*(C'\fR,
\&\f(CW\*(C`index\*(C'\fR, \f(CW\*(C`bzero\*(C'\fR, \f(CW\*(C`conjf\*(C'\fR, and other related functions.
.Ip "\fB\-fno-operator-names\fR" 4
.IX Item "-fno-operator-names"
Do not treat the operator name keywords \f(CW\*(C`and\*(C'\fR, \f(CW\*(C`bitand\*(C'\fR,
\&\f(CW\*(C`bitor\*(C'\fR, \f(CW\*(C`compl\*(C'\fR, \f(CW\*(C`not\*(C'\fR, \f(CW\*(C`or\*(C'\fR and \f(CW\*(C`xor\*(C'\fR as
synonyms as keywords.
.Ip "\fB\-fno-optional-diags\fR" 4
.IX Item "-fno-optional-diags"
Disable diagnostics that the standard says a compiler does not need to
issue.  Currently, the only such diagnostic issued by G++ is the one for
a name having multiple meanings within a class.
.Ip "\fB\-fpermissive\fR" 4
.IX Item "-fpermissive"
Downgrade some diagnostics about nonconformant code from errors to
warnings.  Thus, using \fB\-fpermissive\fR will allow some
nonconforming code to compile.
.Ip "\fB\-frepo\fR" 4
.IX Item "-frepo"
Enable automatic template instantiation at link time.  This option also
implies \fB\-fno-implicit-templates\fR.  
.Ip "\fB\-fno-rtti\fR" 4
.IX Item "-fno-rtti"
Disable generation of information about every class with virtual
functions for use by the \*(C+ runtime type identification features
(\fBdynamic_cast\fR and \fBtypeid\fR).  If you don't use those parts
of the language, you can save some space by using this flag.  Note that
exception handling uses the same information, but it will generate it as
needed.
.Ip "\fB\-fstats\fR" 4
.IX Item "-fstats"
Emit statistics about front-end processing at the end of the compilation.
This information is generally only useful to the G++ development team.
.Ip "\fB\-ftemplate-depth-\fR\fIn\fR" 4
.IX Item "-ftemplate-depth-n"
Set the maximum instantiation depth for template classes to \fIn\fR.
A limit on the template instantiation depth is needed to detect
endless recursions during template class instantiation.  \s-1ANSI/ISO\s0 \*(C+
conforming programs must not rely on a maximum depth greater than 17.
.Ip "\fB\-fuse-cxa-atexit\fR" 4
.IX Item "-fuse-cxa-atexit"
Register destructors for objects with static storage duration with the
\&\f(CW\*(C`_\|_cxa_atexit\*(C'\fR function rather than the \f(CW\*(C`atexit\*(C'\fR function.
This option is required for fully standards-compliant handling of static
destructors, but will only work if your C library supports
\&\f(CW\*(C`_\|_cxa_atexit\*(C'\fR.
.Ip "\fB\-fno-weak\fR" 4
.IX Item "-fno-weak"
Do not use weak symbol support, even if it is provided by the linker.
By default, G++ will use weak symbols if they are available.  This
option exists only for testing, and should not be used by end-users;
it will result in inferior code and has no benefits.  This option may
be removed in a future release of G++.
.Ip "\fB\-nostdinc++\fR" 4
.IX Item "-nostdinc++"
Do not search for header files in the standard directories specific to
\&\*(C+, but do still search the other standard directories.  (This option
is used when building the \*(C+ library.)
.PP
In addition, these optimization, warning, and code generation options
have meanings only for \*(C+ programs:
.Ip "\fB\-fno-default-inline\fR" 4
.IX Item "-fno-default-inline"
Do not assume \fBinline\fR for functions defined inside a class scope.
  Note that these
functions will have linkage like inline functions; they just won't be
inlined by default.
.Ip "\fB\-Wabi\fR (\*(C+ only)" 4
.IX Item "-Wabi ( only)"
Warn when G++ generates code that is probably not compatible with the
vendor-neutral \*(C+ \s-1ABI\s0.  Although an effort has been made to warn about
all such cases, there are probably some cases that are not warned about,
even though G++ is generating incompatible code.  There may also be
cases where warnings are emitted even though the code that is generated
will be compatible.
.Sp
You should rewrite your code to avoid these warnings if you are
concerned about the fact that code generated by G++ may not be binary
compatible with code generated by other compilers.
.Sp
The known incompatibilities at this point include:
.RS 4
.Ip "\(bu" 4
Incorrect handling of tail-padding for bit-fields.  G++ may attempt to
pack data into the same byte as a base class.  For example:
.Sp
.Vb 2
\&        struct A { virtual void f(); int f1 : 1; };
\&        struct B : public A { int f2 : 1; };
.Ve
In this case, G++ will place \f(CW\*(C`B::f2\*(C'\fR into the same byte
as\f(CW\*(C`A::f1\*(C'\fR; other compilers will not.  You can avoid this problem
by explicitly padding \f(CW\*(C`A\*(C'\fR so that its size is a multiple of the
byte size on your platform; that will cause G++ and other compilers to
layout \f(CW\*(C`B\*(C'\fR identically.
.Ip "\(bu" 4
Incorrect handling of tail-padding for virtual bases.  G++ does not use
tail padding when laying out virtual bases.  For example:
.Sp
.Vb 3
\&        struct A { virtual void f(); char c1; };
\&        struct B { B(); char c2; };
\&        struct C : public A, public virtual B {};
.Ve
In this case, G++ will not place \f(CW\*(C`B\*(C'\fR into the tail-padding for
\&\f(CW\*(C`A\*(C'\fR; other compilers will.  You can avoid this problem by
explicitly padding \f(CW\*(C`A\*(C'\fR so that its size is a multiple of its
alignment (ignoring virtual base classes); that will cause G++ and other
compilers to layout \f(CW\*(C`C\*(C'\fR identically.
.Ip "\(bu" 4
Incorrect handling of bit-fields with declared widths greater than that
of their underlying types, when the bit-fields appear in a union.  For
example:
.Sp
.Vb 1
\&        union U { int i : 4096; };
.Ve
Assuming that an \f(CW\*(C`int\*(C'\fR does not have 4096 bits, G++ will make the
union too small by the number of bits in an \f(CW\*(C`int\*(C'\fR.
.Ip "\(bu" 4
Empty classes can be placed at incorrect offsets.  For example:
.Sp
.Vb 1
\&        struct A {};
.Ve
.Vb 4
\&        struct B {
\&          A a;
\&          virtual void f ();
\&        };
.Ve
.Vb 1
\&        struct C : public B, public A {};
.Ve
G++ will place the \f(CW\*(C`A\*(C'\fR base class of \f(CW\*(C`C\*(C'\fR at a nonzero offset;
it should be placed at offset zero.  G++ mistakenly believes that the
\&\f(CW\*(C`A\*(C'\fR data member of \f(CW\*(C`B\*(C'\fR is already at offset zero.
.Ip "\(bu" 4
Names of template functions whose types involve \f(CW\*(C`typename\*(C'\fR or
template template parameters can be mangled incorrectly.
.Sp
.Vb 2
\&        template <typename Q>
\&        void f(typename Q::X) {}
.Ve
.Vb 2
\&        template <template <typename> class Q>
\&        void f(typename Q<int>::X) {}
.Ve
Instantiations of these templates may be mangled incorrectly.
.RE
.RS 4
.RE
.Ip "\fB\-Wctor-dtor-privacy\fR (\*(C+ only)" 4
.IX Item "-Wctor-dtor-privacy ( only)"
Warn when a class seems unusable because all the constructors or
destructors in that class are private, and it has neither friends nor
public static member functions.
.Ip "\fB\-Wnon-virtual-dtor\fR (\*(C+ only)" 4
.IX Item "-Wnon-virtual-dtor ( only)"
Warn when a class appears to be polymorphic, thereby requiring a virtual
destructor, yet it declares a non-virtual one.
This warning is enabled by \fB\-Wall\fR.
.Ip "\fB\-Wreorder\fR (\*(C+ only)" 4
.IX Item "-Wreorder ( only)"
Warn when the order of member initializers given in the code does not
match the order in which they must be executed.  For instance:
.Sp
.Vb 5
\&        struct A {
\&          int i;
\&          int j;
\&          A(): j (0), i (1) { }
\&        };
.Ve
The compiler will rearrange the member initializers for \fBi\fR
and \fBj\fR to match the declaration order of the members, emitting
a warning to that effect.  This warning is enabled by \fB\-Wall\fR.
.PP
The following \fB\-W...\fR options are not affected by \fB\-Wall\fR.
.Ip "\fB\-Weffc++\fR (\*(C+ only)" 4
.IX Item "-Weffc++ ( only)"
Warn about violations of the following style guidelines from Scott Meyers'
\&\fIEffective \*(C+\fR book:
.RS 4
.Ip "\(bu" 4
Item 11:  Define a copy constructor and an assignment operator for classes
with dynamically allocated memory.
.Ip "\(bu" 4
Item 12:  Prefer initialization to assignment in constructors.
.Ip "\(bu" 4
Item 14:  Make destructors virtual in base classes.
.Ip "\(bu" 4
Item 15:  Have \f(CW\*(C`operator=\*(C'\fR return a reference to \f(CW\*(C`*this\*(C'\fR.
.Ip "\(bu" 4
Item 23:  Don't try to return a reference when you must return an object.
.RE
.RS 4
.Sp
Also warn about violations of the following style guidelines from
Scott Meyers' \fIMore Effective \*(C+\fR book:
.RS 4
.RE
.Ip "\(bu" 4
Item 6:  Distinguish between prefix and postfix forms of increment and
decrement operators.
.Ip "\(bu" 4
Item 7:  Never overload \f(CW\*(C`&&\*(C'\fR, \f(CW\*(C`||\*(C'\fR, or \f(CW\*(C`,\*(C'\fR.
.RE
.RS 4
.Sp
When selecting this option, be aware that the standard library
headers do not obey all of these guidelines; use \fBgrep \-v\fR
to filter out those warnings.
.RE
.Ip "\fB\-Wno-deprecated\fR (\*(C+ only)" 4
.IX Item "-Wno-deprecated ( only)"
Do not warn about usage of deprecated features.  
.Ip "\fB\-Wno-non-template-friend\fR (\*(C+ only)" 4
.IX Item "-Wno-non-template-friend ( only)"
Disable warnings when non-templatized friend functions are declared
within a template.  Since the advent of explicit template specification
support in G++, if the name of the friend is an unqualified-id (i.e.,
\&\fBfriend foo(int)\fR), the \*(C+ language specification demands that the
friend declare or define an ordinary, nontemplate function.  (Section
14.5.3).  Before G++ implemented explicit specification, unqualified-ids
could be interpreted as a particular specialization of a templatized
function.  Because this non-conforming behavior is no longer the default
behavior for G++, \fB\-Wnon-template-friend\fR allows the compiler to
check existing code for potential trouble spots and is on by default.
This new compiler behavior can be turned off with
\&\fB\-Wno-non-template-friend\fR which keeps the conformant compiler code
but disables the helpful warning.
.Ip "\fB\-Wold-style-cast\fR (\*(C+ only)" 4
.IX Item "-Wold-style-cast ( only)"
Warn if an old-style (C-style) cast to a non-void type is used within
a \*(C+ program.  The new-style casts (\fBstatic_cast\fR,
\&\fBreinterpret_cast\fR, and \fBconst_cast\fR) are less vulnerable to
unintended effects and much easier to search for.
.Ip "\fB\-Woverloaded-virtual\fR (\*(C+ only)" 4
.IX Item "-Woverloaded-virtual ( only)"
Warn when a function declaration hides virtual functions from a
base class.  For example, in:
.Sp
.Vb 3
\&        struct A {
\&          virtual void f();
\&        };
.Ve
.Vb 3
\&        struct B: public A {
\&          void f(int);
\&        };
.Ve
the \f(CW\*(C`A\*(C'\fR class version of \f(CW\*(C`f\*(C'\fR is hidden in \f(CW\*(C`B\*(C'\fR, and code
like:
.Sp
.Vb 2
\&        B* b;
\&        b->f();
.Ve
will fail to compile.
.Ip "\fB\-Wno-pmf-conversions\fR (\*(C+ only)" 4
.IX Item "-Wno-pmf-conversions ( only)"
Disable the diagnostic for converting a bound pointer to member function
to a plain pointer.
.Ip "\fB\-Wsign-promo\fR (\*(C+ only)" 4
.IX Item "-Wsign-promo ( only)"
Warn when overload resolution chooses a promotion from unsigned or
enumerated type to a signed type, over a conversion to an unsigned type of
the same size.  Previous versions of G++ would try to preserve
unsignedness, but the standard mandates the current behavior.
.Ip "\fB\-Wsynth\fR (\*(C+ only)" 4
.IX Item "-Wsynth ( only)"
Warn when G++'s synthesis behavior does not match that of cfront.  For
instance:
.Sp
.Vb 4
\&        struct A {
\&          operator int ();
\&          A& operator = (int);
\&        };
.Ve
.Vb 5
\&        main ()
\&        {
\&          A a,b;
\&          a = b;
\&        }
.Ve
In this example, G++ will synthesize a default \fBA& operator =
(const A&);\fR, while cfront will use the user-defined \fBoperator =\fR.
.Sh "Options Controlling Objective-C Dialect"
.IX Subsection "Options Controlling Objective-C Dialect"
(\s-1NOTE:\s0 This manual does not describe the Objective-C language itself.  See
<\fBhttp://gcc.gnu.org/readings.html\fR> for references.)
.PP
This section describes the command-line options that are only meaningful
for Objective-C programs, but you can also use most of the \s-1GNU\s0 compiler
options regardless of what language your program is in.  For example,
you might compile a file \f(CW\*(C`some_class.m\*(C'\fR like this:
.PP
.Vb 1
\&        gcc -g -fgnu-runtime -O -c some_class.m
.Ve
In this example, \fB\-fgnu-runtime\fR is an option meant only for
Objective-C programs; you can use the other options with any language
supported by \s-1GCC\s0.
.PP
Here is a list of options that are \fIonly\fR for compiling Objective-C
programs:
.Ip "\fB\-fconstant-string-class=\fR\fIclass-name\fR" 4
.IX Item "-fconstant-string-class=class-name"
Use \fIclass-name\fR as the name of the class to instantiate for each
literal string specified with the syntax \f(CW\*(C`@"..."\*(C'\fR.  The default
class name is \f(CW\*(C`NXConstantString\*(C'\fR if the \s-1GNU\s0 runtime is being used, and
\&\f(CW\*(C`NSConstantString\*(C'\fR if the NeXT runtime is being used (see below).  The
\&\fB\-fconstant-cfstrings\fR option, if also present, will override the
\&\fB\-fconstant-string-class\fR setting and cause \f(CW\*(C`@"..."\*(C'\fR literals
to be laid out as constant CoreFoundation strings.
.Ip "\fB\-fgnu-runtime\fR" 4
.IX Item "-fgnu-runtime"
Generate object code compatible with the standard \s-1GNU\s0 Objective-C
runtime.  This is the default for most types of systems.
.Ip "\fB\-fnext-runtime\fR" 4
.IX Item "-fnext-runtime"
Generate output compatible with the NeXT runtime.  This is the default
for NeXT-based systems, including Darwin and Mac \s-1OS\s0 X.  The macro
\&\f(CW\*(C`_\|_NEXT_RUNTIME_\|_\*(C'\fR is predefined if (and only if) this option is
used.
.Ip "\fB\-fno-nil-receivers\fR" 4
.IX Item "-fno-nil-receivers"
Assume that all Objective-C message dispatches (e.g.,
\&\f(CW\*(C`[receiver message:arg]\*(C'\fR) in this translation unit ensure that the receiver
is not \f(CW\*(C`nil\*(C'\fR.  This allows for more efficient entry points in the runtime to be
used.  Currently, this option is only available in conjunction with
the NeXT runtime on Mac \s-1OS\s0 X 10.3 and later.
.Ip "\fB\-fobjc-exceptions\fR" 4
.IX Item "-fobjc-exceptions"
Enable syntactic support for structured exception handling in Objective-C,
similar to what is offered by \*(C+ and Java.  Currently, this option is only
available in conjunction with the NeXT runtime on Mac \s-1OS\s0 X 10.3 and later.
.Sp
.Vb 23
\&          @try {
\&            ...
\&               @throw expr;
\&            ...
\&          }
\&          @catch (AnObjCClass *exc) {
\&            ...
\&              @throw expr;
\&            ...
\&              @throw;
\&            ...
\&          }
\&          @catch (AnotherClass *exc) {
\&            ...
\&          }
\&          @catch (id allOthers) {
\&            ...
\&          }
\&          @finally {
\&            ...
\&              @throw expr;
\&            ...
\&          }
.Ve
The \f(CW\*(C`@throw\*(C'\fR statement may appear anywhere in an Objective-C or
Objective-\*(C+ program; when used inside of a \f(CW\*(C`@catch\*(C'\fR block, the
\&\f(CW\*(C`@throw\*(C'\fR may appear without an argument (as shown above), in which case
the object caught by the \f(CW\*(C`@catch\*(C'\fR will be rethrown.
.Sp
Note that only (pointers to) Objective-C objects may be thrown and
caught using this scheme.  When an object is thrown, it will be caught
by the nearest \f(CW\*(C`@catch\*(C'\fR clause capable of handling objects of that type,
analogously to how \f(CW\*(C`catch\*(C'\fR blocks work in \*(C+ and Java.  A
\&\f(CW\*(C`@catch(id ...)\*(C'\fR clause (as shown above) may also be provided to catch
any and all Objective-C exceptions not caught by previous \f(CW\*(C`@catch\*(C'\fR
clauses (if any).
.Sp
The \f(CW\*(C`@finally\*(C'\fR clause, if present, will be executed upon exit from the
immediately preceding \f(CW\*(C`@try ... @catch\*(C'\fR section.  This will happen
regardless of whether any exceptions are thrown, caught or rethrown
inside the \f(CW\*(C`@try ... @catch\*(C'\fR section, analogously to the behavior
of the \f(CW\*(C`finally\*(C'\fR clause in Java.
.Sp
There are several caveats to using the new exception mechanism:
.RS 4
.Ip "\(bu" 4
Although currently designed to be binary compatible with \f(CW\*(C`NS_HANDLER\*(C'\fR\-style
idioms provided by the \f(CW\*(C`NSException\*(C'\fR class, the new
exceptions can only be used on Mac \s-1OS\s0 X 10.3 (Panther) and later
systems, due to additional functionality needed in the (NeXT) Objective-C
runtime.
.Ip "\(bu" 4
As mentioned above, the new exceptions do not support handling
types other than Objective-C objects.   Furthermore, when used from
Objective-\*(C+, the Objective-C exception model does not interoperate with \*(C+
exceptions at this time.  This means you cannot \f(CW\*(C`@throw\*(C'\fR an exception
from Objective-C and \f(CW\*(C`catch\*(C'\fR it in \*(C+, or vice versa
(i.e., \f(CW\*(C`throw ... @catch\*(C'\fR).
.RE
.RS 4
.Sp
The \fB\-fobjc-exceptions\fR switch also enables the use of synchronization
blocks for thread-safe execution:
.Sp
.Vb 3
\&          @synchronized (ObjCClass *guard) {
\&            ...
\&          }
.Ve
Upon entering the \f(CW\*(C`@synchronized\*(C'\fR block, a thread of execution shall
first check whether a lock has been placed on the corresponding \f(CW\*(C`guard\*(C'\fR
object by another thread.  If it has, the current thread shall wait until
the other thread relinquishes its lock.  Once \f(CW\*(C`guard\*(C'\fR becomes available,
the current thread will place its own lock on it, execute the code contained in
the \f(CW\*(C`@synchronized\*(C'\fR block, and finally relinquish the lock (thereby
making \f(CW\*(C`guard\*(C'\fR available to other threads).
.Sp
Unlike Java, Objective-C does not allow for entire methods to be marked
\&\f(CW\*(C`@synchronized\*(C'\fR.  Note that throwing exceptions out of
\&\f(CW\*(C`@synchronized\*(C'\fR blocks is allowed, and will cause the guarding object
to be unlocked properly.
.RE
.Ip "\fB\-freplace-objc-classes\fR" 4
.IX Item "-freplace-objc-classes"
Emit a special marker instructing \fB\f(BIld\fB\|(1)\fR not to statically link in
the resulting object file, and allow \fB\f(BIdyld\fB\|(1)\fR to load it in at
run time instead.  This is used in conjunction with the Fix-and-Continue
debugging mode, where the object file in question may be recompiled and
dynamically reloaded in the course of program execution, without the need
to restart the program itself.  Currently, Fix-and-Continue functionality
is only available in conjunction with the NeXT runtime on Mac \s-1OS\s0 X 10.3
and later.
.Ip "\fB\-fzero-link\fR" 4
.IX Item "-fzero-link"
When compiling for the NeXT runtime, the compiler ordinarily replaces calls
to \f(CW\*(C`objc_getClass("...")\*(C'\fR (when the name of the class is known at
compile time) with static class references that get initialized at load time,
which improves run-time performance.  Specifying the \fB\-fzero-link\fR flag
suppresses this behavior and causes calls to \f(CW\*(C`objc_getClass("...")\*(C'\fR
to be retained.  This is useful in Zero-Link debugging mode, since it allows
for individual class implementations to be modified during program execution.
.Ip "\fB\-gen-decls\fR" 4
.IX Item "-gen-decls"
Dump interface declarations for all classes seen in the source file to a
file named \fI\fIsourcename\fI.decl\fR.
.Ip "\fB\-Wno-protocol\fR" 4
.IX Item "-Wno-protocol"
If a class is declared to implement a protocol, a warning is issued for
every method in the protocol that is not implemented by the class.  The
default behavior is to issue a warning for every method not explicitly
implemented in the class, even if a method implementation is inherited
from the superclass.  If you use the \f(CW\*(C`\-Wno\-protocol\*(C'\fR option, then
methods inherited from the superclass are considered to be implemented,
and no warning is issued for them.
.Ip "\fB\-Wselector\fR" 4
.IX Item "-Wselector"
Warn if multiple methods of different types for the same selector are
found during compilation.  The check is performed on the list of methods
in the final stage of compilation.  Additionally, a check is performed
for each selector appearing in a \f(CW\*(C`@selector(...)\*(C'\fR
expression, and a corresponding method for that selector has been found
during compilation.  Because these checks scan the method table only at
the end of compilation, these warnings are not produced if the final
stage of compilation is not reached, for example because an error is
found during compilation, or because the \f(CW\*(C`\-fsyntax\-only\*(C'\fR option is
being used.
.Ip "\fB\-Wundeclared-selector\fR" 4
.IX Item "-Wundeclared-selector"
Warn if a \f(CW\*(C`@selector(...)\*(C'\fR expression referring to an
undeclared selector is found.  A selector is considered undeclared if no
method with that name has been declared before the
\&\f(CW\*(C`@selector(...)\*(C'\fR expression, either explicitly in an
\&\f(CW\*(C`@interface\*(C'\fR or \f(CW\*(C`@protocol\*(C'\fR declaration, or implicitly in
an \f(CW\*(C`@implementation\*(C'\fR section.  This option always performs its
checks as soon as a \f(CW\*(C`@selector(...)\*(C'\fR expression is found,
while \f(CW\*(C`\-Wselector\*(C'\fR only performs its checks in the final stage of
compilation.  This also enforces the coding style convention
that methods and selectors must be declared before being used.
.Ip "\fB\-print-objc-runtime-info\fR" 4
.IX Item "-print-objc-runtime-info"
Generate C header describing the largest structure that is passed by
value, if any.
.Sh "Options to Control Diagnostic Messages Formatting"
.IX Subsection "Options to Control Diagnostic Messages Formatting"
Traditionally, diagnostic messages have been formatted irrespective of
the output device's aspect (e.g. its width, ...).  The options described
below can be used to control the diagnostic messages formatting
algorithm, e.g. how many characters per line, how often source location
information should be reported.  Right now, only the \*(C+ front end can
honor these options.  However it is expected, in the near future, that
the remaining front ends would be able to digest them correctly.
.Ip "\fB\-fmessage-length=\fR\fIn\fR" 4
.IX Item "-fmessage-length=n"
Try to format error messages so that they fit on lines of about \fIn\fR
characters.  The default is 72 characters for \fBg++\fR and 0 for the rest of
the front ends supported by \s-1GCC\s0.  If \fIn\fR is zero, then no
line-wrapping will be done; each error message will appear on a single
line.
.Ip "\fB\-fdiagnostics-show-location=once\fR" 4
.IX Item "-fdiagnostics-show-location=once"
Only meaningful in line-wrapping mode.  Instructs the diagnostic messages
reporter to emit \fIonce\fR source location information; that is, in
case the message is too long to fit on a single physical line and has to
be wrapped, the source location won't be emitted (as prefix) again,
over and over, in subsequent continuation lines.  This is the default
behavior.
.Ip "\fB\-fdiagnostics-show-location=every-line\fR" 4
.IX Item "-fdiagnostics-show-location=every-line"
Only meaningful in line-wrapping mode.  Instructs the diagnostic
messages reporter to emit the same source location information (as
prefix) for physical lines that result from the process of breaking
a message which is too long to fit on a single line.
.Sh "Options to Request or Suppress Warnings"
.IX Subsection "Options to Request or Suppress Warnings"
Warnings are diagnostic messages that report constructions which
are not inherently erroneous but which are risky or suggest there
may have been an error.
.PP
You can request many specific warnings with options beginning \fB\-W\fR,
for example \fB\-Wimplicit\fR to request warnings on implicit
declarations.  Each of these specific warning options also has a
negative form beginning \fB\-Wno-\fR to turn off warnings;
for example, \fB\-Wno-implicit\fR.  This manual lists only one of the
two forms, whichever is not the default.
.PP
The following options control the amount and kinds of warnings produced
by \s-1GCC\s0; for further, language-specific options also refer to
\&\fB\*(C+ Dialect Options\fR and \fBObjective-C Dialect Options\fR.
.Ip "\fB\-fsyntax-only\fR" 4
.IX Item "-fsyntax-only"
Check the code for syntax errors, but don't do anything beyond that.
.Ip "\fB\-pedantic\fR" 4
.IX Item "-pedantic"
Issue all the warnings demanded by strict \s-1ISO\s0 C and \s-1ISO\s0 \*(C+;
reject all programs that use forbidden extensions, and some other
programs that do not follow \s-1ISO\s0 C and \s-1ISO\s0 \*(C+.  For \s-1ISO\s0 C, follows the
version of the \s-1ISO\s0 C standard specified by any \fB\-std\fR option used.
.Sp
Valid \s-1ISO\s0 C and \s-1ISO\s0 \*(C+ programs should compile properly with or without
this option (though a rare few will require \fB\-ansi\fR or a
\&\fB\-std\fR option specifying the required version of \s-1ISO\s0 C).  However,
without this option, certain \s-1GNU\s0 extensions and traditional C and \*(C+
features are supported as well.  With this option, they are rejected.
.Sp
\&\fB\-pedantic\fR does not cause warning messages for use of the
alternate keywords whose names begin and end with \fB_\|_\fR.  Pedantic
warnings are also disabled in the expression that follows
\&\f(CW\*(C`_\|_extension_\|_\*(C'\fR.  However, only system header files should use
these escape routes; application programs should avoid them.
.Sp
Some users try to use \fB\-pedantic\fR to check programs for strict \s-1ISO\s0
C conformance.  They soon find that it does not do quite what they want:
it finds some non-ISO practices, but not all\-\-\-only those for which
\&\s-1ISO\s0 C \fIrequires\fR a diagnostic, and some others for which
diagnostics have been added.
.Sp
A feature to report any failure to conform to \s-1ISO\s0 C might be useful in
some instances, but would require considerable additional work and would
be quite different from \fB\-pedantic\fR.  We don't have plans to
support such a feature in the near future.
.Sp
Where the standard specified with \fB\-std\fR represents a \s-1GNU\s0
extended dialect of C, such as \fBgnu89\fR or \fBgnu99\fR, there is a
corresponding \fIbase standard\fR, the version of \s-1ISO\s0 C on which the \s-1GNU\s0
extended dialect is based.  Warnings from \fB\-pedantic\fR are given
where they are required by the base standard.  (It would not make sense
for such warnings to be given only for features not in the specified \s-1GNU\s0
C dialect, since by definition the \s-1GNU\s0 dialects of C include all
features the compiler supports with the given option, and there would be
nothing to warn about.)
.Ip "\fB\-pedantic-errors\fR" 4
.IX Item "-pedantic-errors"
Like \fB\-pedantic\fR, except that errors are produced rather than
warnings.
.Ip "\fB\-w\fR" 4
.IX Item "-w"
Inhibit all warning messages.
.Ip "\fB\-Wno-import\fR" 4
.IX Item "-Wno-import"
Inhibit warning messages about the use of \fB#import\fR.
.Ip "\fB\-Wchar-subscripts\fR" 4
.IX Item "-Wchar-subscripts"
Warn if an array subscript has type \f(CW\*(C`char\*(C'\fR.  This is a common cause
of error, as programmers often forget that this type is signed on some
machines.
.Ip "\fB\-Wcomment\fR" 4
.IX Item "-Wcomment"
Warn whenever a comment-start sequence \fB/*\fR appears in a \fB/*\fR
comment, or whenever a Backslash-Newline appears in a \fB//\fR comment.
.Ip "\fB\-Wformat\fR" 4
.IX Item "-Wformat"
Check calls to \f(CW\*(C`printf\*(C'\fR and \f(CW\*(C`scanf\*(C'\fR, etc., to make sure that
the arguments supplied have types appropriate to the format string
specified, and that the conversions specified in the format string make
sense.  This includes standard functions, and others specified by format
attributes, in the \f(CW\*(C`printf\*(C'\fR,
\&\f(CW\*(C`scanf\*(C'\fR, \f(CW\*(C`strftime\*(C'\fR and \f(CW\*(C`strfmon\*(C'\fR (an X/Open extension,
not in the C standard) families.
.Sp
The formats are checked against the format features supported by \s-1GNU\s0
libc version 2.2.  These include all \s-1ISO\s0 C90 and C99 features, as well
as features from the Single Unix Specification and some \s-1BSD\s0 and \s-1GNU\s0
extensions.  Other library implementations may not support all these
features; \s-1GCC\s0 does not support warning about features that go beyond a
particular library's limitations.  However, if \fB\-pedantic\fR is used
with \fB\-Wformat\fR, warnings will be given about format features not
in the selected standard version (but not for \f(CW\*(C`strfmon\*(C'\fR formats,
since those are not in any version of the C standard).  
.Sp
Since \fB\-Wformat\fR also checks for null format arguments for
several functions, \fB\-Wformat\fR also implies \fB\-Wnonnull\fR.
.Sp
\&\fB\-Wformat\fR is included in \fB\-Wall\fR.  For more control over some
aspects of format checking, the options \fB\-Wformat-y2k\fR,
\&\fB\-Wno-format-extra-args\fR, \fB\-Wno-format-zero-length\fR,
\&\fB\-Wformat-nonliteral\fR, \fB\-Wformat-security\fR, and
\&\fB\-Wformat=2\fR are available, but are not included in \fB\-Wall\fR.
.Ip "\fB\-Wformat-y2k\fR" 4
.IX Item "-Wformat-y2k"
If \fB\-Wformat\fR is specified, also warn about \f(CW\*(C`strftime\*(C'\fR
formats which may yield only a two-digit year.
.Ip "\fB\-Wno-format-extra-args\fR" 4
.IX Item "-Wno-format-extra-args"
If \fB\-Wformat\fR is specified, do not warn about excess arguments to a
\&\f(CW\*(C`printf\*(C'\fR or \f(CW\*(C`scanf\*(C'\fR format function.  The C standard specifies
that such arguments are ignored.
.Sp
Where the unused arguments lie between used arguments that are
specified with \fB$\fR operand number specifications, normally
warnings are still given, since the implementation could not know what
type to pass to \f(CW\*(C`va_arg\*(C'\fR to skip the unused arguments.  However,
in the case of \f(CW\*(C`scanf\*(C'\fR formats, this option will suppress the
warning if the unused arguments are all pointers, since the Single
Unix Specification says that such unused arguments are allowed.
.Ip "\fB\-Wno-format-zero-length\fR" 4
.IX Item "-Wno-format-zero-length"
If \fB\-Wformat\fR is specified, do not warn about zero-length formats.
The C standard specifies that zero-length formats are allowed.
.Ip "\fB\-Wformat-nonliteral\fR" 4
.IX Item "-Wformat-nonliteral"
If \fB\-Wformat\fR is specified, also warn if the format string is not a
string literal and so cannot be checked, unless the format function
takes its format arguments as a \f(CW\*(C`va_list\*(C'\fR.
.Ip "\fB\-Wformat-security\fR" 4
.IX Item "-Wformat-security"
If \fB\-Wformat\fR is specified, also warn about uses of format
functions that represent possible security problems.  At present, this
warns about calls to \f(CW\*(C`printf\*(C'\fR and \f(CW\*(C`scanf\*(C'\fR functions where the
format string is not a string literal and there are no format arguments,
as in \f(CW\*(C`printf (foo);\*(C'\fR.  This may be a security hole if the format
string came from untrusted input and contains \fB%n\fR.  (This is
currently a subset of what \fB\-Wformat-nonliteral\fR warns about, but
in future warnings may be added to \fB\-Wformat-security\fR that are not
included in \fB\-Wformat-nonliteral\fR.)
.Ip "\fB\-Wformat=2\fR" 4
.IX Item "-Wformat=2"
Enable \fB\-Wformat\fR plus format checks not included in
\&\fB\-Wformat\fR.  Currently equivalent to \fB\-Wformat
\&\-Wformat-nonliteral \-Wformat-security \-Wformat-y2k\fR.
.Ip "\fB\-Wnonnull\fR" 4
.IX Item "-Wnonnull"
Warn about passing a null pointer for arguments marked as
requiring a non-null value by the \f(CW\*(C`nonnull\*(C'\fR function attribute.
.Sp
\&\fB\-Wnonnull\fR is included in \fB\-Wall\fR and \fB\-Wformat\fR.  It
can be disabled with the \fB\-Wno-nonnull\fR option.
.Ip "\fB\-Winit-self\fR (C, \*(C+, and Objective-C only)" 4
.IX Item "-Winit-self (C, , and Objective-C only)"
Warn about uninitialized variables which are initialized with themselves.
Note this option can only be used with the \fB\-Wuninitialized\fR option,
which in turn only works with \fB\-O1\fR and above.
.Sp
For example, \s-1GCC\s0 will warn about \f(CW\*(C`i\*(C'\fR being uninitialized in the
following snippet only when \fB\-Winit-self\fR has been specified:
.Sp
.Vb 5
\&        int f()
\&        {
\&          int i = i;
\&          return i;
\&        }
.Ve
.Ip "\fB\-Wimplicit-int\fR" 4
.IX Item "-Wimplicit-int"
Warn when a declaration does not specify a type.
.Ip "\fB\-Wimplicit-function-declaration\fR" 4
.IX Item "-Wimplicit-function-declaration"
.PD 0
.Ip "\fB\-Werror-implicit-function-declaration\fR" 4
.IX Item "-Werror-implicit-function-declaration"
.PD
Give a warning (or error) whenever a function is used before being
declared.
.Ip "\fB\-Wimplicit\fR" 4
.IX Item "-Wimplicit"
Same as \fB\-Wimplicit-int\fR and \fB\-Wimplicit-function-declaration\fR.
.Ip "\fB\-Wmain\fR" 4
.IX Item "-Wmain"
Warn if the type of \fBmain\fR is suspicious.  \fBmain\fR should be a
function with external linkage, returning int, taking either zero
arguments, two, or three arguments of appropriate types.
.Ip "\fB\-Wmissing-braces\fR" 4
.IX Item "-Wmissing-braces"
Warn if an aggregate or union initializer is not fully bracketed.  In
the following example, the initializer for \fBa\fR is not fully
bracketed, but that for \fBb\fR is fully bracketed.
.Sp
.Vb 2
\&        int a[2][2] = { 0, 1, 2, 3 };
\&        int b[2][2] = { { 0, 1 }, { 2, 3 } };
.Ve
.Ip "\fB\-Wparentheses\fR" 4
.IX Item "-Wparentheses"
Warn if parentheses are omitted in certain contexts, such
as when there is an assignment in a context where a truth value
is expected, or when operators are nested whose precedence people
often get confused about.
.Sp
Also warn about constructions where there may be confusion to which
\&\f(CW\*(C`if\*(C'\fR statement an \f(CW\*(C`else\*(C'\fR branch belongs.  Here is an example of
such a case:
.Sp
.Vb 7
\&        {
\&          if (a)
\&            if (b)
\&              foo ();
\&          else
\&            bar ();
\&        }
.Ve
In C, every \f(CW\*(C`else\*(C'\fR branch belongs to the innermost possible \f(CW\*(C`if\*(C'\fR
statement, which in this example is \f(CW\*(C`if (b)\*(C'\fR.  This is often not
what the programmer expected, as illustrated in the above example by
indentation the programmer chose.  When there is the potential for this
confusion, \s-1GCC\s0 will issue a warning when this flag is specified.
To eliminate the warning, add explicit braces around the innermost
\&\f(CW\*(C`if\*(C'\fR statement so there is no way the \f(CW\*(C`else\*(C'\fR could belong to
the enclosing \f(CW\*(C`if\*(C'\fR.  The resulting code would look like this:
.Sp
.Vb 9
\&        {
\&          if (a)
\&            {
\&              if (b)
\&                foo ();
\&              else
\&                bar ();
\&            }
\&        }
.Ve
.Ip "\fB\-Wsequence-point\fR" 4
.IX Item "-Wsequence-point"
Warn about code that may have undefined semantics because of violations
of sequence point rules in the C standard.
.Sp
The C standard defines the order in which expressions in a C program are
evaluated in terms of \fIsequence points\fR, which represent a partial
ordering between the execution of parts of the program: those executed
before the sequence point, and those executed after it.  These occur
after the evaluation of a full expression (one which is not part of a
larger expression), after the evaluation of the first operand of a
\&\f(CW\*(C`&&\*(C'\fR, \f(CW\*(C`||\*(C'\fR, \f(CW\*(C`? :\*(C'\fR or \f(CW\*(C`,\*(C'\fR (comma) operator, before a
function is called (but after the evaluation of its arguments and the
expression denoting the called function), and in certain other places.
Other than as expressed by the sequence point rules, the order of
evaluation of subexpressions of an expression is not specified.  All
these rules describe only a partial order rather than a total order,
since, for example, if two functions are called within one expression
with no sequence point between them, the order in which the functions
are called is not specified.  However, the standards committee have
ruled that function calls do not overlap.
.Sp
It is not specified when between sequence points modifications to the
values of objects take effect.  Programs whose behavior depends on this
have undefined behavior; the C standard specifies that ``Between the
previous and next sequence point an object shall have its stored value
modified at most once by the evaluation of an expression.  Furthermore,
the prior value shall be read only to determine the value to be
stored.''.  If a program breaks these rules, the results on any
particular implementation are entirely unpredictable.
.Sp
Examples of code with undefined behavior are \f(CW\*(C`a = a++;\*(C'\fR, \f(CW\*(C`a[n]
= b[n++]\*(C'\fR and \f(CW\*(C`a[i++] = i;\*(C'\fR.  Some more complicated cases are not
diagnosed by this option, and it may give an occasional false positive
result, but in general it has been found fairly effective at detecting
this sort of problem in programs.
.Sp
The present implementation of this option only works for C programs.  A
future implementation may also work for \*(C+ programs.
.Sp
The C standard is worded confusingly, therefore there is some debate
over the precise meaning of the sequence point rules in subtle cases.
Links to discussions of the problem, including proposed formal
definitions, may be found on the \s-1GCC\s0 readings page, at
<\fBhttp://gcc.gnu.org/readings.html\fR>.
.Ip "\fB\-Wreturn-type\fR" 4
.IX Item "-Wreturn-type"
Warn whenever a function is defined with a return-type that defaults to
\&\f(CW\*(C`int\*(C'\fR.  Also warn about any \f(CW\*(C`return\*(C'\fR statement with no
return-value in a function whose return-type is not \f(CW\*(C`void\*(C'\fR.
.Sp
For \*(C+, a function without return type always produces a diagnostic
message, even when \fB\-Wno-return-type\fR is specified.  The only
exceptions are \fBmain\fR and functions defined in system headers.
.Ip "\fB\-Wswitch\fR" 4
.IX Item "-Wswitch"
Warn whenever a \f(CW\*(C`switch\*(C'\fR statement has an index of enumerated type
and lacks a \f(CW\*(C`case\*(C'\fR for one or more of the named codes of that
enumeration.  (The presence of a \f(CW\*(C`default\*(C'\fR label prevents this
warning.)  \f(CW\*(C`case\*(C'\fR labels outside the enumeration range also
provoke warnings when this option is used.
.Ip "\fB\-Wswitch-default\fR" 4
.IX Item "-Wswitch-default"
Warn whenever a \f(CW\*(C`switch\*(C'\fR statement does not have a \f(CW\*(C`default\*(C'\fR
case.
.Ip "\fB\-Wswitch-enum\fR" 4
.IX Item "-Wswitch-enum"
Warn whenever a \f(CW\*(C`switch\*(C'\fR statement has an index of enumerated type
and lacks a \f(CW\*(C`case\*(C'\fR for one or more of the named codes of that
enumeration.  \f(CW\*(C`case\*(C'\fR labels outside the enumeration range also
provoke warnings when this option is used.
.Ip "\fB\-Wtrigraphs\fR" 4
.IX Item "-Wtrigraphs"
Warn if any trigraphs are encountered that might change the meaning of
the program (trigraphs within comments are not warned about).
.Ip "\fB\-Wunused-function\fR" 4
.IX Item "-Wunused-function"
Warn whenever a static function is declared but not defined or a
non\e-inline static function is unused.
.Ip "\fB\-Wunused-label\fR" 4
.IX Item "-Wunused-label"
Warn whenever a label is declared but not used.
.Sp
To suppress this warning use the \fBunused\fR attribute.
.Ip "\fB\-Wunused-parameter\fR" 4
.IX Item "-Wunused-parameter"
Warn whenever a function parameter is unused aside from its declaration.
.Sp
To suppress this warning use the \fBunused\fR attribute.
.Ip "\fB\-Wunused-variable\fR" 4
.IX Item "-Wunused-variable"
Warn whenever a local variable or non-constant static variable is unused
aside from its declaration
.Sp
To suppress this warning use the \fBunused\fR attribute.
.Ip "\fB\-Wunused-value\fR" 4
.IX Item "-Wunused-value"
Warn whenever a statement computes a result that is explicitly not used.
.Sp
To suppress this warning cast the expression to \fBvoid\fR.
.Ip "\fB\-Wunused\fR" 4
.IX Item "-Wunused"
All the above \fB\-Wunused\fR options combined.
.Sp
In order to get a warning about an unused function parameter, you must
either specify \fB\-Wextra \-Wunused\fR (note that \fB\-Wall\fR implies
\&\fB\-Wunused\fR), or separately specify \fB\-Wunused-parameter\fR.
.Ip "\fB\-Wuninitialized\fR" 4
.IX Item "-Wuninitialized"
Warn if an automatic variable is used without first being initialized or
if a variable may be clobbered by a \f(CW\*(C`setjmp\*(C'\fR call.
.Sp
These warnings are possible only in optimizing compilation,
because they require data flow information that is computed only
when optimizing.  If you don't specify \fB\-O\fR, you simply won't
get these warnings.
.Sp
If you want to warn about code which uses the uninitialized value of the
variable in its own initializer, use the \fB\-Winit-self\fR option.
.Sp
These warnings occur only for variables that are candidates for
register allocation.  Therefore, they do not occur for a variable that
is declared \f(CW\*(C`volatile\*(C'\fR, or whose address is taken, or whose size
is other than 1, 2, 4 or 8 bytes.  Also, they do not occur for
structures, unions or arrays, even when they are in registers.
.Sp
Note that there may be no warning about a variable that is used only
to compute a value that itself is never used, because such
computations may be deleted by data flow analysis before the warnings
are printed.
.Sp
These warnings are made optional because \s-1GCC\s0 is not smart
enough to see all the reasons why the code might be correct
despite appearing to have an error.  Here is one example of how
this can happen:
.Sp
.Vb 12
\&        {
\&          int x;
\&          switch (y)
\&            {
\&            case 1: x = 1;
\&              break;
\&            case 2: x = 4;
\&              break;
\&            case 3: x = 5;
\&            }
\&          foo (x);
\&        }
.Ve
If the value of \f(CW\*(C`y\*(C'\fR is always 1, 2 or 3, then \f(CW\*(C`x\*(C'\fR is
always initialized, but \s-1GCC\s0 doesn't know this.  Here is
another common case:
.Sp
.Vb 6
\&        {
\&          int save_y;
\&          if (change_y) save_y = y, y = new_y;
\&          ...
\&          if (change_y) y = save_y;
\&        }
.Ve
This has no bug because \f(CW\*(C`save_y\*(C'\fR is used only if it is set.
.Sp
This option also warns when a non-volatile automatic variable might be
changed by a call to \f(CW\*(C`longjmp\*(C'\fR.  These warnings as well are possible
only in optimizing compilation.
.Sp
The compiler sees only the calls to \f(CW\*(C`setjmp\*(C'\fR.  It cannot know
where \f(CW\*(C`longjmp\*(C'\fR will be called; in fact, a signal handler could
call it at any point in the code.  As a result, you may get a warning
even when there is in fact no problem because \f(CW\*(C`longjmp\*(C'\fR cannot
in fact be called at the place which would cause a problem.
.Sp
Some spurious warnings can be avoided if you declare all the functions
you use that never return as \f(CW\*(C`noreturn\*(C'\fR.  
.Ip "\fB\-Wunknown-pragmas\fR" 4
.IX Item "-Wunknown-pragmas"
Warn when a #pragma directive is encountered which is not understood by
\&\s-1GCC\s0.  If this command line option is used, warnings will even be issued
for unknown pragmas in system header files.  This is not the case if
the warnings were only enabled by the \fB\-Wall\fR command line option.
.Ip "\fB\-Wstrict-aliasing\fR" 4
.IX Item "-Wstrict-aliasing"
This option is only active when \fB\-fstrict-aliasing\fR is active.
It warns about code which might break the strict aliasing rules that the
compiler is using for optimization. The warning does not catch all
cases, but does attempt to catch the more common pitfalls. It is
included in \fB\-Wall\fR.
.Ip "\fB\-Wall\fR" 4
.IX Item "-Wall"
All of the above \fB\-W\fR options combined.  This enables all the
warnings about constructions that some users consider questionable, and
that are easy to avoid (or modify to prevent the warning), even in
conjunction with macros.  This also enables some language-specific
warnings described in \fB\*(C+ Dialect Options\fR and
\&\fBObjective-C Dialect Options\fR.
.PP
The following \fB\-W...\fR options are not implied by \fB\-Wall\fR.
Some of them warn about constructions that users generally do not
consider questionable, but which occasionally you might wish to check
for; others warn about constructions that are necessary or hard to avoid
in some cases, and there is no simple way to modify the code to suppress
the warning.
.Ip "\fB\-Wextra\fR" 4
.IX Item "-Wextra"
(This option used to be called \fB\-W\fR.  The older name is still
supported, but the newer name is more descriptive.)  Print extra warning
messages for these events:
.RS 4
.Ip "\(bu" 4
A function can return either with or without a value.  (Falling
off the end of the function body is considered returning without
a value.)  For example, this function would evoke such a
warning:
.Sp
.Vb 5
\&        foo (a)
\&        {
\&          if (a > 0)
\&            return a;
\&        }
.Ve
.Ip "\(bu" 4
An expression-statement or the left-hand side of a comma expression
contains no side effects.
To suppress the warning, cast the unused expression to void.
For example, an expression such as \fBx[i,j]\fR will cause a warning,
but \fBx[(void)i,j]\fR will not.
.Ip "\(bu" 4
An unsigned value is compared against zero with \fB<\fR or \fB>=\fR.
.Ip "\(bu" 4
A comparison like \fBx<=y<=z\fR appears; this is equivalent to
\&\fB(x<=y ? 1 : 0) <= z\fR, which is a different interpretation from
that of ordinary mathematical notation.
.Ip "\(bu" 4
Storage-class specifiers like \f(CW\*(C`static\*(C'\fR are not the first things in
a declaration.  According to the C Standard, this usage is obsolescent.
.Ip "\(bu" 4
The return type of a function has a type qualifier such as \f(CW\*(C`const\*(C'\fR.
Such a type qualifier has no effect, since the value returned by a
function is not an lvalue.  (But don't warn about the \s-1GNU\s0 extension of
\&\f(CW\*(C`volatile void\*(C'\fR return types.  That extension will be warned about
if \fB\-pedantic\fR is specified.)
.Ip "\(bu" 4
If \fB\-Wall\fR or \fB\-Wunused\fR is also specified, warn about unused
arguments.
.Ip "\(bu" 4
A comparison between signed and unsigned values could produce an
incorrect result when the signed value is converted to unsigned.
(But don't warn if \fB\-Wno-sign-compare\fR is also specified.)
.Ip "\(bu" 4
An aggregate has an initializer which does not initialize all members.
For example, the following code would cause such a warning, because
\&\f(CW\*(C`x.h\*(C'\fR would be implicitly initialized to zero:
.Sp
.Vb 2
\&        struct s { int f, g, h; };
\&        struct s x = { 3, 4 };
.Ve
.Ip "\(bu" 4
A function parameter is declared without a type specifier in K&R-style
functions:
.Sp
.Vb 1
\&        void foo(bar) { }
.Ve
.Ip "\(bu" 4
An empty body occurs in an \fBif\fR or \fBelse\fR statement.
.Ip "\(bu" 4
A pointer is compared against integer zero with \fB<\fR, \fB<=\fR,
\&\fB>\fR, or \fB>=\fR.
.Ip "\(bu" 4
A variable might be changed by \fBlongjmp\fR or \fBvfork\fR.
.Ip "\(bu" 4
Any of several floating-point events that often indicate errors, such as
overflow, underflow, loss of precision, etc.
.Ip "*<(\*(C+ only)>" 4
.IX Item "*<( only)>"
An enumerator and a non-enumerator both appear in a conditional expression.
.Ip "*<(\*(C+ only)>" 4
.IX Item "*<( only)>"
A non-static reference or non-static \fBconst\fR member appears in a
class without constructors.
.Ip "*<(\*(C+ only)>" 4
.IX Item "*<( only)>"
Ambiguous virtual bases.
.Ip "*<(\*(C+ only)>" 4
.IX Item "*<( only)>"
Subscripting an array which has been declared \fBregister\fR.
.Ip "*<(\*(C+ only)>" 4
.IX Item "*<( only)>"
Taking the address of a variable which has been declared \fBregister\fR.
.Ip "*<(\*(C+ only)>" 4
.IX Item "*<( only)>"
A base class is not initialized in a derived class' copy constructor.
.RE
.RS 4
.RE
.Ip "\fB\-Wno-div-by-zero\fR" 4
.IX Item "-Wno-div-by-zero"
Do not warn about compile-time integer division by zero.  Floating point
division by zero is not warned about, as it can be a legitimate way of
obtaining infinities and NaNs.
.Ip "\fB\-Wsystem-headers\fR" 4
.IX Item "-Wsystem-headers"
Print warning messages for constructs found in system header files.
Warnings from system headers are normally suppressed, on the assumption
that they usually do not indicate real problems and would only make the
compiler output harder to read.  Using this command line option tells
\&\s-1GCC\s0 to emit warnings from system headers as if they occurred in user
code.  However, note that using \fB\-Wall\fR in conjunction with this
option will \fInot\fR warn about unknown pragmas in system
headers\-\-\-for that, \fB\-Wunknown-pragmas\fR must also be used.
.Ip "\fB\-Wfloat-equal\fR" 4
.IX Item "-Wfloat-equal"
Warn if floating point values are used in equality comparisons.
.Sp
The idea behind this is that sometimes it is convenient (for the
programmer) to consider floating-point values as approximations to
infinitely precise real numbers.  If you are doing this, then you need
to compute (by analyzing the code, or in some other way) the maximum or
likely maximum error that the computation introduces, and allow for it
when performing comparisons (and when producing output, but that's a
different problem).  In particular, instead of testing for equality, you
would check to see whether the two values have ranges that overlap; and
this is done with the relational operators, so equality comparisons are
probably mistaken.
.Ip "\fB\-Wtraditional\fR (C only)" 4
.IX Item "-Wtraditional (C only)"
Warn about certain constructs that behave differently in traditional and
\&\s-1ISO\s0 C.  Also warn about \s-1ISO\s0 C constructs that have no traditional C
equivalent, and/or problematic constructs which should be avoided.
.RS 4
.Ip "\(bu" 4
Macro parameters that appear within string literals in the macro body.
In traditional C macro replacement takes place within string literals,
but does not in \s-1ISO\s0 C.
.Ip "\(bu" 4
In traditional C, some preprocessor directives did not exist.
Traditional preprocessors would only consider a line to be a directive
if the \fB#\fR appeared in column 1 on the line.  Therefore
\&\fB\-Wtraditional\fR warns about directives that traditional C
understands but would ignore because the \fB#\fR does not appear as the
first character on the line.  It also suggests you hide directives like
\&\fB#pragma\fR not understood by traditional C by indenting them.  Some
traditional implementations would not recognize \fB#elif\fR, so it
suggests avoiding it altogether.
.Ip "\(bu" 4
A function-like macro that appears without arguments.
.Ip "\(bu" 4
The unary plus operator.
.Ip "\(bu" 4
The \fBU\fR integer constant suffix, or the \fBF\fR or \fBL\fR floating point
constant suffixes.  (Traditional C does support the \fBL\fR suffix on integer
constants.)  Note, these suffixes appear in macros defined in the system
headers of most modern systems, e.g. the \fB_MIN\fR/\fB_MAX\fR macros in \f(CW\*(C`<limits.h>\*(C'\fR.
Use of these macros in user code might normally lead to spurious
warnings, however \s-1GCC\s0's integrated preprocessor has enough context to
avoid warning in these cases.
.Ip "\(bu" 4
A function declared external in one block and then used after the end of
the block.
.Ip "\(bu" 4
A \f(CW\*(C`switch\*(C'\fR statement has an operand of type \f(CW\*(C`long\*(C'\fR.
.Ip "\(bu" 4
A non-\f(CW\*(C`static\*(C'\fR function declaration follows a \f(CW\*(C`static\*(C'\fR one.
This construct is not accepted by some traditional C compilers.
.Ip "\(bu" 4
The \s-1ISO\s0 type of an integer constant has a different width or
signedness from its traditional type.  This warning is only issued if
the base of the constant is ten.  I.e. hexadecimal or octal values, which
typically represent bit patterns, are not warned about.
.Ip "\(bu" 4
Usage of \s-1ISO\s0 string concatenation is detected.
.Ip "\(bu" 4
Initialization of automatic aggregates.
.Ip "\(bu" 4
Identifier conflicts with labels.  Traditional C lacks a separate
namespace for labels.
.Ip "\(bu" 4
Initialization of unions.  If the initializer is zero, the warning is
omitted.  This is done under the assumption that the zero initializer in
user code appears conditioned on e.g. \f(CW\*(C`_\|_STDC_\|_\*(C'\fR to avoid missing
initializer warnings and relies on default initialization to zero in the
traditional C case.
.Ip "\(bu" 4
Conversions by prototypes between fixed/floating point values and vice
versa.  The absence of these prototypes when compiling with traditional
C would cause serious problems.  This is a subset of the possible
conversion warnings, for the full set use \fB\-Wconversion\fR.
.Ip "\(bu" 4
Use of \s-1ISO\s0 C style function definitions.  This warning intentionally is
\&\fInot\fR issued for prototype declarations or variadic functions
because these \s-1ISO\s0 C features will appear in your code when using
libiberty's traditional C compatibility macros, \f(CW\*(C`PARAMS\*(C'\fR and
\&\f(CW\*(C`VPARAMS\*(C'\fR.  This warning is also bypassed for nested functions
because that feature is already a \s-1GCC\s0 extension and thus not relevant to
traditional C compatibility.
.RE
.RS 4
.RE
.Ip "\fB\-Wdeclaration-after-statement\fR (C only)" 4
.IX Item "-Wdeclaration-after-statement (C only)"
Warn when a declaration is found after a statement in a block.  This
construct, known from \*(C+, was introduced with \s-1ISO\s0 C99 and is by default
allowed in \s-1GCC\s0.  It is not supported by \s-1ISO\s0 C90 and was not supported by
\&\s-1GCC\s0 versions before \s-1GCC\s0 3.0.  
.Ip "\fB\-Wundef\fR" 4
.IX Item "-Wundef"
Warn if an undefined identifier is evaluated in an \fB#if\fR directive.
.Ip "\fB\-Wendif-labels\fR" 4
.IX Item "-Wendif-labels"
Warn whenever an \fB#else\fR or an \fB#endif\fR are followed by text.
.Ip "\fB\-Wshadow\fR" 4
.IX Item "-Wshadow"
Warn whenever a local variable shadows another local variable, parameter or
global variable or whenever a built-in function is shadowed.
.Ip "\fB\-Wlarger-than-\fR\fIlen\fR" 4
.IX Item "-Wlarger-than-len"
Warn whenever an object of larger than \fIlen\fR bytes is defined.
.Ip "\fB\-Wpointer-arith\fR" 4
.IX Item "-Wpointer-arith"
Warn about anything that depends on the ``size of'' a function type or
of \f(CW\*(C`void\*(C'\fR.  \s-1GNU\s0 C assigns these types a size of 1, for
convenience in calculations with \f(CW\*(C`void *\*(C'\fR pointers and pointers
to functions.
.Ip "\fB\-Wbad-function-cast\fR (C only)" 4
.IX Item "-Wbad-function-cast (C only)"
Warn whenever a function call is cast to a non-matching type.
For example, warn if \f(CW\*(C`int malloc()\*(C'\fR is cast to \f(CW\*(C`anything *\*(C'\fR.
.Ip "\fB\-Wcast-qual\fR" 4
.IX Item "-Wcast-qual"
Warn whenever a pointer is cast so as to remove a type qualifier from
the target type.  For example, warn if a \f(CW\*(C`const char *\*(C'\fR is cast
to an ordinary \f(CW\*(C`char *\*(C'\fR.
.Ip "\fB\-Wcast-align\fR" 4
.IX Item "-Wcast-align"
Warn whenever a pointer is cast such that the required alignment of the
target is increased.  For example, warn if a \f(CW\*(C`char *\*(C'\fR is cast to
an \f(CW\*(C`int *\*(C'\fR on machines where integers can only be accessed at
two- or four-byte boundaries.
.Ip "\fB\-Wwrite-strings\fR" 4
.IX Item "-Wwrite-strings"
When compiling C, give string constants the type \f(CW\*(C`const
char[\f(CIlength\f(CW]\*(C'\fR so that
copying the address of one into a non-\f(CW\*(C`const\*(C'\fR \f(CW\*(C`char *\*(C'\fR
pointer will get a warning; when compiling \*(C+, warn about the
deprecated conversion from string constants to \f(CW\*(C`char *\*(C'\fR.
These warnings will help you find at
compile time code that can try to write into a string constant, but
only if you have been very careful about using \f(CW\*(C`const\*(C'\fR in
declarations and prototypes.  Otherwise, it will just be a nuisance;
this is why we did not make \fB\-Wall\fR request these warnings.
.Ip "\fB\-Wconversion\fR" 4
.IX Item "-Wconversion"
Warn if a prototype causes a type conversion that is different from what
would happen to the same argument in the absence of a prototype.  This
includes conversions of fixed point to floating and vice versa, and
conversions changing the width or signedness of a fixed point argument
except when the same as the default promotion.
.Sp
Also, warn if a negative integer constant expression is implicitly
converted to an unsigned type.  For example, warn about the assignment
\&\f(CW\*(C`x = \-1\*(C'\fR if \f(CW\*(C`x\*(C'\fR is unsigned.  But do not warn about explicit
casts like \f(CW\*(C`(unsigned) \-1\*(C'\fR.
.Ip "\fB\-Wsign-compare\fR" 4
.IX Item "-Wsign-compare"
Warn when a comparison between signed and unsigned values could produce
an incorrect result when the signed value is converted to unsigned.
This warning is also enabled by \fB\-Wextra\fR; to get the other warnings
of \fB\-Wextra\fR without this warning, use \fB\-Wextra \-Wno-sign-compare\fR.
.Ip "\fB\-Waggregate-return\fR" 4
.IX Item "-Waggregate-return"
Warn if any functions that return structures or unions are defined or
called.  (In languages where you can return an array, this also elicits
a warning.)
.Ip "\fB\-Wstrict-prototypes\fR (C only)" 4
.IX Item "-Wstrict-prototypes (C only)"
Warn if a function is declared or defined without specifying the
argument types.  (An old-style function definition is permitted without
a warning if preceded by a declaration which specifies the argument
types.)
.Ip "\fB\-Wold-style-definition\fR (C only)" 4
.IX Item "-Wold-style-definition (C only)"
Warn if an old-style function definition is used.  A warning is given
even if there is a previous prototype.
.Ip "\fB\-Wmissing-prototypes\fR (C only)" 4
.IX Item "-Wmissing-prototypes (C only)"
Warn if a global function is defined without a previous prototype
declaration.  This warning is issued even if the definition itself
provides a prototype.  The aim is to detect global functions that fail
to be declared in header files.
.Ip "\fB\-Wmissing-declarations\fR (C only)" 4
.IX Item "-Wmissing-declarations (C only)"
Warn if a global function is defined without a previous declaration.
Do so even if the definition itself provides a prototype.
Use this option to detect global functions that are not declared in
header files.
.Ip "\fB\-Wmissing-noreturn\fR" 4
.IX Item "-Wmissing-noreturn"
Warn about functions which might be candidates for attribute \f(CW\*(C`noreturn\*(C'\fR.
Note these are only possible candidates, not absolute ones.  Care should
be taken to manually verify functions actually do not ever return before
adding the \f(CW\*(C`noreturn\*(C'\fR attribute, otherwise subtle code generation
bugs could be introduced.  You will not get a warning for \f(CW\*(C`main\*(C'\fR in
hosted C environments.
.Ip "\fB\-Wmissing-format-attribute\fR" 4
.IX Item "-Wmissing-format-attribute"
If \fB\-Wformat\fR is enabled, also warn about functions which might be
candidates for \f(CW\*(C`format\*(C'\fR attributes.  Note these are only possible
candidates, not absolute ones.  \s-1GCC\s0 will guess that \f(CW\*(C`format\*(C'\fR
attributes might be appropriate for any function that calls a function
like \f(CW\*(C`vprintf\*(C'\fR or \f(CW\*(C`vscanf\*(C'\fR, but this might not always be the
case, and some functions for which \f(CW\*(C`format\*(C'\fR attributes are
appropriate may not be detected.  This option has no effect unless
\&\fB\-Wformat\fR is enabled (possibly by \fB\-Wall\fR).
.Ip "\fB\-Wno-multichar\fR" 4
.IX Item "-Wno-multichar"
Do not warn if a multicharacter constant (\fB'\s-1FOOF\s0'\fR) is used.
Usually they indicate a typo in the user's code, as they have
implementation-defined values, and should not be used in portable code.
.Ip "\fB\-Wno-deprecated-declarations\fR" 4
.IX Item "-Wno-deprecated-declarations"
Do not warn about uses of functions, variables, and types marked as
deprecated by using the \f(CW\*(C`deprecated\*(C'\fR attribute.
(@pxref{Function Attributes}, \f(CW@pxref\fR{Variable Attributes},
\&\f(CW@pxref\fR{Type Attributes}.)
.Ip "\fB\-Wpacked\fR" 4
.IX Item "-Wpacked"
Warn if a structure is given the packed attribute, but the packed
attribute has no effect on the layout or size of the structure.
Such structures may be mis-aligned for little benefit.  For
instance, in this code, the variable \f(CW\*(C`f.x\*(C'\fR in \f(CW\*(C`struct bar\*(C'\fR
will be misaligned even though \f(CW\*(C`struct bar\*(C'\fR does not itself
have the packed attribute:
.Sp
.Vb 8
\&        struct foo {
\&          int x;
\&          char a, b, c, d;
\&        } __attribute__((packed));
\&        struct bar {
\&          char z;
\&          struct foo f;
\&        };
.Ve
.Ip "\fB\-Wpadded\fR" 4
.IX Item "-Wpadded"
Warn if padding is included in a structure, either to align an element
of the structure or to align the whole structure.  Sometimes when this
happens it is possible to rearrange the fields of the structure to
reduce the padding and so make the structure smaller.
.Ip "\fB\-Wredundant-decls\fR" 4
.IX Item "-Wredundant-decls"
Warn if anything is declared more than once in the same scope, even in
cases where multiple declaration is valid and changes nothing.
.Ip "\fB\-Wnested-externs\fR (C only)" 4
.IX Item "-Wnested-externs (C only)"
Warn if an \f(CW\*(C`extern\*(C'\fR declaration is encountered within a function.
.Ip "\fB\-Wunreachable-code\fR" 4
.IX Item "-Wunreachable-code"
Warn if the compiler detects that code will never be executed.
.Sp
This option is intended to warn when the compiler detects that at
least a whole line of source code will never be executed, because
some condition is never satisfied or because it is after a
procedure that never returns.
.Sp
It is possible for this option to produce a warning even though there
are circumstances under which part of the affected line can be executed,
so care should be taken when removing apparently-unreachable code.
.Sp
For instance, when a function is inlined, a warning may mean that the
line is unreachable in only one inlined copy of the function.
.Sp
This option is not made part of \fB\-Wall\fR because in a debugging
version of a program there is often substantial code which checks
correct functioning of the program and is, hopefully, unreachable
because the program does work.  Another common use of unreachable
code is to provide behavior which is selectable at compile-time.
.Ip "\fB\-Winline\fR" 4
.IX Item "-Winline"
Warn if a function can not be inlined and it was declared as inline.
Even with this option, the compiler will not warn about failures to
inline functions declared in system headers.
.Sp
The compiler uses a variety of heuristics to determine whether or not
to inline a function.  For example, the compiler takes into account
the size of the function being inlined and the the amount of inlining
that has already been done in the current function.  Therefore,
seemingly insignificant changes in the source program can cause the
warnings produced by \fB\-Winline\fR to appear or disappear.
.Ip "\fB\-Wno-invalid-offsetof\fR (\*(C+ only)" 4
.IX Item "-Wno-invalid-offsetof ( only)"
Suppress warnings from applying the \fBoffsetof\fR macro to a non-POD
type.  According to the 1998 \s-1ISO\s0 \*(C+ standard, applying \fBoffsetof\fR
to a non-POD type is undefined.  In existing \*(C+ implementations,
however, \fBoffsetof\fR typically gives meaningful results even when
applied to certain kinds of non-POD types. (Such as a simple
\&\fBstruct\fR that fails to be a \s-1POD\s0 type only by virtue of having a
constructor.)  This flag is for users who are aware that they are
writing nonportable code and who have deliberately chosen to ignore the
warning about it.
.Sp
The restrictions on \fBoffsetof\fR may be relaxed in a future version
of the \*(C+ standard.
.Ip "\fB\-Winvalid-pch\fR" 4
.IX Item "-Winvalid-pch"
Warn if a precompiled header is found in
the search path but can't be used.
.Ip "\fB\-Wlong-long\fR" 4
.IX Item "-Wlong-long"
Warn if \fBlong long\fR type is used.  This is default.  To inhibit
the warning messages, use \fB\-Wno-long-long\fR.  Flags
\&\fB\-Wlong-long\fR and \fB\-Wno-long-long\fR are taken into account
only when \fB\-pedantic\fR flag is used.
.Ip "\fB\-Wdisabled-optimization\fR" 4
.IX Item "-Wdisabled-optimization"
Warn if a requested optimization pass is disabled.  This warning does
not generally indicate that there is anything wrong with your code; it
merely indicates that \s-1GCC\s0's optimizers were unable to handle the code
effectively.  Often, the problem is that your code is too big or too
complex; \s-1GCC\s0 will refuse to optimize programs when the optimization
itself is likely to take inordinate amounts of time.
.Ip "\fB\-Werror\fR" 4
.IX Item "-Werror"
Make all warnings into errors.
.Sh "Options for Debugging Your Program or \s-1GCC\s0"
.IX Subsection "Options for Debugging Your Program or GCC"
\&\s-1GCC\s0 has various special options that are used for debugging
either your program or \s-1GCC:\s0
.Ip "\fB\-g\fR" 4
.IX Item "-g"
Produce debugging information in the operating system's native format
(stabs, \s-1COFF\s0, \s-1XCOFF\s0, or \s-1DWARF\s0).  \s-1GDB\s0 can work with this debugging
information.
.Sp
On most systems that use stabs format, \fB\-g\fR enables use of extra
debugging information that only \s-1GDB\s0 can use; this extra information
makes debugging work better in \s-1GDB\s0 but will probably make other debuggers
crash or
refuse to read the program.  If you want to control for certain whether
to generate the extra information, use \fB\-gstabs+\fR, \fB\-gstabs\fR,
\&\fB\-gxcoff+\fR, \fB\-gxcoff\fR, or \fB\-gvms\fR (see below).
.Sp
Unlike most other C compilers, \s-1GCC\s0 allows you to use \fB\-g\fR with
\&\fB\-O\fR.  The shortcuts taken by optimized code may occasionally
produce surprising results: some variables you declared may not exist
at all; flow of control may briefly move where you did not expect it;
some statements may not be executed because they compute constant
results or their values were already at hand; some statements may
execute in different places because they were moved out of loops.
.Sp
Nevertheless it proves possible to debug optimized output.  This makes
it reasonable to use the optimizer for programs that might have bugs.
.Sp
The following options are useful when \s-1GCC\s0 is generated with the
capability for more than one debugging format.
.Ip "\fB\-ggdb\fR" 4
.IX Item "-ggdb"
Produce debugging information for use by \s-1GDB\s0.  This means to use the
most expressive format available (\s-1DWARF\s0 2, stabs, or the native format
if neither of those are supported), including \s-1GDB\s0 extensions if at all
possible.
.Ip "\fB\-gstabs\fR" 4
.IX Item "-gstabs"
Produce debugging information in stabs format (if that is supported),
without \s-1GDB\s0 extensions.  This is the format used by \s-1DBX\s0 on most \s-1BSD\s0
systems.  On \s-1MIPS\s0, Alpha and System V Release 4 systems this option
produces stabs debugging output which is not understood by \s-1DBX\s0 or \s-1SDB\s0.
On System V Release 4 systems this option requires the \s-1GNU\s0 assembler.
.Ip "\fB\-feliminate-unused-debug-symbols\fR" 4
.IX Item "-feliminate-unused-debug-symbols"
Produce debugging information in stabs format (if that is supported),
for only symbols that are actually used.
.Ip "\fB\-gstabs+\fR" 4
.IX Item "-gstabs+"
Produce debugging information in stabs format (if that is supported),
using \s-1GNU\s0 extensions understood only by the \s-1GNU\s0 debugger (\s-1GDB\s0).  The
use of these extensions is likely to make other debuggers crash or
refuse to read the program.
.Ip "\fB\-gcoff\fR" 4
.IX Item "-gcoff"
Produce debugging information in \s-1COFF\s0 format (if that is supported).
This is the format used by \s-1SDB\s0 on most System V systems prior to
System V Release 4.
.Ip "\fB\-gxcoff\fR" 4
.IX Item "-gxcoff"
Produce debugging information in \s-1XCOFF\s0 format (if that is supported).
This is the format used by the \s-1DBX\s0 debugger on \s-1IBM\s0 \s-1RS/6000\s0 systems.
.Ip "\fB\-gxcoff+\fR" 4
.IX Item "-gxcoff+"
Produce debugging information in \s-1XCOFF\s0 format (if that is supported),
using \s-1GNU\s0 extensions understood only by the \s-1GNU\s0 debugger (\s-1GDB\s0).  The
use of these extensions is likely to make other debuggers crash or
refuse to read the program, and may cause assemblers other than the \s-1GNU\s0
assembler (\s-1GAS\s0) to fail with an error.
.Ip "\fB\-gdwarf-2\fR" 4
.IX Item "-gdwarf-2"
Produce debugging information in \s-1DWARF\s0 version 2 format (if that is
supported).  This is the format used by \s-1DBX\s0 on \s-1IRIX\s0 6.
.Ip "\fB\-gvms\fR" 4
.IX Item "-gvms"
Produce debugging information in \s-1VMS\s0 debug format (if that is
supported).  This is the format used by \s-1DEBUG\s0 on \s-1VMS\s0 systems.
.Ip "\fB\-g\fR\fIlevel\fR" 4
.IX Item "-glevel"
.PD 0
.Ip "\fB\-ggdb\fR\fIlevel\fR" 4
.IX Item "-ggdblevel"
.Ip "\fB\-gstabs\fR\fIlevel\fR" 4
.IX Item "-gstabslevel"
.Ip "\fB\-gcoff\fR\fIlevel\fR" 4
.IX Item "-gcofflevel"
.Ip "\fB\-gxcoff\fR\fIlevel\fR" 4
.IX Item "-gxcofflevel"
.Ip "\fB\-gvms\fR\fIlevel\fR" 4
.IX Item "-gvmslevel"
.PD
Request debugging information and also use \fIlevel\fR to specify how
much information.  The default level is 2.
.Sp
Level 1 produces minimal information, enough for making backtraces in
parts of the program that you don't plan to debug.  This includes
descriptions of functions and external variables, but no information
about local variables and no line numbers.
.Sp
Level 3 includes extra information, such as all the macro definitions
present in the program.  Some debuggers support macro expansion when
you use \fB\-g3\fR.
.Sp
Note that in order to avoid confusion between \s-1DWARF1\s0 debug level 2,
and \s-1DWARF2\s0 \fB\-gdwarf-2\fR does not accept a concatenated debug
level.  Instead use an additional \fB\-g\fR\fIlevel\fR option to
change the debug level for \s-1DWARF2\s0.
.Ip "\fB\-feliminate-dwarf2\-dups\fR" 4
.IX Item "-feliminate-dwarf2-dups"
Compress \s-1DWARF2\s0 debugging information by eliminating duplicated
information about each symbol.  This option only makes sense when
generating \s-1DWARF2\s0 debugging information with \fB\-gdwarf-2\fR.
.Ip "\fB\-p\fR" 4
.IX Item "-p"
Generate extra code to write profile information suitable for the
analysis program \fBprof\fR.  You must use this option when compiling
the source files you want data about, and you must also use it when
linking.
.Ip "\fB\-pg\fR" 4
.IX Item "-pg"
Generate extra code to write profile information suitable for the
analysis program \fBgprof\fR.  You must use this option when compiling
the source files you want data about, and you must also use it when
linking.
.Ip "\fB\-Q\fR" 4
.IX Item "-Q"
Makes the compiler print out each function name as it is compiled, and
print some statistics about each pass when it finishes.
.Ip "\fB\-ftime-report\fR" 4
.IX Item "-ftime-report"
Makes the compiler print some statistics about the time consumed by each
pass when it finishes.
.Ip "\fB\-fmem-report\fR" 4
.IX Item "-fmem-report"
Makes the compiler print some statistics about permanent memory
allocation when it finishes.
.Ip "\fB\-fprofile-arcs\fR" 4
.IX Item "-fprofile-arcs"
Add code so that program flow \fIarcs\fR are instrumented.  During
execution the program records how many times each branch and call is
executed and how many times it is taken or returns.  When the compiled
program exits it saves this data to a file called
\&\fI\fIauxname\fI.gcda\fR for each source file. The data may be used for
profile-directed optimizations (\fB\-fbranch-probabilities\fR), or for
test coverage analysis (\fB\-ftest-coverage\fR). Each object file's
\&\fIauxname\fR is generated from the name of the output file, if
explicitly specified and it is not the final executable, otherwise it is
the basename of the source file. In both cases any suffix is removed
(e.g.  \fIfoo.gcda\fR for input file \fIdir/foo.c\fR, or
\&\fIdir/foo.gcda\fR for output file specified as \fB\-o dir/foo.o\fR).
.RS 4
.Ip "@bullet" 4
.IX Item "@bullet"
Compile the source files with \fB\-fprofile-arcs\fR plus optimization
and code generation options. For test coverage analysis, use the
additional \fB\-ftest-coverage\fR option. You do not need to profile
every source file in a program.
.Ip "@cvmmfu" 4
.IX Item "@cvmmfu"
Link your object files with \fB\-lgcov\fR or \fB\-fprofile-arcs\fR
(the latter implies the former).
.Ip "@dwnngv" 4
.IX Item "@dwnngv"
Run the program on a representative workload to generate the arc profile
information. This may be repeated any number of times. You can run
concurrent instances of your program, and provided that the file system
supports locking, the data files will be correctly updated. Also
\&\f(CW\*(C`fork\*(C'\fR calls are detected and correctly handled (double counting
will not happen).
.Ip "@exoohw" 4
.IX Item "@exoohw"
For profile-directed optimizations, compile the source files again with
the same optimization and code generation options plus
\&\fB\-fbranch-probabilities\fR.
.Ip "@fyppix" 4
.IX Item "@fyppix"
For test coverage analysis, use \fBgcov\fR to produce human readable
information from the \fI.gcno\fR and \fI.gcda\fR files. Refer to the
\&\fBgcov\fR documentation for further information.
.RE
.RS 4
.Sp
With \fB\-fprofile-arcs\fR, for each function of your program \s-1GCC\s0
creates a program flow graph, then finds a spanning tree for the graph.
Only arcs that are not on the spanning tree have to be instrumented: the
compiler adds code to count the number of times that these arcs are
executed.  When an arc is the only exit or only entrance to a block, the
instrumentation code can be added to the block; otherwise, a new basic
block must be created to hold the instrumentation code.
.RE
.Ip "\fB\-ftest-coverage\fR" 4
.IX Item "-ftest-coverage"
Produce a notes file that the \fBgcov\fR code-coverage utility can use to
show program coverage. Each source file's note file is called
\&\fI\fIauxname\fI.gcno\fR. Refer to the \fB\-fprofile-arcs\fR option
above for a description of \fIauxname\fR and instructions on how to
generate test coverage data. Coverage data will match the source files
more closely, if you do not optimize.
.Ip "\fB\-d\fR\fIletters\fR" 4
.IX Item "-dletters"
Says to make debugging dumps during compilation at times specified by
\&\fIletters\fR.  This is used for debugging the compiler.  The file names
for most of the dumps are made by appending a pass number and a word to
the \fIdumpname\fR. \fIdumpname\fR is generated from the name of the
output file, if explicitly specified and it is not an executable,
otherwise it is the basename of the source file. In both cases any
suffix is removed (e.g.  \fIfoo.01.rtl\fR or \fIfoo.02.sibling\fR).
Here are the possible letters for use in \fIletters\fR, and their
meanings:
.RS 4
.Ip "\fBA\fR" 4
.IX Item "A"
Annotate the assembler output with miscellaneous debugging information.
.Ip "\fBb\fR" 4
.IX Item "b"
Dump after computing branch probabilities, to \fI\fIfile\fI.12.bp\fR.
.Ip "\fBB\fR" 4
.IX Item "B"
Dump after block reordering, to \fI\fIfile\fI.31.bbro\fR.
.Ip "\fBc\fR" 4
.IX Item "c"
Dump after instruction combination, to the file \fI\fIfile\fI.20.combine\fR.
.Ip "\fBC\fR" 4
.IX Item "C"
Dump after the first if conversion, to the file \fI\fIfile\fI.14.ce1\fR.
Also dump after the second if conversion, to the file \fI\fIfile\fI.21.ce2\fR.
.Ip "\fBd\fR" 4
.IX Item "d"
Dump after branch target load optimization, to to \fI\fIfile\fI.32.btl\fR.
Also dump after delayed branch scheduling, to \fI\fIfile\fI.36.dbr\fR.
.Ip "\fBD\fR" 4
.IX Item "D"
Dump all macro definitions, at the end of preprocessing, in addition to
normal output.
.Ip "\fBE\fR" 4
.IX Item "E"
Dump after the third if conversion, to \fI\fIfile\fI.30.ce3\fR.
.Ip "\fBf\fR" 4
.IX Item "f"
Dump after control and data flow analysis, to \fI\fIfile\fI.11.cfg\fR.
Also dump after life analysis, to \fI\fIfile\fI.19.life\fR.
.Ip "\fBF\fR" 4
.IX Item "F"
Dump after purging \f(CW\*(C`ADDRESSOF\*(C'\fR codes, to \fI\fIfile\fI.07.addressof\fR.
.Ip "\fBg\fR" 4
.IX Item "g"
Dump after global register allocation, to \fI\fIfile\fI.25.greg\fR.
.Ip "\fBG\fR" 4
.IX Item "G"
Dump after \s-1GCSE\s0, to \fI\fIfile\fI.08.gcse\fR.
Also dump after jump bypassing and control flow optimizations, to
\&\fI\fIfile\fI.10.bypass\fR.
.Ip "\fBh\fR" 4
.IX Item "h"
Dump after finalization of \s-1EH\s0 handling code, to \fI\fIfile\fI.03.eh\fR.
.Ip "\fBi\fR" 4
.IX Item "i"
Dump after sibling call optimizations, to \fI\fIfile\fI.02.sibling\fR.
.Ip "\fBj\fR" 4
.IX Item "j"
Dump after the first jump optimization, to \fI\fIfile\fI.04.jump\fR.
.Ip "\fBk\fR" 4
.IX Item "k"
Dump after conversion from registers to stack, to \fI\fIfile\fI.34.stack\fR.
.Ip "\fBl\fR" 4
.IX Item "l"
Dump after local register allocation, to \fI\fIfile\fI.24.lreg\fR.
.Ip "\fBL\fR" 4
.IX Item "L"
Dump after loop optimization passes, to \fI\fIfile\fI.09.loop\fR and
\&\fI\fIfile\fI.16.loop2\fR.
.Ip "\fBM\fR" 4
.IX Item "M"
Dump after performing the machine dependent reorganization pass, to
\&\fI\fIfile\fI.35.mach\fR.
.Ip "\fBn\fR" 4
.IX Item "n"
Dump after register renumbering, to \fI\fIfile\fI.29.rnreg\fR.
.Ip "\fBN\fR" 4
.IX Item "N"
Dump after the register move pass, to \fI\fIfile\fI.22.regmove\fR.
.Ip "\fBo\fR" 4
.IX Item "o"
Dump after post-reload optimizations, to \fI\fIfile\fI.26.postreload\fR.
.Ip "\fBr\fR" 4
.IX Item "r"
Dump after \s-1RTL\s0 generation, to \fI\fIfile\fI.01.rtl\fR.
.Ip "\fBR\fR" 4
.IX Item "R"
Dump after the second scheduling pass, to \fI\fIfile\fI.33.sched2\fR.
.Ip "\fBs\fR" 4
.IX Item "s"
Dump after \s-1CSE\s0 (including the jump optimization that sometimes follows
\&\s-1CSE\s0), to \fI\fIfile\fI.06.cse\fR.
.Ip "\fBS\fR" 4
.IX Item "S"
Dump after the first scheduling pass, to \fI\fIfile\fI.23.sched\fR.
.Ip "\fBt\fR" 4
.IX Item "t"
Dump after the second \s-1CSE\s0 pass (including the jump optimization that
sometimes follows \s-1CSE\s0), to \fI\fIfile\fI.18.cse2\fR.
.Ip "\fBT\fR" 4
.IX Item "T"
Dump after running tracer, to \fI\fIfile\fI.15.tracer\fR.
.Ip "\fBu\fR" 4
.IX Item "u"
Dump after null pointer elimination pass to \fI\fIfile\fI.05.null\fR.
.Ip "\fBU\fR" 4
.IX Item "U"
Dump callgraph and unit-at-a-time optimization \fI\fIfile\fI.00.unit\fR.
.Ip "\fBV\fR" 4
.IX Item "V"
Dump after the value profile transformations, to \fI\fIfile\fI.13.vpt\fR.
.Ip "\fBw\fR" 4
.IX Item "w"
Dump after the second flow pass, to \fI\fIfile\fI.27.flow2\fR.
.Ip "\fBz\fR" 4
.IX Item "z"
Dump after the peephole pass, to \fI\fIfile\fI.28.peephole2\fR.
.Ip "\fBZ\fR" 4
.IX Item "Z"
Dump after constructing the web, to \fI\fIfile\fI.17.web\fR.
.Ip "\fBa\fR" 4
.IX Item "a"
Produce all the dumps listed above.
.Ip "\fBH\fR" 4
.IX Item "H"
Produce a core dump whenever an error occurs.
.Ip "\fBm\fR" 4
.IX Item "m"
Print statistics on memory usage, at the end of the run, to
standard error.
.Ip "\fBp\fR" 4
.IX Item "p"
Annotate the assembler output with a comment indicating which
pattern and alternative was used.  The length of each instruction is
also printed.
.Ip "\fBP\fR" 4
.IX Item "P"
Dump the \s-1RTL\s0 in the assembler output as a comment before each instruction.
Also turns on \fB\-dp\fR annotation.
.Ip "\fBv\fR" 4
.IX Item "v"
For each of the other indicated dump files (except for
\&\fI\fIfile\fI.01.rtl\fR), dump a representation of the control flow graph
suitable for viewing with \s-1VCG\s0 to \fI\fIfile\fI.\fIpass\fI.vcg\fR.
.Ip "\fBx\fR" 4
.IX Item "x"
Just generate \s-1RTL\s0 for a function instead of compiling it.  Usually used
with \fBr\fR.
.Ip "\fBy\fR" 4
.IX Item "y"
Dump debugging information during parsing, to standard error.
.RE
.RS 4
.RE
.Ip "\fB\-fdump-unnumbered\fR" 4
.IX Item "-fdump-unnumbered"
When doing debugging dumps (see \fB\-d\fR option above), suppress instruction
numbers and line number note output.  This makes it more feasible to
use diff on debugging dumps for compiler invocations with different
options, in particular with and without \fB\-g\fR.
.Ip "\fB\-fdump-translation-unit\fR (C and \*(C+ only)" 4
.IX Item "-fdump-translation-unit (C and  only)"
.PD 0
.Ip "\fB\-fdump-translation-unit-\fR\fIoptions\fR\fB \fR(C and \*(C+ only)" 4
.IX Item "-fdump-translation-unit-options (C and  only)"
.PD
Dump a representation of the tree structure for the entire translation
unit to a file.  The file name is made by appending \fI.tu\fR to the
source file name.  If the \fB-\fR\fIoptions\fR form is used, \fIoptions\fR
controls the details of the dump as described for the
\&\fB\-fdump-tree\fR options.
.Ip "\fB\-fdump-class-hierarchy\fR (\*(C+ only)" 4
.IX Item "-fdump-class-hierarchy ( only)"
.PD 0
.Ip "\fB\-fdump-class-hierarchy-\fR\fIoptions\fR\fB \fR(\*(C+ only)" 4
.IX Item "-fdump-class-hierarchy-options ( only)"
.PD
Dump a representation of each class's hierarchy and virtual function
table layout to a file.  The file name is made by appending \fI.class\fR
to the source file name.  If the \fB-\fR\fIoptions\fR form is used,
\&\fIoptions\fR controls the details of the dump as described for the
\&\fB\-fdump-tree\fR options.
.Ip "\fB\-fdump-tree-\fR\fIswitch\fR\fB \fR(\*(C+ only)" 4
.IX Item "-fdump-tree-switch ( only)"
.PD 0
.Ip "\fB\-fdump-tree-\fR\fIswitch\fR\fB-\fR\fIoptions\fR\fB \fR(\*(C+ only)" 4
.IX Item "-fdump-tree-switch-options ( only)"
.PD
Control the dumping at various stages of processing the intermediate
language tree to a file.  The file name is generated by appending a switch
specific suffix to the source file name.  If the \fB-\fR\fIoptions\fR
form is used, \fIoptions\fR is a list of \fB-\fR separated options that
control the details of the dump. Not all options are applicable to all
dumps, those which are not meaningful will be ignored. The following
options are available
.RS 4
.Ip "\fBaddress\fR" 4
.IX Item "address"
Print the address of each node.  Usually this is not meaningful as it
changes according to the environment and source file. Its primary use
is for tying up a dump file with a debug environment.
.Ip "\fBslim\fR" 4
.IX Item "slim"
Inhibit dumping of members of a scope or body of a function merely
because that scope has been reached. Only dump such items when they
are directly reachable by some other path.
.Ip "\fBall\fR" 4
.IX Item "all"
Turn on all options.
.RE
.RS 4
.Sp
The following tree dumps are possible:
.RS 4
.RE
.Ip "\fBoriginal\fR" 4
.IX Item "original"
Dump before any tree based optimization, to \fI\fIfile\fI.original\fR.
.Ip "\fBoptimized\fR" 4
.IX Item "optimized"
Dump after all tree based optimization, to \fI\fIfile\fI.optimized\fR.
.Ip "\fBinlined\fR" 4
.IX Item "inlined"
Dump after function inlining, to \fI\fIfile\fI.inlined\fR.
.RE
.RS 4
.RE
.Ip "\fB\-frandom-seed=\fR\fIstring\fR" 4
.IX Item "-frandom-seed=string"
This option provides a seed that \s-1GCC\s0 uses when it would otherwise use
random numbers.  It is used to generate certain symbol names
that have to be different in every compiled file. It is also used to
place unique stamps in coverage data files and the object files that
produce them. You can use the \fB\-frandom-seed\fR option to produce
reproducibly identical object files.
.Sp
The \fIstring\fR should be different for every file you compile.
.Ip "\fB\-fsched-verbose=\fR\fIn\fR" 4
.IX Item "-fsched-verbose=n"
On targets that use instruction scheduling, this option controls the
amount of debugging output the scheduler prints.  This information is
written to standard error, unless \fB\-dS\fR or \fB\-dR\fR is
specified, in which case it is output to the usual dump
listing file, \fI.sched\fR or \fI.sched2\fR respectively.  However
for \fIn\fR greater than nine, the output is always printed to standard
error.
.Sp
For \fIn\fR greater than zero, \fB\-fsched-verbose\fR outputs the
same information as \fB\-dRS\fR.  For \fIn\fR greater than one, it
also output basic block probabilities, detailed ready list information
and unit/insn info.  For \fIn\fR greater than two, it includes \s-1RTL\s0
at abort point, control-flow and regions info.  And for \fIn\fR over
four, \fB\-fsched-verbose\fR also includes dependence info.
.Ip "\fB\-save-temps\fR" 4
.IX Item "-save-temps"
Store the usual ``temporary'' intermediate files permanently; place them
in the current directory and name them based on the source file.  Thus,
compiling \fIfoo.c\fR with \fB\-c \-save-temps\fR would produce files
\&\fIfoo.i\fR and \fIfoo.s\fR, as well as \fIfoo.o\fR.  This creates a
preprocessed \fIfoo.i\fR output file even though the compiler now
normally uses an integrated preprocessor.
.Ip "\fB\-time\fR" 4
.IX Item "-time"
Report the \s-1CPU\s0 time taken by each subprocess in the compilation
sequence.  For C source files, this is the compiler proper and assembler
(plus the linker if linking is done).  The output looks like this:
.Sp
.Vb 2
\&        # cc1 0.12 0.01
\&        # as 0.00 0.01
.Ve
The first number on each line is the ``user time,'' that is time spent
executing the program itself.  The second number is ``system time,''
time spent executing operating system routines on behalf of the program.
Both numbers are in seconds.
.Ip "\fB\-print-file-name=\fR\fIlibrary\fR" 4
.IX Item "-print-file-name=library"
Print the full absolute name of the library file \fIlibrary\fR that
would be used when linking\-\-\-and don't do anything else.  With this
option, \s-1GCC\s0 does not compile or link anything; it just prints the
file name.
.Ip "\fB\-print-multi-directory\fR" 4
.IX Item "-print-multi-directory"
Print the directory name corresponding to the multilib selected by any
other switches present in the command line.  This directory is supposed
to exist in \fB\s-1GCC_EXEC_PREFIX\s0\fR.
.Ip "\fB\-print-multi-lib\fR" 4
.IX Item "-print-multi-lib"
Print the mapping from multilib directory names to compiler switches
that enable them.  The directory name is separated from the switches by
\&\fB;\fR, and each switch starts with an \fB@} instead of the
\&\f(CB@samp\fB{-\fR, without spaces between multiple switches.  This is supposed to
ease shell-processing.
.Ip "\fB\-print-prog-name=\fR\fIprogram\fR" 4
.IX Item "-print-prog-name=program"
Like \fB\-print-file-name\fR, but searches for a program such as \fBcpp\fR.
.Ip "\fB\-print-libgcc-file-name\fR" 4
.IX Item "-print-libgcc-file-name"
Same as \fB\-print-file-name=libgcc.a\fR.
.Sp
This is useful when you use \fB\-nostdlib\fR or \fB\-nodefaultlibs\fR
but you do want to link with \fIlibgcc.a\fR.  You can do
.Sp
.Vb 1
\&        gcc -nostdlib <files>... `gcc -print-libgcc-file-name`
.Ve
.Ip "\fB\-print-search-dirs\fR" 4
.IX Item "-print-search-dirs"
Print the name of the configured installation directory and a list of
program and library directories \fBgcc\fR will search\-\-\-and don't do anything else.
.Sp
This is useful when \fBgcc\fR prints the error message
\&\fBinstallation problem, cannot exec cpp0: No such file or directory\fR.
To resolve this you either need to put \fIcpp0\fR and the other compiler
components where \fBgcc\fR expects to find them, or you can set the environment
variable \fB\s-1GCC_EXEC_PREFIX\s0\fR to the directory where you installed them.
Don't forget the trailing '/'.
.Ip "\fB\-dumpmachine\fR" 4
.IX Item "-dumpmachine"
Print the compiler's target machine (for example,
\&\fBi686\-pc-linux-gnu\fR)\-\-\-and don't do anything else.
.Ip "\fB\-dumpversion\fR" 4
.IX Item "-dumpversion"
Print the compiler version (for example, \fB3.0\fR)\-\-\-and don't do
anything else.
.Ip "\fB\-dumpspecs\fR" 4
.IX Item "-dumpspecs"
Print the compiler's built-in specs\-\-\-and don't do anything else.  (This
is used when \s-1GCC\s0 itself is being built.)  
.Ip "\fB\-feliminate-unused-debug-types\fR" 4
.IX Item "-feliminate-unused-debug-types"
Normally, when producing \s-1DWARF2\s0 output, \s-1GCC\s0 will emit debugging
information for all types declared in a compilation
unit, regardless of whether or not they are actually used
in that compilation unit.  Sometimes this is useful, such as
if, in the debugger, you want to cast a value to a type that is
not actually used in your program (but is declared).  More often,
however, this results in a significant amount of wasted space.
With this option, \s-1GCC\s0 will avoid producing debug symbol output
for types that are nowhere used in the source file being compiled.
.Sh "Options That Control Optimization"
.IX Subsection "Options That Control Optimization"
These options control various sorts of optimizations.
.PP
Without any optimization option, the compiler's goal is to reduce the
cost of compilation and to make debugging produce the expected
results.  Statements are independent: if you stop the program with a
breakpoint between statements, you can then assign a new value to any
variable or change the program counter to any other statement in the
function and get exactly the results you would expect from the source
code.
.PP
Turning on optimization flags makes the compiler attempt to improve
the performance and/or code size at the expense of compilation time
and possibly the ability to debug the program.
.PP
The compiler performs optimization based on the knowledge it has of
the program.  Using the \fB\-funit-at-a-time\fR flag will allow the
compiler to consider information gained from later functions in the
file when compiling a function.  Compiling multiple files at once to a
single output file (and using \fB\-funit-at-a-time\fR) will allow
the compiler to use information gained from all of the files when
compiling each of them.
.PP
Not all optimizations are controlled directly by a flag.  Only
optimizations that have a flag are listed.
.Ip "\fB\-O\fR" 4
.IX Item "-O"
.PD 0
.Ip "\fB\-O1\fR" 4
.IX Item "-O1"
.PD
Optimize.  Optimizing compilation takes somewhat more time, and a lot
more memory for a large function.
.Sp
With \fB\-O\fR, the compiler tries to reduce code size and execution
time, without performing any optimizations that take a great deal of
compilation time.
.Sp
\&\fB\-O\fR turns on the following optimization flags:
\&\fB\-fdefer-pop 
\&\-fmerge-constants 
\&\-fthread-jumps 
\&\-floop-optimize 
\&\-fif-conversion 
\&\-fif-conversion2 
\&\-fdelayed-branch 
\&\-fguess-branch-probability 
\&\-fcprop-registers\fR
.Sp
\&\fB\-O\fR also turns on \fB\-fomit-frame-pointer\fR on machines
where doing so does not interfere with debugging.
.Ip "\fB\-O2\fR" 4
.IX Item "-O2"
Optimize even more.  \s-1GCC\s0 performs nearly all supported optimizations
that do not involve a space-speed tradeoff.  The compiler does not
perform loop unrolling or function inlining when you specify \fB\-O2\fR.
As compared to \fB\-O\fR, this option increases both compilation time
and the performance of the generated code.
.Sp
\&\fB\-O2\fR turns on all optimization flags specified by \fB\-O\fR.  It
also turns on the following optimization flags:
\&\fB\-fforce-mem 
\&\-foptimize-sibling-calls 
\&\-fstrength-reduce 
\&\-fcse-follow-jumps  \-fcse-skip-blocks 
\&\-frerun-cse-after-loop  \-frerun-loop-opt 
\&\-fgcse  \-fgcse-lm  \-fgcse-sm  \-fgcse-las 
\&\-fdelete-null-pointer-checks 
\&\-fexpensive-optimizations 
\&\-fregmove 
\&\-fschedule-insns  \-fschedule-insns2 
\&\-fsched-interblock  \-fsched-spec 
\&\-fcaller-saves 
\&\-fpeephole2 
\&\-freorder-blocks  \-freorder-functions 
\&\-fstrict-aliasing 
\&\-funit-at-a-time 
\&\-falign-functions  \-falign-jumps 
\&\-falign-loops  \-falign-labels 
\&\-fcrossjumping\fR
.Sp
Please note the warning under \fB\-fgcse\fR about
invoking \fB\-O2\fR on programs that use computed gotos.
.Ip "\fB\-O3\fR" 4
.IX Item "-O3"
Optimize yet more.  \fB\-O3\fR turns on all optimizations specified by
\&\fB\-O2\fR and also turns on the \fB\-finline-functions\fR,
\&\fB\-fweb\fR and \fB\-frename-registers\fR options.
.Ip "\fB\-O0\fR" 4
.IX Item "-O0"
Do not optimize.  This is the default.
.Ip "\fB\-Os\fR" 4
.IX Item "-Os"
Optimize for size.  \fB\-Os\fR enables all \fB\-O2\fR optimizations that
do not typically increase code size.  It also performs further
optimizations designed to reduce code size.
.Sp
\&\fB\-Os\fR disables the following optimization flags:
\&\fB\-falign-functions  \-falign-jumps  \-falign-loops 
\&\-falign-labels  \-freorder-blocks  \-fprefetch-loop-arrays\fR
.Sp
If you use multiple \fB\-O\fR options, with or without level numbers,
the last such option is the one that is effective.
.PP
Options of the form \fB\-f\fR\fIflag\fR specify machine-independent
flags.  Most flags have both positive and negative forms; the negative
form of \fB\-ffoo\fR would be \fB\-fno-foo\fR.  In the table
below, only one of the forms is listed\-\-\-the one you typically will
use.  You can figure out the other form by either removing \fBno-\fR
or adding it.
.PP
The following options control specific optimizations.  They are either
activated by \fB\-O\fR options or are related to ones that are.  You
can use the following flags in the rare cases when ``fine-tuning'' of
optimizations to be performed is desired.
.Ip "\fB\-fno-default-inline\fR" 4
.IX Item "-fno-default-inline"
Do not make member functions inline by default merely because they are
defined inside the class scope (\*(C+ only).  Otherwise, when you specify
\&\fB\-O\fR, member functions defined inside class scope are compiled
inline by default; i.e., you don't need to add \fBinline\fR in front of
the member function name.
.Ip "\fB\-fno-defer-pop\fR" 4
.IX Item "-fno-defer-pop"
Always pop the arguments to each function call as soon as that function
returns.  For machines which must pop arguments after a function call,
the compiler normally lets arguments accumulate on the stack for several
function calls and pops them all at once.
.Sp
Disabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.Ip "\fB\-fforce-mem\fR" 4
.IX Item "-fforce-mem"
Force memory operands to be copied into registers before doing
arithmetic on them.  This produces better code by making all memory
references potential common subexpressions.  When they are not common
subexpressions, instruction combination should eliminate the separate
register-load.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.Ip "\fB\-fforce-addr\fR" 4
.IX Item "-fforce-addr"
Force memory address constants to be copied into registers before
doing arithmetic on them.  This may produce better code just as
\&\fB\-fforce-mem\fR may.
.Ip "\fB\-fomit-frame-pointer\fR" 4
.IX Item "-fomit-frame-pointer"
Don't keep the frame pointer in a register for functions that
don't need one.  This avoids the instructions to save, set up and
restore frame pointers; it also makes an extra register available
in many functions.  \fBIt also makes debugging impossible on
some machines.\fR
.Sp
On some machines, such as the \s-1VAX\s0, this flag has no effect, because
the standard calling sequence automatically handles the frame pointer
and nothing is saved by pretending it doesn't exist.  The
machine-description macro \f(CW\*(C`FRAME_POINTER_REQUIRED\*(C'\fR controls
whether a target machine supports this flag.  
.Sp
Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.Ip "\fB\-foptimize-sibling-calls\fR" 4
.IX Item "-foptimize-sibling-calls"
Optimize sibling and tail recursive calls.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.Ip "\fB\-fno-inline\fR" 4
.IX Item "-fno-inline"
Don't pay attention to the \f(CW\*(C`inline\*(C'\fR keyword.  Normally this option
is used to keep the compiler from expanding any functions inline.
Note that if you are not optimizing, no functions can be expanded inline.
.Ip "\fB\-finline-functions\fR" 4
.IX Item "-finline-functions"
Integrate all simple functions into their callers.  The compiler
heuristically decides which functions are simple enough to be worth
integrating in this way.
.Sp
If all calls to a given function are integrated, and the function is
declared \f(CW\*(C`static\*(C'\fR, then the function is normally not output as
assembler code in its own right.
.Sp
Enabled at level \fB\-O3\fR.
.Ip "\fB\-finline-limit=\fR\fIn\fR" 4
.IX Item "-finline-limit=n"
By default, \s-1GCC\s0 limits the size of functions that can be inlined.  This flag
allows the control of this limit for functions that are explicitly marked as
inline (i.e., marked with the inline keyword or defined within the class
definition in c++).  \fIn\fR is the size of functions that can be inlined in
number of pseudo instructions (not counting parameter handling).  The default
value of \fIn\fR is 600.
Increasing this value can result in more inlined code at
the cost of compilation time and memory consumption.  Decreasing usually makes
the compilation faster and less code will be inlined (which presumably
means slower programs).  This option is particularly useful for programs that
use inlining heavily such as those based on recursive templates with \*(C+.
.Sp
Inlining is actually controlled by a number of parameters, which may be
specified individually by using \fB\*(--param\fR \fIname\fR\fB=\fR\fIvalue\fR.
The \fB\-finline-limit=\fR\fIn\fR option sets some of these parameters
as follows:
.RS 4
.Sp
.Vb 8
\& @item max-inline-insns-single
\&  is set to I<n>/2.
\& @item max-inline-insns-auto
\&  is set to I<n>/2.
\& @item min-inline-insns
\&  is set to 130 or I<n>/4, whichever is smaller.
\& @item max-inline-insns-rtl
\&  is set to I<n>.
.Ve
.RE
.RS 4
.Sp
See below for a documentation of the individual
parameters controlling inlining.
.Sp
\&\fINote:\fR pseudo instruction represents, in this particular context, an
abstract measurement of function's size.  In no way, it represents a count
of assembly instructions and as such its exact meaning might change from one
release to an another.
.RE
.Ip "\fB\-fkeep-inline-functions\fR" 4
.IX Item "-fkeep-inline-functions"
Even if all calls to a given function are integrated, and the function
is declared \f(CW\*(C`static\*(C'\fR, nevertheless output a separate run-time
callable version of the function.  This switch does not affect
\&\f(CW\*(C`extern inline\*(C'\fR functions.
.Ip "\fB\-fkeep-static-consts\fR" 4
.IX Item "-fkeep-static-consts"
Emit variables declared \f(CW\*(C`static const\*(C'\fR when optimization isn't turned
on, even if the variables aren't referenced.
.Sp
\&\s-1GCC\s0 enables this option by default.  If you want to force the compiler to
check if the variable was referenced, regardless of whether or not
optimization is turned on, use the \fB\-fno-keep-static-consts\fR option.
.Ip "\fB\-fmerge-constants\fR" 4
.IX Item "-fmerge-constants"
Attempt to merge identical constants (string constants and floating point
constants) across compilation units.
.Sp
This option is the default for optimized compilation if the assembler and
linker support it.  Use \fB\-fno-merge-constants\fR to inhibit this
behavior.
.Sp
Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.Ip "\fB\-fmerge-all-constants\fR" 4
.IX Item "-fmerge-all-constants"
Attempt to merge identical constants and identical variables.
.Sp
This option implies \fB\-fmerge-constants\fR.  In addition to
\&\fB\-fmerge-constants\fR this considers e.g. even constant initialized
arrays or initialized constant variables with integral or floating point
types.  Languages like C or \*(C+ require each non-automatic variable to
have distinct location, so using this option will result in non-conforming
behavior.
.Ip "\fB\-fnew-ra\fR" 4
.IX Item "-fnew-ra"
Use a graph coloring register allocator.  Currently this option is meant
only for testing.  Users should not specify this option, since it is not
yet ready for production use.
.Ip "\fB\-fno-branch-count-reg\fR" 4
.IX Item "-fno-branch-count-reg"
Do not use ``decrement and branch'' instructions on a count register,
but instead generate a sequence of instructions that decrement a
register, compare it against zero, then branch based upon the result.
This option is only meaningful on architectures that support such
instructions, which include x86, PowerPC, \s-1IA-64\s0 and S/390.
.Sp
The default is \fB\-fbranch-count-reg\fR, enabled when
\&\fB\-fstrength-reduce\fR is enabled.
.Ip "\fB\-fno-function-cse\fR" 4
.IX Item "-fno-function-cse"
Do not put function addresses in registers; make each instruction that
calls a constant function contain the function's address explicitly.
.Sp
This option results in less efficient code, but some strange hacks
that alter the assembler output may be confused by the optimizations
performed when this option is not used.
.Sp
The default is \fB\-ffunction-cse\fR
.Ip "\fB\-fno-zero-initialized-in-bss\fR" 4
.IX Item "-fno-zero-initialized-in-bss"
If the target supports a \s-1BSS\s0 section, \s-1GCC\s0 by default puts variables that
are initialized to zero into \s-1BSS\s0.  This can save space in the resulting
code.
.Sp
This option turns off this behavior because some programs explicitly
rely on variables going to the data section.  E.g., so that the
resulting executable can find the beginning of that section and/or make
assumptions based on that.
.Sp
The default is \fB\-fzero-initialized-in-bss\fR.
.Ip "\fB\-fstrength-reduce\fR" 4
.IX Item "-fstrength-reduce"
Perform the optimizations of loop strength reduction and
elimination of iteration variables.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.Ip "\fB\-fthread-jumps\fR" 4
.IX Item "-fthread-jumps"
Perform optimizations where we check to see if a jump branches to a
location where another comparison subsumed by the first is found.  If
so, the first branch is redirected to either the destination of the
second branch or a point immediately following it, depending on whether
the condition is known to be true or false.
.Sp
Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.Ip "\fB\-fcse-follow-jumps\fR" 4
.IX Item "-fcse-follow-jumps"
In common subexpression elimination, scan through jump instructions
when the target of the jump is not reached by any other path.  For
example, when \s-1CSE\s0 encounters an \f(CW\*(C`if\*(C'\fR statement with an
\&\f(CW\*(C`else\*(C'\fR clause, \s-1CSE\s0 will follow the jump when the condition
tested is false.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.Ip "\fB\-fcse-skip-blocks\fR" 4
.IX Item "-fcse-skip-blocks"
This is similar to \fB\-fcse-follow-jumps\fR, but causes \s-1CSE\s0 to
follow jumps which conditionally skip over blocks.  When \s-1CSE\s0
encounters a simple \f(CW\*(C`if\*(C'\fR statement with no else clause,
\&\fB\-fcse-skip-blocks\fR causes \s-1CSE\s0 to follow the jump around the
body of the \f(CW\*(C`if\*(C'\fR.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.Ip "\fB\-frerun-cse-after-loop\fR" 4
.IX Item "-frerun-cse-after-loop"
Re-run common subexpression elimination after loop optimizations has been
performed.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.Ip "\fB\-frerun-loop-opt\fR" 4
.IX Item "-frerun-loop-opt"
Run the loop optimizer twice.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.Ip "\fB\-fgcse\fR" 4
.IX Item "-fgcse"
Perform a global common subexpression elimination pass.
This pass also performs global constant and copy propagation.
.Sp
\&\fINote:\fR When compiling a program using computed gotos, a \s-1GCC\s0
extension, you may get better runtime performance if you disable
the global common subexpression elimination pass by adding
\&\fB\-fno-gcse\fR to the command line.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.Ip "\fB\-fgcse-lm\fR" 4
.IX Item "-fgcse-lm"
When \fB\-fgcse-lm\fR is enabled, global common subexpression elimination will
attempt to move loads which are only killed by stores into themselves.  This
allows a loop containing a load/store sequence to be changed to a load outside
the loop, and a copy/store within the loop.
.Sp
Enabled by default when gcse is enabled.
.Ip "\fB\-fgcse-sm\fR" 4
.IX Item "-fgcse-sm"
When \fB\-fgcse-sm\fR is enabled, a store motion pass is run after
global common subexpression elimination.  This pass will attempt to move
stores out of loops.  When used in conjunction with \fB\-fgcse-lm\fR,
loops containing a load/store sequence can be changed to a load before
the loop and a store after the loop.
.Sp
Enabled by default when gcse is enabled.
.Ip "\fB\-fgcse-las\fR" 4
.IX Item "-fgcse-las"
When \fB\-fgcse-las\fR is enabled, the global common subexpression
elimination pass eliminates redundant loads that come after stores to the
same memory location (both partial and full redundancies).
.Sp
Enabled by default when gcse is enabled.
.Ip "\fB\-floop-optimize\fR" 4
.IX Item "-floop-optimize"
Perform loop optimizations: move constant expressions out of loops, simplify
exit test conditions and optionally do strength-reduction and loop unrolling as
well.
.Sp
Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.Ip "\fB\-fcrossjumping\fR" 4
.IX Item "-fcrossjumping"
Perform cross-jumping transformation. This transformation unifies equivalent code and save code size. The
resulting code may or may not perform better than without cross-jumping.
.Sp
Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.Ip "\fB\-fif-conversion\fR" 4
.IX Item "-fif-conversion"
Attempt to transform conditional jumps into branch-less equivalents.  This
include use of conditional moves, min, max, set flags and abs instructions, and
some tricks doable by standard arithmetics.  The use of conditional execution
on chips where it is available is controlled by \f(CW\*(C`if\-conversion2\*(C'\fR.
.Sp
Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.Ip "\fB\-fif-conversion2\fR" 4
.IX Item "-fif-conversion2"
Use conditional execution (where available) to transform conditional jumps into
branch-less equivalents.
.Sp
Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.Ip "\fB\-fdelete-null-pointer-checks\fR" 4
.IX Item "-fdelete-null-pointer-checks"
Use global dataflow analysis to identify and eliminate useless checks
for null pointers.  The compiler assumes that dereferencing a null
pointer would have halted the program.  If a pointer is checked after
it has already been dereferenced, it cannot be null.
.Sp
In some environments, this assumption is not true, and programs can
safely dereference null pointers.  Use
\&\fB\-fno-delete-null-pointer-checks\fR to disable this optimization
for programs which depend on that behavior.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.Ip "\fB\-fexpensive-optimizations\fR" 4
.IX Item "-fexpensive-optimizations"
Perform a number of minor optimizations that are relatively expensive.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.Ip "\fB\-foptimize-register-move\fR" 4
.IX Item "-foptimize-register-move"
.PD 0
.Ip "\fB\-fregmove\fR" 4
.IX Item "-fregmove"
.PD
Attempt to reassign register numbers in move instructions and as
operands of other simple instructions in order to maximize the amount of
register tying.  This is especially helpful on machines with two-operand
instructions.
.Sp
Note \fB\-fregmove\fR and \fB\-foptimize-register-move\fR are the same
optimization.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.Ip "\fB\-fdelayed-branch\fR" 4
.IX Item "-fdelayed-branch"
If supported for the target machine, attempt to reorder instructions
to exploit instruction slots available after delayed branch
instructions.
.Sp
Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.Ip "\fB\-fschedule-insns\fR" 4
.IX Item "-fschedule-insns"
If supported for the target machine, attempt to reorder instructions to
eliminate execution stalls due to required data being unavailable.  This
helps machines that have slow floating point or memory load instructions
by allowing other instructions to be issued until the result of the load
or floating point instruction is required.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.Ip "\fB\-fschedule-insns2\fR" 4
.IX Item "-fschedule-insns2"
Similar to \fB\-fschedule-insns\fR, but requests an additional pass of
instruction scheduling after register allocation has been done.  This is
especially useful on machines with a relatively small number of
registers and where memory load instructions take more than one cycle.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.Ip "\fB\-fno-sched-interblock\fR" 4
.IX Item "-fno-sched-interblock"
Don't schedule instructions across basic blocks.  This is normally
enabled by default when scheduling before register allocation, i.e.
with \fB\-fschedule-insns\fR or at \fB\-O2\fR or higher.
.Ip "\fB\-fno-sched-spec\fR" 4
.IX Item "-fno-sched-spec"
Don't allow speculative motion of non-load instructions.  This is normally
enabled by default when scheduling before register allocation, i.e.
with \fB\-fschedule-insns\fR or at \fB\-O2\fR or higher.
.Ip "\fB\-fsched-spec-load\fR" 4
.IX Item "-fsched-spec-load"
Allow speculative motion of some load instructions.  This only makes
sense when scheduling before register allocation, i.e. with
\&\fB\-fschedule-insns\fR or at \fB\-O2\fR or higher.
.Ip "\fB\-fsched-spec-load-dangerous\fR" 4
.IX Item "-fsched-spec-load-dangerous"
Allow speculative motion of more load instructions.  This only makes
sense when scheduling before register allocation, i.e. with
\&\fB\-fschedule-insns\fR or at \fB\-O2\fR or higher.
.Ip "\fB\-fsched-stalled-insns=\fR\fIn\fR" 4
.IX Item "-fsched-stalled-insns=n"
Define how many insns (if any) can be moved prematurely from the queue
of stalled insns into the ready list, during the second scheduling pass.
.Ip "\fB\-fsched-stalled-insns-dep=\fR\fIn\fR" 4
.IX Item "-fsched-stalled-insns-dep=n"
Define how many insn groups (cycles) will be examined for a dependency
on a stalled insn that is candidate for premature removal from the queue
of stalled insns.  Has an effect only during the second scheduling pass,
and only if \fB\-fsched-stalled-insns\fR is used and its value is not zero.
.Ip "\fB\-fsched2\-use-superblocks\fR" 4
.IX Item "-fsched2-use-superblocks"
When scheduling after register allocation, do use superblock scheduling
algorithm.  Superblock scheduling allows motion across basic block boundaries
resulting on faster schedules.  This option is experimental, as not all machine
descriptions used by \s-1GCC\s0 model the \s-1CPU\s0 closely enough to avoid unreliable
results from the algorithm.
.Sp
This only makes sense when scheduling after register allocation, i.e. with
\&\fB\-fschedule-insns2\fR or at \fB\-O2\fR or higher.
.Ip "\fB\-fsched2\-use-traces\fR" 4
.IX Item "-fsched2-use-traces"
Use \fB\-fsched2\-use-superblocks\fR algorithm when scheduling after register
allocation and additionally perform code duplication in order to increase the
size of superblocks using tracer pass.  See \fB\-ftracer\fR for details on
trace formation.
.Sp
This mode should produce faster but significantly longer programs.  Also
without \f(CW\*(C`\-fbranch\-probabilities\*(C'\fR the traces constructed may not match the
reality and hurt the performance.  This only makes
sense when scheduling after register allocation, i.e. with
\&\fB\-fschedule-insns2\fR or at \fB\-O2\fR or higher.
.Ip "\fB\-fcaller-saves\fR" 4
.IX Item "-fcaller-saves"
Enable values to be allocated in registers that will be clobbered by
function calls, by emitting extra instructions to save and restore the
registers around such calls.  Such allocation is done only when it
seems to result in better code than would otherwise be produced.
.Sp
This option is always enabled by default on certain machines, usually
those which have no call-preserved registers to use instead.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.Ip "\fB\-fmove-all-movables\fR" 4
.IX Item "-fmove-all-movables"
Forces all invariant computations in loops to be moved
outside the loop.
.Ip "\fB\-freduce-all-givs\fR" 4
.IX Item "-freduce-all-givs"
Forces all general-induction variables in loops to be
strength-reduced.
.Sp
\&\fINote:\fR When compiling programs written in Fortran,
\&\fB\-fmove-all-movables\fR and \fB\-freduce-all-givs\fR are enabled
by default when you use the optimizer.
.Sp
These options may generate better or worse code; results are highly
dependent on the structure of loops within the source code.
.Sp
These two options are intended to be removed someday, once
they have helped determine the efficacy of various
approaches to improving loop optimizations.
.Sp
Please contact <\fBgcc@gcc.gnu.org\fR>, and describe how use of
these options affects the performance of your production code.
Examples of code that runs \fIslower\fR when these options are
\&\fIenabled\fR are very valuable.
.Ip "\fB\-fno-peephole\fR" 4
.IX Item "-fno-peephole"
.PD 0
.Ip "\fB\-fno-peephole2\fR" 4
.IX Item "-fno-peephole2"
.PD
Disable any machine-specific peephole optimizations.  The difference
between \fB\-fno-peephole\fR and \fB\-fno-peephole2\fR is in how they
are implemented in the compiler; some targets use one, some use the
other, a few use both.
.Sp
\&\fB\-fpeephole\fR is enabled by default.
\&\fB\-fpeephole2\fR enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.Ip "\fB\-fno-guess-branch-probability\fR" 4
.IX Item "-fno-guess-branch-probability"
Do not guess branch probabilities using a randomized model.
.Sp
Sometimes \s-1GCC\s0 will opt to use a randomized model to guess branch
probabilities, when none are available from either profiling feedback
(\fB\-fprofile-arcs\fR) or \fB_\|_builtin_expect\fR.  This means that
different runs of the compiler on the same program may produce different
object code.
.Sp
In a hard real-time system, people don't want different runs of the
compiler to produce code that has different behavior; minimizing
non-determinism is of paramount import.  This switch allows users to
reduce non-determinism, possibly at the expense of inferior
optimization.
.Sp
The default is \fB\-fguess-branch-probability\fR at levels
\&\fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.Ip "\fB\-freorder-blocks\fR" 4
.IX Item "-freorder-blocks"
Reorder basic blocks in the compiled function in order to reduce number of
taken branches and improve code locality.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR.
.Ip "\fB\-freorder-functions\fR" 4
.IX Item "-freorder-functions"
Reorder basic blocks in the compiled function in order to reduce number of
taken branches and improve code locality. This is implemented by using special
subsections \f(CW\*(C`text.hot\*(C'\fR for most frequently executed functions and
\&\f(CW\*(C`text.unlikely\*(C'\fR for unlikely executed functions.  Reordering is done by
the linker so object file format must support named sections and linker must
place them in a reasonable way.
.Sp
Also profile feedback must be available in to make this option effective.  See
\&\fB\-fprofile-arcs\fR for details.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.Ip "\fB\-fstrict-aliasing\fR" 4
.IX Item "-fstrict-aliasing"
Allows the compiler to assume the strictest aliasing rules applicable to
the language being compiled.  For C (and \*(C+), this activates
optimizations based on the type of expressions.  In particular, an
object of one type is assumed never to reside at the same address as an
object of a different type, unless the types are almost the same.  For
example, an \f(CW\*(C`unsigned int\*(C'\fR can alias an \f(CW\*(C`int\*(C'\fR, but not a
\&\f(CW\*(C`void*\*(C'\fR or a \f(CW\*(C`double\*(C'\fR.  A character type may alias any other
type.
.Sp
Pay special attention to code like this:
.Sp
.Vb 4
\&        union a_union {
\&          int i;
\&          double d;
\&        };
.Ve
.Vb 5
\&        int f() {
\&          a_union t;
\&          t.d = 3.0;
\&          return t.i;
\&        }
.Ve
The practice of reading from a different union member than the one most
recently written to (called ``type-punning'') is common.  Even with
\&\fB\-fstrict-aliasing\fR, type-punning is allowed, provided the memory
is accessed through the union type.  So, the code above will work as
expected.  However, this code might not:
.Sp
.Vb 7
\&        int f() {
\&          a_union t;
\&          int* ip;
\&          t.d = 3.0;
\&          ip = &t.i;
\&          return *ip;
\&        }
.Ve
Every language that wishes to perform language-specific alias analysis
should define a function that computes, given an \f(CW\*(C`tree\*(C'\fR
node, an alias set for the node.  Nodes in different alias sets are not
allowed to alias.  For an example, see the C front-end function
\&\f(CW\*(C`c_get_alias_set\*(C'\fR.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.Ip "\fB\-falign-functions\fR" 4
.IX Item "-falign-functions"
.PD 0
.Ip "\fB\-falign-functions=\fR\fIn\fR" 4
.IX Item "-falign-functions=n"
.PD
Align the start of functions to the next power-of-two greater than
\&\fIn\fR, skipping up to \fIn\fR bytes.  For instance,
\&\fB\-falign-functions=32\fR aligns functions to the next 32\-byte
boundary, but \fB\-falign-functions=24\fR would align to the next
32\-byte boundary only if this can be done by skipping 23 bytes or less.
.Sp
\&\fB\-fno-align-functions\fR and \fB\-falign-functions=1\fR are
equivalent and mean that functions will not be aligned.
.Sp
Some assemblers only support this flag when \fIn\fR is a power of two;
in that case, it is rounded up.
.Sp
If \fIn\fR is not specified or is zero, use a machine-dependent default.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR.
.Ip "\fB\-falign-labels\fR" 4
.IX Item "-falign-labels"
.PD 0
.Ip "\fB\-falign-labels=\fR\fIn\fR" 4
.IX Item "-falign-labels=n"
.PD
Align all branch targets to a power-of-two boundary, skipping up to
\&\fIn\fR bytes like \fB\-falign-functions\fR.  This option can easily
make code slower, because it must insert dummy operations for when the
branch target is reached in the usual flow of the code.
.Sp
\&\fB\-fno-align-labels\fR and \fB\-falign-labels=1\fR are
equivalent and mean that labels will not be aligned.
.Sp
If \fB\-falign-loops\fR or \fB\-falign-jumps\fR are applicable and
are greater than this value, then their values are used instead.
.Sp
If \fIn\fR is not specified or is zero, use a machine-dependent default
which is very likely to be \fB1\fR, meaning no alignment.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR.
.Ip "\fB\-falign-loops\fR" 4
.IX Item "-falign-loops"
.PD 0
.Ip "\fB\-falign-loops=\fR\fIn\fR" 4
.IX Item "-falign-loops=n"
.PD
Align loops to a power-of-two boundary, skipping up to \fIn\fR bytes
like \fB\-falign-functions\fR.  The hope is that the loop will be
executed many times, which will make up for any execution of the dummy
operations.
.Sp
\&\fB\-fno-align-loops\fR and \fB\-falign-loops=1\fR are
equivalent and mean that loops will not be aligned.
.Sp
If \fIn\fR is not specified or is zero, use a machine-dependent default.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR.
.Ip "\fB\-falign-jumps\fR" 4
.IX Item "-falign-jumps"
.PD 0
.Ip "\fB\-falign-jumps=\fR\fIn\fR" 4
.IX Item "-falign-jumps=n"
.PD
Align branch targets to a power-of-two boundary, for branch targets
where the targets can only be reached by jumping, skipping up to \fIn\fR
bytes like \fB\-falign-functions\fR.  In this case, no dummy operations
need be executed.
.Sp
\&\fB\-fno-align-jumps\fR and \fB\-falign-jumps=1\fR are
equivalent and mean that loops will not be aligned.
.Sp
If \fIn\fR is not specified or is zero, use a machine-dependent default.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR.
.Ip "\fB\-frename-registers\fR" 4
.IX Item "-frename-registers"
Attempt to avoid false dependencies in scheduled code by making use
of registers left over after register allocation.  This optimization
will most benefit processors with lots of registers.  It can, however,
make debugging impossible, since variables will no longer stay in
a ``home register''.
.Ip "\fB\-fweb\fR" 4
.IX Item "-fweb"
Constructs webs as commonly used for register allocation purposes and assign
each web individual pseudo register.  This allows the register allocation pass
to operate on pseudos directly, but also strengthens several other optimization
passes, such as \s-1CSE\s0, loop optimizer and trivial dead code remover.  It can,
however, make debugging impossible, since variables will no longer stay in a
``home register''.
.Sp
Enabled at levels \fB\-O3\fR.
.Ip "\fB\-fno-cprop-registers\fR" 4
.IX Item "-fno-cprop-registers"
After register allocation and post-register allocation instruction splitting,
we perform a copy-propagation pass to try to reduce scheduling dependencies
and occasionally eliminate the copy.
.Sp
Disabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.Ip "\fB\-fprofile-generate\fR" 4
.IX Item "-fprofile-generate"
Enable options usually used for instrumenting application to produce
profile useful for later recompilation with profile feedback based
optimization.  You must use \f(CW\*(C`\-fprofile\-generate\*(C'\fR both when
compiling and when linking your program.
.Sp
The following options are enabled: \f(CW\*(C`\-fprofile\-arcs\*(C'\fR, \f(CW\*(C`\-fprofile\-values\*(C'\fR, \f(CW\*(C`\-fvpt\*(C'\fR.
.Ip "\fB\-fprofile-use\fR" 4
.IX Item "-fprofile-use"
Enable profile feedback directed optimizations, and optimizations
generally profitable only with profile feedback available.
.Sp
The following options are enabled: \f(CW\*(C`\-fbranch\-probabilities\*(C'\fR,
\&\f(CW\*(C`\-fvpt\*(C'\fR, \f(CW\*(C`\-funroll\-loops\*(C'\fR, \f(CW\*(C`\-fpeel\-loops\*(C'\fR, \f(CW\*(C`\-ftracer\*(C'\fR.
.PP
The following options control compiler behavior regarding floating
point arithmetic.  These options trade off between speed and
correctness.  All must be specifically enabled.
.Ip "\fB\-ffloat-store\fR" 4
.IX Item "-ffloat-store"
Do not store floating point variables in registers, and inhibit other
options that might change whether a floating point value is taken from a
register or memory.
.Sp
This option prevents undesirable excess precision on machines such as
the 68000 where the floating registers (of the 68881) keep more
precision than a \f(CW\*(C`double\*(C'\fR is supposed to have.  Similarly for the
x86 architecture.  For most programs, the excess precision does only
good, but a few programs rely on the precise definition of \s-1IEEE\s0 floating
point.  Use \fB\-ffloat-store\fR for such programs, after modifying
them to store all pertinent intermediate computations into variables.
.Ip "\fB\-ffast-math\fR" 4
.IX Item "-ffast-math"
Sets \fB\-fno-math-errno\fR, \fB\-funsafe-math-optimizations\fR, \fB\-fno-trapping-math\fR, \fB\-ffinite-math-only\fR,
\&\fB\-fno-rounding-math\fR and \fB\-fno-signaling-nans\fR.
.Sp
This option causes the preprocessor macro \f(CW\*(C`_\|_FAST_MATH_\|_\*(C'\fR to be defined.
.Sp
This option should never be turned on by any \fB\-O\fR option since
it can result in incorrect output for programs which depend on
an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications for
math functions.
.Ip "\fB\-fno-math-errno\fR" 4
.IX Item "-fno-math-errno"
Do not set \s-1ERRNO\s0 after calling math functions that are executed
with a single instruction, e.g., sqrt.  A program that relies on
\&\s-1IEEE\s0 exceptions for math error handling may want to use this flag
for speed while maintaining \s-1IEEE\s0 arithmetic compatibility.
.Sp
This option should never be turned on by any \fB\-O\fR option since
it can result in incorrect output for programs which depend on
an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications for
math functions.
.Sp
The default is \fB\-fmath-errno\fR.
.Ip "\fB\-funsafe-math-optimizations\fR" 4
.IX Item "-funsafe-math-optimizations"
Allow optimizations for floating-point arithmetic that (a) assume
that arguments and results are valid and (b) may violate \s-1IEEE\s0 or
\&\s-1ANSI\s0 standards.  When used at link-time, it may include libraries
or startup files that change the default \s-1FPU\s0 control word or other
similar optimizations.
.Sp
This option should never be turned on by any \fB\-O\fR option since
it can result in incorrect output for programs which depend on
an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications for
math functions.
.Sp
The default is \fB\-fno-unsafe-math-optimizations\fR.
.Ip "\fB\-ffinite-math-only\fR" 4
.IX Item "-ffinite-math-only"
Allow optimizations for floating-point arithmetic that assume
that arguments and results are not NaNs or +\-Infs.
.Sp
This option should never be turned on by any \fB\-O\fR option since
it can result in incorrect output for programs which depend on
an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications.
.Sp
The default is \fB\-fno-finite-math-only\fR.
.Ip "\fB\-fno-trapping-math\fR" 4
.IX Item "-fno-trapping-math"
Compile code assuming that floating-point operations cannot generate
user-visible traps.  These traps include division by zero, overflow,
underflow, inexact result and invalid operation.  This option implies
\&\fB\-fno-signaling-nans\fR.  Setting this option may allow faster
code if one relies on ``non-stop'' \s-1IEEE\s0 arithmetic, for example.
.Sp
This option should never be turned on by any \fB\-O\fR option since
it can result in incorrect output for programs which depend on
an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications for
math functions.
.Sp
The default is \fB\-ftrapping-math\fR.
.Ip "\fB\-frounding-math\fR" 4
.IX Item "-frounding-math"
Disable transformations and optimizations that assume default floating
point rounding behavior.  This is round-to-zero for all floating point
to integer conversions, and round-to-nearest for all other arithmetic
truncations.  This option should be specified for programs that change
the \s-1FP\s0 rounding mode dynamically, or that may be executed with a
non-default rounding mode.  This option disables constant folding of
floating point expressions at compile-time (which may be affected by
rounding mode) and arithmetic transformations that are unsafe in the
presence of sign-dependent rounding modes.
.Sp
The default is \fB\-fno-rounding-math\fR.
.Sp
This option is experimental and does not currently guarantee to
disable all \s-1GCC\s0 optimizations that are affected by rounding mode.
Future versions of \s-1GCC\s0 may provide finer control of this setting
using C99's \f(CW\*(C`FENV_ACCESS\*(C'\fR pragma.  This command line option
will be used to specify the default state for \f(CW\*(C`FENV_ACCESS\*(C'\fR.
.Ip "\fB\-fsignaling-nans\fR" 4
.IX Item "-fsignaling-nans"
Compile code assuming that \s-1IEEE\s0 signaling NaNs may generate user-visible
traps during floating-point operations.  Setting this option disables
optimizations that may change the number of exceptions visible with
signaling NaNs.  This option implies \fB\-ftrapping-math\fR.
.Sp
This option causes the preprocessor macro \f(CW\*(C`_\|_SUPPORT_SNAN_\|_\*(C'\fR to
be defined.
.Sp
The default is \fB\-fno-signaling-nans\fR.
.Sp
This option is experimental and does not currently guarantee to
disable all \s-1GCC\s0 optimizations that affect signaling NaN behavior.
.Ip "\fB\-fsingle-precision-constant\fR" 4
.IX Item "-fsingle-precision-constant"
Treat floating point constant as single precision constant instead of
implicitly converting it to double precision constant.
.PP
The following options control optimizations that may improve
performance, but are not enabled by any \fB\-O\fR options.  This
section includes experimental options that may produce broken code.
.Ip "\fB\-fbranch-probabilities\fR" 4
.IX Item "-fbranch-probabilities"
After running a program compiled with \fB\-fprofile-arcs\fR, you can compile it a second time using
\&\fB\-fbranch-probabilities\fR, to improve optimizations based on
the number of times each branch was taken.  When the program
compiled with \fB\-fprofile-arcs\fR exits it saves arc execution
counts to a file called \fI\fIsourcename\fI.gcda\fR for each source
file  The information in this data file is very dependent on the
structure of the generated code, so you must use the same source code
and the same optimization options for both compilations.
.Sp
With \fB\-fbranch-probabilities\fR, \s-1GCC\s0 puts a
\&\fB\s-1REG_BR_PROB\s0\fR note on each \fB\s-1JUMP_INSN\s0\fR and \fB\s-1CALL_INSN\s0\fR.
These can be used to improve optimization.  Currently, they are only
used in one place: in \fIreorg.c\fR, instead of guessing which path a
branch is mostly to take, the \fB\s-1REG_BR_PROB\s0\fR values are used to
exactly determine which path is taken more often.
.Ip "\fB\-fprofile-values\fR" 4
.IX Item "-fprofile-values"
If combined with \fB\-fprofile-arcs\fR, it adds code so that some
data about values of expressions in the program is gathered.
.Sp
With \fB\-fbranch-probabilities\fR, it reads back the data gathered
from profiling values of expressions and adds \fB\s-1REG_VALUE_PROFILE\s0\fR
notes to instructions for their later usage in optimizations.
.Ip "\fB\-fvpt\fR" 4
.IX Item "-fvpt"
If combined with \fB\-fprofile-arcs\fR, it instructs the compiler to add
a code to gather information about values of expressions.
.Sp
With \fB\-fbranch-probabilities\fR, it reads back the data gathered
and actually performs the optimizations based on them.
Currently the optimizations include specialization of division operation
using the knowledge about the value of the denominator.
.Ip "\fB\-fnew-ra\fR" 4
.IX Item "-fnew-ra"
Use a graph coloring register allocator.  Currently this option is meant
for testing, so we are interested to hear about miscompilations with
\&\fB\-fnew-ra\fR.
.Ip "\fB\-ftracer\fR" 4
.IX Item "-ftracer"
Perform tail duplication to enlarge superblock size. This transformation
simplifies the control flow of the function allowing other optimizations to do
better job.
.Ip "\fB\-funit-at-a-time\fR" 4
.IX Item "-funit-at-a-time"
Parse the whole compilation unit before starting to produce code.
This allows some extra optimizations to take place but consumes more
memory.
.Ip "\fB\-funroll-loops\fR" 4
.IX Item "-funroll-loops"
Unroll loops whose number of iterations can be determined at compile time or
upon entry to the loop.  \fB\-funroll-loops\fR implies
\&\fB\-frerun-cse-after-loop\fR.  It also turns on complete loop peeling
(i.e. complete removal of loops with small constant number of iterations).
This option makes code larger, and may or may not make it run faster.
.Ip "\fB\-funroll-all-loops\fR" 4
.IX Item "-funroll-all-loops"
Unroll all loops, even if their number of iterations is uncertain when
the loop is entered.  This usually makes programs run more slowly.
\&\fB\-funroll-all-loops\fR implies the same options as
\&\fB\-funroll-loops\fR.
.Ip "\fB\-fpeel-loops\fR" 4
.IX Item "-fpeel-loops"
Peels the loops for that there is enough information that they do not
roll much (from profile feedback).  It also turns on complete loop peeling
(i.e. complete removal of loops with small constant number of iterations).
.Ip "\fB\-funswitch-loops\fR" 4
.IX Item "-funswitch-loops"
Move branches with loop invariant conditions out of the loop, with duplicates
of the loop on both branches (modified according to result of the condition).
.Ip "\fB\-fold-unroll-loops\fR" 4
.IX Item "-fold-unroll-loops"
Unroll loops whose number of iterations can be determined at compile
time or upon entry to the loop, using the old loop unroller whose loop
recognition is based on notes from frontend.  \fB\-fold-unroll-loops\fR implies
both \fB\-fstrength-reduce\fR and \fB\-frerun-cse-after-loop\fR.  This
option makes code larger, and may or may not make it run faster.
.Ip "\fB\-fold-unroll-all-loops\fR" 4
.IX Item "-fold-unroll-all-loops"
Unroll all loops, even if their number of iterations is uncertain when
the loop is entered. This is done using the old loop unroller whose loop
recognition is based on notes from frontend.  This usually makes programs run more slowly.
\&\fB\-fold-unroll-all-loops\fR implies the same options as
\&\fB\-fold-unroll-loops\fR.
.Ip "\fB\-funswitch-loops\fR" 4
.IX Item "-funswitch-loops"
Move branches with loop invariant conditions out of the loop, with duplicates
of the loop on both branches (modified according to result of the condition).
.Ip "\fB\-funswitch-loops\fR" 4
.IX Item "-funswitch-loops"
Move branches with loop invariant conditions out of the loop, with duplicates
of the loop on both branches (modified according to result of the condition).
.Ip "\fB\-fprefetch-loop-arrays\fR" 4
.IX Item "-fprefetch-loop-arrays"
If supported by the target machine, generate instructions to prefetch
memory to improve the performance of loops that access large arrays.
.Sp
Disabled at level \fB\-Os\fR.
.Ip "\fB\-ffunction-sections\fR" 4
.IX Item "-ffunction-sections"
.PD 0
.Ip "\fB\-fdata-sections\fR" 4
.IX Item "-fdata-sections"
.PD
Place each function or data item into its own section in the output
file if the target supports arbitrary sections.  The name of the
function or the name of the data item determines the section's name
in the output file.
.Sp
Use these options on systems where the linker can perform optimizations
to improve locality of reference in the instruction space.  Most systems
using the \s-1ELF\s0 object format and \s-1SPARC\s0 processors running Solaris 2 have
linkers with such optimizations.  \s-1AIX\s0 may have these optimizations in
the future.
.Sp
Only use these options when there are significant benefits from doing
so.  When you specify these options, the assembler and linker will
create larger object and executable files and will also be slower.
You will not be able to use \f(CW\*(C`gprof\*(C'\fR on all systems if you
specify this option and you may have problems with debugging if
you specify both this option and \fB\-g\fR.
.Ip "\fB\-fbranch-target-load-optimize\fR" 4
.IX Item "-fbranch-target-load-optimize"
Perform branch target register load optimization before prologue / epilogue
threading.
The use of target registers can typically be exposed only during reload,
thus hoisting loads out of loops and doing inter-block scheduling needs
a separate optimization pass.
.Ip "\fB\-fbranch-target-load-optimize2\fR" 4
.IX Item "-fbranch-target-load-optimize2"
Perform branch target register load optimization after prologue / epilogue
threading.
.Ip "\fB\*(--param\fR \fIname\fR\fB=\fR\fIvalue\fR" 4
.IX Item "param name=value"
In some places, \s-1GCC\s0 uses various constants to control the amount of
optimization that is done.  For example, \s-1GCC\s0 will not inline functions
that contain more that a certain number of instructions.  You can
control some of these constants on the command-line using the
\&\fB\*(--param\fR option.
.Sp
The names of specific parameters, and the meaning of the values, are
tied to the internals of the compiler, and are subject to change
without notice in future releases.
.Sp
In each case, the \fIvalue\fR is an integer.  The allowable choices for
\&\fIname\fR are given in the following table:
.RS 4
.Ip "\fBmax-crossjump-edges\fR" 4
.IX Item "max-crossjump-edges"
The maximum number of incoming edges to consider for crossjumping.
The algorithm used by \fB\-fcrossjumping\fR is O(N^2) in
the number of edges incoming to each block.  Increasing values mean
more aggressive optimization, making the compile time increase with
probably small improvement in executable size.
.Ip "\fBmax-delay-slot-insn-search\fR" 4
.IX Item "max-delay-slot-insn-search"
The maximum number of instructions to consider when looking for an
instruction to fill a delay slot.  If more than this arbitrary number of
instructions is searched, the time savings from filling the delay slot
will be minimal so stop searching.  Increasing values mean more
aggressive optimization, making the compile time increase with probably
small improvement in executable run time.
.Ip "\fBmax-delay-slot-live-search\fR" 4
.IX Item "max-delay-slot-live-search"
When trying to fill delay slots, the maximum number of instructions to
consider when searching for a block with valid live register
information.  Increasing this arbitrarily chosen value means more
aggressive optimization, increasing the compile time.  This parameter
should be removed when the delay slot code is rewritten to maintain the
control-flow graph.
.Ip "\fBmax-gcse-memory\fR" 4
.IX Item "max-gcse-memory"
The approximate maximum amount of memory that will be allocated in
order to perform the global common subexpression elimination
optimization.  If more memory than specified is required, the
optimization will not be done.
.Ip "\fBmax-gcse-passes\fR" 4
.IX Item "max-gcse-passes"
The maximum number of passes of \s-1GCSE\s0 to run.
.Ip "\fBmax-pending-list-length\fR" 4
.IX Item "max-pending-list-length"
The maximum number of pending dependencies scheduling will allow
before flushing the current state and starting over.  Large functions
with few branches or calls can create excessively large lists which
needlessly consume memory and resources.
.Ip "\fBmax-inline-insns-single\fR" 4
.IX Item "max-inline-insns-single"
Several parameters control the tree inliner used in gcc.
This number sets the maximum number of instructions (counted in \s-1GCC\s0's
internal representation) in a single function that the tree inliner
will consider for inlining.  This only affects functions declared
inline and methods implemented in a class declaration (\*(C+).
The default value is 500.
.Ip "\fBmax-inline-insns-auto\fR" 4
.IX Item "max-inline-insns-auto"
When you use \fB\-finline-functions\fR (included in \fB\-O3\fR),
a lot of functions that would otherwise not be considered for inlining
by the compiler will be investigated.  To those functions, a different
(more restrictive) limit compared to functions declared inline can
be applied.
The default value is 100.
.Ip "\fBlarge-function-insns\fR" 4
.IX Item "large-function-insns"
The limit specifying really large functions.  For functions greater than this
limit inlining is constrained by \fB\*(--param large-function-growth\fR.
This parameter is useful primarily to avoid extreme compilation time caused by non-linear
algorithms used by the backend.
This parameter is ignored when \fB\-funit-at-a-time\fR is not used.
The default value is 3000.
.Ip "\fBlarge-function-growth\fR" 4
.IX Item "large-function-growth"
Specifies maximal growth of large function caused by inlining in percents.
This parameter is ignored when \fB\-funit-at-a-time\fR is not used.
The default value is 200.
.Ip "\fBinline-unit-growth\fR" 4
.IX Item "inline-unit-growth"
Specifies maximal overall growth of the compilation unit caused by inlining.
This parameter is ignored when \fB\-funit-at-a-time\fR is not used.
The default value is 150.
.Ip "\fBmax-inline-insns-rtl\fR" 4
.IX Item "max-inline-insns-rtl"
For languages that use the \s-1RTL\s0 inliner (this happens at a later stage
than tree inlining), you can set the maximum allowable size (counted
in \s-1RTL\s0 instructions) for the \s-1RTL\s0 inliner with this parameter.
The default value is 600.
.Ip "\fBmax-unrolled-insns\fR" 4
.IX Item "max-unrolled-insns"
The maximum number of instructions that a loop should have if that loop
is unrolled, and if the loop is unrolled, it determines how many times
the loop code is unrolled.
.Ip "\fBmax-average-unrolled-insns\fR" 4
.IX Item "max-average-unrolled-insns"
The maximum number of instructions biased by probabilities of their execution
that a loop should have if that loop is unrolled, and if the loop is unrolled,
it determines how many times the loop code is unrolled.
.Ip "\fBmax-unroll-times\fR" 4
.IX Item "max-unroll-times"
The maximum number of unrollings of a single loop.
.Ip "\fBmax-peeled-insns\fR" 4
.IX Item "max-peeled-insns"
The maximum number of instructions that a loop should have if that loop
is peeled, and if the loop is peeled, it determines how many times
the loop code is peeled.
.Ip "\fBmax-peel-times\fR" 4
.IX Item "max-peel-times"
The maximum number of peelings of a single loop.
.Ip "\fBmax-completely-peeled-insns\fR" 4
.IX Item "max-completely-peeled-insns"
The maximum number of insns of a completely peeled loop.
.Ip "\fBmax-completely-peel-times\fR" 4
.IX Item "max-completely-peel-times"
The maximum number of iterations of a loop to be suitable for complete peeling.
.Ip "\fBmax-unswitch-insns\fR" 4
.IX Item "max-unswitch-insns"
The maximum number of insns of an unswitched loop.
.Ip "\fBmax-unswitch-level\fR" 4
.IX Item "max-unswitch-level"
The maximum number of branches unswitched in a single loop.
.Ip "\fBhot-bb-count-fraction\fR" 4
.IX Item "hot-bb-count-fraction"
Select fraction of the maximal count of repetitions of basic block in program
given basic block needs to have to be considered hot.
.Ip "\fBhot-bb-frequency-fraction\fR" 4
.IX Item "hot-bb-frequency-fraction"
Select fraction of the maximal frequency of executions of basic block in
function given basic block needs to have to be considered hot
.Ip "\fBtracer-dynamic-coverage\fR" 4
.IX Item "tracer-dynamic-coverage"
.PD 0
.Ip "\fBtracer-dynamic-coverage-feedback\fR" 4
.IX Item "tracer-dynamic-coverage-feedback"
.PD
This value is used to limit superblock formation once the given percentage of
executed instructions is covered.  This limits unnecessary code size
expansion.
.Sp
The \fBtracer-dynamic-coverage-feedback\fR is used only when profile
feedback is available.  The real profiles (as opposed to statically estimated
ones) are much less balanced allowing the threshold to be larger value.
.Ip "\fBtracer-max-code-growth\fR" 4
.IX Item "tracer-max-code-growth"
Stop tail duplication once code growth has reached given percentage.  This is
rather hokey argument, as most of the duplicates will be eliminated later in
cross jumping, so it may be set to much higher values than is the desired code
growth.
.Ip "\fBtracer-min-branch-ratio\fR" 4
.IX Item "tracer-min-branch-ratio"
Stop reverse growth when the reverse probability of best edge is less than this
threshold (in percent).
.Ip "\fBtracer-min-branch-ratio\fR" 4
.IX Item "tracer-min-branch-ratio"
.PD 0
.Ip "\fBtracer-min-branch-ratio-feedback\fR" 4
.IX Item "tracer-min-branch-ratio-feedback"
.PD
Stop forward growth if the best edge do have probability lower than this
threshold.
.Sp
Similarly to \fBtracer-dynamic-coverage\fR two values are present, one for
compilation for profile feedback and one for compilation without.  The value
for compilation with profile feedback needs to be more conservative (higher) in
order to make tracer effective.
.Ip "\fBmax-cse-path-length\fR" 4
.IX Item "max-cse-path-length"
Maximum number of basic blocks on path that cse considers.
.Ip "\fBggc-min-expand\fR" 4
.IX Item "ggc-min-expand"
\&\s-1GCC\s0 uses a garbage collector to manage its own memory allocation.  This
parameter specifies the minimum percentage by which the garbage
collector's heap should be allowed to expand between collections.
Tuning this may improve compilation speed; it has no effect on code
generation.
.Sp
The default is 30% + 70% * (\s-1RAM/1GB\s0) with an upper bound of 100% when
\&\s-1RAM\s0 >= 1GB.  If \f(CW\*(C`getrlimit\*(C'\fR is available, the notion of \*(L"\s-1RAM\s0\*(R" is
the smallest of actual \s-1RAM\s0, \s-1RLIMIT_RSS\s0, \s-1RLIMIT_DATA\s0 and \s-1RLIMIT_AS\s0.  If
\&\s-1GCC\s0 is not able to calculate \s-1RAM\s0 on a particular platform, the lower
bound of 30% is used.  Setting this parameter and
\&\fBggc-min-heapsize\fR to zero causes a full collection to occur at
every opportunity.  This is extremely slow, but can be useful for
debugging.
.Ip "\fBggc-min-heapsize\fR" 4
.IX Item "ggc-min-heapsize"
Minimum size of the garbage collector's heap before it begins bothering
to collect garbage.  The first collection occurs after the heap expands
by \fBggc-min-expand\fR% beyond \fBggc-min-heapsize\fR.  Again,
tuning this may improve compilation speed, and has no effect on code
generation.
.Sp
The default is \s-1RAM/8\s0, with a lower bound of 4096 (four megabytes) and an
upper bound of 131072 (128 megabytes).  If \f(CW\*(C`getrlimit\*(C'\fR is
available, the notion of \*(L"\s-1RAM\s0\*(R" is the smallest of actual \s-1RAM\s0,
\&\s-1RLIMIT_RSS\s0, \s-1RLIMIT_DATA\s0 and \s-1RLIMIT_AS\s0.  If \s-1GCC\s0 is not able to calculate
\&\s-1RAM\s0 on a particular platform, the lower bound is used.  Setting this
parameter very large effectively disables garbage collection.  Setting
this parameter and \fBggc-min-expand\fR to zero causes a full
collection to occur at every opportunity.
.Ip "\fBmax-reload-search-insns\fR" 4
.IX Item "max-reload-search-insns"
The maximum number of instruction reload should look backward for equivalent
register.  Increasing values mean more aggressive optimization, making the
compile time increase with probably slightly better performance.  The default
value is 100.
.Ip "\fBmax-cselib-memory-location\fR" 4
.IX Item "max-cselib-memory-location"
The maximum number of memory locations cselib should take into acount.
Increasing values mean more aggressive optimization, making the compile time
increase with probably slightly better performance.  The default value is 500.
.Ip "\fBreorder-blocks-duplicate\fR" 4
.IX Item "reorder-blocks-duplicate"
.PD 0
.Ip "\fBreorder-blocks-duplicate-feedback\fR" 4
.IX Item "reorder-blocks-duplicate-feedback"
.PD
Used by basic block reordering pass to decide whether to use unconditional
branch or duplicate the code on its destination.  Code is duplicated when its
estimated size is smaller than this value multiplied by the estimated size of
unconditional jump in the hot spots of the program.
.Sp
The \fBreorder-block-duplicate-feedback\fR is used only when profile
feedback is available and may be set to higher values than
\&\fBreorder-block-duplicate\fR since information about the hot spots is more
accurate.
.RE
.RS 4
.RE
.Sh "Options Controlling the Preprocessor"
.IX Subsection "Options Controlling the Preprocessor"
These options control the C preprocessor, which is run on each C source
file before actual compilation.
.PP
If you use the \fB\-E\fR option, nothing is done except preprocessing.
Some of these options make sense only together with \fB\-E\fR because
they cause the preprocessor output to be unsuitable for actual
compilation.
.Sp
You can use \fB\-Wp,\fR\fIoption\fR to bypass the compiler driver
and pass \fIoption\fR directly through to the preprocessor.  If
\&\fIoption\fR contains commas, it is split into multiple options at the
commas.  However, many options are modified, translated or interpreted
by the compiler driver before being passed to the preprocessor, and
\&\fB\-Wp\fR forcibly bypasses this phase.  The preprocessor's direct
interface is undocumented and subject to change, so whenever possible
you should avoid using \fB\-Wp\fR and let the driver handle the
options instead.
.Ip "\fB\-Xpreprocessor\fR \fIoption\fR" 4
.IX Item "-Xpreprocessor option"
Pass \fIoption\fR as an option to the preprocessor.  You can use this to
supply system-specific preprocessor options which \s-1GCC\s0 does not know how to
recognize.
.Sp
If you want to pass an option that takes an argument, you must use
\&\fB\-Xpreprocessor\fR twice, once for the option and once for the argument.
.Ip "\fB\-D\fR \fIname\fR" 4
.IX Item "-D name"
Predefine \fIname\fR as a macro, with definition \f(CW\*(C`1\*(C'\fR.
.Ip "\fB\-D\fR \fIname\fR\fB=\fR\fIdefinition\fR" 4
.IX Item "-D name=definition"
Predefine \fIname\fR as a macro, with definition \fIdefinition\fR.
The contents of \fIdefinition\fR are tokenized and processed as if
they appeared during translation phase three in a \fB#define\fR
directive.  In particular, the definition will be truncated by
embedded newline characters.
.Sp
If you are invoking the preprocessor from a shell or shell-like
program you may need to use the shell's quoting syntax to protect
characters such as spaces that have a meaning in the shell syntax.
.Sp
If you wish to define a function-like macro on the command line, write
its argument list with surrounding parentheses before the equals sign
(if any).  Parentheses are meaningful to most shells, so you will need
to quote the option.  With \fBsh\fR and \fBcsh\fR,
\&\fB\-D'\fR\fIname\fR\fB(\fR\fIargs...\fR\fB)=\fR\fIdefinition\fR\fB'\fR works.
.Sp
\&\fB\-D\fR and \fB\-U\fR options are processed in the order they
are given on the command line.  All \fB\-imacros\fR \fIfile\fR and
\&\fB\-include\fR \fIfile\fR options are processed after all
\&\fB\-D\fR and \fB\-U\fR options.
.Ip "\fB\-U\fR \fIname\fR" 4
.IX Item "-U name"
Cancel any previous definition of \fIname\fR, either built in or
provided with a \fB\-D\fR option.
.Ip "\fB\-undef\fR" 4
.IX Item "-undef"
Do not predefine any system-specific or GCC-specific macros.  The
standard predefined macros remain defined.
.Ip "\fB\-I\fR \fIdir\fR" 4
.IX Item "-I dir"
Add the directory \fIdir\fR to the list of directories to be searched
for header files.
Directories named by \fB\-I\fR are searched before the standard
system include directories.  If the directory \fIdir\fR is a standard
system include directory, the option is ignored to ensure that the
default search order for system directories and the special treatment
of system headers are not defeated
\&.
.Ip "\fB\-o\fR \fIfile\fR" 4
.IX Item "-o file"
Write output to \fIfile\fR.  This is the same as specifying \fIfile\fR
as the second non-option argument to \fBcpp\fR.  \fBgcc\fR has a
different interpretation of a second non-option argument, so you must
use \fB\-o\fR to specify the output file.
.Ip "\fB\-Wall\fR" 4
.IX Item "-Wall"
Turns on all optional warnings which are desirable for normal code.
At present this is \fB\-Wcomment\fR, \fB\-Wtrigraphs\fR,
\&\fB\-Wmultichar\fR and a warning about integer promotion causing a
change of sign in \f(CW\*(C`#if\*(C'\fR expressions.  Note that many of the
preprocessor's warnings are on by default and have no options to
control them.
.Ip "\fB\-Wcomment\fR" 4
.IX Item "-Wcomment"
.PD 0
.Ip "\fB\-Wcomments\fR" 4
.IX Item "-Wcomments"
.PD
Warn whenever a comment-start sequence \fB/*\fR appears in a \fB/*\fR
comment, or whenever a backslash-newline appears in a \fB//\fR comment.
(Both forms have the same effect.)
.Ip "\fB\-Wtrigraphs\fR" 4
.IX Item "-Wtrigraphs"
@anchor{Wtrigraphs}
Most trigraphs in comments cannot affect the meaning of the program.
However, a trigraph that would form an escaped newline (\fB??/\fR at
the end of a line) can, by changing where the comment begins or ends.
Therefore, only trigraphs that would form escaped newlines produce
warnings inside a comment.
.Sp
This option is implied by \fB\-Wall\fR.  If \fB\-Wall\fR is not
given, this option is still enabled unless trigraphs are enabled.  To
get trigraph conversion without warnings, but get the other
\&\fB\-Wall\fR warnings, use \fB\-trigraphs \-Wall \-Wno-trigraphs\fR.
.Ip "\fB\-Wtraditional\fR" 4
.IX Item "-Wtraditional"
Warn about certain constructs that behave differently in traditional and
\&\s-1ISO\s0 C.  Also warn about \s-1ISO\s0 C constructs that have no traditional C
equivalent, and problematic constructs which should be avoided.
.Ip "\fB\-Wimport\fR" 4
.IX Item "-Wimport"
Warn the first time \fB#import\fR is used.
.Ip "\fB\-Wundef\fR" 4
.IX Item "-Wundef"
Warn whenever an identifier which is not a macro is encountered in an
\&\fB#if\fR directive, outside of \fBdefined\fR.  Such identifiers are
replaced with zero.
.Ip "\fB\-Wunused-macros\fR" 4
.IX Item "-Wunused-macros"
Warn about macros defined in the main file that are unused.  A macro
is \fIused\fR if it is expanded or tested for existence at least once.
The preprocessor will also warn if the macro has not been used at the
time it is redefined or undefined.
.Sp
Built-in macros, macros defined on the command line, and macros
defined in include files are not warned about.
.Sp
\&\fBNote:\fR If a macro is actually used, but only used in skipped
conditional blocks, then \s-1CPP\s0 will report it as unused.  To avoid the
warning in such a case, you might improve the scope of the macro's
definition by, for example, moving it into the first skipped block.
Alternatively, you could provide a dummy use with something like:
.Sp
.Vb 2
\&        #if defined the_macro_causing_the_warning
\&        #endif
.Ve
.Ip "\fB\-Wendif-labels\fR" 4
.IX Item "-Wendif-labels"
Warn whenever an \fB#else\fR or an \fB#endif\fR are followed by text.
This usually happens in code of the form
.Sp
.Vb 5
\&        #if FOO
\&        ...
\&        #else FOO
\&        ...
\&        #endif FOO
.Ve
The second and third \f(CW\*(C`FOO\*(C'\fR should be in comments, but often are not
in older programs.  This warning is on by default.
.Ip "\fB\-Werror\fR" 4
.IX Item "-Werror"
Make all warnings into hard errors.  Source code which triggers warnings
will be rejected.
.Ip "\fB\-Wsystem-headers\fR" 4
.IX Item "-Wsystem-headers"
Issue warnings for code in system headers.  These are normally unhelpful
in finding bugs in your own code, therefore suppressed.  If you are
responsible for the system library, you may want to see them.
.Ip "\fB\-w\fR" 4
.IX Item "-w"
Suppress all warnings, including those which \s-1GNU\s0 \s-1CPP\s0 issues by default.
.Ip "\fB\-pedantic\fR" 4
.IX Item "-pedantic"
Issue all the mandatory diagnostics listed in the C standard.  Some of
them are left out by default, since they trigger frequently on harmless
code.
.Ip "\fB\-pedantic-errors\fR" 4
.IX Item "-pedantic-errors"
Issue all the mandatory diagnostics, and make all mandatory diagnostics
into errors.  This includes mandatory diagnostics that \s-1GCC\s0 issues
without \fB\-pedantic\fR but treats as warnings.
.Ip "\fB\-M\fR" 4
.IX Item "-M"
Instead of outputting the result of preprocessing, output a rule
suitable for \fBmake\fR describing the dependencies of the main
source file.  The preprocessor outputs one \fBmake\fR rule containing
the object file name for that source file, a colon, and the names of all
the included files, including those coming from \fB\-include\fR or
\&\fB\-imacros\fR command line options.
.Sp
Unless specified explicitly (with \fB\-MT\fR or \fB\-MQ\fR), the
object file name consists of the basename of the source file with any
suffix replaced with object file suffix.  If there are many included
files then the rule is split into several lines using \fB\e\fR\-newline.
The rule has no commands.
.Sp
This option does not suppress the preprocessor's debug output, such as
\&\fB\-dM\fR.  To avoid mixing such debug output with the dependency
rules you should explicitly specify the dependency output file with
\&\fB\-MF\fR, or use an environment variable like
\&\fB\s-1DEPENDENCIES_OUTPUT\s0\fR.  Debug output
will still be sent to the regular output stream as normal.
.Sp
Passing \fB\-M\fR to the driver implies \fB\-E\fR, and suppresses
warnings with an implicit \fB\-w\fR.
.Ip "\fB\-MM\fR" 4
.IX Item "-MM"
Like \fB\-M\fR but do not mention header files that are found in
system header directories, nor header files that are included,
directly or indirectly, from such a header.
.Sp
This implies that the choice of angle brackets or double quotes in an
\&\fB#include\fR directive does not in itself determine whether that
header will appear in \fB\-MM\fR dependency output.  This is a
slight change in semantics from \s-1GCC\s0 versions 3.0 and earlier.
.Sp
@anchor{dashMF}
.Ip "\fB\-MF\fR \fIfile\fR" 4
.IX Item "-MF file"
When used with \fB\-M\fR or \fB\-MM\fR, specifies a
file to write the dependencies to.  If no \fB\-MF\fR switch is given
the preprocessor sends the rules to the same place it would have sent
preprocessed output.
.Sp
When used with the driver options \fB\-MD\fR or \fB\-MMD\fR,
\&\fB\-MF\fR overrides the default dependency output file.
.Ip "\fB\-MG\fR" 4
.IX Item "-MG"
In conjunction with an option such as \fB\-M\fR requesting
dependency generation, \fB\-MG\fR assumes missing header files are
generated files and adds them to the dependency list without raising
an error.  The dependency filename is taken directly from the
\&\f(CW\*(C`#include\*(C'\fR directive without prepending any path.  \fB\-MG\fR
also suppresses preprocessed output, as a missing header file renders
this useless.
.Sp
This feature is used in automatic updating of makefiles.
.Ip "\fB\-MP\fR" 4
.IX Item "-MP"
This option instructs \s-1CPP\s0 to add a phony target for each dependency
other than the main file, causing each to depend on nothing.  These
dummy rules work around errors \fBmake\fR gives if you remove header
files without updating the \fIMakefile\fR to match.
.Sp
This is typical output:
.Sp
.Vb 1
\&        test.o: test.c test.h
.Ve
.Vb 1
\&        test.h:
.Ve
.Ip "\fB\-MT\fR \fItarget\fR" 4
.IX Item "-MT target"
Change the target of the rule emitted by dependency generation.  By
default \s-1CPP\s0 takes the name of the main input file, including any path,
deletes any file suffix such as \fB.c\fR, and appends the platform's
usual object suffix.  The result is the target.
.Sp
An \fB\-MT\fR option will set the target to be exactly the string you
specify.  If you want multiple targets, you can specify them as a single
argument to \fB\-MT\fR, or use multiple \fB\-MT\fR options.
.Sp
For example, \fB\-MT\ '$(objpfx)foo.o'\fR might give
.Sp
.Vb 1
\&        $(objpfx)foo.o: foo.c
.Ve
.Ip "\fB\-MQ\fR \fItarget\fR" 4
.IX Item "-MQ target"
Same as \fB\-MT\fR, but it quotes any characters which are special to
Make.  \fB\-MQ\ '$(objpfx)foo.o'\fR gives
.Sp
.Vb 1
\&        $$(objpfx)foo.o: foo.c
.Ve
The default target is automatically quoted, as if it were given with
\&\fB\-MQ\fR.
.Ip "\fB\-MD\fR" 4
.IX Item "-MD"
\&\fB\-MD\fR is equivalent to \fB\-M \-MF\fR \fIfile\fR, except that
\&\fB\-E\fR is not implied.  The driver determines \fIfile\fR based on
whether an \fB\-o\fR option is given.  If it is, the driver uses its
argument but with a suffix of \fI.d\fR, otherwise it take the
basename of the input file and applies a \fI.d\fR suffix.
.Sp
If \fB\-MD\fR is used in conjunction with \fB\-E\fR, any
\&\fB\-o\fR switch is understood to specify the dependency output file
(but \f(CW@pxref\fR{dashMF,,\-MF}), but if used without \fB\-E\fR, each \fB\-o\fR
is understood to specify a target object file.
.Sp
Since \fB\-E\fR is not implied, \fB\-MD\fR can be used to generate
a dependency output file as a side-effect of the compilation process.
.Ip "\fB\-MMD\fR" 4
.IX Item "-MMD"
Like \fB\-MD\fR except mention only user header files, not system
\&\-header files.
.Ip "\fB\-fpch-deps\fR" 4
.IX Item "-fpch-deps"
When using precompiled headers, this flag
will cause the dependency-output flags to also list the files from the
precompiled header's dependencies.  If not specified only the
precompiled header would be listed and not the files that were used to
create it because those files are not consulted when a precompiled
header is used.
.Ip "\fB\-x c\fR" 4
.IX Item "-x c"
.PD 0
.Ip "\fB\-x c++\fR" 4
.IX Item "-x c++"
.Ip "\fB\-x objective-c\fR" 4
.IX Item "-x objective-c"
.Ip "\fB\-x assembler-with-cpp\fR" 4
.IX Item "-x assembler-with-cpp"
.PD
Specify the source language: C, \*(C+, Objective-C, or assembly.  This has
nothing to do with standards conformance or extensions; it merely
selects which base syntax to expect.  If you give none of these options,
cpp will deduce the language from the extension of the source file:
\&\fB.c\fR, \fB.cc\fR, \fB.m\fR, or \fB.S\fR.  Some other common
extensions for \*(C+ and assembly are also recognized.  If cpp does not
recognize the extension, it will treat the file as C; this is the most
generic mode.
.Sp
\&\fBNote:\fR Previous versions of cpp accepted a \fB\-lang\fR option
which selected both the language and the standards conformance level.
This option has been removed, because it conflicts with the \fB\-l\fR
option.
.Ip "\fB\-std=\fR\fIstandard\fR" 4
.IX Item "-std=standard"
.PD 0
.Ip "\fB\-ansi\fR" 4
.IX Item "-ansi"
.PD
Specify the standard to which the code should conform.  Currently \s-1CPP\s0
knows about C and \*(C+ standards; others may be added in the future.
.Sp
\&\fIstandard\fR
may be one of:
.RS 4
.if n .Ip "\f(CW""""iso9899:1990""""\fR" 4
.el .Ip "\f(CWiso9899:1990\fR" 4
.IX Item "iso9899:1990"
.PD 0
.if n .Ip "\f(CW""""c89""""\fR" 4
.el .Ip "\f(CWc89\fR" 4
.IX Item "c89"
.PD
The \s-1ISO\s0 C standard from 1990.  \fBc89\fR is the customary shorthand for
this version of the standard.
.Sp
The \fB\-ansi\fR option is equivalent to \fB\-std=c89\fR.
.if n .Ip "\f(CW""""iso9899:199409""""\fR" 4
.el .Ip "\f(CWiso9899:199409\fR" 4
.IX Item "iso9899:199409"
The 1990 C standard, as amended in 1994.
.if n .Ip "\f(CW""""iso9899:1999""""\fR" 4
.el .Ip "\f(CWiso9899:1999\fR" 4
.IX Item "iso9899:1999"
.PD 0
.if n .Ip "\f(CW""""c99""""\fR" 4
.el .Ip "\f(CWc99\fR" 4
.IX Item "c99"
.if n .Ip "\f(CW""""iso9899:199x""""\fR" 4
.el .Ip "\f(CWiso9899:199x\fR" 4
.IX Item "iso9899:199x"
.if n .Ip "\f(CW""""c9x""""\fR" 4
.el .Ip "\f(CWc9x\fR" 4
.IX Item "c9x"
.PD
The revised \s-1ISO\s0 C standard, published in December 1999.  Before
publication, this was known as C9X.
.if n .Ip "\f(CW""""gnu89""""\fR" 4
.el .Ip "\f(CWgnu89\fR" 4
.IX Item "gnu89"
The 1990 C standard plus \s-1GNU\s0 extensions.  This is the default.
.if n .Ip "\f(CW""""gnu99""""\fR" 4
.el .Ip "\f(CWgnu99\fR" 4
.IX Item "gnu99"
.PD 0
.if n .Ip "\f(CW""""gnu9x""""\fR" 4
.el .Ip "\f(CWgnu9x\fR" 4
.IX Item "gnu9x"
.PD
The 1999 C standard plus \s-1GNU\s0 extensions.
.if n .Ip "\f(CW""""c++98""""\fR" 4
.el .Ip "\f(CWc++98\fR" 4
.IX Item "c++98"
The 1998 \s-1ISO\s0 \*(C+ standard plus amendments.
.if n .Ip "\f(CW""""gnu++98""""\fR" 4
.el .Ip "\f(CWgnu++98\fR" 4
.IX Item "gnu++98"
The same as \fB\-std=c++98\fR plus \s-1GNU\s0 extensions.  This is the
default for \*(C+ code.
.RE
.RS 4
.RE
.Ip "\fB\-I-\fR" 4
.IX Item "-I-"
Split the include path.  Any directories specified with \fB\-I\fR
options before \fB\-I-\fR are searched only for headers requested with
\&\f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR; they are not searched for
\&\f(CW\*(C`#include\ <\f(CIfile\f(CW>\*(C'\fR.  If additional directories are
specified with \fB\-I\fR options after the \fB\-I-\fR, those
directories are searched for all \fB#include\fR directives.
.Sp
In addition, \fB\-I-\fR inhibits the use of the directory of the current
file directory as the first search directory for \f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR.
.Ip "\fB\-nostdinc\fR" 4
.IX Item "-nostdinc"
Do not search the standard system directories for header files.
Only the directories you have specified with \fB\-I\fR options
(and the directory of the current file, if appropriate) are searched.
.Ip "\fB\-nostdinc++\fR" 4
.IX Item "-nostdinc++"
Do not search for header files in the \*(C+\-specific standard directories,
but do still search the other standard directories.  (This option is
used when building the \*(C+ library.)
.Ip "\fB\-include\fR \fIfile\fR" 4
.IX Item "-include file"
Process \fIfile\fR as if \f(CW\*(C`#include "file"\*(C'\fR appeared as the first
line of the primary source file.  However, the first directory searched
for \fIfile\fR is the preprocessor's working directory \fIinstead of\fR
the directory containing the main source file.  If not found there, it
is searched for in the remainder of the \f(CW\*(C`#include "..."\*(C'\fR search
chain as normal.
.Sp
If multiple \fB\-include\fR options are given, the files are included
in the order they appear on the command line.
.Ip "\fB\-imacros\fR \fIfile\fR" 4
.IX Item "-imacros file"
Exactly like \fB\-include\fR, except that any output produced by
scanning \fIfile\fR is thrown away.  Macros it defines remain defined.
This allows you to acquire all the macros from a header without also
processing its declarations.
.Sp
All files specified by \fB\-imacros\fR are processed before all files
specified by \fB\-include\fR.
.Ip "\fB\-idirafter\fR \fIdir\fR" 4
.IX Item "-idirafter dir"
Search \fIdir\fR for header files, but do it \fIafter\fR all
directories specified with \fB\-I\fR and the standard system directories
have been exhausted.  \fIdir\fR is treated as a system include directory.
.Ip "\fB\-iprefix\fR \fIprefix\fR" 4
.IX Item "-iprefix prefix"
Specify \fIprefix\fR as the prefix for subsequent \fB\-iwithprefix\fR
options.  If the prefix represents a directory, you should include the
final \fB/\fR.
.Ip "\fB\-iwithprefix\fR \fIdir\fR" 4
.IX Item "-iwithprefix dir"
.PD 0
.Ip "\fB\-iwithprefixbefore\fR \fIdir\fR" 4
.IX Item "-iwithprefixbefore dir"
.PD
Append \fIdir\fR to the prefix specified previously with
\&\fB\-iprefix\fR, and add the resulting directory to the include search
path.  \fB\-iwithprefixbefore\fR puts it in the same place \fB\-I\fR
would; \fB\-iwithprefix\fR puts it where \fB\-idirafter\fR would.
.Ip "\fB\-isystem\fR \fIdir\fR" 4
.IX Item "-isystem dir"
Search \fIdir\fR for header files, after all directories specified by
\&\fB\-I\fR but before the standard system directories.  Mark it
as a system directory, so that it gets the same special treatment as
is applied to the standard system directories.
.Ip "\fB\-fdollars-in-identifiers\fR" 4
.IX Item "-fdollars-in-identifiers"
@anchor{fdollars-in-identifiers}
Accept \fB$\fR in identifiers.
.Ip "\fB\-fpreprocessed\fR" 4
.IX Item "-fpreprocessed"
Indicate to the preprocessor that the input file has already been
preprocessed.  This suppresses things like macro expansion, trigraph
conversion, escaped newline splicing, and processing of most directives.
The preprocessor still recognizes and removes comments, so that you can
pass a file preprocessed with \fB\-C\fR to the compiler without
problems.  In this mode the integrated preprocessor is little more than
a tokenizer for the front ends.
.Sp
\&\fB\-fpreprocessed\fR is implicit if the input file has one of the
extensions \fB.i\fR, \fB.ii\fR or \fB.mi\fR.  These are the
extensions that \s-1GCC\s0 uses for preprocessed files created by
\&\fB\-save-temps\fR.
.Ip "\fB\-ftabstop=\fR\fIwidth\fR" 4
.IX Item "-ftabstop=width"
Set the distance between tab stops.  This helps the preprocessor report
correct column numbers in warnings or errors, even if tabs appear on the
line.  If the value is less than 1 or greater than 100, the option is
ignored.  The default is 8.
.Ip "\fB\-fexec-charset=\fR\fIcharset\fR" 4
.IX Item "-fexec-charset=charset"
Set the execution character set, used for string and character
constants.  The default is \s-1UTF-8\s0.  \fIcharset\fR can be any encoding
supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine.
.Ip "\fB\-fwide-exec-charset=\fR\fIcharset\fR" 4
.IX Item "-fwide-exec-charset=charset"
Set the wide execution character set, used for wide string and
character constants.  The default is \s-1UTF-32\s0 or \s-1UTF-16\s0, whichever
corresponds to the width of \f(CW\*(C`wchar_t\*(C'\fR.  As with
\&\fB\-ftarget-charset\fR, \fIcharset\fR can be any encoding supported
by the system's \f(CW\*(C`iconv\*(C'\fR library routine; however, you will have
problems with encodings that do not fit exactly in \f(CW\*(C`wchar_t\*(C'\fR.
.Ip "\fB\-finput-charset=\fR\fIcharset\fR" 4
.IX Item "-finput-charset=charset"
Set the input character set, used for translation from the character
set of the input file to the source character set used by \s-1GCC\s0. If the
locale does not specify, or \s-1GCC\s0 cannot get this information from the
locale, the default is \s-1UTF-8\s0. This can be overridden by either the locale
or this command line option. Currently the command line option takes
precedence if there's a conflict. \fIcharset\fR can be any encoding
supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine.
.Ip "\fB\-fworking-directory\fR" 4
.IX Item "-fworking-directory"
Enable generation of linemarkers in the preprocessor output that will
let the compiler know the current working directory at the time of
preprocessing.  When this option is enabled, the preprocessor will
emit, after the initial linemarker, a second linemarker with the
current working directory followed by two slashes.  \s-1GCC\s0 will use this
directory, when it's present in the preprocessed input, as the
directory emitted as the current working directory in some debugging
information formats.  This option is implicitly enabled if debugging
information is enabled, but this can be inhibited with the negated
form \fB\-fno-working-directory\fR.  If the \fB\-P\fR flag is
present in the command line, this option has no effect, since no
\&\f(CW\*(C`#line\*(C'\fR directives are emitted whatsoever.
.Ip "\fB\-fno-show-column\fR" 4
.IX Item "-fno-show-column"
Do not print column numbers in diagnostics.  This may be necessary if
diagnostics are being scanned by a program that does not understand the
column numbers, such as \fBdejagnu\fR.
.Ip "\fB\-A\fR \fIpredicate\fR\fB=\fR\fIanswer\fR" 4
.IX Item "-A predicate=answer"
Make an assertion with the predicate \fIpredicate\fR and answer
\&\fIanswer\fR.  This form is preferred to the older form \fB\-A\fR
\&\fIpredicate\fR\fB(\fR\fIanswer\fR\fB)\fR, which is still supported, because
it does not use shell special characters.
.Ip "\fB\-A -\fR\fIpredicate\fR\fB=\fR\fIanswer\fR" 4
.IX Item "-A -predicate=answer"
Cancel an assertion with the predicate \fIpredicate\fR and answer
\&\fIanswer\fR.
.Ip "\fB\-dCHARS\fR" 4
.IX Item "-dCHARS"
\&\fI\s-1CHARS\s0\fR is a sequence of one or more of the following characters,
and must not be preceded by a space.  Other characters are interpreted
by the compiler proper, or reserved for future versions of \s-1GCC\s0, and so
are silently ignored.  If you specify characters whose behavior
conflicts, the result is undefined.
.RS 4
.Ip "\fBM\fR" 4
.IX Item "M"
Instead of the normal output, generate a list of \fB#define\fR
directives for all the macros defined during the execution of the
preprocessor, including predefined macros.  This gives you a way of
finding out what is predefined in your version of the preprocessor.
Assuming you have no file \fIfoo.h\fR, the command
.Sp
.Vb 1
\&        touch foo.h; cpp -dM foo.h
.Ve
will show all the predefined macros.
.Ip "\fBD\fR" 4
.IX Item "D"
Like \fBM\fR except in two respects: it does \fInot\fR include the
predefined macros, and it outputs \fIboth\fR the \fB#define\fR
directives and the result of preprocessing.  Both kinds of output go to
the standard output file.
.Ip "\fBN\fR" 4
.IX Item "N"
Like \fBD\fR, but emit only the macro names, not their expansions.
.Ip "\fBI\fR" 4
.IX Item "I"
Output \fB#include\fR directives in addition to the result of
preprocessing.
.RE
.RS 4
.RE
.Ip "\fB\-P\fR" 4
.IX Item "-P"
Inhibit generation of linemarkers in the output from the preprocessor.
This might be useful when running the preprocessor on something that is
not C code, and will be sent to a program which might be confused by the
linemarkers.
.Ip "\fB\-C\fR" 4
.IX Item "-C"
Do not discard comments.  All comments are passed through to the output
file, except for comments in processed directives, which are deleted
along with the directive.
.Sp
You should be prepared for side effects when using \fB\-C\fR; it
causes the preprocessor to treat comments as tokens in their own right.
For example, comments appearing at the start of what would be a
directive line have the effect of turning that line into an ordinary
source line, since the first token on the line is no longer a \fB#\fR.
.Ip "\fB\-CC\fR" 4
.IX Item "-CC"
Do not discard comments, including during macro expansion.  This is
like \fB\-C\fR, except that comments contained within macros are
also passed through to the output file where the macro is expanded.
.Sp
In addition to the side-effects of the \fB\-C\fR option, the
\&\fB\-CC\fR option causes all \*(C+\-style comments inside a macro
to be converted to C-style comments.  This is to prevent later use
of that macro from inadvertently commenting out the remainder of
the source line.
.Sp
The \fB\-CC\fR option is generally used to support lint comments.
.Ip "\fB\-traditional-cpp\fR" 4
.IX Item "-traditional-cpp"
Try to imitate the behavior of old-fashioned C preprocessors, as
opposed to \s-1ISO\s0 C preprocessors.
.Ip "\fB\-trigraphs\fR" 4
.IX Item "-trigraphs"
Process trigraph sequences.
These are three-character sequences, all starting with \fB??\fR, that
are defined by \s-1ISO\s0 C to stand for single characters.  For example,
\&\fB??/\fR stands for \fB\e\fR, so \fB'??/n'\fR is a character
constant for a newline.  By default, \s-1GCC\s0 ignores trigraphs, but in
standard-conforming modes it converts them.  See the \fB\-std\fR and
\&\fB\-ansi\fR options.
.Sp
The nine trigraphs and their replacements are
.Sp
.Vb 2
\&        Trigraph:       ??(  ??)  ??<  ??>  ??=  ??/  ??'  ??!  ??-
\&        Replacement:      [    ]    {    }    #    \e    ^    |    ~
.Ve
.Ip "\fB\-remap\fR" 4
.IX Item "-remap"
Enable special code to work around file systems which only permit very
short file names, such as \s-1MS-DOS\s0.
.Ip "\fB\*(--help\fR" 4
.IX Item "help"
.PD 0
.Ip "\fB\*(--target-help\fR" 4
.IX Item "target-help"
.PD
Print text describing all the command line options instead of
preprocessing anything.
.Ip "\fB\-v\fR" 4
.IX Item "-v"
Verbose mode.  Print out \s-1GNU\s0 \s-1CPP\s0's version number at the beginning of
execution, and report the final form of the include path.
.Ip "\fB\-H\fR" 4
.IX Item "-H"
Print the name of each header file used, in addition to other normal
activities.  Each name is indented to show how deep in the
\&\fB#include\fR stack it is.  Precompiled header files are also
printed, even if they are found to be invalid; an invalid precompiled
header file is printed with \fB...x\fR and a valid one with \fB...!\fR .
.Ip "\fB\-version\fR" 4
.IX Item "-version"
.PD 0
.Ip "\fB\*(--version\fR" 4
.IX Item "version"
.PD
Print out \s-1GNU\s0 \s-1CPP\s0's version number.  With one dash, proceed to
preprocess as normal.  With two dashes, exit immediately.
.Sh "Passing Options to the Assembler"
.IX Subsection "Passing Options to the Assembler"
You can pass options to the assembler.
.Ip "\fB\-Wa,\fR\fIoption\fR" 4
.IX Item "-Wa,option"
Pass \fIoption\fR as an option to the assembler.  If \fIoption\fR
contains commas, it is split into multiple options at the commas.
.Ip "\fB\-Xassembler\fR \fIoption\fR" 4
.IX Item "-Xassembler option"
Pass \fIoption\fR as an option to the assembler.  You can use this to
supply system-specific assembler options which \s-1GCC\s0 does not know how to
recognize.
.Sp
If you want to pass an option that takes an argument, you must use
\&\fB\-Xassembler\fR twice, once for the option and once for the argument.
.Sh "Options for Linking"
.IX Subsection "Options for Linking"
These options come into play when the compiler links object files into
an executable output file.  They are meaningless if the compiler is
not doing a link step.
.Ip "\fIobject-file-name\fR" 4
.IX Item "object-file-name"
A file name that does not end in a special recognized suffix is
considered to name an object file or library.  (Object files are
distinguished from libraries by the linker according to the file
contents.)  If linking is done, these object files are used as input
to the linker.
.Ip "\fB\-c\fR" 4
.IX Item "-c"
.PD 0
.Ip "\fB\-S\fR" 4
.IX Item "-S"
.Ip "\fB\-E\fR" 4
.IX Item "-E"
.PD
If any of these options is used, then the linker is not run, and
object file names should not be used as arguments.  
.Ip "\fB\-l\fR\fIlibrary\fR" 4
.IX Item "-llibrary"
.PD 0
.Ip "\fB\-l\fR \fIlibrary\fR" 4
.IX Item "-l library"
.PD
Search the library named \fIlibrary\fR when linking.  (The second
alternative with the library as a separate argument is only for
\&\s-1POSIX\s0 compliance and is not recommended.)
.Sp
It makes a difference where in the command you write this option; the
linker searches and processes libraries and object files in the order they
are specified.  Thus, \fBfoo.o \-lz bar.o\fR searches library \fBz\fR
after file \fIfoo.o\fR but before \fIbar.o\fR.  If \fIbar.o\fR refers
to functions in \fBz\fR, those functions may not be loaded.
.Sp
The linker searches a standard list of directories for the library,
which is actually a file named \fIlib\fIlibrary\fI.a\fR.  The linker
then uses this file as if it had been specified precisely by name.
.Sp
The directories searched include several standard system directories
plus any that you specify with \fB\-L\fR.
.Sp
Normally the files found this way are library files\-\-\-archive files
whose members are object files.  The linker handles an archive file by
scanning through it for members which define symbols that have so far
been referenced but not defined.  But if the file that is found is an
ordinary object file, it is linked in the usual fashion.  The only
difference between using an \fB\-l\fR option and specifying a file name
is that \fB\-l\fR surrounds \fIlibrary\fR with \fBlib\fR and \fB.a\fR
and searches several directories.
.Ip "\fB\-lobjc\fR" 4
.IX Item "-lobjc"
You need this special case of the \fB\-l\fR option in order to
link an Objective-C program.
.Ip "\fB\-nostartfiles\fR" 4
.IX Item "-nostartfiles"
Do not use the standard system startup files when linking.
The standard system libraries are used normally, unless \fB\-nostdlib\fR
or \fB\-nodefaultlibs\fR is used.
.Ip "\fB\-nodefaultlibs\fR" 4
.IX Item "-nodefaultlibs"
Do not use the standard system libraries when linking.
Only the libraries you specify will be passed to the linker.
The standard startup files are used normally, unless \fB\-nostartfiles\fR
is used.  The compiler may generate calls to memcmp, memset, and memcpy
for System V (and \s-1ISO\s0 C) environments or to bcopy and bzero for
\&\s-1BSD\s0 environments.  These entries are usually resolved by entries in
libc.  These entry points should be supplied through some other
mechanism when this option is specified.
.Ip "\fB\-nostdlib\fR" 4
.IX Item "-nostdlib"
Do not use the standard system startup files or libraries when linking.
No startup files and only the libraries you specify will be passed to
the linker.  The compiler may generate calls to memcmp, memset, and memcpy
for System V (and \s-1ISO\s0 C) environments or to bcopy and bzero for
\&\s-1BSD\s0 environments.  These entries are usually resolved by entries in
libc.  These entry points should be supplied through some other
mechanism when this option is specified.
.Sp
One of the standard libraries bypassed by \fB\-nostdlib\fR and
\&\fB\-nodefaultlibs\fR is \fIlibgcc.a\fR, a library of internal subroutines
that \s-1GCC\s0 uses to overcome shortcomings of particular machines, or special
needs for some languages.
.Sp
In most cases, you need \fIlibgcc.a\fR even when you want to avoid
other standard libraries.  In other words, when you specify \fB\-nostdlib\fR
or \fB\-nodefaultlibs\fR you should usually specify \fB\-lgcc\fR as well.
This ensures that you have no unresolved references to internal \s-1GCC\s0
library subroutines.  (For example, \fB_\|_main\fR, used to ensure \*(C+
constructors will be called.)
.Ip "\fB\-pie\fR" 4
.IX Item "-pie"
Produce a position independent executable on targets which support it.
For predictable results, you must also specify the same set of options
that were used to generate code (\fB\-fpie\fR, \fB\-fPIE\fR,
or model suboptions) when you specify this option.
.Ip "\fB\-s\fR" 4
.IX Item "-s"
Remove all symbol table and relocation information from the executable.
.Ip "\fB\-static\fR" 4
.IX Item "-static"
On systems that support dynamic linking, this prevents linking with the shared
libraries.  On other systems, this option has no effect.
.Ip "\fB\-shared\fR" 4
.IX Item "-shared"
Produce a shared object which can then be linked with other objects to
form an executable.  Not all systems support this option.  For predictable
results, you must also specify the same set of options that were used to
generate code (\fB\-fpic\fR, \fB\-fPIC\fR, or model suboptions)
when you specify this option.[1]
.Ip "\fB\-shared-libgcc\fR" 4
.IX Item "-shared-libgcc"
.PD 0
.Ip "\fB\-static-libgcc\fR" 4
.IX Item "-static-libgcc"
.PD
On systems that provide \fIlibgcc\fR as a shared library, these options
force the use of either the shared or static version respectively.
If no shared version of \fIlibgcc\fR was built when the compiler was
configured, these options have no effect.
.Sp
There are several situations in which an application should use the
shared \fIlibgcc\fR instead of the static version.  The most common
of these is when the application wishes to throw and catch exceptions
across different shared libraries.  In that case, each of the libraries
as well as the application itself should use the shared \fIlibgcc\fR.
.Sp
Therefore, the G++ and \s-1GCJ\s0 drivers automatically add
\&\fB\-shared-libgcc\fR whenever you build a shared library or a main
executable, because \*(C+ and Java programs typically use exceptions, so
this is the right thing to do.
.Sp
If, instead, you use the \s-1GCC\s0 driver to create shared libraries, you may
find that they will not always be linked with the shared \fIlibgcc\fR.
If \s-1GCC\s0 finds, at its configuration time, that you have a non-GNU linker
or a \s-1GNU\s0 linker that does not support option \fB\*(--eh-frame-hdr\fR,
it will link the shared version of \fIlibgcc\fR into shared libraries
by default.  Otherwise, it will take advantage of the linker and optimize
away the linking with the shared version of \fIlibgcc\fR, linking with
the static version of libgcc by default.  This allows exceptions to
propagate through such shared libraries, without incurring relocation
costs at library load time.
.Sp
However, if a library or main executable is supposed to throw or catch
exceptions, you must link it using the G++ or \s-1GCJ\s0 driver, as appropriate
for the languages used in the program, or using the option
\&\fB\-shared-libgcc\fR, such that it is linked with the shared
\&\fIlibgcc\fR.
.Ip "\fB\-symbolic\fR" 4
.IX Item "-symbolic"
Bind references to global symbols when building a shared object.  Warn
about any unresolved references (unless overridden by the link editor
option \fB\-Xlinker \-z \-Xlinker defs\fR).  Only a few systems support
this option.
.Ip "\fB\-Xlinker\fR \fIoption\fR" 4
.IX Item "-Xlinker option"
Pass \fIoption\fR as an option to the linker.  You can use this to
supply system-specific linker options which \s-1GCC\s0 does not know how to
recognize.
.Sp
If you want to pass an option that takes an argument, you must use
\&\fB\-Xlinker\fR twice, once for the option and once for the argument.
For example, to pass \fB\-assert definitions\fR, you must write
\&\fB\-Xlinker \-assert \-Xlinker definitions\fR.  It does not work to write
\&\fB\-Xlinker \*(L"\-assert definitions\*(R"\fR, because this passes the entire
string as a single argument, which is not what the linker expects.
.Ip "\fB\-Wl,\fR\fIoption\fR" 4
.IX Item "-Wl,option"
Pass \fIoption\fR as an option to the linker.  If \fIoption\fR contains
commas, it is split into multiple options at the commas.
.Ip "\fB\-u\fR \fIsymbol\fR" 4
.IX Item "-u symbol"
Pretend the symbol \fIsymbol\fR is undefined, to force linking of
library modules to define it.  You can use \fB\-u\fR multiple times with
different symbols to force loading of additional library modules.
.Sh "Options for Directory Search"
.IX Subsection "Options for Directory Search"
These options specify directories to search for header files, for
libraries and for parts of the compiler:
.Ip "\fB\-I\fR\fIdir\fR" 4
.IX Item "-Idir"
Add the directory \fIdir\fR to the head of the list of directories to be
searched for header files.  This can be used to override a system header
file, substituting your own version, since these directories are
searched before the system header file directories.  However, you should
not use this option to add directories that contain vendor-supplied
system header files (use \fB\-isystem\fR for that).  If you use more than
one \fB\-I\fR option, the directories are scanned in left-to-right
order; the standard system directories come after.
.Sp
If a standard system include directory, or a directory specified with
\&\fB\-isystem\fR, is also specified with \fB\-I\fR, the \fB\-I\fR
option will be ignored.  The directory will still be searched but as a
system directory at its normal position in the system include chain.
This is to ensure that \s-1GCC\s0's procedure to fix buggy system headers and
the ordering for the include_next directive are not inadvertently changed.
If you really need to change the search order for system directories,
use the \fB\-nostdinc\fR and/or \fB\-isystem\fR options.
.Ip "\fB\-I-\fR" 4
.IX Item "-I-"
Any directories you specify with \fB\-I\fR options before the \fB\-I-\fR
option are searched only for the case of \fB#include "\fR\fIfile\fR\fB"\fR;
they are not searched for \fB#include <\fR\fIfile\fR\fB>\fR.
.Sp
If additional directories are specified with \fB\-I\fR options after
the \fB\-I-\fR, these directories are searched for all \fB#include\fR
directives.  (Ordinarily \fIall\fR \fB\-I\fR directories are used
this way.)
.Sp
In addition, the \fB\-I-\fR option inhibits the use of the current
directory (where the current input file came from) as the first search
directory for \fB#include "\fR\fIfile\fR\fB"\fR.  There is no way to
override this effect of \fB\-I-\fR.  With \fB\-I.\fR you can specify
searching the directory which was current when the compiler was
invoked.  That is not exactly the same as what the preprocessor does
by default, but it is often satisfactory.
.Sp
\&\fB\-I-\fR does not inhibit the use of the standard system directories
for header files.  Thus, \fB\-I-\fR and \fB\-nostdinc\fR are
independent.
.Ip "\fB\-L\fR\fIdir\fR" 4
.IX Item "-Ldir"
Add directory \fIdir\fR to the list of directories to be searched
for \fB\-l\fR.
.Ip "\fB\-B\fR\fIprefix\fR" 4
.IX Item "-Bprefix"
This option specifies where to find the executables, libraries,
include files, and data files of the compiler itself.
.Sp
The compiler driver program runs one or more of the subprograms
\&\fIcpp\fR, \fIcc1\fR, \fIas\fR and \fIld\fR.  It tries
\&\fIprefix\fR as a prefix for each program it tries to run, both with and
without \fImachine\fR\fB/\fR\fIversion\fR\fB/\fR.
.Sp
For each subprogram to be run, the compiler driver first tries the
\&\fB\-B\fR prefix, if any.  If that name is not found, or if \fB\-B\fR
was not specified, the driver tries two standard prefixes, which are
\&\fI/usr/lib/gcc/\fR and \fI/usr/local/lib/gcc/\fR.  If neither of
those results in a file name that is found, the unmodified program
name is searched for using the directories specified in your
\&\fB\s-1PATH\s0\fR environment variable.
.Sp
The compiler will check to see if the path provided by the \fB\-B\fR
refers to a directory, and if necessary it will add a directory
separator character at the end of the path.
.Sp
\&\fB\-B\fR prefixes that effectively specify directory names also apply
to libraries in the linker, because the compiler translates these
options into \fB\-L\fR options for the linker.  They also apply to
includes files in the preprocessor, because the compiler translates these
options into \fB\-isystem\fR options for the preprocessor.  In this case,
the compiler appends \fBinclude\fR to the prefix.
.Sp
The run-time support file \fIlibgcc.a\fR can also be searched for using
the \fB\-B\fR prefix, if needed.  If it is not found there, the two
standard prefixes above are tried, and that is all.  The file is left
out of the link if it is not found by those means.
.Sp
Another way to specify a prefix much like the \fB\-B\fR prefix is to use
the environment variable \fB\s-1GCC_EXEC_PREFIX\s0\fR.  
.Sp
As a special kludge, if the path provided by \fB\-B\fR is
\&\fI[dir/]stage\fIN\fI/\fR, where \fIN\fR is a number in the range 0 to
9, then it will be replaced by \fI[dir/]include\fR.  This is to help
with boot-strapping the compiler.
.Ip "\fB\-specs=\fR\fIfile\fR" 4
.IX Item "-specs=file"
Process \fIfile\fR after the compiler reads in the standard \fIspecs\fR
file, in order to override the defaults that the \fIgcc\fR driver
program uses when determining what switches to pass to \fIcc1\fR,
\&\fIcc1plus\fR, \fIas\fR, \fIld\fR, etc.  More than one
\&\fB\-specs=\fR\fIfile\fR can be specified on the command line, and they
are processed in order, from left to right.
.Sh "Specifying Target Machine and Compiler Version"
.IX Subsection "Specifying Target Machine and Compiler Version"
The usual way to run \s-1GCC\s0 is to run the executable called \fIgcc\fR, or
\&\fI<machine>\-gcc\fR when cross-compiling, or
\&\fI<machine>\-gcc-<version>\fR to run a version other than the one that
was installed last.  Sometimes this is inconvenient, so \s-1GCC\s0 provides
options that will switch to another cross-compiler or version.
.Ip "\fB\-b\fR \fImachine\fR" 4
.IX Item "-b machine"
The argument \fImachine\fR specifies the target machine for compilation.
.Sp
The value to use for \fImachine\fR is the same as was specified as the
machine type when configuring \s-1GCC\s0 as a cross-compiler.  For
example, if a cross-compiler was configured with \fBconfigure
i386v\fR, meaning to compile for an 80386 running System V, then you
would specify \fB\-b i386v\fR to run that cross compiler.
.Ip "\fB\-V\fR \fIversion\fR" 4
.IX Item "-V version"
The argument \fIversion\fR specifies which version of \s-1GCC\s0 to run.
This is useful when multiple versions are installed.  For example,
\&\fIversion\fR might be \fB2.0\fR, meaning to run \s-1GCC\s0 version 2.0.
.PP
The \fB\-V\fR and \fB\-b\fR options work by running the
\&\fI<machine>\-gcc-<version>\fR executable, so there's no real reason to
use them if you can just run that directly.
.Sh "Hardware Models and Configurations"
.IX Subsection "Hardware Models and Configurations"
Earlier we discussed the standard option \fB\-b\fR which chooses among
different installed compilers for completely different target
machines, such as \s-1VAX\s0 vs. 68000 vs. 80386.
.PP
In addition, each of these target machine types can have its own
special options, starting with \fB\-m\fR, to choose among various
hardware models or configurations\-\-\-for example, 68010 vs 68020,
floating coprocessor or none.  A single installed version of the
compiler can compile for any model or configuration, according to the
options specified.
.PP
Some configurations of the compiler also support additional special
options, usually for compatibility with other compilers on the same
platform.
.PP
These options are defined by the macro \f(CW\*(C`TARGET_SWITCHES\*(C'\fR in the
machine description.  The default for the options is also defined by
that macro, which enables you to change the defaults.
.PP
.I "M680x0 Options"
.IX Subsection "M680x0 Options"
.PP
These are the \fB\-m\fR options defined for the 68000 series.  The default
values for these options depends on which style of 68000 was selected when
the compiler was configured; the defaults for the most common choices are
given below.
.Ip "\fB\-m68000\fR" 4
.IX Item "-m68000"
.PD 0
.Ip "\fB\-mc68000\fR" 4
.IX Item "-mc68000"
.PD
Generate output for a 68000.  This is the default
when the compiler is configured for 68000\-based systems.
.Sp
Use this option for microcontrollers with a 68000 or \s-1EC000\s0 core,
including the 68008, 68302, 68306, 68307, 68322, 68328 and 68356.
.Ip "\fB\-m68020\fR" 4
.IX Item "-m68020"
.PD 0
.Ip "\fB\-mc68020\fR" 4
.IX Item "-mc68020"
.PD
Generate output for a 68020.  This is the default
when the compiler is configured for 68020\-based systems.
.Ip "\fB\-m68881\fR" 4
.IX Item "-m68881"
Generate output containing 68881 instructions for floating point.
This is the default for most 68020 systems unless \fB\*(--nfp\fR was
specified when the compiler was configured.
.Ip "\fB\-m68030\fR" 4
.IX Item "-m68030"
Generate output for a 68030.  This is the default when the compiler is
configured for 68030\-based systems.
.Ip "\fB\-m68040\fR" 4
.IX Item "-m68040"
Generate output for a 68040.  This is the default when the compiler is
configured for 68040\-based systems.
.Sp
This option inhibits the use of 68881/68882 instructions that have to be
emulated by software on the 68040.  Use this option if your 68040 does not
have code to emulate those instructions.
.Ip "\fB\-m68060\fR" 4
.IX Item "-m68060"
Generate output for a 68060.  This is the default when the compiler is
configured for 68060\-based systems.
.Sp
This option inhibits the use of 68020 and 68881/68882 instructions that
have to be emulated by software on the 68060.  Use this option if your 68060
does not have code to emulate those instructions.
.Ip "\fB\-mcpu32\fR" 4
.IX Item "-mcpu32"
Generate output for a \s-1CPU32\s0.  This is the default
when the compiler is configured for CPU32\-based systems.
.Sp
Use this option for microcontrollers with a
\&\s-1CPU32\s0 or \s-1CPU32+\s0 core, including the 68330, 68331, 68332, 68333, 68334,
68336, 68340, 68341, 68349 and 68360.
.Ip "\fB\-m5200\fR" 4
.IX Item "-m5200"
Generate output for a 520X ``coldfire'' family cpu.  This is the default
when the compiler is configured for 520X-based systems.
.Sp
Use this option for microcontroller with a 5200 core, including
the \s-1MCF5202\s0, \s-1MCF5203\s0, \s-1MCF5204\s0 and \s-1MCF5202\s0.
.Ip "\fB\-m68020\-40\fR" 4
.IX Item "-m68020-40"
Generate output for a 68040, without using any of the new instructions.
This results in code which can run relatively efficiently on either a
68020/68881 or a 68030 or a 68040.  The generated code does use the
68881 instructions that are emulated on the 68040.
.Ip "\fB\-m68020\-60\fR" 4
.IX Item "-m68020-60"
Generate output for a 68060, without using any of the new instructions.
This results in code which can run relatively efficiently on either a
68020/68881 or a 68030 or a 68040.  The generated code does use the
68881 instructions that are emulated on the 68060.
.Ip "\fB\-msoft-float\fR" 4
.IX Item "-msoft-float"
Generate output containing library calls for floating point.
\&\fBWarning:\fR the requisite libraries are not available for all m68k
targets.  Normally the facilities of the machine's usual C compiler are
used, but this can't be done directly in cross-compilation.  You must
make your own arrangements to provide suitable library functions for
cross-compilation.  The embedded targets \fBm68k-*\-aout\fR and
\&\fBm68k-*\-coff\fR do provide software floating point support.
.Ip "\fB\-mshort\fR" 4
.IX Item "-mshort"
Consider type \f(CW\*(C`int\*(C'\fR to be 16 bits wide, like \f(CW\*(C`short int\*(C'\fR.
.Ip "\fB\-mnobitfield\fR" 4
.IX Item "-mnobitfield"
Do not use the bit-field instructions.  The \fB\-m68000\fR, \fB\-mcpu32\fR
and \fB\-m5200\fR options imply \fB\-mnobitfield\fR.
.Ip "\fB\-mbitfield\fR" 4
.IX Item "-mbitfield"
Do use the bit-field instructions.  The \fB\-m68020\fR option implies
\&\fB\-mbitfield\fR.  This is the default if you use a configuration
designed for a 68020.
.Ip "\fB\-mrtd\fR" 4
.IX Item "-mrtd"
Use a different function-calling convention, in which functions
that take a fixed number of arguments return with the \f(CW\*(C`rtd\*(C'\fR
instruction, which pops their arguments while returning.  This
saves one instruction in the caller since there is no need to pop
the arguments there.
.Sp
\&\fBWarning:\fR this calling convention is incompatible with the
one normally used on Unix or with \s-1GCC\s0, so you cannot use it if you
need to call libraries compiled with the Unix compiler or with \s-1GCC\s0
without the switch.
.Sp
Also, you must provide function prototypes for all functions that
take variable numbers of arguments (including \f(CW\*(C`printf\*(C'\fR);
otherwise incorrect code will be generated for calls to those
functions.
.Sp
In addition, seriously incorrect code will result if you call a
function with too many arguments.  (Normally, extra arguments are
harmlessly ignored.)
.Sp
The \f(CW\*(C`rtd\*(C'\fR instruction is supported by the 68010, 68020, 68030,
68040, 68060 and \s-1CPU32\s0 processors, but not by the 68000 or 5200.
.Ip "\fB\-malign-int\fR" 4
.IX Item "-malign-int"
.PD 0
.Ip "\fB\-mno-align-int\fR" 4
.IX Item "-mno-align-int"
.PD
Control whether \s-1GCC\s0 aligns \f(CW\*(C`int\*(C'\fR, \f(CW\*(C`long\*(C'\fR, \f(CW\*(C`long long\*(C'\fR,
\&\f(CW\*(C`float\*(C'\fR, \f(CW\*(C`double\*(C'\fR, and \f(CW\*(C`long double\*(C'\fR variables on a 32\-bit
boundary (\fB\-malign-int\fR) or a 16\-bit boundary (\fB\-mno-align-int\fR).
Aligning variables on 32\-bit boundaries produces code that runs somewhat
faster on processors with 32\-bit busses at the expense of more memory.
.Sp
\&\fBWarning:\fR if you use the \fB\-malign-int\fR switch, \s-1GCC\s0 will
align structures containing the above types  differently than
most published application binary interface specifications for the m68k.
.Ip "\fB\-mpcrel\fR" 4
.IX Item "-mpcrel"
Use the pc-relative addressing mode of the 68000 directly, instead of
using a global offset table.  At present, this option implies \fB\-fpic\fR,
allowing at most a 16\-bit offset for pc-relative addressing.  \fB\-fPIC\fR is
not presently supported with \fB\-mpcrel\fR, though this could be supported for
68020 and higher processors.
.Ip "\fB\-mno-strict-align\fR" 4
.IX Item "-mno-strict-align"
.PD 0
.Ip "\fB\-mstrict-align\fR" 4
.IX Item "-mstrict-align"
.PD
Do not (do) assume that unaligned memory references will be handled by
the system.
.Ip "\fB\-msep-data\fR" 4
.IX Item "-msep-data"
Generate code that allows the data segment to be located in a different
area of memory from the text segment.  This allows for execute in place in
an environment without virtual memory management.  This option implies \-fPIC.
.Ip "\fB\-mno-sep-data\fR" 4
.IX Item "-mno-sep-data"
Generate code that assumes that the data segment follows the text segment.
This is the default.
.Ip "\fB\-mid-shared-library\fR" 4
.IX Item "-mid-shared-library"
Generate code that supports shared libraries via the library \s-1ID\s0 method.
This allows for execute in place and shared libraries in an environment
without virtual memory management.  This option implies \-fPIC.
.Ip "\fB\-mno-id-shared-library\fR" 4
.IX Item "-mno-id-shared-library"
Generate code that doesn't assume \s-1ID\s0 based shared libraries are being used.
This is the default.
.Ip "\fB\-mshared-library-id=n\fR" 4
.IX Item "-mshared-library-id=n"
Specified the identification number of the \s-1ID\s0 based shared library being
compiled.  Specifying a value of 0 will generate more compact code, specifying
other values will force the allocation of that number to the current
library but is no more space or time efficient than omitting this option.
.PP
.I "M68hc1x Options"
.IX Subsection "M68hc1x Options"
.PP
These are the \fB\-m\fR options defined for the 68hc11 and 68hc12
microcontrollers.  The default values for these options depends on
which style of microcontroller was selected when the compiler was configured;
the defaults for the most common choices are given below.
.Ip "\fB\-m6811\fR" 4
.IX Item "-m6811"
.PD 0
.Ip "\fB\-m68hc11\fR" 4
.IX Item "-m68hc11"
.PD
Generate output for a 68HC11.  This is the default
when the compiler is configured for 68HC11\-based systems.
.Ip "\fB\-m6812\fR" 4
.IX Item "-m6812"
.PD 0
.Ip "\fB\-m68hc12\fR" 4
.IX Item "-m68hc12"
.PD
Generate output for a 68HC12.  This is the default
when the compiler is configured for 68HC12\-based systems.
.Ip "\fB\-m68S12\fR" 4
.IX Item "-m68S12"
.PD 0
.Ip "\fB\-m68hcs12\fR" 4
.IX Item "-m68hcs12"
.PD
Generate output for a 68HCS12.
.Ip "\fB\-mauto-incdec\fR" 4
.IX Item "-mauto-incdec"
Enable the use of 68HC12 pre and post auto-increment and auto-decrement
addressing modes.
.Ip "\fB\-minmax\fR" 4
.IX Item "-minmax"
.PD 0
.Ip "\fB\-nominmax\fR" 4
.IX Item "-nominmax"
.PD
Enable the use of 68HC12 min and max instructions.
.Ip "\fB\-mlong-calls\fR" 4
.IX Item "-mlong-calls"
.PD 0
.Ip "\fB\-mno-long-calls\fR" 4
.IX Item "-mno-long-calls"
.PD
Treat all calls as being far away (near).  If calls are assumed to be
far away, the compiler will use the \f(CW\*(C`call\*(C'\fR instruction to
call a function and the \f(CW\*(C`rtc\*(C'\fR instruction for returning.
.Ip "\fB\-mshort\fR" 4
.IX Item "-mshort"
Consider type \f(CW\*(C`int\*(C'\fR to be 16 bits wide, like \f(CW\*(C`short int\*(C'\fR.
.Ip "\fB\-msoft-reg-count=\fR\fIcount\fR" 4
.IX Item "-msoft-reg-count=count"
Specify the number of pseudo-soft registers which are used for the
code generation.  The maximum number is 32.  Using more pseudo-soft
register may or may not result in better code depending on the program.
The default is 4 for 68HC11 and 2 for 68HC12.
.PP
.I "\s-1VAX\s0 Options"
.IX Subsection "VAX Options"
.PP
These \fB\-m\fR options are defined for the \s-1VAX:\s0
.Ip "\fB\-munix\fR" 4
.IX Item "-munix"
Do not output certain jump instructions (\f(CW\*(C`aobleq\*(C'\fR and so on)
that the Unix assembler for the \s-1VAX\s0 cannot handle across long
ranges.
.Ip "\fB\-mgnu\fR" 4
.IX Item "-mgnu"
Do output those jump instructions, on the assumption that you
will assemble with the \s-1GNU\s0 assembler.
.Ip "\fB\-mg\fR" 4
.IX Item "-mg"
Output code for g-format floating point numbers instead of d-format.
.PP
.I "\s-1SPARC\s0 Options"
.IX Subsection "SPARC Options"
.PP
These \fB\-m\fR options are supported on the \s-1SPARC:\s0
.Ip "\fB\-mno-app-regs\fR" 4
.IX Item "-mno-app-regs"
.PD 0
.Ip "\fB\-mapp-regs\fR" 4
.IX Item "-mapp-regs"
.PD
Specify \fB\-mapp-regs\fR to generate output using the global registers
2 through 4, which the \s-1SPARC\s0 \s-1SVR4\s0 \s-1ABI\s0 reserves for applications.  This
is the default.
.Sp
To be fully \s-1SVR4\s0 \s-1ABI\s0 compliant at the cost of some performance loss,
specify \fB\-mno-app-regs\fR.  You should compile libraries and system
software with this option.
.Ip "\fB\-mfpu\fR" 4
.IX Item "-mfpu"
.PD 0
.Ip "\fB\-mhard-float\fR" 4
.IX Item "-mhard-float"
.PD
Generate output containing floating point instructions.  This is the
default.
.Ip "\fB\-mno-fpu\fR" 4
.IX Item "-mno-fpu"
.PD 0
.Ip "\fB\-msoft-float\fR" 4
.IX Item "-msoft-float"
.PD
Generate output containing library calls for floating point.
\&\fBWarning:\fR the requisite libraries are not available for all \s-1SPARC\s0
targets.  Normally the facilities of the machine's usual C compiler are
used, but this cannot be done directly in cross-compilation.  You must make
your own arrangements to provide suitable library functions for
cross-compilation.  The embedded targets \fBsparc-*\-aout\fR and
\&\fBsparclite-*\-*\fR do provide software floating point support.
.Sp
\&\fB\-msoft-float\fR changes the calling convention in the output file;
therefore, it is only useful if you compile \fIall\fR of a program with
this option.  In particular, you need to compile \fIlibgcc.a\fR, the
library that comes with \s-1GCC\s0, with \fB\-msoft-float\fR in order for
this to work.
.Ip "\fB\-mhard-quad-float\fR" 4
.IX Item "-mhard-quad-float"
Generate output containing quad-word (long double) floating point
instructions.
.Ip "\fB\-msoft-quad-float\fR" 4
.IX Item "-msoft-quad-float"
Generate output containing library calls for quad-word (long double)
floating point instructions.  The functions called are those specified
in the \s-1SPARC\s0 \s-1ABI\s0.  This is the default.
.Sp
As of this writing, there are no \s-1SPARC\s0 implementations that have hardware
support for the quad-word floating point instructions.  They all invoke
a trap handler for one of these instructions, and then the trap handler
emulates the effect of the instruction.  Because of the trap handler overhead,
this is much slower than calling the \s-1ABI\s0 library routines.  Thus the
\&\fB\-msoft-quad-float\fR option is the default.
.Ip "\fB\-mno-flat\fR" 4
.IX Item "-mno-flat"
.PD 0
.Ip "\fB\-mflat\fR" 4
.IX Item "-mflat"
.PD
With \fB\-mflat\fR, the compiler does not generate save/restore instructions
and will use a ``flat'' or single register window calling convention.
This model uses \f(CW%i7\fR as the frame pointer and is compatible with the normal
register window model.  Code from either may be intermixed.
The local registers and the input registers (0\*(--5) are still treated as
``call saved'' registers and will be saved on the stack as necessary.
.Sp
With \fB\-mno-flat\fR (the default), the compiler emits save/restore
instructions (except for leaf functions) and is the normal mode of operation.
.Sp
These options are deprecated and will be deleted in a future \s-1GCC\s0 release.
.Ip "\fB\-mno-unaligned-doubles\fR" 4
.IX Item "-mno-unaligned-doubles"
.PD 0
.Ip "\fB\-munaligned-doubles\fR" 4
.IX Item "-munaligned-doubles"
.PD
Assume that doubles have 8 byte alignment.  This is the default.
.Sp
With \fB\-munaligned-doubles\fR, \s-1GCC\s0 assumes that doubles have 8 byte
alignment only if they are contained in another type, or if they have an
absolute address.  Otherwise, it assumes they have 4 byte alignment.
Specifying this option avoids some rare compatibility problems with code
generated by other compilers.  It is not the default because it results
in a performance loss, especially for floating point code.
.Ip "\fB\-mno-faster-structs\fR" 4
.IX Item "-mno-faster-structs"
.PD 0
.Ip "\fB\-mfaster-structs\fR" 4
.IX Item "-mfaster-structs"
.PD
With \fB\-mfaster-structs\fR, the compiler assumes that structures
should have 8 byte alignment.  This enables the use of pairs of
\&\f(CW\*(C`ldd\*(C'\fR and \f(CW\*(C`std\*(C'\fR instructions for copies in structure
assignment, in place of twice as many \f(CW\*(C`ld\*(C'\fR and \f(CW\*(C`st\*(C'\fR pairs.
However, the use of this changed alignment directly violates the \s-1SPARC\s0
\&\s-1ABI\s0.  Thus, it's intended only for use on targets where the developer
acknowledges that their resulting code will not be directly in line with
the rules of the \s-1ABI\s0.
.Ip "\fB\-mimpure-text\fR" 4
.IX Item "-mimpure-text"
\&\fB\-mimpure-text\fR, used in addition to \fB\-shared\fR, tells
the compiler to not pass \fB\-z text\fR to the linker when linking a
shared object.  Using this option, you can link position-dependent
code into a shared object.
.Sp
\&\fB\-mimpure-text\fR suppresses the ``relocations remain against
allocatable but non-writable sections'' linker error message.
However, the necessary relocations will trigger copy-on-write, and the
shared object is not actually shared across processes.  Instead of
using \fB\-mimpure-text\fR, you should compile all source code with
\&\fB\-fpic\fR or \fB\-fPIC\fR.
.Sp
This option is only available on SunOS and Solaris.
.Ip "\fB\-mv8\fR" 4
.IX Item "-mv8"
.PD 0
.Ip "\fB\-msparclite\fR" 4
.IX Item "-msparclite"
.PD
These two options select variations on the \s-1SPARC\s0 architecture.
These options are deprecated and will be deleted in a future \s-1GCC\s0 release.
They have been replaced with \fB\-mcpu=xxx\fR.
.Ip "\fB\-mcypress\fR" 4
.IX Item "-mcypress"
.PD 0
.Ip "\fB\-msupersparc\fR" 4
.IX Item "-msupersparc"
.Ip "\fB\-mf930\fR" 4
.IX Item "-mf930"
.Ip "\fB\-mf934\fR" 4
.IX Item "-mf934"
.PD
These four options select the processor for which the code is optimized.
These options are deprecated and will be deleted in a future \s-1GCC\s0 release.
They have been replaced with \fB\-mcpu=xxx\fR.
.Ip "\fB\-mcpu=\fR\fIcpu_type\fR" 4
.IX Item "-mcpu=cpu_type"
Set the instruction set, register set, and instruction scheduling parameters
for machine type \fIcpu_type\fR.  Supported values for \fIcpu_type\fR are
\&\fBv7\fR, \fBcypress\fR, \fBv8\fR, \fBsupersparc\fR, \fBsparclite\fR,
\&\fBf930\fR, \fBf934\fR, \fBhypersparc\fR, \fBsparclite86x\fR,
\&\fBsparclet\fR, \fBtsc701\fR, \fBv9\fR, \fBultrasparc\fR, and
\&\fBultrasparc3\fR.
.Sp
Default instruction scheduling parameters are used for values that select
an architecture and not an implementation.  These are \fBv7\fR, \fBv8\fR,
\&\fBsparclite\fR, \fBsparclet\fR, \fBv9\fR.
.Sp
Here is a list of each supported architecture and their supported
implementations.
.Sp
.Vb 5
\&            v7:             cypress
\&            v8:             supersparc, hypersparc
\&            sparclite:      f930, f934, sparclite86x
\&            sparclet:       tsc701
\&            v9:             ultrasparc, ultrasparc3
.Ve
By default (unless configured otherwise), \s-1GCC\s0 generates code for the V7
variant of the \s-1SPARC\s0 architecture.  With \fB\-mcpu=cypress\fR, the compiler
additionally optimizes it for the Cypress \s-1CY7C602\s0 chip, as used in the
SPARCStation/SPARCServer 3xx series.  This is also appropriate for the older
SPARCStation 1, 2, \s-1IPX\s0 etc.
.Sp
With \fB\-mcpu=v8\fR, \s-1GCC\s0 generates code for the V8 variant of the \s-1SPARC\s0
architecture.  The only difference from V7 code is that the compiler emits
the integer multiply and integer divide instructions which exist in \s-1SPARC-V8\s0
but not in \s-1SPARC-V7\s0.  With \fB\-mcpu=supersparc\fR, the compiler additionally
optimizes it for the SuperSPARC chip, as used in the SPARCStation 10, 1000 and
2000 series.
.Sp
With \fB\-mcpu=sparclite\fR, \s-1GCC\s0 generates code for the SPARClite variant of
the \s-1SPARC\s0 architecture.  This adds the integer multiply, integer divide step
and scan (\f(CW\*(C`ffs\*(C'\fR) instructions which exist in SPARClite but not in \s-1SPARC-V7\s0.
With \fB\-mcpu=f930\fR, the compiler additionally optimizes it for the
Fujitsu \s-1MB86930\s0 chip, which is the original SPARClite, with no \s-1FPU\s0.  With
\&\fB\-mcpu=f934\fR, the compiler additionally optimizes it for the Fujitsu
\&\s-1MB86934\s0 chip, which is the more recent SPARClite with \s-1FPU\s0.
.Sp
With \fB\-mcpu=sparclet\fR, \s-1GCC\s0 generates code for the SPARClet variant of
the \s-1SPARC\s0 architecture.  This adds the integer multiply, multiply/accumulate,
integer divide step and scan (\f(CW\*(C`ffs\*(C'\fR) instructions which exist in SPARClet
but not in \s-1SPARC-V7\s0.  With \fB\-mcpu=tsc701\fR, the compiler additionally
optimizes it for the \s-1TEMIC\s0 SPARClet chip.
.Sp
With \fB\-mcpu=v9\fR, \s-1GCC\s0 generates code for the V9 variant of the \s-1SPARC\s0
architecture.  This adds 64\-bit integer and floating-point move instructions,
3 additional floating-point condition code registers and conditional move
instructions.  With \fB\-mcpu=ultrasparc\fR, the compiler additionally
optimizes it for the Sun UltraSPARC I/II chips.  With
\&\fB\-mcpu=ultrasparc3\fR, the compiler additionally optimizes it for the
Sun UltraSPARC \s-1III\s0 chip.
.Ip "\fB\-mtune=\fR\fIcpu_type\fR" 4
.IX Item "-mtune=cpu_type"
Set the instruction scheduling parameters for machine type
\&\fIcpu_type\fR, but do not set the instruction set or register set that the
option \fB\-mcpu=\fR\fIcpu_type\fR would.
.Sp
The same values for \fB\-mcpu=\fR\fIcpu_type\fR can be used for
\&\fB\-mtune=\fR\fIcpu_type\fR, but the only useful values are those
that select a particular cpu implementation.  Those are \fBcypress\fR,
\&\fBsupersparc\fR, \fBhypersparc\fR, \fBf930\fR, \fBf934\fR,
\&\fBsparclite86x\fR, \fBtsc701\fR, \fBultrasparc\fR, and
\&\fBultrasparc3\fR.
.Ip "\fB\-mv8plus\fR" 4
.IX Item "-mv8plus"
.PD 0
.Ip "\fB\-mno-v8plus\fR" 4
.IX Item "-mno-v8plus"
.PD
With \fB\-mv8plus\fR, \s-1GCC\s0 generates code for the \s-1SPARC-V8+\s0 \s-1ABI\s0.  The
difference from the V8 \s-1ABI\s0 is that the global and out registers are
considered 64\-bit wide.  This is enabled by default on Solaris in 32\-bit
mode for all \s-1SPARC-V9\s0 processors.
.Ip "\fB\-mvis\fR" 4
.IX Item "-mvis"
.PD 0
.Ip "\fB\-mno-vis\fR" 4
.IX Item "-mno-vis"
.PD
With \fB\-mvis\fR, \s-1GCC\s0 generates code that takes advantage of the UltraSPARC
Visual Instruction Set extensions.  The default is \fB\-mno-vis\fR.
.PP
These \fB\-m\fR options are supported in addition to the above
on \s-1SPARC-V9\s0 processors in 64\-bit environments:
.Ip "\fB\-mlittle-endian\fR" 4
.IX Item "-mlittle-endian"
Generate code for a processor running in little-endian mode. It is only
available for a few configurations and most notably not on Solaris.
.Ip "\fB\-m32\fR" 4
.IX Item "-m32"
.PD 0
.Ip "\fB\-m64\fR" 4
.IX Item "-m64"
.PD
Generate code for a 32\-bit or 64\-bit environment.
The 32\-bit environment sets int, long and pointer to 32 bits.
The 64\-bit environment sets int to 32 bits and long and pointer
to 64 bits.
.Ip "\fB\-mcmodel=medlow\fR" 4
.IX Item "-mcmodel=medlow"
Generate code for the Medium/Low code model: 64\-bit addresses, programs
must be linked in the low 32 bits of memory.  Programs can be statically
or dynamically linked.
.Ip "\fB\-mcmodel=medmid\fR" 4
.IX Item "-mcmodel=medmid"
Generate code for the Medium/Middle code model: 64\-bit addresses, programs
must be linked in the low 44 bits of memory, the text and data segments must
be less than 2GB in size and the data segment must be located within 2GB of
the text segment.
.Ip "\fB\-mcmodel=medany\fR" 4
.IX Item "-mcmodel=medany"
Generate code for the Medium/Anywhere code model: 64\-bit addresses, programs
may be linked anywhere in memory, the text and data segments must be less
than 2GB in size and the data segment must be located within 2GB of the
text segment.
.Ip "\fB\-mcmodel=embmedany\fR" 4
.IX Item "-mcmodel=embmedany"
Generate code for the Medium/Anywhere code model for embedded systems:
64\-bit addresses, the text and data segments must be less than 2GB in
size, both starting anywhere in memory (determined at link time).  The
global register \f(CW%g4\fR points to the base of the data segment.  Programs
are statically linked and \s-1PIC\s0 is not supported.
.Ip "\fB\-mstack-bias\fR" 4
.IX Item "-mstack-bias"
.PD 0
.Ip "\fB\-mno-stack-bias\fR" 4
.IX Item "-mno-stack-bias"
.PD
With \fB\-mstack-bias\fR, \s-1GCC\s0 assumes that the stack pointer, and
frame pointer if present, are offset by \-2047 which must be added back
when making stack frame references.  This is the default in 64\-bit mode.
Otherwise, assume no such offset is present.
.PP
These switches are supported in addition to the above on Solaris:
.Ip "\fB\-threads\fR" 4
.IX Item "-threads"
Add support for multithreading using the Solaris threads library.  This
option sets flags for both the preprocessor and linker.  This option does
not affect the thread safety of object code produced by the compiler or
that of libraries supplied with it.
.Ip "\fB\-pthreads\fR" 4
.IX Item "-pthreads"
Add support for multithreading using the \s-1POSIX\s0 threads library.  This
option sets flags for both the preprocessor and linker.  This option does
not affect the thread safety of object code produced  by the compiler or
that of libraries supplied with it.
.PP
.I "\s-1ARM\s0 Options"
.IX Subsection "ARM Options"
.PP
These \fB\-m\fR options are defined for Advanced \s-1RISC\s0 Machines (\s-1ARM\s0)
architectures:
.Ip "\fB\-mapcs-frame\fR" 4
.IX Item "-mapcs-frame"
Generate a stack frame that is compliant with the \s-1ARM\s0 Procedure Call
Standard for all functions, even if this is not strictly necessary for
correct execution of the code.  Specifying \fB\-fomit-frame-pointer\fR
with this option will cause the stack frames not to be generated for
leaf functions.  The default is \fB\-mno-apcs-frame\fR.
.Ip "\fB\-mapcs\fR" 4
.IX Item "-mapcs"
This is a synonym for \fB\-mapcs-frame\fR.
.Ip "\fB\-mapcs-26\fR" 4
.IX Item "-mapcs-26"
Generate code for a processor running with a 26\-bit program counter,
and conforming to the function calling standards for the \s-1APCS\s0 26\-bit
option.
.Sp
This option is deprecated.  Future releases of the \s-1GCC\s0 will only support
generating code that runs in apcs-32 mode.
.Ip "\fB\-mapcs-32\fR" 4
.IX Item "-mapcs-32"
Generate code for a processor running with a 32\-bit program counter,
and conforming to the function calling standards for the \s-1APCS\s0 32\-bit
option.
.Sp
This flag is deprecated.  Future releases of \s-1GCC\s0 will make this flag
unconditional.
.Ip "\fB\-mthumb-interwork\fR" 4
.IX Item "-mthumb-interwork"
Generate code which supports calling between the \s-1ARM\s0 and Thumb
instruction sets.  Without this option the two instruction sets cannot
be reliably used inside one program.  The default is
\&\fB\-mno-thumb-interwork\fR, since slightly larger code is generated
when \fB\-mthumb-interwork\fR is specified.
.Ip "\fB\-mno-sched-prolog\fR" 4
.IX Item "-mno-sched-prolog"
Prevent the reordering of instructions in the function prolog, or the
merging of those instruction with the instructions in the function's
body.  This means that all functions will start with a recognizable set
of instructions (or in fact one of a choice from a small set of
different function prologues), and this information can be used to
locate the start if functions inside an executable piece of code.  The
default is \fB\-msched-prolog\fR.
.Ip "\fB\-mhard-float\fR" 4
.IX Item "-mhard-float"
Generate output containing floating point instructions.  This is the
default.
.Ip "\fB\-msoft-float\fR" 4
.IX Item "-msoft-float"
Generate output containing library calls for floating point.
\&\fBWarning:\fR the requisite libraries are not available for all \s-1ARM\s0
targets.  Normally the facilities of the machine's usual C compiler are
used, but this cannot be done directly in cross-compilation.  You must make
your own arrangements to provide suitable library functions for
cross-compilation.
.Sp
\&\fB\-msoft-float\fR changes the calling convention in the output file;
therefore, it is only useful if you compile \fIall\fR of a program with
this option.  In particular, you need to compile \fIlibgcc.a\fR, the
library that comes with \s-1GCC\s0, with \fB\-msoft-float\fR in order for
this to work.
.Ip "\fB\-mlittle-endian\fR" 4
.IX Item "-mlittle-endian"
Generate code for a processor running in little-endian mode.  This is
the default for all standard configurations.
.Ip "\fB\-mbig-endian\fR" 4
.IX Item "-mbig-endian"
Generate code for a processor running in big-endian mode; the default is
to compile code for a little-endian processor.
.Ip "\fB\-mwords-little-endian\fR" 4
.IX Item "-mwords-little-endian"
This option only applies when generating code for big-endian processors.
Generate code for a little-endian word order but a big-endian byte
order.  That is, a byte order of the form \fB32107654\fR.  Note: this
option should only be used if you require compatibility with code for
big-endian \s-1ARM\s0 processors generated by versions of the compiler prior to
2.8.
.Ip "\fB\-malignment-traps\fR" 4
.IX Item "-malignment-traps"
Generate code that will not trap if the \s-1MMU\s0 has alignment traps enabled.
On \s-1ARM\s0 architectures prior to ARMv4, there were no instructions to
access half-word objects stored in memory.  However, when reading from
memory a feature of the \s-1ARM\s0 architecture allows a word load to be used,
even if the address is unaligned, and the processor core will rotate the
data as it is being loaded.  This option tells the compiler that such
misaligned accesses will cause a \s-1MMU\s0 trap and that it should instead
synthesize the access as a series of byte accesses.  The compiler can
still use word accesses to load half-word data if it knows that the
address is aligned to a word boundary.
.Sp
This option has no effect when compiling for \s-1ARM\s0 architecture 4 or later,
since these processors have instructions to directly access half-word
objects in memory.
.Ip "\fB\-mno-alignment-traps\fR" 4
.IX Item "-mno-alignment-traps"
Generate code that assumes that the \s-1MMU\s0 will not trap unaligned
accesses.  This produces better code when the target instruction set
does not have half-word memory operations (i.e. implementations prior to
ARMv4).
.Sp
Note that you cannot use this option to access unaligned word objects,
since the processor will only fetch one 32\-bit aligned object from
memory.
.Sp
The default setting is \fB\-malignment-traps\fR, since this produces
code that will also run on processors implementing \s-1ARM\s0 architecture
version 6 or later.
.Sp
This option is deprecated and will be removed in the next release of \s-1GCC\s0.
.Ip "\fB\-mcpu=\fR\fIname\fR" 4
.IX Item "-mcpu=name"
This specifies the name of the target \s-1ARM\s0 processor.  \s-1GCC\s0 uses this name
to determine what kind of instructions it can emit when generating
assembly code.  Permissible names are: \fBarm2\fR, \fBarm250\fR,
\&\fBarm3\fR, \fBarm6\fR, \fBarm60\fR, \fBarm600\fR, \fBarm610\fR,
\&\fBarm620\fR, \fBarm7\fR, \fBarm7m\fR, \fBarm7d\fR, \fBarm7dm\fR,
\&\fBarm7di\fR, \fBarm7dmi\fR, \fBarm70\fR, \fBarm700\fR,
\&\fBarm700i\fR, \fBarm710\fR, \fBarm710c\fR, \fBarm7100\fR,
\&\fBarm7500\fR, \fBarm7500fe\fR, \fBarm7tdmi\fR, \fBarm8\fR,
\&\fBstrongarm\fR, \fBstrongarm110\fR, \fBstrongarm1100\fR,
\&\fBarm8\fR, \fBarm810\fR, \fBarm9\fR, \fBarm9e\fR, \fBarm920\fR,
\&\fBarm920t\fR, \fBarm926ejs\fR, \fBarm940t\fR, \fBarm9tdmi\fR,
\&\fBarm10tdmi\fR, \fBarm1020t\fR, \fBarm1026ejs\fR,
\&\fBarm1136js\fR, \fBarm1136jfs\fR ,\fBxscale\fR, \fBiwmmxt\fR,
\&\fBep9312\fR.
.Ip "\fB\-mtune=\fR\fIname\fR" 4
.IX Item "-mtune=name"
This option is very similar to the \fB\-mcpu=\fR option, except that
instead of specifying the actual target processor type, and hence
restricting which instructions can be used, it specifies that \s-1GCC\s0 should
tune the performance of the code as if the target were of the type
specified in this option, but still choosing the instructions that it
will generate based on the cpu specified by a \fB\-mcpu=\fR option.
For some \s-1ARM\s0 implementations better performance can be obtained by using
this option.
.Ip "\fB\-march=\fR\fIname\fR" 4
.IX Item "-march=name"
This specifies the name of the target \s-1ARM\s0 architecture.  \s-1GCC\s0 uses this
name to determine what kind of instructions it can emit when generating
assembly code.  This option can be used in conjunction with or instead
of the \fB\-mcpu=\fR option.  Permissible names are: \fBarmv2\fR,
\&\fBarmv2a\fR, \fBarmv3\fR, \fBarmv3m\fR, \fBarmv4\fR, \fBarmv4t\fR,
\&\fBarmv5\fR, \fBarmv5t\fR, \fBarmv5te\fR, \fBarmv6j\fR,
\&\fBiwmmxt\fR, \fBep9312\fR.
.Ip "\fB\-mfpe=\fR\fInumber\fR" 4
.IX Item "-mfpe=number"
.PD 0
.Ip "\fB\-mfp=\fR\fInumber\fR" 4
.IX Item "-mfp=number"
.PD
This specifies the version of the floating point emulation available on
the target.  Permissible values are 2 and 3.  \fB\-mfp=\fR is a synonym
for \fB\-mfpe=\fR, for compatibility with older versions of \s-1GCC\s0.
.Ip "\fB\-mstructure-size-boundary=\fR\fIn\fR" 4
.IX Item "-mstructure-size-boundary=n"
The size of all structures and unions will be rounded up to a multiple
of the number of bits set by this option.  Permissible values are 8 and
32.  The default value varies for different toolchains.  For the \s-1COFF\s0
targeted toolchain the default value is 8.  Specifying the larger number
can produce faster, more efficient code, but can also increase the size
of the program.  The two values are potentially incompatible.  Code
compiled with one value cannot necessarily expect to work with code or
libraries compiled with the other value, if they exchange information
using structures or unions.
.Ip "\fB\-mabort-on-noreturn\fR" 4
.IX Item "-mabort-on-noreturn"
Generate a call to the function \f(CW\*(C`abort\*(C'\fR at the end of a
\&\f(CW\*(C`noreturn\*(C'\fR function.  It will be executed if the function tries to
return.
.Ip "\fB\-mlong-calls\fR" 4
.IX Item "-mlong-calls"
.PD 0
.Ip "\fB\-mno-long-calls\fR" 4
.IX Item "-mno-long-calls"
.PD
Tells the compiler to perform function calls by first loading the
address of the function into a register and then performing a subroutine
call on this register.  This switch is needed if the target function
will lie outside of the 64 megabyte addressing range of the offset based
version of subroutine call instruction.
.Sp
Even if this switch is enabled, not all function calls will be turned
into long calls.  The heuristic is that static functions, functions
which have the \fBshort-call\fR attribute, functions that are inside
the scope of a \fB#pragma no_long_calls\fR directive and functions whose
definitions have already been compiled within the current compilation
unit, will not be turned into long calls.  The exception to this rule is
that weak function definitions, functions with the \fBlong-call\fR
attribute or the \fBsection\fR attribute, and functions that are within
the scope of a \fB#pragma long_calls\fR directive, will always be
turned into long calls.
.Sp
This feature is not enabled by default.  Specifying
\&\fB\-mno-long-calls\fR will restore the default behavior, as will
placing the function calls within the scope of a \fB#pragma
long_calls_off\fR directive.  Note these switches have no effect on how
the compiler generates code to handle function calls via function
pointers.
.Ip "\fB\-mnop-fun-dllimport\fR" 4
.IX Item "-mnop-fun-dllimport"
Disable support for the \f(CW\*(C`dllimport\*(C'\fR attribute.
.Ip "\fB\-msingle-pic-base\fR" 4
.IX Item "-msingle-pic-base"
Treat the register used for \s-1PIC\s0 addressing as read-only, rather than
loading it in the prologue for each function.  The run-time system is
responsible for initializing this register with an appropriate value
before execution begins.
.Ip "\fB\-mpic-register=\fR\fIreg\fR" 4
.IX Item "-mpic-register=reg"
Specify the register to be used for \s-1PIC\s0 addressing.  The default is R10
unless stack-checking is enabled, when R9 is used.
.Ip "\fB\-mcirrus-fix-invalid-insns\fR" 4
.IX Item "-mcirrus-fix-invalid-insns"
Insert NOPs into the instruction stream to in order to work around
problems with invalid Maverick instruction combinations.  This option
is only valid if the \fB\-mcpu=ep9312\fR option has been used to
enable generation of instructions for the Cirrus Maverick floating
point co-processor.  This option is not enabled by default, since the
problem is only present in older Maverick implementations.  The default
can be re-enabled by use of the \fB\-mno-cirrus-fix-invalid-insns\fR
switch.
.Ip "\fB\-mpoke-function-name\fR" 4
.IX Item "-mpoke-function-name"
Write the name of each function into the text section, directly
preceding the function prologue.  The generated code is similar to this:
.Sp
.Vb 9
\&             t0
\&                 .ascii "arm_poke_function_name", 0
\&                 .align
\&             t1
\&                 .word 0xff000000 + (t1 - t0)
\&             arm_poke_function_name
\&                 mov     ip, sp
\&                 stmfd   sp!, {fp, ip, lr, pc}
\&                 sub     fp, ip, #4
.Ve
When performing a stack backtrace, code can inspect the value of
\&\f(CW\*(C`pc\*(C'\fR stored at \f(CW\*(C`fp + 0\*(C'\fR.  If the trace function then looks at
location \f(CW\*(C`pc \- 12\*(C'\fR and the top 8 bits are set, then we know that
there is a function name embedded immediately preceding this location
and has length \f(CW\*(C`((pc[\-3]) & 0xff000000)\*(C'\fR.
.Ip "\fB\-mthumb\fR" 4
.IX Item "-mthumb"
Generate code for the 16\-bit Thumb instruction set.  The default is to
use the 32\-bit \s-1ARM\s0 instruction set.
.Ip "\fB\-mtpcs-frame\fR" 4
.IX Item "-mtpcs-frame"
Generate a stack frame that is compliant with the Thumb Procedure Call
Standard for all non-leaf functions.  (A leaf function is one that does
not call any other functions.)  The default is \fB\-mno-tpcs-frame\fR.
.Ip "\fB\-mtpcs-leaf-frame\fR" 4
.IX Item "-mtpcs-leaf-frame"
Generate a stack frame that is compliant with the Thumb Procedure Call
Standard for all leaf functions.  (A leaf function is one that does
not call any other functions.)  The default is \fB\-mno-apcs-leaf-frame\fR.
.Ip "\fB\-mcallee-super-interworking\fR" 4
.IX Item "-mcallee-super-interworking"
Gives all externally visible functions in the file being compiled an \s-1ARM\s0
instruction set header which switches to Thumb mode before executing the
rest of the function.  This allows these functions to be called from
non-interworking code.
.Ip "\fB\-mcaller-super-interworking\fR" 4
.IX Item "-mcaller-super-interworking"
Allows calls via function pointers (including virtual functions) to
execute correctly regardless of whether the target code has been
compiled for interworking or not.  There is a small overhead in the cost
of executing a function pointer if this option is enabled.
.PP
.I "\s-1MN10300\s0 Options"
.IX Subsection "MN10300 Options"
.PP
These \fB\-m\fR options are defined for Matsushita \s-1MN10300\s0 architectures:
.Ip "\fB\-mmult-bug\fR" 4
.IX Item "-mmult-bug"
Generate code to avoid bugs in the multiply instructions for the \s-1MN10300\s0
processors.  This is the default.
.Ip "\fB\-mno-mult-bug\fR" 4
.IX Item "-mno-mult-bug"
Do not generate code to avoid bugs in the multiply instructions for the
\&\s-1MN10300\s0 processors.
.Ip "\fB\-mam33\fR" 4
.IX Item "-mam33"
Generate code which uses features specific to the \s-1AM33\s0 processor.
.Ip "\fB\-mno-am33\fR" 4
.IX Item "-mno-am33"
Do not generate code which uses features specific to the \s-1AM33\s0 processor.  This
is the default.
.Ip "\fB\-mno-crt0\fR" 4
.IX Item "-mno-crt0"
Do not link in the C run-time initialization object file.
.Ip "\fB\-mrelax\fR" 4
.IX Item "-mrelax"
Indicate to the linker that it should perform a relaxation optimization pass
to shorten branches, calls and absolute memory addresses.  This option only
has an effect when used on the command line for the final link step.
.Sp
This option makes symbolic debugging impossible.
.PP
.I "M32R/D Options"
.IX Subsection "M32R/D Options"
.PP
These \fB\-m\fR options are defined for Renesas M32R/D architectures:
.Ip "\fB\-m32r2\fR" 4
.IX Item "-m32r2"
Generate code for the M32R/2.
.Ip "\fB\-m32rx\fR" 4
.IX Item "-m32rx"
Generate code for the M32R/X.
.Ip "\fB\-m32r\fR" 4
.IX Item "-m32r"
Generate code for the M32R.  This is the default.
.Ip "\fB\-mmodel=small\fR" 4
.IX Item "-mmodel=small"
Assume all objects live in the lower 16MB of memory (so that their addresses
can be loaded with the \f(CW\*(C`ld24\*(C'\fR instruction), and assume all subroutines
are reachable with the \f(CW\*(C`bl\*(C'\fR instruction.
This is the default.
.Sp
The addressability of a particular object can be set with the
\&\f(CW\*(C`model\*(C'\fR attribute.
.Ip "\fB\-mmodel=medium\fR" 4
.IX Item "-mmodel=medium"
Assume objects may be anywhere in the 32\-bit address space (the compiler
will generate \f(CW\*(C`seth/add3\*(C'\fR instructions to load their addresses), and
assume all subroutines are reachable with the \f(CW\*(C`bl\*(C'\fR instruction.
.Ip "\fB\-mmodel=large\fR" 4
.IX Item "-mmodel=large"
Assume objects may be anywhere in the 32\-bit address space (the compiler
will generate \f(CW\*(C`seth/add3\*(C'\fR instructions to load their addresses), and
assume subroutines may not be reachable with the \f(CW\*(C`bl\*(C'\fR instruction
(the compiler will generate the much slower \f(CW\*(C`seth/add3/jl\*(C'\fR
instruction sequence).
.Ip "\fB\-msdata=none\fR" 4
.IX Item "-msdata=none"
Disable use of the small data area.  Variables will be put into
one of \fB.data\fR, \fBbss\fR, or \fB.rodata\fR (unless the
\&\f(CW\*(C`section\*(C'\fR attribute has been specified).
This is the default.
.Sp
The small data area consists of sections \fB.sdata\fR and \fB.sbss\fR.
Objects may be explicitly put in the small data area with the
\&\f(CW\*(C`section\*(C'\fR attribute using one of these sections.
.Ip "\fB\-msdata=sdata\fR" 4
.IX Item "-msdata=sdata"
Put small global and static data in the small data area, but do not
generate special code to reference them.
.Ip "\fB\-msdata=use\fR" 4
.IX Item "-msdata=use"
Put small global and static data in the small data area, and generate
special instructions to reference them.
.Ip "\fB\-G\fR \fInum\fR" 4
.IX Item "-G num"
Put global and static objects less than or equal to \fInum\fR bytes
into the small data or bss sections instead of the normal data or bss
sections.  The default value of \fInum\fR is 8.
The \fB\-msdata\fR option must be set to one of \fBsdata\fR or \fBuse\fR
for this option to have any effect.
.Sp
All modules should be compiled with the same \fB\-G\fR \fInum\fR value.
Compiling with different values of \fInum\fR may or may not work; if it
doesn't the linker will give an error message\-\-\-incorrect code will not be
generated.
.Ip "\fB\-mdebug\fR" 4
.IX Item "-mdebug"
Makes the M32R specific code in the compiler display some statistics
that might help in debugging programs.
.Ip "\fB\-malign-loops\fR" 4
.IX Item "-malign-loops"
Align all loops to a 32\-byte boundary.
.Ip "\fB\-mno-align-loops\fR" 4
.IX Item "-mno-align-loops"
Do not enforce a 32\-byte alignment for loops.  This is the default.
.Ip "\fB\-missue-rate=\fR\fInumber\fR" 4
.IX Item "-missue-rate=number"
Issue \fInumber\fR instructions per cycle.  \fInumber\fR can only be 1
or 2.
.Ip "\fB\-mbranch-cost=\fR\fInumber\fR" 4
.IX Item "-mbranch-cost=number"
\&\fInumber\fR can only be 1 or 2.  If it is 1 then branches will be
preferred over conditional code, if it is 2, then the opposite will
apply.
.Ip "\fB\-mflush-trap=\fR\fInumber\fR" 4
.IX Item "-mflush-trap=number"
Specifies the trap number to use to flush the cache.  The default is
12.  Valid numbers are between 0 and 15 inclusive.
.Ip "\fB\-mno-flush-trap\fR" 4
.IX Item "-mno-flush-trap"
Specifies that the cache cannot be flushed by using a trap.
.Ip "\fB\-mflush-func=\fR\fIname\fR" 4
.IX Item "-mflush-func=name"
Specifies the name of the operating system function to call to flush
the cache.  The default is \fI_flush_cache\fR, but a function call
will only be used if a trap is not available.
.Ip "\fB\-mno-flush-func\fR" 4
.IX Item "-mno-flush-func"
Indicates that there is no \s-1OS\s0 function for flushing the cache.
.PP
.I "\s-1IBM\s0 \s-1RS/6000\s0 and PowerPC Options"
.IX Subsection "IBM RS/6000 and PowerPC Options"
.PP
These \fB\-m\fR options are defined for the \s-1IBM\s0 \s-1RS/6000\s0 and PowerPC:
.Ip "\fB\-mpower\fR" 4
.IX Item "-mpower"
.PD 0
.Ip "\fB\-mno-power\fR" 4
.IX Item "-mno-power"
.Ip "\fB\-mpower2\fR" 4
.IX Item "-mpower2"
.Ip "\fB\-mno-power2\fR" 4
.IX Item "-mno-power2"
.Ip "\fB\-mpowerpc\fR" 4
.IX Item "-mpowerpc"
.Ip "\fB\-mno-powerpc\fR" 4
.IX Item "-mno-powerpc"
.Ip "\fB\-mpowerpc-gpopt\fR" 4
.IX Item "-mpowerpc-gpopt"
.Ip "\fB\-mno-powerpc-gpopt\fR" 4
.IX Item "-mno-powerpc-gpopt"
.Ip "\fB\-mpowerpc-gfxopt\fR" 4
.IX Item "-mpowerpc-gfxopt"
.Ip "\fB\-mno-powerpc-gfxopt\fR" 4
.IX Item "-mno-powerpc-gfxopt"
.Ip "\fB\-mpowerpc64\fR" 4
.IX Item "-mpowerpc64"
.Ip "\fB\-mno-powerpc64\fR" 4
.IX Item "-mno-powerpc64"
.PD
\&\s-1GCC\s0 supports two related instruction set architectures for the
\&\s-1RS/6000\s0 and PowerPC.  The \fI\s-1POWER\s0\fR instruction set are those
instructions supported by the \fBrios\fR chip set used in the original
\&\s-1RS/6000\s0 systems and the \fIPowerPC\fR instruction set is the
architecture of the Motorola MPC5xx, MPC6xx, MPC8xx microprocessors, and
the \s-1IBM\s0 4xx microprocessors.
.Sp
Neither architecture is a subset of the other.  However there is a
large common subset of instructions supported by both.  An \s-1MQ\s0
register is included in processors supporting the \s-1POWER\s0 architecture.
.Sp
You use these options to specify which instructions are available on the
processor you are using.  The default value of these options is
determined when configuring \s-1GCC\s0.  Specifying the
\&\fB\-mcpu=\fR\fIcpu_type\fR overrides the specification of these
options.  We recommend you use the \fB\-mcpu=\fR\fIcpu_type\fR option
rather than the options listed above.
.Sp
The \fB\-mpower\fR option allows \s-1GCC\s0 to generate instructions that
are found only in the \s-1POWER\s0 architecture and to use the \s-1MQ\s0 register.
Specifying \fB\-mpower2\fR implies \fB\-power\fR and also allows \s-1GCC\s0
to generate instructions that are present in the \s-1POWER2\s0 architecture but
not the original \s-1POWER\s0 architecture.
.Sp
The \fB\-mpowerpc\fR option allows \s-1GCC\s0 to generate instructions that
are found only in the 32\-bit subset of the PowerPC architecture.
Specifying \fB\-mpowerpc-gpopt\fR implies \fB\-mpowerpc\fR and also allows
\&\s-1GCC\s0 to use the optional PowerPC architecture instructions in the
General Purpose group, including floating-point square root.  Specifying
\&\fB\-mpowerpc-gfxopt\fR implies \fB\-mpowerpc\fR and also allows \s-1GCC\s0 to
use the optional PowerPC architecture instructions in the Graphics
group, including floating-point select.
.Sp
The \fB\-mpowerpc64\fR option allows \s-1GCC\s0 to generate the additional
64\-bit instructions that are found in the full PowerPC64 architecture
and to treat GPRs as 64\-bit, doubleword quantities.  \s-1GCC\s0 defaults to
\&\fB\-mno-powerpc64\fR.
.Sp
If you specify both \fB\-mno-power\fR and \fB\-mno-powerpc\fR, \s-1GCC\s0
will use only the instructions in the common subset of both
architectures plus some special \s-1AIX\s0 common-mode calls, and will not use
the \s-1MQ\s0 register.  Specifying both \fB\-mpower\fR and \fB\-mpowerpc\fR
permits \s-1GCC\s0 to use any instruction from either architecture and to
allow use of the \s-1MQ\s0 register; specify this for the Motorola \s-1MPC601\s0.
.Ip "\fB\-mnew-mnemonics\fR" 4
.IX Item "-mnew-mnemonics"
.PD 0
.Ip "\fB\-mold-mnemonics\fR" 4
.IX Item "-mold-mnemonics"
.PD
Select which mnemonics to use in the generated assembler code.  With
\&\fB\-mnew-mnemonics\fR, \s-1GCC\s0 uses the assembler mnemonics defined for
the PowerPC architecture.  With \fB\-mold-mnemonics\fR it uses the
assembler mnemonics defined for the \s-1POWER\s0 architecture.  Instructions
defined in only one architecture have only one mnemonic; \s-1GCC\s0 uses that
mnemonic irrespective of which of these options is specified.
.Sp
\&\s-1GCC\s0 defaults to the mnemonics appropriate for the architecture in
use.  Specifying \fB\-mcpu=\fR\fIcpu_type\fR sometimes overrides the
value of these option.  Unless you are building a cross-compiler, you
should normally not specify either \fB\-mnew-mnemonics\fR or
\&\fB\-mold-mnemonics\fR, but should instead accept the default.
.Ip "\fB\-mcpu=\fR\fIcpu_type\fR" 4
.IX Item "-mcpu=cpu_type"
Set architecture type, register usage, choice of mnemonics, and
instruction scheduling parameters for machine type \fIcpu_type\fR.
Supported values for \fIcpu_type\fR are \fB401\fR, \fB403\fR,
\&\fB405\fR, \fB405fp\fR, \fB440\fR, \fB440fp\fR, \fB505\fR,
\&\fB601\fR, \fB602\fR, \fB603\fR, \fB603e\fR, \fB604\fR,
\&\fB604e\fR, \fB620\fR, \fB630\fR, \fB740\fR, \fB7400\fR,
\&\fB7450\fR, \fB750\fR, \fB801\fR, \fB821\fR, \fB823\fR,
\&\fB860\fR, \fB970\fR, \fBcommon\fR, \fBec603e\fR, \fBG3\fR,
\&\fBG4\fR, \fBG5\fR, \fBpower\fR, \fBpower2\fR, \fBpower3\fR,
\&\fBpower4\fR, \fBpower5\fR, \fBpowerpc\fR, \fBpowerpc64\fR,
\&\fBrios\fR, \fBrios1\fR, \fBrios2\fR, \fBrsc\fR, and \fBrs64a\fR.
.Sp
\&\fB\-mcpu=common\fR selects a completely generic processor.  Code
generated under this option will run on any \s-1POWER\s0 or PowerPC processor.
\&\s-1GCC\s0 will use only the instructions in the common subset of both
architectures, and will not use the \s-1MQ\s0 register.  \s-1GCC\s0 assumes a generic
processor model for scheduling purposes.
.Sp
\&\fB\-mcpu=power\fR, \fB\-mcpu=power2\fR, \fB\-mcpu=powerpc\fR, and
\&\fB\-mcpu=powerpc64\fR specify generic \s-1POWER\s0, \s-1POWER2\s0, pure 32\-bit
PowerPC (i.e., not \s-1MPC601\s0), and 64\-bit PowerPC architecture machine
types, with an appropriate, generic processor model assumed for
scheduling purposes.
.Sp
The other options specify a specific processor.  Code generated under
those options will run best on that processor, and may not run at all on
others.
.Sp
The \fB\-mcpu\fR options automatically enable or disable the
following options: \fB\-maltivec\fR, \fB\-mhard-float\fR,
\&\fB\-mmfcrf\fR, \fB\-mmultiple\fR, \fB\-mnew-mnemonics\fR,
\&\fB\-mpower\fR, \fB\-mpower2\fR, \fB\-mpowerpc64\fR,
\&\fB\-mpowerpc-gpopt\fR, \fB\-mpowerpc-gfxopt\fR,
\&\fB\-mstring\fR.  The particular options set for any particular \s-1CPU\s0
will vary between compiler versions, depending on what setting seems
to produce optimal code for that \s-1CPU\s0; it doesn't necessarily reflect
the actual hardware's capabilities.  If you wish to set an individual
option to a particular value, you may specify it after the
\&\fB\-mcpu\fR option, like \fB\-mcpu=970 \-mno-altivec\fR.
.Sp
On \s-1AIX\s0, the \fB\-maltivec\fR and \fB\-mpowerpc64\fR options are
not enabled or disabled by the \fB\-mcpu\fR option at present, since
\&\s-1AIX\s0 does not have full support for these options.  You may still
enable or disable them individually if you're sure it'll work in your
environment.
.Ip "\fB\-mtune=\fR\fIcpu_type\fR" 4
.IX Item "-mtune=cpu_type"
Set the instruction scheduling parameters for machine type
\&\fIcpu_type\fR, but do not set the architecture type, register usage, or
choice of mnemonics, as \fB\-mcpu=\fR\fIcpu_type\fR would.  The same
values for \fIcpu_type\fR are used for \fB\-mtune\fR as for
\&\fB\-mcpu\fR.  If both are specified, the code generated will use the
architecture, registers, and mnemonics set by \fB\-mcpu\fR, but the
scheduling parameters set by \fB\-mtune\fR.
.Ip "\fB\-maltivec\fR" 4
.IX Item "-maltivec"
.PD 0
.Ip "\fB\-mno-altivec\fR" 4
.IX Item "-mno-altivec"
.PD
These switches enable or disable the use of built-in functions that
allow access to the AltiVec instruction set.  You may also need to set
\&\fB\-mabi=altivec\fR to adjust the current \s-1ABI\s0 with AltiVec \s-1ABI\s0
enhancements.
.Ip "\fB\-mabi=spe\fR" 4
.IX Item "-mabi=spe"
Extend the current \s-1ABI\s0 with \s-1SPE\s0 \s-1ABI\s0 extensions.  This does not change
the default \s-1ABI\s0, instead it adds the \s-1SPE\s0 \s-1ABI\s0 extensions to the current
\&\s-1ABI\s0.
.Ip "\fB\-mabi=no-spe\fR" 4
.IX Item "-mabi=no-spe"
Disable Booke \s-1SPE\s0 \s-1ABI\s0 extensions for the current \s-1ABI\s0.
.Ip "\fB\-misel=\fR\fIyes/no\fR" 4
.IX Item "-misel=yes/no"
.PD 0
.Ip "\fB\-misel\fR" 4
.IX Item "-misel"
.PD
This switch enables or disables the generation of \s-1ISEL\s0 instructions.
.Ip "\fB\-mspe=\fR\fIyes/no\fR" 4
.IX Item "-mspe=yes/no"
.PD 0
.Ip "\fB\-mspe\fR" 4
.IX Item "-mspe"
.PD
This switch enables or disables the generation of \s-1SPE\s0 simd
instructions.
.Ip "\fB\-mfloat-gprs=\fR\fIyes/no\fR" 4
.IX Item "-mfloat-gprs=yes/no"
.PD 0
.Ip "\fB\-mfloat-gprs\fR" 4
.IX Item "-mfloat-gprs"
.PD
This switch enables or disables the generation of floating point
operations on the general purpose registers for architectures that
support it.  This option is currently only available on the \s-1MPC8540\s0.
.Ip "\fB\-mfull-toc\fR" 4
.IX Item "-mfull-toc"
.PD 0
.Ip "\fB\-mno-fp-in-toc\fR" 4
.IX Item "-mno-fp-in-toc"
.Ip "\fB\-mno-sum-in-toc\fR" 4
.IX Item "-mno-sum-in-toc"
.Ip "\fB\-mminimal-toc\fR" 4
.IX Item "-mminimal-toc"
.PD
Modify generation of the \s-1TOC\s0 (Table Of Contents), which is created for
every executable file.  The \fB\-mfull-toc\fR option is selected by
default.  In that case, \s-1GCC\s0 will allocate at least one \s-1TOC\s0 entry for
each unique non-automatic variable reference in your program.  \s-1GCC\s0
will also place floating-point constants in the \s-1TOC\s0.  However, only
16,384 entries are available in the \s-1TOC\s0.
.Sp
If you receive a linker error message that saying you have overflowed
the available \s-1TOC\s0 space, you can reduce the amount of \s-1TOC\s0 space used
with the \fB\-mno-fp-in-toc\fR and \fB\-mno-sum-in-toc\fR options.
\&\fB\-mno-fp-in-toc\fR prevents \s-1GCC\s0 from putting floating-point
constants in the \s-1TOC\s0 and \fB\-mno-sum-in-toc\fR forces \s-1GCC\s0 to
generate code to calculate the sum of an address and a constant at
run-time instead of putting that sum into the \s-1TOC\s0.  You may specify one
or both of these options.  Each causes \s-1GCC\s0 to produce very slightly
slower and larger code at the expense of conserving \s-1TOC\s0 space.
.Sp
If you still run out of space in the \s-1TOC\s0 even when you specify both of
these options, specify \fB\-mminimal-toc\fR instead.  This option causes
\&\s-1GCC\s0 to make only one \s-1TOC\s0 entry for every file.  When you specify this
option, \s-1GCC\s0 will produce code that is slower and larger but which
uses extremely little \s-1TOC\s0 space.  You may wish to use this option
only on files that contain less frequently executed code.
.Ip "\fB\-maix64\fR" 4
.IX Item "-maix64"
.PD 0
.Ip "\fB\-maix32\fR" 4
.IX Item "-maix32"
.PD
Enable 64\-bit \s-1AIX\s0 \s-1ABI\s0 and calling convention: 64\-bit pointers, 64\-bit
\&\f(CW\*(C`long\*(C'\fR type, and the infrastructure needed to support them.
Specifying \fB\-maix64\fR implies \fB\-mpowerpc64\fR and
\&\fB\-mpowerpc\fR, while \fB\-maix32\fR disables the 64\-bit \s-1ABI\s0 and
implies \fB\-mno-powerpc64\fR.  \s-1GCC\s0 defaults to \fB\-maix32\fR.
.Ip "\fB\-mxl-call\fR" 4
.IX Item "-mxl-call"
.PD 0
.Ip "\fB\-mno-xl-call\fR" 4
.IX Item "-mno-xl-call"
.PD
On \s-1AIX\s0, pass floating-point arguments to prototyped functions beyond the
register save area (\s-1RSA\s0) on the stack in addition to argument FPRs.  The
\&\s-1AIX\s0 calling convention was extended but not initially documented to
handle an obscure K&R C case of calling a function that takes the
address of its arguments with fewer arguments than declared.  \s-1AIX\s0 \s-1XL\s0
compilers access floating point arguments which do not fit in the
\&\s-1RSA\s0 from the stack when a subroutine is compiled without
optimization.  Because always storing floating-point arguments on the
stack is inefficient and rarely needed, this option is not enabled by
default and only is necessary when calling subroutines compiled by \s-1AIX\s0
\&\s-1XL\s0 compilers without optimization.
.Ip "\fB\-mpe\fR" 4
.IX Item "-mpe"
Support \fI\s-1IBM\s0 \s-1RS/6000\s0 \s-1SP\s0\fR \fIParallel Environment\fR (\s-1PE\s0).  Link an
application written to use message passing with special startup code to
enable the application to run.  The system must have \s-1PE\s0 installed in the
standard location (\fI/usr/lpp/ppe.poe/\fR), or the \fIspecs\fR file
must be overridden with the \fB\-specs=\fR option to specify the
appropriate directory location.  The Parallel Environment does not
support threads, so the \fB\-mpe\fR option and the \fB\-pthread\fR
option are incompatible.
.Ip "\fB\-malign-natural\fR" 4
.IX Item "-malign-natural"
.PD 0
.Ip "\fB\-malign-power\fR" 4
.IX Item "-malign-power"
.PD
On \s-1AIX\s0, Darwin, and 64\-bit PowerPC GNU/Linux, the option
\&\fB\-malign-natural\fR overrides the ABI-defined alignment of larger
types, such as floating-point doubles, on their natural size-based boundary.
The option \fB\-malign-power\fR instructs \s-1GCC\s0 to follow the ABI-specified
alignment rules.  \s-1GCC\s0 defaults to the standard alignment defined in the \s-1ABI\s0.
.Ip "\fB\-msoft-float\fR" 4
.IX Item "-msoft-float"
.PD 0
.Ip "\fB\-mhard-float\fR" 4
.IX Item "-mhard-float"
.PD
Generate code that does not use (uses) the floating-point register set.
Software floating point emulation is provided if you use the
\&\fB\-msoft-float\fR option, and pass the option to \s-1GCC\s0 when linking.
.Ip "\fB\-mmultiple\fR" 4
.IX Item "-mmultiple"
.PD 0
.Ip "\fB\-mno-multiple\fR" 4
.IX Item "-mno-multiple"
.PD
Generate code that uses (does not use) the load multiple word
instructions and the store multiple word instructions.  These
instructions are generated by default on \s-1POWER\s0 systems, and not
generated on PowerPC systems.  Do not use \fB\-mmultiple\fR on little
endian PowerPC systems, since those instructions do not work when the
processor is in little endian mode.  The exceptions are \s-1PPC740\s0 and
\&\s-1PPC750\s0 which permit the instructions usage in little endian mode.
.Ip "\fB\-mstring\fR" 4
.IX Item "-mstring"
.PD 0
.Ip "\fB\-mno-string\fR" 4
.IX Item "-mno-string"
.PD
Generate code that uses (does not use) the load string instructions
and the store string word instructions to save multiple registers and
do small block moves.  These instructions are generated by default on
\&\s-1POWER\s0 systems, and not generated on PowerPC systems.  Do not use
\&\fB\-mstring\fR on little endian PowerPC systems, since those
instructions do not work when the processor is in little endian mode.
The exceptions are \s-1PPC740\s0 and \s-1PPC750\s0 which permit the instructions
usage in little endian mode.
.Ip "\fB\-mupdate\fR" 4
.IX Item "-mupdate"
.PD 0
.Ip "\fB\-mno-update\fR" 4
.IX Item "-mno-update"
.PD
Generate code that uses (does not use) the load or store instructions
that update the base register to the address of the calculated memory
location.  These instructions are generated by default.  If you use
\&\fB\-mno-update\fR, there is a small window between the time that the
stack pointer is updated and the address of the previous frame is
stored, which means code that walks the stack frame across interrupts or
signals may get corrupted data.
.Ip "\fB\-mfused-madd\fR" 4
.IX Item "-mfused-madd"
.PD 0
.Ip "\fB\-mno-fused-madd\fR" 4
.IX Item "-mno-fused-madd"
.PD
Generate code that uses (does not use) the floating point multiply and
accumulate instructions.  These instructions are generated by default if
hardware floating is used.
.Ip "\fB\-mno-bit-align\fR" 4
.IX Item "-mno-bit-align"
.PD 0
.Ip "\fB\-mbit-align\fR" 4
.IX Item "-mbit-align"
.PD
On System V.4 and embedded PowerPC systems do not (do) force structures
and unions that contain bit-fields to be aligned to the base type of the
bit-field.
.Sp
For example, by default a structure containing nothing but 8
\&\f(CW\*(C`unsigned\*(C'\fR bit-fields of length 1 would be aligned to a 4 byte
boundary and have a size of 4 bytes.  By using \fB\-mno-bit-align\fR,
the structure would be aligned to a 1 byte boundary and be one byte in
size.
.Ip "\fB\-mno-strict-align\fR" 4
.IX Item "-mno-strict-align"
.PD 0
.Ip "\fB\-mstrict-align\fR" 4
.IX Item "-mstrict-align"
.PD
On System V.4 and embedded PowerPC systems do not (do) assume that
unaligned memory references will be handled by the system.
.Ip "\fB\-mrelocatable\fR" 4
.IX Item "-mrelocatable"
.PD 0
.Ip "\fB\-mno-relocatable\fR" 4
.IX Item "-mno-relocatable"
.PD
On embedded PowerPC systems generate code that allows (does not allow)
the program to be relocated to a different address at runtime.  If you
use \fB\-mrelocatable\fR on any module, all objects linked together must
be compiled with \fB\-mrelocatable\fR or \fB\-mrelocatable-lib\fR.
.Ip "\fB\-mrelocatable-lib\fR" 4
.IX Item "-mrelocatable-lib"
.PD 0
.Ip "\fB\-mno-relocatable-lib\fR" 4
.IX Item "-mno-relocatable-lib"
.PD
On embedded PowerPC systems generate code that allows (does not allow)
the program to be relocated to a different address at runtime.  Modules
compiled with \fB\-mrelocatable-lib\fR can be linked with either modules
compiled without \fB\-mrelocatable\fR and \fB\-mrelocatable-lib\fR or
with modules compiled with the \fB\-mrelocatable\fR options.
.Ip "\fB\-mno-toc\fR" 4
.IX Item "-mno-toc"
.PD 0
.Ip "\fB\-mtoc\fR" 4
.IX Item "-mtoc"
.PD
On System V.4 and embedded PowerPC systems do not (do) assume that
register 2 contains a pointer to a global area pointing to the addresses
used in the program.
.Ip "\fB\-mlittle\fR" 4
.IX Item "-mlittle"
.PD 0
.Ip "\fB\-mlittle-endian\fR" 4
.IX Item "-mlittle-endian"
.PD
On System V.4 and embedded PowerPC systems compile code for the
processor in little endian mode.  The \fB\-mlittle-endian\fR option is
the same as \fB\-mlittle\fR.
.Ip "\fB\-mbig\fR" 4
.IX Item "-mbig"
.PD 0
.Ip "\fB\-mbig-endian\fR" 4
.IX Item "-mbig-endian"
.PD
On System V.4 and embedded PowerPC systems compile code for the
processor in big endian mode.  The \fB\-mbig-endian\fR option is
the same as \fB\-mbig\fR.
.Ip "\fB\-mdynamic-no-pic\fR" 4
.IX Item "-mdynamic-no-pic"
On Darwin and Mac \s-1OS\s0 X systems, compile code so that it is not
relocatable, but that its external references are relocatable.  The
resulting code is suitable for applications, but not shared
libraries.
.Ip "\fB\-mprioritize-restricted-insns=\fR\fIpriority\fR" 4
.IX Item "-mprioritize-restricted-insns=priority"
This option controls the priority that is assigned to
dispatch-slot restricted instructions during the second scheduling
pass.  The argument \fIpriority\fR takes the value \fI0/1/2\fR to assign
\&\fIno/highest/second-highest\fR priority to dispatch slot restricted
instructions.
.Ip "\fB\-msched-costly-dep=\fR\fIdependence_type\fR" 4
.IX Item "-msched-costly-dep=dependence_type"
This option controls which dependences are considered costly
by the target during instruction scheduling.  The argument
\&\fIdependence_type\fR takes one of the following values:
\&\fIno\fR: no dependence is costly,
\&\fIall\fR: all dependences are costly,
\&\fItrue_store_to_load\fR: a true dependence from store to load is costly,
\&\fIstore_to_load\fR: any dependence from store to load is costly,
\&\fInumber\fR: any dependence which latency >= \fInumber\fR is costly.
.Ip "\fB\-minsert-sched-nops=\fR\fIscheme\fR" 4
.IX Item "-minsert-sched-nops=scheme"
This option controls which nop insertion scheme will be used during
the second scheduling pass. The argument \fIscheme\fR takes one of the
following values:
\&\fIno\fR: Don't insert nops.
\&\fIpad\fR: Pad with nops any dispatch group which has vacant issue slots,
according to the scheduler's grouping.
\&\fIregroup_exact\fR: Insert nops to force costly dependent insns into
separate groups.  Insert exactly as many nops as needed to force an insn
to a new group, according to the estimated processor grouping.
\&\fInumber\fR: Insert nops to force costly dependent insns into
separate groups.  Insert \fInumber\fR nops to force an insn to a new group.
.Ip "\fB\-mcall-sysv\fR" 4
.IX Item "-mcall-sysv"
On System V.4 and embedded PowerPC systems compile code using calling
conventions that adheres to the March 1995 draft of the System V
Application Binary Interface, PowerPC processor supplement.  This is the
default unless you configured \s-1GCC\s0 using \fBpowerpc-*\-eabiaix\fR.
.Ip "\fB\-mcall-sysv-eabi\fR" 4
.IX Item "-mcall-sysv-eabi"
Specify both \fB\-mcall-sysv\fR and \fB\-meabi\fR options.
.Ip "\fB\-mcall-sysv-noeabi\fR" 4
.IX Item "-mcall-sysv-noeabi"
Specify both \fB\-mcall-sysv\fR and \fB\-mno-eabi\fR options.
.Ip "\fB\-mcall-solaris\fR" 4
.IX Item "-mcall-solaris"
On System V.4 and embedded PowerPC systems compile code for the Solaris
operating system.
.Ip "\fB\-mcall-linux\fR" 4
.IX Item "-mcall-linux"
On System V.4 and embedded PowerPC systems compile code for the
Linux-based \s-1GNU\s0 system.
.Ip "\fB\-mcall-gnu\fR" 4
.IX Item "-mcall-gnu"
On System V.4 and embedded PowerPC systems compile code for the
Hurd-based \s-1GNU\s0 system.
.Ip "\fB\-mcall-netbsd\fR" 4
.IX Item "-mcall-netbsd"
On System V.4 and embedded PowerPC systems compile code for the
NetBSD operating system.
.Ip "\fB\-maix-struct-return\fR" 4
.IX Item "-maix-struct-return"
Return all structures in memory (as specified by the \s-1AIX\s0 \s-1ABI\s0).
.Ip "\fB\-msvr4\-struct-return\fR" 4
.IX Item "-msvr4-struct-return"
Return structures smaller than 8 bytes in registers (as specified by the
\&\s-1SVR4\s0 \s-1ABI\s0).
.Ip "\fB\-mabi=altivec\fR" 4
.IX Item "-mabi=altivec"
Extend the current \s-1ABI\s0 with AltiVec \s-1ABI\s0 extensions.  This does not
change the default \s-1ABI\s0, instead it adds the AltiVec \s-1ABI\s0 extensions to
the current \s-1ABI\s0.
.Ip "\fB\-mabi=no-altivec\fR" 4
.IX Item "-mabi=no-altivec"
Disable AltiVec \s-1ABI\s0 extensions for the current \s-1ABI\s0.
.Ip "\fB\-mprototype\fR" 4
.IX Item "-mprototype"
.PD 0
.Ip "\fB\-mno-prototype\fR" 4
.IX Item "-mno-prototype"
.PD
On System V.4 and embedded PowerPC systems assume that all calls to
variable argument functions are properly prototyped.  Otherwise, the
compiler must insert an instruction before every non prototyped call to
set or clear bit 6 of the condition code register (\fI\s-1CR\s0\fR) to
indicate whether floating point values were passed in the floating point
registers in case the function takes a variable arguments.  With
\&\fB\-mprototype\fR, only calls to prototyped variable argument functions
will set or clear the bit.
.Ip "\fB\-msim\fR" 4
.IX Item "-msim"
On embedded PowerPC systems, assume that the startup module is called
\&\fIsim-crt0.o\fR and that the standard C libraries are \fIlibsim.a\fR and
\&\fIlibc.a\fR.  This is the default for \fBpowerpc-*\-eabisim\fR.
configurations.
.Ip "\fB\-mmvme\fR" 4
.IX Item "-mmvme"
On embedded PowerPC systems, assume that the startup module is called
\&\fIcrt0.o\fR and the standard C libraries are \fIlibmvme.a\fR and
\&\fIlibc.a\fR.
.Ip "\fB\-mads\fR" 4
.IX Item "-mads"
On embedded PowerPC systems, assume that the startup module is called
\&\fIcrt0.o\fR and the standard C libraries are \fIlibads.a\fR and
\&\fIlibc.a\fR.
.Ip "\fB\-myellowknife\fR" 4
.IX Item "-myellowknife"
On embedded PowerPC systems, assume that the startup module is called
\&\fIcrt0.o\fR and the standard C libraries are \fIlibyk.a\fR and
\&\fIlibc.a\fR.
.Ip "\fB\-mvxworks\fR" 4
.IX Item "-mvxworks"
On System V.4 and embedded PowerPC systems, specify that you are
compiling for a VxWorks system.
.Ip "\fB\-mwindiss\fR" 4
.IX Item "-mwindiss"
Specify that you are compiling for the WindISS simulation environment.
.Ip "\fB\-memb\fR" 4
.IX Item "-memb"
On embedded PowerPC systems, set the \fI\s-1PPC_EMB\s0\fR bit in the \s-1ELF\s0 flags
header to indicate that \fBeabi\fR extended relocations are used.
.Ip "\fB\-meabi\fR" 4
.IX Item "-meabi"
.PD 0
.Ip "\fB\-mno-eabi\fR" 4
.IX Item "-mno-eabi"
.PD
On System V.4 and embedded PowerPC systems do (do not) adhere to the
Embedded Applications Binary Interface (eabi) which is a set of
modifications to the System V.4 specifications.  Selecting \fB\-meabi\fR
means that the stack is aligned to an 8 byte boundary, a function
\&\f(CW\*(C`_\|_eabi\*(C'\fR is called to from \f(CW\*(C`main\*(C'\fR to set up the eabi
environment, and the \fB\-msdata\fR option can use both \f(CW\*(C`r2\*(C'\fR and
\&\f(CW\*(C`r13\*(C'\fR to point to two separate small data areas.  Selecting
\&\fB\-mno-eabi\fR means that the stack is aligned to a 16 byte boundary,
do not call an initialization function from \f(CW\*(C`main\*(C'\fR, and the
\&\fB\-msdata\fR option will only use \f(CW\*(C`r13\*(C'\fR to point to a single
small data area.  The \fB\-meabi\fR option is on by default if you
configured \s-1GCC\s0 using one of the \fBpowerpc*\-*\-eabi*\fR options.
.Ip "\fB\-msdata=eabi\fR" 4
.IX Item "-msdata=eabi"
On System V.4 and embedded PowerPC systems, put small initialized
\&\f(CW\*(C`const\*(C'\fR global and static data in the \fB.sdata2\fR section, which
is pointed to by register \f(CW\*(C`r2\*(C'\fR.  Put small initialized
non-\f(CW\*(C`const\*(C'\fR global and static data in the \fB.sdata\fR section,
which is pointed to by register \f(CW\*(C`r13\*(C'\fR.  Put small uninitialized
global and static data in the \fB.sbss\fR section, which is adjacent to
the \fB.sdata\fR section.  The \fB\-msdata=eabi\fR option is
incompatible with the \fB\-mrelocatable\fR option.  The
\&\fB\-msdata=eabi\fR option also sets the \fB\-memb\fR option.
.Ip "\fB\-msdata=sysv\fR" 4
.IX Item "-msdata=sysv"
On System V.4 and embedded PowerPC systems, put small global and static
data in the \fB.sdata\fR section, which is pointed to by register
\&\f(CW\*(C`r13\*(C'\fR.  Put small uninitialized global and static data in the
\&\fB.sbss\fR section, which is adjacent to the \fB.sdata\fR section.
The \fB\-msdata=sysv\fR option is incompatible with the
\&\fB\-mrelocatable\fR option.
.Ip "\fB\-msdata=default\fR" 4
.IX Item "-msdata=default"
.PD 0
.Ip "\fB\-msdata\fR" 4
.IX Item "-msdata"
.PD
On System V.4 and embedded PowerPC systems, if \fB\-meabi\fR is used,
compile code the same as \fB\-msdata=eabi\fR, otherwise compile code the
same as \fB\-msdata=sysv\fR.
.Ip "\fB\-msdata-data\fR" 4
.IX Item "-msdata-data"
On System V.4 and embedded PowerPC systems, put small global and static
data in the \fB.sdata\fR section.  Put small uninitialized global and
static data in the \fB.sbss\fR section.  Do not use register \f(CW\*(C`r13\*(C'\fR
to address small data however.  This is the default behavior unless
other \fB\-msdata\fR options are used.
.Ip "\fB\-msdata=none\fR" 4
.IX Item "-msdata=none"
.PD 0
.Ip "\fB\-mno-sdata\fR" 4
.IX Item "-mno-sdata"
.PD
On embedded PowerPC systems, put all initialized global and static data
in the \fB.data\fR section, and all uninitialized data in the
\&\fB.bss\fR section.
.Ip "\fB\-G\fR \fInum\fR" 4
.IX Item "-G num"
On embedded PowerPC systems, put global and static items less than or
equal to \fInum\fR bytes into the small data or bss sections instead of
the normal data or bss section.  By default, \fInum\fR is 8.  The
\&\fB\-G\fR \fInum\fR switch is also passed to the linker.
All modules should be compiled with the same \fB\-G\fR \fInum\fR value.
.Ip "\fB\-mregnames\fR" 4
.IX Item "-mregnames"
.PD 0
.Ip "\fB\-mno-regnames\fR" 4
.IX Item "-mno-regnames"
.PD
On System V.4 and embedded PowerPC systems do (do not) emit register
names in the assembly language output using symbolic forms.
.Ip "\fB\-mlongcall\fR" 4
.IX Item "-mlongcall"
.PD 0
.Ip "\fB\-mno-longcall\fR" 4
.IX Item "-mno-longcall"
.PD
Default to making all function calls via pointers, so that functions
which reside further than 64 megabytes (67,108,864 bytes) from the
current location can be called.  This setting can be overridden by the
\&\f(CW\*(C`shortcall\*(C'\fR function attribute, or by \f(CW\*(C`#pragma longcall(0)\*(C'\fR.
.Sp
Some linkers are capable of detecting out-of-range calls and generating
glue code on the fly.  On these systems, long calls are unnecessary and
generate slower code.  As of this writing, the \s-1AIX\s0 linker can do this,
as can the \s-1GNU\s0 linker for PowerPC/64.  It is planned to add this feature
to the \s-1GNU\s0 linker for 32\-bit PowerPC systems as well.
.Sp
On Mach-O (Darwin) systems, this option directs the compiler emit to
the glue for every direct call, and the Darwin linker decides whether
to use or discard it.
.Sp
In the future, we may cause \s-1GCC\s0 to ignore all longcall specifications
when the linker is known to generate glue.
.Ip "\fB\-pthread\fR" 4
.IX Item "-pthread"
Adds support for multithreading with the \fIpthreads\fR library.
This option sets flags for both the preprocessor and linker.
.PP
.I "Darwin Options"
.IX Subsection "Darwin Options"
.PP
These options are defined for all architectures running the Darwin operating
system.  They are useful for compatibility with other Mac \s-1OS\s0 compilers.
.Ip "\fB\-all_load\fR" 4
.IX Item "-all_load"
Loads all members of static archive libraries.
See man \fIld\fR\|(1) for more information.
.Ip "\fB\-arch_errors_fatal\fR" 4
.IX Item "-arch_errors_fatal"
Cause the errors having to do with files that have the wrong architecture
to be fatal.
.Ip "\fB\-bind_at_load\fR" 4
.IX Item "-bind_at_load"
Causes the output file to be marked such that the dynamic linker will
bind all undefined references when the file is loaded or launched.
.Ip "\fB\-bundle\fR" 4
.IX Item "-bundle"
Produce a Mach-o bundle format file.
See man \fIld\fR\|(1) for more information.
.Ip "\fB\-bundle_loader\fR \fIexecutable\fR" 4
.IX Item "-bundle_loader executable"
This specifies the \fIexecutable\fR that will be loading the build
output file being linked. See man \fIld\fR\|(1) for more information.
.Ip "\fB\-allowable_client\fR  \fIclient_name\fR" 4
.IX Item "-allowable_client  client_name"
.PD 0
.Ip "\fB\-arch_only\fR" 4
.IX Item "-arch_only"
.Ip "\fB\-client_name\fR" 4
.IX Item "-client_name"
.Ip "\fB\-compatibility_version\fR" 4
.IX Item "-compatibility_version"
.Ip "\fB\-current_version\fR" 4
.IX Item "-current_version"
.Ip "\fB\-dependency-file\fR" 4
.IX Item "-dependency-file"
.Ip "\fB\-dylib_file\fR" 4
.IX Item "-dylib_file"
.Ip "\fB\-dylinker_install_name\fR" 4
.IX Item "-dylinker_install_name"
.Ip "\fB\-dynamic\fR" 4
.IX Item "-dynamic"
.Ip "\fB\-dynamiclib\fR" 4
.IX Item "-dynamiclib"
.Ip "\fB\-exported_symbols_list\fR" 4
.IX Item "-exported_symbols_list"
.Ip "\fB\-filelist\fR" 4
.IX Item "-filelist"
.Ip "\fB\-flat_namespace\fR" 4
.IX Item "-flat_namespace"
.Ip "\fB\-force_cpusubtype_ALL\fR" 4
.IX Item "-force_cpusubtype_ALL"
.Ip "\fB\-force_flat_namespace\fR" 4
.IX Item "-force_flat_namespace"
.Ip "\fB\-headerpad_max_install_names\fR" 4
.IX Item "-headerpad_max_install_names"
.Ip "\fB\-image_base\fR" 4
.IX Item "-image_base"
.Ip "\fB\-init\fR" 4
.IX Item "-init"
.Ip "\fB\-install_name\fR" 4
.IX Item "-install_name"
.Ip "\fB\-keep_private_externs\fR" 4
.IX Item "-keep_private_externs"
.Ip "\fB\-multi_module\fR" 4
.IX Item "-multi_module"
.Ip "\fB\-multiply_defined\fR" 4
.IX Item "-multiply_defined"
.Ip "\fB\-multiply_defined_unused\fR" 4
.IX Item "-multiply_defined_unused"
.Ip "\fB\-noall_load\fR" 4
.IX Item "-noall_load"
.Ip "\fB\-nofixprebinding\fR" 4
.IX Item "-nofixprebinding"
.Ip "\fB\-nomultidefs\fR" 4
.IX Item "-nomultidefs"
.Ip "\fB\-noprebind\fR" 4
.IX Item "-noprebind"
.Ip "\fB\-noseglinkedit\fR" 4
.IX Item "-noseglinkedit"
.Ip "\fB\-pagezero_size\fR" 4
.IX Item "-pagezero_size"
.Ip "\fB\-prebind\fR" 4
.IX Item "-prebind"
.Ip "\fB\-prebind_all_twolevel_modules\fR" 4
.IX Item "-prebind_all_twolevel_modules"
.Ip "\fB\-private_bundle\fR" 4
.IX Item "-private_bundle"
.Ip "\fB\-read_only_relocs\fR" 4
.IX Item "-read_only_relocs"
.Ip "\fB\-sectalign\fR" 4
.IX Item "-sectalign"
.Ip "\fB\-sectobjectsymbols\fR" 4
.IX Item "-sectobjectsymbols"
.Ip "\fB\-whyload\fR" 4
.IX Item "-whyload"
.Ip "\fB\-seg1addr\fR" 4
.IX Item "-seg1addr"
.Ip "\fB\-sectcreate\fR" 4
.IX Item "-sectcreate"
.Ip "\fB\-sectobjectsymbols\fR" 4
.IX Item "-sectobjectsymbols"
.Ip "\fB\-sectorder\fR" 4
.IX Item "-sectorder"
.Ip "\fB\-seg_addr_table\fR" 4
.IX Item "-seg_addr_table"
.Ip "\fB\-seg_addr_table_filename\fR" 4
.IX Item "-seg_addr_table_filename"
.Ip "\fB\-seglinkedit\fR" 4
.IX Item "-seglinkedit"
.Ip "\fB\-segprot\fR" 4
.IX Item "-segprot"
.Ip "\fB\-segs_read_only_addr\fR" 4
.IX Item "-segs_read_only_addr"
.Ip "\fB\-segs_read_write_addr\fR" 4
.IX Item "-segs_read_write_addr"
.Ip "\fB\-single_module\fR" 4
.IX Item "-single_module"
.Ip "\fB\-static\fR" 4
.IX Item "-static"
.Ip "\fB\-sub_library\fR" 4
.IX Item "-sub_library"
.Ip "\fB\-sub_umbrella\fR" 4
.IX Item "-sub_umbrella"
.Ip "\fB\-twolevel_namespace\fR" 4
.IX Item "-twolevel_namespace"
.Ip "\fB\-umbrella\fR" 4
.IX Item "-umbrella"
.Ip "\fB\-undefined\fR" 4
.IX Item "-undefined"
.Ip "\fB\-unexported_symbols_list\fR" 4
.IX Item "-unexported_symbols_list"
.Ip "\fB\-weak_reference_mismatches\fR" 4
.IX Item "-weak_reference_mismatches"
.Ip "\fB\-whatsloaded\fR" 4
.IX Item "-whatsloaded"
.PD
These options are available for Darwin linker. Darwin linker man page
describes them in detail.
.PP
.I "\s-1MIPS\s0 Options"
.IX Subsection "MIPS Options"
.Ip "\fB\-EB\fR" 4
.IX Item "-EB"
Generate big-endian code.
.Ip "\fB\-EL\fR" 4
.IX Item "-EL"
Generate little-endian code.  This is the default for \fBmips*el-*\-*\fR
configurations.
.Ip "\fB\-march=\fR\fIarch\fR" 4
.IX Item "-march=arch"
Generate code that will run on \fIarch\fR, which can be the name of a
generic \s-1MIPS\s0 \s-1ISA\s0, or the name of a particular processor.
The \s-1ISA\s0 names are:
\&\fBmips1\fR, \fBmips2\fR, \fBmips3\fR, \fBmips4\fR,
\&\fBmips32\fR, \fBmips32r2\fR, and \fBmips64\fR.
The processor names are:
\&\fB4kc\fR, \fB4kp\fR, \fB5kc\fR, \fB20kc\fR,
\&\fBm4k\fR,
\&\fBr2000\fR, \fBr3000\fR, \fBr3900\fR, \fBr4000\fR, \fBr4400\fR,
\&\fBr4600\fR, \fBr4650\fR, \fBr6000\fR, \fBr8000\fR, \fBrm7000\fR,
\&\fBrm9000\fR,
\&\fBorion\fR,
\&\fBsb1\fR,
\&\fBvr4100\fR, \fBvr4111\fR, \fBvr4120\fR, \fBvr4300\fR,
\&\fBvr5000\fR, \fBvr5400\fR and \fBvr5500\fR.
The special value \fBfrom-abi\fR selects the
most compatible architecture for the selected \s-1ABI\s0 (that is,
\&\fBmips1\fR for 32\-bit ABIs and \fBmips3\fR for 64\-bit ABIs).
.Sp
In processor names, a final \fB000\fR can be abbreviated as \fBk\fR
(for example, \fB\-march=r2k\fR).  Prefixes are optional, and
\&\fBvr\fR may be written \fBr\fR.
.Sp
\&\s-1GCC\s0 defines two macros based on the value of this option.  The first
is \fB_MIPS_ARCH\fR, which gives the name of target architecture, as
a string.  The second has the form \fB_MIPS_ARCH_\fR\fIfoo\fR,
where \fIfoo\fR is the capitalized value of \fB_MIPS_ARCH\fR.
For example, \fB\-march=r2000\fR will set \fB_MIPS_ARCH\fR
to \fB\*(L"r2000\*(R"\fR and define the macro \fB_MIPS_ARCH_R2000\fR.
.Sp
Note that the \fB_MIPS_ARCH\fR macro uses the processor names given
above.  In other words, it will have the full prefix and will not
abbreviate \fB000\fR as \fBk\fR.  In the case of \fBfrom-abi\fR,
the macro names the resolved architecture (either \fB\*(L"mips1\*(R"\fR or
\&\fB\*(L"mips3\*(R"\fR).  It names the default architecture when no
\&\fB\-march\fR option is given.
.Ip "\fB\-mtune=\fR\fIarch\fR" 4
.IX Item "-mtune=arch"
Optimize for \fIarch\fR.  Among other things, this option controls
the way instructions are scheduled, and the perceived cost of arithmetic
operations.  The list of \fIarch\fR values is the same as for
\&\fB\-march\fR.
.Sp
When this option is not used, \s-1GCC\s0 will optimize for the processor
specified by \fB\-march\fR.  By using \fB\-march\fR and
\&\fB\-mtune\fR together, it is possible to generate code that will
run on a family of processors, but optimize the code for one
particular member of that family.
.Sp
\&\fB\-mtune\fR defines the macros \fB_MIPS_TUNE\fR and
\&\fB_MIPS_TUNE_\fR\fIfoo\fR, which work in the same way as the
\&\fB\-march\fR ones described above.
.Ip "\fB\-mips1\fR" 4
.IX Item "-mips1"
Equivalent to \fB\-march=mips1\fR.
.Ip "\fB\-mips2\fR" 4
.IX Item "-mips2"
Equivalent to \fB\-march=mips2\fR.
.Ip "\fB\-mips3\fR" 4
.IX Item "-mips3"
Equivalent to \fB\-march=mips3\fR.
.Ip "\fB\-mips4\fR" 4
.IX Item "-mips4"
Equivalent to \fB\-march=mips4\fR.
.Ip "\fB\-mips32\fR" 4
.IX Item "-mips32"
Equivalent to \fB\-march=mips32\fR.
.Ip "\fB\-mips32r2\fR" 4
.IX Item "-mips32r2"
Equivalent to \fB\-march=mips32r2\fR.
.Ip "\fB\-mips64\fR" 4
.IX Item "-mips64"
Equivalent to \fB\-march=mips64\fR.
.Ip "\fB\-mips16\fR" 4
.IX Item "-mips16"
.PD 0
.Ip "\fB\-mno-mips16\fR" 4
.IX Item "-mno-mips16"
.PD
Use (do not use) the \s-1MIPS16\s0 \s-1ISA\s0.
.Ip "\fB\-mabi=32\fR" 4
.IX Item "-mabi=32"
.PD 0
.Ip "\fB\-mabi=o64\fR" 4
.IX Item "-mabi=o64"
.Ip "\fB\-mabi=n32\fR" 4
.IX Item "-mabi=n32"
.Ip "\fB\-mabi=64\fR" 4
.IX Item "-mabi=64"
.Ip "\fB\-mabi=eabi\fR" 4
.IX Item "-mabi=eabi"
.PD
Generate code for the given \s-1ABI\s0.
.Sp
Note that the \s-1EABI\s0 has a 32\-bit and a 64\-bit variant.  \s-1GCC\s0 normally
generates 64\-bit code when you select a 64\-bit architecture, but you
can use \fB\-mgp32\fR to get 32\-bit code instead.
.Ip "\fB\-mabicalls\fR" 4
.IX Item "-mabicalls"
.PD 0
.Ip "\fB\-mno-abicalls\fR" 4
.IX Item "-mno-abicalls"
.PD
Generate (do not generate) SVR4\-style position-independent code.
\&\fB\-mabicalls\fR is the default for SVR4\-based systems.
.Ip "\fB\-mxgot\fR" 4
.IX Item "-mxgot"
.PD 0
.Ip "\fB\-mno-xgot\fR" 4
.IX Item "-mno-xgot"
.PD
Lift (do not lift) the usual restrictions on the size of the global
offset table.
.Sp
\&\s-1GCC\s0 normally uses a single instruction to load values from the \s-1GOT\s0.
While this is relatively efficient, it will only work if the \s-1GOT\s0
is smaller than about 64k.  Anything larger will cause the linker
to report an error such as:
.Sp
.Vb 1
\&        relocation truncated to fit: R_MIPS_GOT16 foobar
.Ve
If this happens, you should recompile your code with \fB\-mxgot\fR.
It should then work with very large GOTs, although it will also be
less efficient, since it will take three instructions to fetch the
value of a global symbol.
.Sp
Note that some linkers can create multiple GOTs.  If you have such a
linker, you should only need to use \fB\-mxgot\fR when a single object
file accesses more than 64k's worth of \s-1GOT\s0 entries.  Very few do.
.Sp
These options have no effect unless \s-1GCC\s0 is generating position
independent code.
.Ip "\fB\-membedded-pic\fR" 4
.IX Item "-membedded-pic"
.PD 0
.Ip "\fB\-mno-embedded-pic\fR" 4
.IX Item "-mno-embedded-pic"
.PD
Generate (do not generate) position-independent code suitable for some
embedded systems.  All calls are made using \s-1PC\s0 relative addresses, and
all data is addressed using the \f(CW$gp\fR register.  No more than 65536
bytes of global data may be used.  This requires \s-1GNU\s0 as and \s-1GNU\s0 ld,
which do most of the work.
.Ip "\fB\-mgp32\fR" 4
.IX Item "-mgp32"
Assume that general-purpose registers are 32 bits wide.
.Ip "\fB\-mgp64\fR" 4
.IX Item "-mgp64"
Assume that general-purpose registers are 64 bits wide.
.Ip "\fB\-mfp32\fR" 4
.IX Item "-mfp32"
Assume that floating-point registers are 32 bits wide.
.Ip "\fB\-mfp64\fR" 4
.IX Item "-mfp64"
Assume that floating-point registers are 64 bits wide.
.Ip "\fB\-mhard-float\fR" 4
.IX Item "-mhard-float"
Use floating-point coprocessor instructions.
.Ip "\fB\-msoft-float\fR" 4
.IX Item "-msoft-float"
Do not use floating-point coprocessor instructions.  Implement
floating-point calculations using library calls instead.
.Ip "\fB\-msingle-float\fR" 4
.IX Item "-msingle-float"
Assume that the floating-point coprocessor only supports single-precision
operations.
.Ip "\fB\-mdouble-float\fR" 4
.IX Item "-mdouble-float"
Assume that the floating-point coprocessor supports double-precision
operations.  This is the default.
.Ip "\fB\-mint64\fR" 4
.IX Item "-mint64"
Force \f(CW\*(C`int\*(C'\fR and \f(CW\*(C`long\*(C'\fR types to be 64 bits wide.  See
\&\fB\-mlong32\fR for an explanation of the default and the way
that the pointer size is determined.
.Ip "\fB\-mlong64\fR" 4
.IX Item "-mlong64"
Force \f(CW\*(C`long\*(C'\fR types to be 64 bits wide.  See \fB\-mlong32\fR for
an explanation of the default and the way that the pointer size is
determined.
.Ip "\fB\-mlong32\fR" 4
.IX Item "-mlong32"
Force \f(CW\*(C`long\*(C'\fR, \f(CW\*(C`int\*(C'\fR, and pointer types to be 32 bits wide.
.Sp
The default size of \f(CW\*(C`int\*(C'\fRs, \f(CW\*(C`long\*(C'\fRs and pointers depends on
the \s-1ABI\s0.  All the supported ABIs use 32\-bit \f(CW\*(C`int\*(C'\fRs.  The n64 \s-1ABI\s0
uses 64\-bit \f(CW\*(C`long\*(C'\fRs, as does the 64\-bit \s-1EABI\s0; the others use
32\-bit \f(CW\*(C`long\*(C'\fRs.  Pointers are the same size as \f(CW\*(C`long\*(C'\fRs,
or the same size as integer registers, whichever is smaller.
.Ip "\fB\-G\fR \fInum\fR" 4
.IX Item "-G num"
Put global and static items less than or equal to \fInum\fR bytes into
the small data or bss section instead of the normal data or bss section.
This allows the data to be accessed using a single instruction.
.Sp
All modules should be compiled with the same \fB\-G\fR \fInum\fR
value.
.Ip "\fB\-membedded-data\fR" 4
.IX Item "-membedded-data"
.PD 0
.Ip "\fB\-mno-embedded-data\fR" 4
.IX Item "-mno-embedded-data"
.PD
Allocate variables to the read-only data section first if possible, then
next in the small data section if possible, otherwise in data.  This gives
slightly slower code than the default, but reduces the amount of \s-1RAM\s0 required
when executing, and thus may be preferred for some embedded systems.
.Ip "\fB\-muninit-const-in-rodata\fR" 4
.IX Item "-muninit-const-in-rodata"
.PD 0
.Ip "\fB\-mno-uninit-const-in-rodata\fR" 4
.IX Item "-mno-uninit-const-in-rodata"
.PD
Put uninitialized \f(CW\*(C`const\*(C'\fR variables in the read-only data section.
This option is only meaningful in conjunction with \fB\-membedded-data\fR.
.Ip "\fB\-msplit-addresses\fR" 4
.IX Item "-msplit-addresses"
.PD 0
.Ip "\fB\-mno-split-addresses\fR" 4
.IX Item "-mno-split-addresses"
.PD
Enable (disable) use of the \f(CW\*(C`%hi()\*(C'\fR and \f(CW\*(C`%lo()\*(C'\fR assembler
relocation operators.  This option has been superceded by
\&\fB\-mexplicit-relocs\fR but is retained for backwards compatibility.
.Ip "\fB\-mexplicit-relocs\fR" 4
.IX Item "-mexplicit-relocs"
.PD 0
.Ip "\fB\-mno-explicit-relocs\fR" 4
.IX Item "-mno-explicit-relocs"
.PD
Use (do not use) assembler relocation operators when dealing with symbolic
addresses.  The alternative, selected by \fB\-mno-explicit-relocs\fR,
is to use assembler macros instead.
.Sp
\&\fB\-mexplicit-relocs\fR is usually the default if \s-1GCC\s0 was
configured to use an assembler that supports relocation operators.
However, there are two exceptions:
.RS 4
.Ip "\(bu" 4
\&\s-1GCC\s0 is not yet able to generate explicit relocations for the combination
of \fB\-mabi=64\fR and \fB\-mno-abicalls\fR.  This will be addressed
in a future release.
.Ip "\(bu" 4
The combination of \fB\-mabicalls\fR and \fB\-fno-unit-at-a-time\fR
implies \fB\-mno-explicit-relocs\fR unless explicitly overridden.
This is because, when generating abicalls, the choice of relocation
depends on whether a symbol is local or global.  In some rare cases,
\&\s-1GCC\s0 will not be able to decide this until the whole compilation unit
has been read.
.RE
.RS 4
.RE
.Ip "\fB\-mrnames\fR" 4
.IX Item "-mrnames"
.PD 0
.Ip "\fB\-mno-rnames\fR" 4
.IX Item "-mno-rnames"
.PD
Generate (do not generate) code that refers to registers using their
software names.  The default is \fB\-mno-rnames\fR, which tells \s-1GCC\s0
to use hardware names like \fB$4\fR instead of software names like
\&\fBa0\fR.  The only assembler known to support \fB\-rnames\fR is
the Algorithmics assembler.
.Ip "\fB\-mcheck-zero-division\fR" 4
.IX Item "-mcheck-zero-division"
.PD 0
.Ip "\fB\-mno-check-zero-division\fR" 4
.IX Item "-mno-check-zero-division"
.PD
Trap (do not trap) on integer division by zero.  The default is
\&\fB\-mcheck-zero-division\fR.
.Ip "\fB\-mmemcpy\fR" 4
.IX Item "-mmemcpy"
.PD 0
.Ip "\fB\-mno-memcpy\fR" 4
.IX Item "-mno-memcpy"
.PD
Force (do not force) the use of \f(CW\*(C`memcpy()\*(C'\fR for non-trivial block
moves.  The default is \fB\-mno-memcpy\fR, which allows \s-1GCC\s0 to inline
most constant-sized copies.
.Ip "\fB\-mlong-calls\fR" 4
.IX Item "-mlong-calls"
.PD 0
.Ip "\fB\-mno-long-calls\fR" 4
.IX Item "-mno-long-calls"
.PD
Disable (do not disable) use of the \f(CW\*(C`jal\*(C'\fR instruction.  Calling
functions using \f(CW\*(C`jal\*(C'\fR is more efficient but requires the caller
and callee to be in the same 256 megabyte segment.
.Sp
This option has no effect on abicalls code.  The default is
\&\fB\-mno-long-calls\fR.
.Ip "\fB\-mmad\fR" 4
.IX Item "-mmad"
.PD 0
.Ip "\fB\-mno-mad\fR" 4
.IX Item "-mno-mad"
.PD
Enable (disable) use of the \f(CW\*(C`mad\*(C'\fR, \f(CW\*(C`madu\*(C'\fR and \f(CW\*(C`mul\*(C'\fR
instructions, as provided by the R4650 \s-1ISA\s0.
.Ip "\fB\-mfused-madd\fR" 4
.IX Item "-mfused-madd"
.PD 0
.Ip "\fB\-mno-fused-madd\fR" 4
.IX Item "-mno-fused-madd"
.PD
Enable (disable) use of the floating point multiply-accumulate
instructions, when they are available.  The default is
\&\fB\-mfused-madd\fR.
.Sp
When multiply-accumulate instructions are used, the intermediate
product is calculated to infinite precision and is not subject to
the \s-1FCSR\s0 Flush to Zero bit.  This may be undesirable in some
circumstances.
.Ip "\fB\-nocpp\fR" 4
.IX Item "-nocpp"
Tell the \s-1MIPS\s0 assembler to not run its preprocessor over user
assembler files (with a \fB.s\fR suffix) when assembling them.
.Ip "\fB\-mfix-sb1\fR" 4
.IX Item "-mfix-sb1"
.PD 0
.Ip "\fB\-mno-fix-sb1\fR" 4
.IX Item "-mno-fix-sb1"
.PD
Work around certain \s-1SB-1\s0 \s-1CPU\s0 core errata.
(This flag currently works around the \s-1SB-1\s0 revision 2
``F1'' and ``F2'' floating point errata.)
.Ip "\fB\-mflush-func=\fR\fIfunc\fR" 4
.IX Item "-mflush-func=func"
.PD 0
.Ip "\fB\-mno-flush-func\fR" 4
.IX Item "-mno-flush-func"
.PD
Specifies the function to call to flush the I and D caches, or to not
call any such function.  If called, the function must take the same
arguments as the common \f(CW\*(C`_flush_func()\*(C'\fR, that is, the address of the
memory range for which the cache is being flushed, the size of the
memory range, and the number 3 (to flush both caches).  The default
depends on the target \s-1GCC\s0 was configured for, but commonly is either
\&\fB_flush_func\fR or \fB_\|_cpu_flush\fR.
.Ip "\fB\-mbranch-likely\fR" 4
.IX Item "-mbranch-likely"
.PD 0
.Ip "\fB\-mno-branch-likely\fR" 4
.IX Item "-mno-branch-likely"
.PD
Enable or disable use of Branch Likely instructions, regardless of the
default for the selected architecture.  By default, Branch Likely
instructions may be generated if they are supported by the selected
architecture.  An exception is for the \s-1MIPS32\s0 and \s-1MIPS64\s0 architectures
and processors which implement those architectures; for those, Branch
Likely instructions will not be generated by default because the \s-1MIPS32\s0
and \s-1MIPS64\s0 architectures specifically deprecate their use.
.PP
.I "Intel 386 and \s-1AMD\s0 x86\-64 Options"
.IX Subsection "Intel 386 and AMD x86-64 Options"
.PP
These \fB\-m\fR options are defined for the i386 and x86\-64 family of
computers:
.Ip "\fB\-mtune=\fR\fIcpu-type\fR" 4
.IX Item "-mtune=cpu-type"
Tune to \fIcpu-type\fR everything applicable about the generated code, except
for the \s-1ABI\s0 and the set of available instructions.  The choices for
\&\fIcpu-type\fR are:
.RS 4
.Ip "\fIi386\fR" 4
.IX Item "i386"
Original Intel's i386 \s-1CPU\s0.
.Ip "\fIi486\fR" 4
.IX Item "i486"
Intel's i486 \s-1CPU\s0.  (No scheduling is implemented for this chip.)
.Ip "\fIi586, pentium\fR" 4
.IX Item "i586, pentium"
Intel Pentium \s-1CPU\s0 with no \s-1MMX\s0 support.
.Ip "\fIpentium-mmx\fR" 4
.IX Item "pentium-mmx"
Intel PentiumMMX \s-1CPU\s0 based on Pentium core with \s-1MMX\s0 instruction set support.
.Ip "\fIi686, pentiumpro\fR" 4
.IX Item "i686, pentiumpro"
Intel PentiumPro \s-1CPU\s0.
.Ip "\fIpentium2\fR" 4
.IX Item "pentium2"
Intel Pentium2 \s-1CPU\s0 based on PentiumPro core with \s-1MMX\s0 instruction set support.
.Ip "\fIpentium3, pentium3m\fR" 4
.IX Item "pentium3, pentium3m"
Intel Pentium3 \s-1CPU\s0 based on PentiumPro core with \s-1MMX\s0 and \s-1SSE\s0 instruction set
support.
.Ip "\fIpentium-m\fR" 4
.IX Item "pentium-m"
Low power version of Intel Pentium3 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0 and \s-1SSE2\s0 instruction set
support.  Used by Centrino notebooks.
.Ip "\fIpentium4, pentium4m\fR" 4
.IX Item "pentium4, pentium4m"
Intel Pentium4 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0 and \s-1SSE2\s0 instruction set support.
.Ip "\fIprescott\fR" 4
.IX Item "prescott"
Improved version of Intel Pentium4 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0 and \s-1SSE3\s0 instruction
set support.
.Ip "\fInocona\fR" 4
.IX Item "nocona"
Improved version of Intel Pentium4 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0,
\&\s-1SSE2\s0 and \s-1SSE3\s0 instruction set support.
.Ip "\fIk6\fR" 4
.IX Item "k6"
\&\s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 instruction set support.
.Ip "\fIk6\-2, k6\-3\fR" 4
.IX Item "k6-2, k6-3"
Improved versions of \s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 and 3dNOW! instruction set support.
.Ip "\fIathlon, athlon-tbird\fR" 4
.IX Item "athlon, athlon-tbird"
\&\s-1AMD\s0 Athlon \s-1CPU\s0 with \s-1MMX\s0, 3dNOW!, enhanced 3dNOW! and \s-1SSE\s0 prefetch instructions
support.
.Ip "\fIathlon-4, athlon-xp, athlon-mp\fR" 4
.IX Item "athlon-4, athlon-xp, athlon-mp"
Improved \s-1AMD\s0 Athlon \s-1CPU\s0 with \s-1MMX\s0, 3dNOW!, enhanced 3dNOW! and full \s-1SSE\s0
instruction set support.
.Ip "\fIk8, opteron, athlon64, athlon-fx\fR" 4
.IX Item "k8, opteron, athlon64, athlon-fx"
\&\s-1AMD\s0 K8 core based CPUs with x86\-64 instruction set support.  (This supersets
\&\s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, 3dNOW!, enhanced 3dNOW! and 64\-bit instruction set extensions.)
.Ip "\fIwinchip-c6\fR" 4
.IX Item "winchip-c6"
\&\s-1IDT\s0 Winchip C6 \s-1CPU\s0, dealt in same way as i486 with additional \s-1MMX\s0 instruction
set support.
.Ip "\fIwinchip2\fR" 4
.IX Item "winchip2"
\&\s-1IDT\s0 Winchip2 \s-1CPU\s0, dealt in same way as i486 with additional \s-1MMX\s0 and 3dNOW!
instruction set support.
.Ip "\fIc3\fR" 4
.IX Item "c3"
Via C3 \s-1CPU\s0 with \s-1MMX\s0 and 3dNOW!  instruction set support.  (No scheduling is
implemented for this chip.)
.Ip "\fIc3\-2\fR" 4
.IX Item "c3-2"
Via C3\-2 \s-1CPU\s0 with \s-1MMX\s0 and \s-1SSE\s0 instruction set support.  (No scheduling is
implemented for this chip.)
.RE
.RS 4
.Sp
While picking a specific \fIcpu-type\fR will schedule things appropriately
for that particular chip, the compiler will not generate any code that
does not run on the i386 without the \fB\-march=\fR\fIcpu-type\fR option
being used.
.RE
.Ip "\fB\-march=\fR\fIcpu-type\fR" 4
.IX Item "-march=cpu-type"
Generate instructions for the machine type \fIcpu-type\fR.  The choices
for \fIcpu-type\fR are the same as for \fB\-mtune\fR.  Moreover,
specifying \fB\-march=\fR\fIcpu-type\fR implies \fB\-mtune=\fR\fIcpu-type\fR.
.Ip "\fB\-mcpu=\fR\fIcpu-type\fR" 4
.IX Item "-mcpu=cpu-type"
A deprecated synonym for \fB\-mtune\fR.
.Ip "\fB\-m386\fR" 4
.IX Item "-m386"
.PD 0
.Ip "\fB\-m486\fR" 4
.IX Item "-m486"
.Ip "\fB\-mpentium\fR" 4
.IX Item "-mpentium"
.Ip "\fB\-mpentiumpro\fR" 4
.IX Item "-mpentiumpro"
.PD
These options are synonyms for \fB\-mtune=i386\fR, \fB\-mtune=i486\fR,
\&\fB\-mtune=pentium\fR, and \fB\-mtune=pentiumpro\fR respectively.
These synonyms are deprecated.
.Ip "\fB\-mfpmath=\fR\fIunit\fR" 4
.IX Item "-mfpmath=unit"
Generate floating point arithmetics for selected unit \fIunit\fR.  The choices
for \fIunit\fR are:
.RS 4
.Ip "\fB387\fR" 4
.IX Item "387"
Use the standard 387 floating point coprocessor present majority of chips and
emulated otherwise.  Code compiled with this option will run almost everywhere.
The temporary results are computed in 80bit precision instead of precision
specified by the type resulting in slightly different results compared to most
of other chips. See \fB\-ffloat-store\fR for more detailed description.
.Sp
This is the default choice for i386 compiler.
.Ip "\fBsse\fR" 4
.IX Item "sse"
Use scalar floating point instructions present in the \s-1SSE\s0 instruction set.
This instruction set is supported by Pentium3 and newer chips, in the \s-1AMD\s0 line
by Athlon-4, Athlon-xp and Athlon-mp chips.  The earlier version of \s-1SSE\s0
instruction set supports only single precision arithmetics, thus the double and
extended precision arithmetics is still done using 387.  Later version, present
only in Pentium4 and the future \s-1AMD\s0 x86\-64 chips supports double precision
arithmetics too.
.Sp
For i387 you need to use \fB\-march=\fR\fIcpu-type\fR, \fB\-msse\fR or
\&\fB\-msse2\fR switches to enable \s-1SSE\s0 extensions and make this option
effective.  For x86\-64 compiler, these extensions are enabled by default.
.Sp
The resulting code should be considerably faster in the majority of cases and avoid
the numerical instability problems of 387 code, but may break some existing
code that expects temporaries to be 80bit.
.Sp
This is the default choice for the x86\-64 compiler.
.Ip "\fBsse,387\fR" 4
.IX Item "sse,387"
Attempt to utilize both instruction sets at once.  This effectively double the
amount of available registers and on chips with separate execution units for
387 and \s-1SSE\s0 the execution resources too.  Use this option with care, as it is
still experimental, because the \s-1GCC\s0 register allocator does not model separate
functional units well resulting in instable performance.
.RE
.RS 4
.RE
.Ip "\fB\-masm=\fR\fIdialect\fR" 4
.IX Item "-masm=dialect"
Output asm instructions using selected \fIdialect\fR. Supported choices are
\&\fBintel\fR or \fBatt\fR (the default one).
.Ip "\fB\-mieee-fp\fR" 4
.IX Item "-mieee-fp"
.PD 0
.Ip "\fB\-mno-ieee-fp\fR" 4
.IX Item "-mno-ieee-fp"
.PD
Control whether or not the compiler uses \s-1IEEE\s0 floating point
comparisons.  These handle correctly the case where the result of a
comparison is unordered.
.Ip "\fB\-msoft-float\fR" 4
.IX Item "-msoft-float"
Generate output containing library calls for floating point.
\&\fBWarning:\fR the requisite libraries are not part of \s-1GCC\s0.
Normally the facilities of the machine's usual C compiler are used, but
this can't be done directly in cross-compilation.  You must make your
own arrangements to provide suitable library functions for
cross-compilation.
.Sp
On machines where a function returns floating point results in the 80387
register stack, some floating point opcodes may be emitted even if
\&\fB\-msoft-float\fR is used.
.Ip "\fB\-mno-fp-ret-in-387\fR" 4
.IX Item "-mno-fp-ret-in-387"
Do not use the \s-1FPU\s0 registers for return values of functions.
.Sp
The usual calling convention has functions return values of types
\&\f(CW\*(C`float\*(C'\fR and \f(CW\*(C`double\*(C'\fR in an \s-1FPU\s0 register, even if there
is no \s-1FPU\s0.  The idea is that the operating system should emulate
an \s-1FPU\s0.
.Sp
The option \fB\-mno-fp-ret-in-387\fR causes such values to be returned
in ordinary \s-1CPU\s0 registers instead.
.Ip "\fB\-mno-fancy-math-387\fR" 4
.IX Item "-mno-fancy-math-387"
Some 387 emulators do not support the \f(CW\*(C`sin\*(C'\fR, \f(CW\*(C`cos\*(C'\fR and
\&\f(CW\*(C`sqrt\*(C'\fR instructions for the 387.  Specify this option to avoid
generating those instructions.  This option is the default on FreeBSD,
OpenBSD and NetBSD.  This option is overridden when \fB\-march\fR
indicates that the target cpu will always have an \s-1FPU\s0 and so the
instruction will not need emulation.  As of revision 2.6.1, these
instructions are not generated unless you also use the
\&\fB\-funsafe-math-optimizations\fR switch.
.Ip "\fB\-malign-double\fR" 4
.IX Item "-malign-double"
.PD 0
.Ip "\fB\-mno-align-double\fR" 4
.IX Item "-mno-align-double"
.PD
Control whether \s-1GCC\s0 aligns \f(CW\*(C`double\*(C'\fR, \f(CW\*(C`long double\*(C'\fR, and
\&\f(CW\*(C`long long\*(C'\fR variables on a two word boundary or a one word
boundary.  Aligning \f(CW\*(C`double\*(C'\fR variables on a two word boundary will
produce code that runs somewhat faster on a \fBPentium\fR at the
expense of more memory.
.Sp
\&\fBWarning:\fR if you use the \fB\-malign-double\fR switch,
structures containing the above types will be aligned differently than
the published application binary interface specifications for the 386
and will not be binary compatible with structures in code compiled
without that switch.
.Ip "\fB\-m96bit-long-double\fR" 4
.IX Item "-m96bit-long-double"
.PD 0
.Ip "\fB\-m128bit-long-double\fR" 4
.IX Item "-m128bit-long-double"
.PD
These switches control the size of \f(CW\*(C`long double\*(C'\fR type. The i386
application binary interface specifies the size to be 96 bits,
so \fB\-m96bit-long-double\fR is the default in 32 bit mode.
.Sp
Modern architectures (Pentium and newer) would prefer \f(CW\*(C`long double\*(C'\fR
to be aligned to an 8 or 16 byte boundary.  In arrays or structures
conforming to the \s-1ABI\s0, this would not be possible.  So specifying a
\&\fB\-m128bit-long-double\fR will align \f(CW\*(C`long double\*(C'\fR
to a 16 byte boundary by padding the \f(CW\*(C`long double\*(C'\fR with an additional
32 bit zero.
.Sp
In the x86\-64 compiler, \fB\-m128bit-long-double\fR is the default choice as
its \s-1ABI\s0 specifies that \f(CW\*(C`long double\*(C'\fR is to be aligned on 16 byte boundary.
.Sp
Notice that neither of these options enable any extra precision over the x87
standard of 80 bits for a \f(CW\*(C`long double\*(C'\fR.
.Sp
\&\fBWarning:\fR if you override the default value for your target \s-1ABI\s0, the
structures and arrays containing \f(CW\*(C`long double\*(C'\fR variables will change
their size as well as function calling convention for function taking
\&\f(CW\*(C`long double\*(C'\fR will be modified.  Hence they will not be binary
compatible with arrays or structures in code compiled without that switch.
.Ip "\fB\-msvr3\-shlib\fR" 4
.IX Item "-msvr3-shlib"
.PD 0
.Ip "\fB\-mno-svr3\-shlib\fR" 4
.IX Item "-mno-svr3-shlib"
.PD
Control whether \s-1GCC\s0 places uninitialized local variables into the
\&\f(CW\*(C`bss\*(C'\fR or \f(CW\*(C`data\*(C'\fR segments.  \fB\-msvr3\-shlib\fR places them
into \f(CW\*(C`bss\*(C'\fR.  These options are meaningful only on System V Release 3.
.Ip "\fB\-mrtd\fR" 4
.IX Item "-mrtd"
Use a different function-calling convention, in which functions that
take a fixed number of arguments return with the \f(CW\*(C`ret\*(C'\fR \fInum\fR
instruction, which pops their arguments while returning.  This saves one
instruction in the caller since there is no need to pop the arguments
there.
.Sp
You can specify that an individual function is called with this calling
sequence with the function attribute \fBstdcall\fR.  You can also
override the \fB\-mrtd\fR option by using the function attribute
\&\fBcdecl\fR.  
.Sp
\&\fBWarning:\fR this calling convention is incompatible with the one
normally used on Unix, so you cannot use it if you need to call
libraries compiled with the Unix compiler.
.Sp
Also, you must provide function prototypes for all functions that
take variable numbers of arguments (including \f(CW\*(C`printf\*(C'\fR);
otherwise incorrect code will be generated for calls to those
functions.
.Sp
In addition, seriously incorrect code will result if you call a
function with too many arguments.  (Normally, extra arguments are
harmlessly ignored.)
.Ip "\fB\-mregparm=\fR\fInum\fR" 4
.IX Item "-mregparm=num"
Control how many registers are used to pass integer arguments.  By
default, no registers are used to pass arguments, and at most 3
registers can be used.  You can control this behavior for a specific
function by using the function attribute \fBregparm\fR.
.Sp
\&\fBWarning:\fR if you use this switch, and
\&\fInum\fR is nonzero, then you must build all modules with the same
value, including any libraries.  This includes the system libraries and
startup modules.
.Ip "\fB\-mpreferred-stack-boundary=\fR\fInum\fR" 4
.IX Item "-mpreferred-stack-boundary=num"
Attempt to keep the stack boundary aligned to a 2 raised to \fInum\fR
byte boundary.  If \fB\-mpreferred-stack-boundary\fR is not specified,
the default is 4 (16 bytes or 128 bits), except when optimizing for code
size (\fB\-Os\fR), in which case the default is the minimum correct
alignment (4 bytes for x86, and 8 bytes for x86\-64).
.Sp
On Pentium and PentiumPro, \f(CW\*(C`double\*(C'\fR and \f(CW\*(C`long double\*(C'\fR values
should be aligned to an 8 byte boundary (see \fB\-malign-double\fR) or
suffer significant run time performance penalties.  On Pentium \s-1III\s0, the
Streaming \s-1SIMD\s0 Extension (\s-1SSE\s0) data type \f(CW\*(C`_\|_m128\*(C'\fR suffers similar
penalties if it is not 16 byte aligned.
.Sp
To ensure proper alignment of this values on the stack, the stack boundary
must be as aligned as that required by any value stored on the stack.
Further, every function must be generated such that it keeps the stack
aligned.  Thus calling a function compiled with a higher preferred
stack boundary from a function compiled with a lower preferred stack
boundary will most likely misalign the stack.  It is recommended that
libraries that use callbacks always use the default setting.
.Sp
This extra alignment does consume extra stack space, and generally
increases code size.  Code that is sensitive to stack space usage, such
as embedded systems and operating system kernels, may want to reduce the
preferred alignment to \fB\-mpreferred-stack-boundary=2\fR.
.Ip "\fB\-mmmx\fR" 4
.IX Item "-mmmx"
.PD 0
.Ip "\fB\-mno-mmx\fR" 4
.IX Item "-mno-mmx"
.Ip "\fB\-msse\fR" 4
.IX Item "-msse"
.Ip "\fB\-mno-sse\fR" 4
.IX Item "-mno-sse"
.Ip "\fB\-msse2\fR" 4
.IX Item "-msse2"
.Ip "\fB\-mno-sse2\fR" 4
.IX Item "-mno-sse2"
.Ip "\fB\-msse3\fR" 4
.IX Item "-msse3"
.Ip "\fB\-mno-sse3\fR" 4
.IX Item "-mno-sse3"
.Ip "\fB\-m3dnow\fR" 4
.IX Item "-m3dnow"
.Ip "\fB\-mno-3dnow\fR" 4
.IX Item "-mno-3dnow"
.PD
These switches enable or disable the use of built-in functions that allow
direct access to the \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0 and 3Dnow extensions of the
instruction set.
.Sp
To have \s-1SSE/SSE2\s0 instructions generated automatically from floating-point
code, see \fB\-mfpmath=sse\fR.
.Ip "\fB\-mpush-args\fR" 4
.IX Item "-mpush-args"
.PD 0
.Ip "\fB\-mno-push-args\fR" 4
.IX Item "-mno-push-args"
.PD
Use \s-1PUSH\s0 operations to store outgoing parameters.  This method is shorter
and usually equally fast as method using \s-1SUB/MOV\s0 operations and is enabled
by default.  In some cases disabling it may improve performance because of
improved scheduling and reduced dependencies.
.Ip "\fB\-maccumulate-outgoing-args\fR" 4
.IX Item "-maccumulate-outgoing-args"
If enabled, the maximum amount of space required for outgoing arguments will be
computed in the function prologue.  This is faster on most modern CPUs
because of reduced dependencies, improved scheduling and reduced stack usage
when preferred stack boundary is not equal to 2.  The drawback is a notable
increase in code size.  This switch implies \fB\-mno-push-args\fR.
.Ip "\fB\-mthreads\fR" 4
.IX Item "-mthreads"
Support thread-safe exception handling on \fBMingw32\fR.  Code that relies
on thread-safe exception handling must compile and link all code with the
\&\fB\-mthreads\fR option.  When compiling, \fB\-mthreads\fR defines
\&\fB\-D_MT\fR; when linking, it links in a special thread helper library
\&\fB\-lmingwthrd\fR which cleans up per thread exception handling data.
.Ip "\fB\-mno-align-stringops\fR" 4
.IX Item "-mno-align-stringops"
Do not align destination of inlined string operations.  This switch reduces
code size and improves performance in case the destination is already aligned,
but \s-1GCC\s0 doesn't know about it.
.Ip "\fB\-minline-all-stringops\fR" 4
.IX Item "-minline-all-stringops"
By default \s-1GCC\s0 inlines string operations only when destination is known to be
aligned at least to 4 byte boundary.  This enables more inlining, increase code
size, but may improve performance of code that depends on fast memcpy, strlen
and memset for short lengths.
.Ip "\fB\-momit-leaf-frame-pointer\fR" 4
.IX Item "-momit-leaf-frame-pointer"
Don't keep the frame pointer in a register for leaf functions.  This
avoids the instructions to save, set up and restore frame pointers and
makes an extra register available in leaf functions.  The option
\&\fB\-fomit-frame-pointer\fR removes the frame pointer for all functions
which might make debugging harder.
.Ip "\fB\-mtls-direct-seg-refs\fR" 4
.IX Item "-mtls-direct-seg-refs"
.PD 0
.Ip "\fB\-mno-tls-direct-seg-refs\fR" 4
.IX Item "-mno-tls-direct-seg-refs"
.PD
Controls whether \s-1TLS\s0 variables may be accessed with offsets from the
\&\s-1TLS\s0 segment register (\f(CW\*(C`%gs\*(C'\fR for 32\-bit, \f(CW\*(C`%fs\*(C'\fR for 64\-bit),
or whether the thread base pointer must be added.  Whether or not this
is legal depends on the operating system, and whether it maps the
segment to cover the entire \s-1TLS\s0 area.
.Sp
For systems that use \s-1GNU\s0 libc, the default is on.
.PP
These \fB\-m\fR switches are supported in addition to the above
on \s-1AMD\s0 x86\-64 processors in 64\-bit environments.
.Ip "\fB\-m32\fR" 4
.IX Item "-m32"
.PD 0
.Ip "\fB\-m64\fR" 4
.IX Item "-m64"
.PD
Generate code for a 32\-bit or 64\-bit environment.
The 32\-bit environment sets int, long and pointer to 32 bits and
generates code that runs on any i386 system.
The 64\-bit environment sets int to 32 bits and long and pointer
to 64 bits and generates code for \s-1AMD\s0's x86\-64 architecture.
.Ip "\fB\-mno-red-zone\fR" 4
.IX Item "-mno-red-zone"
Do not use a so called red zone for x86\-64 code.  The red zone is mandated
by the x86\-64 \s-1ABI\s0, it is a 128\-byte area beyond the location of the
stack pointer that will not be modified by signal or interrupt handlers
and therefore can be used for temporary data without adjusting the stack
pointer.  The flag \fB\-mno-red-zone\fR disables this red zone.
.Ip "\fB\-mcmodel=small\fR" 4
.IX Item "-mcmodel=small"
Generate code for the small code model: the program and its symbols must
be linked in the lower 2 \s-1GB\s0 of the address space.  Pointers are 64 bits.
Programs can be statically or dynamically linked.  This is the default
code model.
.Ip "\fB\-mcmodel=kernel\fR" 4
.IX Item "-mcmodel=kernel"
Generate code for the kernel code model.  The kernel runs in the
negative 2 \s-1GB\s0 of the address space.
This model has to be used for Linux kernel code.
.Ip "\fB\-mcmodel=medium\fR" 4
.IX Item "-mcmodel=medium"
Generate code for the medium model: The program is linked in the lower 2
\&\s-1GB\s0 of the address space but symbols can be located anywhere in the
address space.  Programs can be statically or dynamically linked, but
building of shared libraries are not supported with the medium model.
.Ip "\fB\-mcmodel=large\fR" 4
.IX Item "-mcmodel=large"
Generate code for the large model: This model makes no assumptions
about addresses and sizes of sections.  Currently \s-1GCC\s0 does not implement
this model.
.Ip "\fB\-mstack-arg-probe\fR" 4
.IX Item "-mstack-arg-probe"
Emit code in function prologue to probe the stack when allocating more
than \s-1CHECK_STACK_LIMIT\s0 bytes in one go. 
.Sp
Currently, this is the default on windows systems (cygwin and mingw32),
which define \s-1CHECK_STACK_LIMIT\s0 as 4000. On these systems, touching the
stack at 4K increments is necessary to ensure that the guard pages used
by the \s-1OS\s0 virtual memory manger are allocated in correct sequence.
.PP
.I "\s-1HPPA\s0 Options"
.IX Subsection "HPPA Options"
.PP
These \fB\-m\fR options are defined for the \s-1HPPA\s0 family of computers:
.Ip "\fB\-march=\fR\fIarchitecture-type\fR" 4
.IX Item "-march=architecture-type"
Generate code for the specified architecture.  The choices for
\&\fIarchitecture-type\fR are \fB1.0\fR for \s-1PA\s0 1.0, \fB1.1\fR for \s-1PA\s0
1.1, and \fB2.0\fR for \s-1PA\s0 2.0 processors.  Refer to
\&\fI/usr/lib/sched.models\fR on an \s-1HP-UX\s0 system to determine the proper
architecture option for your machine.  Code compiled for lower numbered
architectures will run on higher numbered architectures, but not the
other way around.
.Sp
\&\s-1PA\s0 2.0 support currently requires gas snapshot 19990413 or later.  The
next release of binutils (current is 2.9.1) will probably contain \s-1PA\s0 2.0
support.
.Ip "\fB\-mpa-risc-1\-0\fR" 4
.IX Item "-mpa-risc-1-0"
.PD 0
.Ip "\fB\-mpa-risc-1\-1\fR" 4
.IX Item "-mpa-risc-1-1"
.Ip "\fB\-mpa-risc-2\-0\fR" 4
.IX Item "-mpa-risc-2-0"
.PD
Synonyms for \fB\-march=1.0\fR, \fB\-march=1.1\fR, and \fB\-march=2.0\fR respectively.
.Ip "\fB\-mbig-switch\fR" 4
.IX Item "-mbig-switch"
Generate code suitable for big switch tables.  Use this option only if
the assembler/linker complain about out of range branches within a switch
table.
.Ip "\fB\-mjump-in-delay\fR" 4
.IX Item "-mjump-in-delay"
Fill delay slots of function calls with unconditional jump instructions
by modifying the return pointer for the function call to be the target
of the conditional jump.
.Ip "\fB\-mdisable-fpregs\fR" 4
.IX Item "-mdisable-fpregs"
Prevent floating point registers from being used in any manner.  This is
necessary for compiling kernels which perform lazy context switching of
floating point registers.  If you use this option and attempt to perform
floating point operations, the compiler will abort.
.Ip "\fB\-mdisable-indexing\fR" 4
.IX Item "-mdisable-indexing"
Prevent the compiler from using indexing address modes.  This avoids some
rather obscure problems when compiling \s-1MIG\s0 generated code under \s-1MACH\s0.
.Ip "\fB\-mno-space-regs\fR" 4
.IX Item "-mno-space-regs"
Generate code that assumes the target has no space registers.  This allows
\&\s-1GCC\s0 to generate faster indirect calls and use unscaled index address modes.
.Sp
Such code is suitable for level 0 \s-1PA\s0 systems and kernels.
.Ip "\fB\-mfast-indirect-calls\fR" 4
.IX Item "-mfast-indirect-calls"
Generate code that assumes calls never cross space boundaries.  This
allows \s-1GCC\s0 to emit code which performs faster indirect calls.
.Sp
This option will not work in the presence of shared libraries or nested
functions.
.Ip "\fB\-mlong-load-store\fR" 4
.IX Item "-mlong-load-store"
Generate 3\-instruction load and store sequences as sometimes required by
the \s-1HP-UX\s0 10 linker.  This is equivalent to the \fB+k\fR option to
the \s-1HP\s0 compilers.
.Ip "\fB\-mportable-runtime\fR" 4
.IX Item "-mportable-runtime"
Use the portable calling conventions proposed by \s-1HP\s0 for \s-1ELF\s0 systems.
.Ip "\fB\-mgas\fR" 4
.IX Item "-mgas"
Enable the use of assembler directives only \s-1GAS\s0 understands.
.Ip "\fB\-mschedule=\fR\fIcpu-type\fR" 4
.IX Item "-mschedule=cpu-type"
Schedule code according to the constraints for the machine type
\&\fIcpu-type\fR.  The choices for \fIcpu-type\fR are \fB700\fR
\&\fB7100\fR, \fB7100LC\fR, \fB7200\fR, \fB7300\fR and \fB8000\fR.  Refer
to \fI/usr/lib/sched.models\fR on an \s-1HP-UX\s0 system to determine the
proper scheduling option for your machine.  The default scheduling is
\&\fB8000\fR.
.Ip "\fB\-mlinker-opt\fR" 4
.IX Item "-mlinker-opt"
Enable the optimization pass in the \s-1HP-UX\s0 linker.  Note this makes symbolic
debugging impossible.  It also triggers a bug in the \s-1HP-UX\s0 8 and \s-1HP-UX\s0 9
linkers in which they give bogus error messages when linking some programs.
.Ip "\fB\-msoft-float\fR" 4
.IX Item "-msoft-float"
Generate output containing library calls for floating point.
\&\fBWarning:\fR the requisite libraries are not available for all \s-1HPPA\s0
targets.  Normally the facilities of the machine's usual C compiler are
used, but this cannot be done directly in cross-compilation.  You must make
your own arrangements to provide suitable library functions for
cross-compilation.  The embedded target \fBhppa1.1\-*\-pro\fR
does provide software floating point support.
.Sp
\&\fB\-msoft-float\fR changes the calling convention in the output file;
therefore, it is only useful if you compile \fIall\fR of a program with
this option.  In particular, you need to compile \fIlibgcc.a\fR, the
library that comes with \s-1GCC\s0, with \fB\-msoft-float\fR in order for
this to work.
.Ip "\fB\-msio\fR" 4
.IX Item "-msio"
Generate the predefine, \f(CW\*(C`_SIO\*(C'\fR, for server \s-1IO\s0.  The default is
\&\fB\-mwsio\fR.  This generates the predefines, \f(CW\*(C`_\|_hp9000s700\*(C'\fR,
\&\f(CW\*(C`_\|_hp9000s700_\|_\*(C'\fR and \f(CW\*(C`_WSIO\*(C'\fR, for workstation \s-1IO\s0.  These
options are available under \s-1HP-UX\s0 and \s-1HI-UX\s0.
.Ip "\fB\-mgnu-ld\fR" 4
.IX Item "-mgnu-ld"
Use \s-1GNU\s0 ld specific options.  This passes \fB\-shared\fR to ld when
building a shared library.  It is the default when \s-1GCC\s0 is configured,
explicitly or implicitly, with the \s-1GNU\s0 linker.  This option does not
have any affect on which ld is called, it only changes what parameters
are passed to that ld.  The ld that is called is determined by the
\&\fB\*(--with-ld\fR configure option, \s-1GCC\s0's program search path, and
finally by the user's \fB\s-1PATH\s0\fR.  The linker used by \s-1GCC\s0 can be printed
using \fBwhich `gcc \-print-prog-name=ld`\fR.
.Ip "\fB\-mhp-ld\fR" 4
.IX Item "-mhp-ld"
Use \s-1HP\s0 ld specific options.  This passes \fB\-b\fR to ld when building
a shared library and passes \fB+Accept TypeMismatch\fR to ld on all
links.  It is the default when \s-1GCC\s0 is configured, explicitly or
implicitly, with the \s-1HP\s0 linker.  This option does not have any affect on
which ld is called, it only changes what parameters are passed to that
ld.  The ld that is called is determined by the \fB\*(--with-ld\fR
configure option, \s-1GCC\s0's program search path, and finally by the user's
\&\fB\s-1PATH\s0\fR.  The linker used by \s-1GCC\s0 can be printed using \fBwhich
`gcc \-print-prog-name=ld`\fR.
.Ip "\fB\-mlong-calls\fR" 4
.IX Item "-mlong-calls"
Generate code that uses long call sequences.  This ensures that a call
is always able to reach linker generated stubs.  The default is to generate
long calls only when the distance from the call site to the beginning
of the function or translation unit, as the case may be, exceeds a
predefined limit set by the branch type being used.  The limits for
normal calls are 7,600,000 and 240,000 bytes, respectively for the
\&\s-1PA\s0 2.0 and \s-1PA\s0 1.X architectures.  Sibcalls are always limited at
240,000 bytes.
.Sp
Distances are measured from the beginning of functions when using the
\&\fB\-ffunction-sections\fR option, or when using the \fB\-mgas\fR
and \fB\-mno-portable-runtime\fR options together under \s-1HP-UX\s0 with
the \s-1SOM\s0 linker.
.Sp
It is normally not desirable to use this option as it will degrade
performance.  However, it may be useful in large applications,
particularly when partial linking is used to build the application.
.Sp
The types of long calls used depends on the capabilities of the
assembler and linker, and the type of code being generated.  The
impact on systems that support long absolute calls, and long pic
symbol-difference or pc-relative calls should be relatively small.
However, an indirect call is used on 32\-bit \s-1ELF\s0 systems in pic code
and it is quite long.
.Ip "\fB\-nolibdld\fR" 4
.IX Item "-nolibdld"
Suppress the generation of link options to search libdld.sl when the
\&\fB\-static\fR option is specified on \s-1HP-UX\s0 10 and later.
.Ip "\fB\-static\fR" 4
.IX Item "-static"
The \s-1HP-UX\s0 implementation of setlocale in libc has a dependency on
libdld.sl.  There isn't an archive version of libdld.sl.  Thus,
when the \fB\-static\fR option is specified, special link options
are needed to resolve this dependency.
.Sp
On \s-1HP-UX\s0 10 and later, the \s-1GCC\s0 driver adds the necessary options to
link with libdld.sl when the \fB\-static\fR option is specified.
This causes the resulting binary to be dynamic.  On the 64\-bit port,
the linkers generate dynamic binaries by default in any case.  The
\&\fB\-nolibdld\fR option can be used to prevent the \s-1GCC\s0 driver from
adding these link options.
.Ip "\fB\-threads\fR" 4
.IX Item "-threads"
Add support for multithreading with the \fIdce thread\fR library
under \s-1HP-UX\s0.  This option sets flags for both the preprocessor and
linker.
.PP
.I "Intel 960 Options"
.IX Subsection "Intel 960 Options"
.PP
These \fB\-m\fR options are defined for the Intel 960 implementations:
.Ip "\fB\-m\fR\fIcpu-type\fR" 4
.IX Item "-mcpu-type"
Assume the defaults for the machine type \fIcpu-type\fR for some of
the other options, including instruction scheduling, floating point
support, and addressing modes.  The choices for \fIcpu-type\fR are
\&\fBka\fR, \fBkb\fR, \fBmc\fR, \fBca\fR, \fBcf\fR,
\&\fBsa\fR, and \fBsb\fR.
The default is
\&\fBkb\fR.
.Ip "\fB\-mnumerics\fR" 4
.IX Item "-mnumerics"
.PD 0
.Ip "\fB\-msoft-float\fR" 4
.IX Item "-msoft-float"
.PD
The \fB\-mnumerics\fR option indicates that the processor does support
floating-point instructions.  The \fB\-msoft-float\fR option indicates
that floating-point support should not be assumed.
.Ip "\fB\-mleaf-procedures\fR" 4
.IX Item "-mleaf-procedures"
.PD 0
.Ip "\fB\-mno-leaf-procedures\fR" 4
.IX Item "-mno-leaf-procedures"
.PD
Do (or do not) attempt to alter leaf procedures to be callable with the
\&\f(CW\*(C`bal\*(C'\fR instruction as well as \f(CW\*(C`call\*(C'\fR.  This will result in more
efficient code for explicit calls when the \f(CW\*(C`bal\*(C'\fR instruction can be
substituted by the assembler or linker, but less efficient code in other
cases, such as calls via function pointers, or using a linker that doesn't
support this optimization.
.Ip "\fB\-mtail-call\fR" 4
.IX Item "-mtail-call"
.PD 0
.Ip "\fB\-mno-tail-call\fR" 4
.IX Item "-mno-tail-call"
.PD
Do (or do not) make additional attempts (beyond those of the
machine-independent portions of the compiler) to optimize tail-recursive
calls into branches.  You may not want to do this because the detection of
cases where this is not valid is not totally complete.  The default is
\&\fB\-mno-tail-call\fR.
.Ip "\fB\-mcomplex-addr\fR" 4
.IX Item "-mcomplex-addr"
.PD 0
.Ip "\fB\-mno-complex-addr\fR" 4
.IX Item "-mno-complex-addr"
.PD
Assume (or do not assume) that the use of a complex addressing mode is a
win on this implementation of the i960.  Complex addressing modes may not
be worthwhile on the K-series, but they definitely are on the C-series.
The default is currently \fB\-mcomplex-addr\fR for all processors except
the \s-1CB\s0 and \s-1CC\s0.
.Ip "\fB\-mcode-align\fR" 4
.IX Item "-mcode-align"
.PD 0
.Ip "\fB\-mno-code-align\fR" 4
.IX Item "-mno-code-align"
.PD
Align code to 8\-byte boundaries for faster fetching (or don't bother).
Currently turned on by default for C-series implementations only.
.Ip "\fB\-mic-compat\fR" 4
.IX Item "-mic-compat"
.PD 0
.Ip "\fB\-mic2.0\-compat\fR" 4
.IX Item "-mic2.0-compat"
.Ip "\fB\-mic3.0\-compat\fR" 4
.IX Item "-mic3.0-compat"
.PD
Enable compatibility with iC960 v2.0 or v3.0.
.Ip "\fB\-masm-compat\fR" 4
.IX Item "-masm-compat"
.PD 0
.Ip "\fB\-mintel-asm\fR" 4
.IX Item "-mintel-asm"
.PD
Enable compatibility with the iC960 assembler.
.Ip "\fB\-mstrict-align\fR" 4
.IX Item "-mstrict-align"
.PD 0
.Ip "\fB\-mno-strict-align\fR" 4
.IX Item "-mno-strict-align"
.PD
Do not permit (do permit) unaligned accesses.
.Ip "\fB\-mold-align\fR" 4
.IX Item "-mold-align"
Enable structure-alignment compatibility with Intel's gcc release version
1.3 (based on gcc 1.37).  This option implies \fB\-mstrict-align\fR.
.Ip "\fB\-mlong-double-64\fR" 4
.IX Item "-mlong-double-64"
Implement type \fBlong double\fR as 64\-bit floating point numbers.
Without the option \fBlong double\fR is implemented by 80\-bit
floating point numbers.  The only reason we have it because there is
no 128\-bit \fBlong double\fR support in \fBfp-bit.c\fR yet.  So it
is only useful for people using soft-float targets.  Otherwise, we
should recommend against use of it.
.PP
.I "\s-1DEC\s0 Alpha Options"
.IX Subsection "DEC Alpha Options"
.PP
These \fB\-m\fR options are defined for the \s-1DEC\s0 Alpha implementations:
.Ip "\fB\-mno-soft-float\fR" 4
.IX Item "-mno-soft-float"
.PD 0
.Ip "\fB\-msoft-float\fR" 4
.IX Item "-msoft-float"
.PD
Use (do not use) the hardware floating-point instructions for
floating-point operations.  When \fB\-msoft-float\fR is specified,
functions in \fIlibgcc.a\fR will be used to perform floating-point
operations.  Unless they are replaced by routines that emulate the
floating-point operations, or compiled in such a way as to call such
emulations routines, these routines will issue floating-point
operations.   If you are compiling for an Alpha without floating-point
operations, you must ensure that the library is built so as not to call
them.
.Sp
Note that Alpha implementations without floating-point operations are
required to have floating-point registers.
.Ip "\fB\-mfp-reg\fR" 4
.IX Item "-mfp-reg"
.PD 0
.Ip "\fB\-mno-fp-regs\fR" 4
.IX Item "-mno-fp-regs"
.PD
Generate code that uses (does not use) the floating-point register set.
\&\fB\-mno-fp-regs\fR implies \fB\-msoft-float\fR.  If the floating-point
register set is not used, floating point operands are passed in integer
registers as if they were integers and floating-point results are passed
in \f(CW\*(C`$0\*(C'\fR instead of \f(CW\*(C`$f0\*(C'\fR.  This is a non-standard calling sequence,
so any function with a floating-point argument or return value called by code
compiled with \fB\-mno-fp-regs\fR must also be compiled with that
option.
.Sp
A typical use of this option is building a kernel that does not use,
and hence need not save and restore, any floating-point registers.
.Ip "\fB\-mieee\fR" 4
.IX Item "-mieee"
The Alpha architecture implements floating-point hardware optimized for
maximum performance.  It is mostly compliant with the \s-1IEEE\s0 floating
point standard.  However, for full compliance, software assistance is
required.  This option generates code fully \s-1IEEE\s0 compliant code
\&\fIexcept\fR that the \fIinexact-flag\fR is not maintained (see below).
If this option is turned on, the preprocessor macro \f(CW\*(C`_IEEE_FP\*(C'\fR is
defined during compilation.  The resulting code is less efficient but is
able to correctly support denormalized numbers and exceptional \s-1IEEE\s0
values such as not-a-number and plus/minus infinity.  Other Alpha
compilers call this option \fB\-ieee_with_no_inexact\fR.
.Ip "\fB\-mieee-with-inexact\fR" 4
.IX Item "-mieee-with-inexact"
This is like \fB\-mieee\fR except the generated code also maintains
the \s-1IEEE\s0 \fIinexact-flag\fR.  Turning on this option causes the
generated code to implement fully-compliant \s-1IEEE\s0 math.  In addition to
\&\f(CW\*(C`_IEEE_FP\*(C'\fR, \f(CW\*(C`_IEEE_FP_EXACT\*(C'\fR is defined as a preprocessor
macro.  On some Alpha implementations the resulting code may execute
significantly slower than the code generated by default.  Since there is
very little code that depends on the \fIinexact-flag\fR, you should
normally not specify this option.  Other Alpha compilers call this
option \fB\-ieee_with_inexact\fR.
.Ip "\fB\-mfp-trap-mode=\fR\fItrap-mode\fR" 4
.IX Item "-mfp-trap-mode=trap-mode"
This option controls what floating-point related traps are enabled.
Other Alpha compilers call this option \fB\-fptm\fR \fItrap-mode\fR.
The trap mode can be set to one of four values:
.RS 4
.Ip "\fBn\fR" 4
.IX Item "n"
This is the default (normal) setting.  The only traps that are enabled
are the ones that cannot be disabled in software (e.g., division by zero
trap).
.Ip "\fBu\fR" 4
.IX Item "u"
In addition to the traps enabled by \fBn\fR, underflow traps are enabled
as well.
.Ip "\fBsu\fR" 4
.IX Item "su"
Like \fBsu\fR, but the instructions are marked to be safe for software
completion (see Alpha architecture manual for details).
.Ip "\fBsui\fR" 4
.IX Item "sui"
Like \fBsu\fR, but inexact traps are enabled as well.
.RE
.RS 4
.RE
.Ip "\fB\-mfp-rounding-mode=\fR\fIrounding-mode\fR" 4
.IX Item "-mfp-rounding-mode=rounding-mode"
Selects the \s-1IEEE\s0 rounding mode.  Other Alpha compilers call this option
\&\fB\-fprm\fR \fIrounding-mode\fR.  The \fIrounding-mode\fR can be one
of:
.RS 4
.Ip "\fBn\fR" 4
.IX Item "n"
Normal \s-1IEEE\s0 rounding mode.  Floating point numbers are rounded towards
the nearest machine number or towards the even machine number in case
of a tie.
.Ip "\fBm\fR" 4
.IX Item "m"
Round towards minus infinity.
.Ip "\fBc\fR" 4
.IX Item "c"
Chopped rounding mode.  Floating point numbers are rounded towards zero.
.Ip "\fBd\fR" 4
.IX Item "d"
Dynamic rounding mode.  A field in the floating point control register
(\fIfpcr\fR, see Alpha architecture reference manual) controls the
rounding mode in effect.  The C library initializes this register for
rounding towards plus infinity.  Thus, unless your program modifies the
\&\fIfpcr\fR, \fBd\fR corresponds to round towards plus infinity.
.RE
.RS 4
.RE
.Ip "\fB\-mtrap-precision=\fR\fItrap-precision\fR" 4
.IX Item "-mtrap-precision=trap-precision"
In the Alpha architecture, floating point traps are imprecise.  This
means without software assistance it is impossible to recover from a
floating trap and program execution normally needs to be terminated.
\&\s-1GCC\s0 can generate code that can assist operating system trap handlers
in determining the exact location that caused a floating point trap.
Depending on the requirements of an application, different levels of
precisions can be selected:
.RS 4
.Ip "\fBp\fR" 4
.IX Item "p"
Program precision.  This option is the default and means a trap handler
can only identify which program caused a floating point exception.
.Ip "\fBf\fR" 4
.IX Item "f"
Function precision.  The trap handler can determine the function that
caused a floating point exception.
.Ip "\fBi\fR" 4
.IX Item "i"
Instruction precision.  The trap handler can determine the exact
instruction that caused a floating point exception.
.RE
.RS 4
.Sp
Other Alpha compilers provide the equivalent options called
\&\fB\-scope_safe\fR and \fB\-resumption_safe\fR.
.RE
.Ip "\fB\-mieee-conformant\fR" 4
.IX Item "-mieee-conformant"
This option marks the generated code as \s-1IEEE\s0 conformant.  You must not
use this option unless you also specify \fB\-mtrap-precision=i\fR and either
\&\fB\-mfp-trap-mode=su\fR or \fB\-mfp-trap-mode=sui\fR.  Its only effect
is to emit the line \fB.eflag 48\fR in the function prologue of the
generated assembly file.  Under \s-1DEC\s0 Unix, this has the effect that
IEEE-conformant math library routines will be linked in.
.Ip "\fB\-mbuild-constants\fR" 4
.IX Item "-mbuild-constants"
Normally \s-1GCC\s0 examines a 32\- or 64\-bit integer constant to
see if it can construct it from smaller constants in two or three
instructions.  If it cannot, it will output the constant as a literal and
generate code to load it from the data segment at runtime.
.Sp
Use this option to require \s-1GCC\s0 to construct \fIall\fR integer constants
using code, even if it takes more instructions (the maximum is six).
.Sp
You would typically use this option to build a shared library dynamic
loader.  Itself a shared library, it must relocate itself in memory
before it can find the variables and constants in its own data segment.
.Ip "\fB\-malpha-as\fR" 4
.IX Item "-malpha-as"
.PD 0
.Ip "\fB\-mgas\fR" 4
.IX Item "-mgas"
.PD
Select whether to generate code to be assembled by the vendor-supplied
assembler (\fB\-malpha-as\fR) or by the \s-1GNU\s0 assembler \fB\-mgas\fR.
.Ip "\fB\-mbwx\fR" 4
.IX Item "-mbwx"
.PD 0
.Ip "\fB\-mno-bwx\fR" 4
.IX Item "-mno-bwx"
.Ip "\fB\-mcix\fR" 4
.IX Item "-mcix"
.Ip "\fB\-mno-cix\fR" 4
.IX Item "-mno-cix"
.Ip "\fB\-mfix\fR" 4
.IX Item "-mfix"
.Ip "\fB\-mno-fix\fR" 4
.IX Item "-mno-fix"
.Ip "\fB\-mmax\fR" 4
.IX Item "-mmax"
.Ip "\fB\-mno-max\fR" 4
.IX Item "-mno-max"
.PD
Indicate whether \s-1GCC\s0 should generate code to use the optional \s-1BWX\s0,
\&\s-1CIX\s0, \s-1FIX\s0 and \s-1MAX\s0 instruction sets.  The default is to use the instruction
sets supported by the \s-1CPU\s0 type specified via \fB\-mcpu=\fR option or that
of the \s-1CPU\s0 on which \s-1GCC\s0 was built if none was specified.
.Ip "\fB\-mfloat-vax\fR" 4
.IX Item "-mfloat-vax"
.PD 0
.Ip "\fB\-mfloat-ieee\fR" 4
.IX Item "-mfloat-ieee"
.PD
Generate code that uses (does not use) \s-1VAX\s0 F and G floating point
arithmetic instead of \s-1IEEE\s0 single and double precision.
.Ip "\fB\-mexplicit-relocs\fR" 4
.IX Item "-mexplicit-relocs"
.PD 0
.Ip "\fB\-mno-explicit-relocs\fR" 4
.IX Item "-mno-explicit-relocs"
.PD
Older Alpha assemblers provided no way to generate symbol relocations
except via assembler macros.  Use of these macros does not allow
optimal instruction scheduling.  \s-1GNU\s0 binutils as of version 2.12
supports a new syntax that allows the compiler to explicitly mark
which relocations should apply to which instructions.  This option
is mostly useful for debugging, as \s-1GCC\s0 detects the capabilities of
the assembler when it is built and sets the default accordingly.
.Ip "\fB\-msmall-data\fR" 4
.IX Item "-msmall-data"
.PD 0
.Ip "\fB\-mlarge-data\fR" 4
.IX Item "-mlarge-data"
.PD
When \fB\-mexplicit-relocs\fR is in effect, static data is
accessed via \fIgp-relative\fR relocations.  When \fB\-msmall-data\fR
is used, objects 8 bytes long or smaller are placed in a \fIsmall data area\fR
(the \f(CW\*(C`.sdata\*(C'\fR and \f(CW\*(C`.sbss\*(C'\fR sections) and are accessed via
16\-bit relocations off of the \f(CW\*(C`$gp\*(C'\fR register.  This limits the
size of the small data area to 64KB, but allows the variables to be
directly accessed via a single instruction.
.Sp
The default is \fB\-mlarge-data\fR.  With this option the data area
is limited to just below 2GB.  Programs that require more than 2GB of
data must use \f(CW\*(C`malloc\*(C'\fR or \f(CW\*(C`mmap\*(C'\fR to allocate the data in the
heap instead of in the program's data segment.
.Sp
When generating code for shared libraries, \fB\-fpic\fR implies
\&\fB\-msmall-data\fR and \fB\-fPIC\fR implies \fB\-mlarge-data\fR.
.Ip "\fB\-msmall-text\fR" 4
.IX Item "-msmall-text"
.PD 0
.Ip "\fB\-mlarge-text\fR" 4
.IX Item "-mlarge-text"
.PD
When \fB\-msmall-text\fR is used, the compiler assumes that the
code of the entire program (or shared library) fits in 4MB, and is
thus reachable with a branch instruction.  When \fB\-msmall-data\fR
is used, the compiler can assume that all local symbols share the
same \f(CW\*(C`$gp\*(C'\fR value, and thus reduce the number of instructions
required for a function call from 4 to 1.
.Sp
The default is \fB\-mlarge-text\fR.
.Ip "\fB\-mcpu=\fR\fIcpu_type\fR" 4
.IX Item "-mcpu=cpu_type"
Set the instruction set and instruction scheduling parameters for
machine type \fIcpu_type\fR.  You can specify either the \fB\s-1EV\s0\fR
style name or the corresponding chip number.  \s-1GCC\s0 supports scheduling
parameters for the \s-1EV4\s0, \s-1EV5\s0 and \s-1EV6\s0 family of processors and will
choose the default values for the instruction set from the processor
you specify.  If you do not specify a processor type, \s-1GCC\s0 will default
to the processor on which the compiler was built.
.Sp
Supported values for \fIcpu_type\fR are
.RS 4
.Ip "\fBev4\fR" 4
.IX Item "ev4"
.PD 0
.Ip "\fBev45\fR" 4
.IX Item "ev45"
.Ip "\fB21064\fR" 4
.IX Item "21064"
.PD
Schedules as an \s-1EV4\s0 and has no instruction set extensions.
.Ip "\fBev5\fR" 4
.IX Item "ev5"
.PD 0
.Ip "\fB21164\fR" 4
.IX Item "21164"
.PD
Schedules as an \s-1EV5\s0 and has no instruction set extensions.
.Ip "\fBev56\fR" 4
.IX Item "ev56"
.PD 0
.Ip "\fB21164a\fR" 4
.IX Item "21164a"
.PD
Schedules as an \s-1EV5\s0 and supports the \s-1BWX\s0 extension.
.Ip "\fBpca56\fR" 4
.IX Item "pca56"
.PD 0
.Ip "\fB21164pc\fR" 4
.IX Item "21164pc"
.Ip "\fB21164PC\fR" 4
.IX Item "21164PC"
.PD
Schedules as an \s-1EV5\s0 and supports the \s-1BWX\s0 and \s-1MAX\s0 extensions.
.Ip "\fBev6\fR" 4
.IX Item "ev6"
.PD 0
.Ip "\fB21264\fR" 4
.IX Item "21264"
.PD
Schedules as an \s-1EV6\s0 and supports the \s-1BWX\s0, \s-1FIX\s0, and \s-1MAX\s0 extensions.
.Ip "\fBev67\fR" 4
.IX Item "ev67"
.PD 0
.Ip "\fB21264a\fR" 4
.IX Item "21264a"
.PD
Schedules as an \s-1EV6\s0 and supports the \s-1BWX\s0, \s-1CIX\s0, \s-1FIX\s0, and \s-1MAX\s0 extensions.
.RE
.RS 4
.RE
.Ip "\fB\-mtune=\fR\fIcpu_type\fR" 4
.IX Item "-mtune=cpu_type"
Set only the instruction scheduling parameters for machine type
\&\fIcpu_type\fR.  The instruction set is not changed.
.Ip "\fB\-mmemory-latency=\fR\fItime\fR" 4
.IX Item "-mmemory-latency=time"
Sets the latency the scheduler should assume for typical memory
references as seen by the application.  This number is highly
dependent on the memory access patterns used by the application
and the size of the external cache on the machine.
.Sp
Valid options for \fItime\fR are
.RS 4
.Ip "\fInumber\fR" 4
.IX Item "number"
A decimal number representing clock cycles.
.Ip "\fBL1\fR" 4
.IX Item "L1"
.PD 0
.Ip "\fBL2\fR" 4
.IX Item "L2"
.Ip "\fBL3\fR" 4
.IX Item "L3"
.Ip "\fBmain\fR" 4
.IX Item "main"
.PD
The compiler contains estimates of the number of clock cycles for
``typical'' \s-1EV4\s0 & \s-1EV5\s0 hardware for the Level 1, 2 & 3 caches
(also called Dcache, Scache, and Bcache), as well as to main memory.
Note that L3 is only valid for \s-1EV5\s0.
.RE
.RS 4
.RE
.PP
.I "\s-1DEC\s0 Alpha/VMS Options"
.IX Subsection "DEC Alpha/VMS Options"
.PP
These \fB\-m\fR options are defined for the \s-1DEC\s0 Alpha/VMS implementations:
.Ip "\fB\-mvms-return-codes\fR" 4
.IX Item "-mvms-return-codes"
Return \s-1VMS\s0 condition codes from main.  The default is to return \s-1POSIX\s0
style condition (e.g. error) codes.
.PP
.I "H8/300 Options"
.IX Subsection "H8/300 Options"
.PP
These \fB\-m\fR options are defined for the H8/300 implementations:
.Ip "\fB\-mrelax\fR" 4
.IX Item "-mrelax"
Shorten some address references at link time, when possible; uses the
linker option \fB\-relax\fR.  
.Ip "\fB\-mh\fR" 4
.IX Item "-mh"
Generate code for the H8/300H.
.Ip "\fB\-ms\fR" 4
.IX Item "-ms"
Generate code for the H8S.
.Ip "\fB\-mn\fR" 4
.IX Item "-mn"
Generate code for the H8S and H8/300H in the normal mode.  This switch
must be used either with \-mh or \-ms.
.Ip "\fB\-ms2600\fR" 4
.IX Item "-ms2600"
Generate code for the H8S/2600.  This switch must be used with \fB\-ms\fR.
.Ip "\fB\-mint32\fR" 4
.IX Item "-mint32"
Make \f(CW\*(C`int\*(C'\fR data 32 bits by default.
.Ip "\fB\-malign-300\fR" 4
.IX Item "-malign-300"
On the H8/300H and H8S, use the same alignment rules as for the H8/300.
The default for the H8/300H and H8S is to align longs and floats on 4
byte boundaries.
\&\fB\-malign-300\fR causes them to be aligned on 2 byte boundaries.
This option has no effect on the H8/300.
.PP
.I "\s-1SH\s0 Options"
.IX Subsection "SH Options"
.PP
These \fB\-m\fR options are defined for the \s-1SH\s0 implementations:
.Ip "\fB\-m1\fR" 4
.IX Item "-m1"
Generate code for the \s-1SH1\s0.
.Ip "\fB\-m2\fR" 4
.IX Item "-m2"
Generate code for the \s-1SH2\s0.
.Ip "\fB\-m2e\fR" 4
.IX Item "-m2e"
Generate code for the SH2e.
.Ip "\fB\-m3\fR" 4
.IX Item "-m3"
Generate code for the \s-1SH3\s0.
.Ip "\fB\-m3e\fR" 4
.IX Item "-m3e"
Generate code for the SH3e.
.Ip "\fB\-m4\-nofpu\fR" 4
.IX Item "-m4-nofpu"
Generate code for the \s-1SH4\s0 without a floating-point unit.
.Ip "\fB\-m4\-single-only\fR" 4
.IX Item "-m4-single-only"
Generate code for the \s-1SH4\s0 with a floating-point unit that only
supports single-precision arithmetic.
.Ip "\fB\-m4\-single\fR" 4
.IX Item "-m4-single"
Generate code for the \s-1SH4\s0 assuming the floating-point unit is in
single-precision mode by default.
.Ip "\fB\-m4\fR" 4
.IX Item "-m4"
Generate code for the \s-1SH4\s0.
.Ip "\fB\-mb\fR" 4
.IX Item "-mb"
Compile code for the processor in big endian mode.
.Ip "\fB\-ml\fR" 4
.IX Item "-ml"
Compile code for the processor in little endian mode.
.Ip "\fB\-mdalign\fR" 4
.IX Item "-mdalign"
Align doubles at 64\-bit boundaries.  Note that this changes the calling
conventions, and thus some functions from the standard C library will
not work unless you recompile it first with \fB\-mdalign\fR.
.Ip "\fB\-mrelax\fR" 4
.IX Item "-mrelax"
Shorten some address references at link time, when possible; uses the
linker option \fB\-relax\fR.
.Ip "\fB\-mbigtable\fR" 4
.IX Item "-mbigtable"
Use 32\-bit offsets in \f(CW\*(C`switch\*(C'\fR tables.  The default is to use
16\-bit offsets.
.Ip "\fB\-mfmovd\fR" 4
.IX Item "-mfmovd"
Enable the use of the instruction \f(CW\*(C`fmovd\*(C'\fR.
.Ip "\fB\-mhitachi\fR" 4
.IX Item "-mhitachi"
Comply with the calling conventions defined by Renesas.
.Ip "\fB\-mnomacsave\fR" 4
.IX Item "-mnomacsave"
Mark the \f(CW\*(C`MAC\*(C'\fR register as call-clobbered, even if
\&\fB\-mhitachi\fR is given.
.Ip "\fB\-mieee\fR" 4
.IX Item "-mieee"
Increase IEEE-compliance of floating-point code.
.Ip "\fB\-misize\fR" 4
.IX Item "-misize"
Dump instruction size and location in the assembly code.
.Ip "\fB\-mpadstruct\fR" 4
.IX Item "-mpadstruct"
This option is deprecated.  It pads structures to multiple of 4 bytes,
which is incompatible with the \s-1SH\s0 \s-1ABI\s0.
.Ip "\fB\-mspace\fR" 4
.IX Item "-mspace"
Optimize for space instead of speed.  Implied by \fB\-Os\fR.
.Ip "\fB\-mprefergot\fR" 4
.IX Item "-mprefergot"
When generating position-independent code, emit function calls using
the Global Offset Table instead of the Procedure Linkage Table.
.Ip "\fB\-musermode\fR" 4
.IX Item "-musermode"
Generate a library function call to invalidate instruction cache
entries, after fixing up a trampoline.  This library function call
doesn't assume it can write to the whole memory address space.  This
is the default when the target is \f(CW\*(C`sh\-*\-linux*\*(C'\fR.
.PP
.I "Options for System V"
.IX Subsection "Options for System V"
.PP
These additional options are available on System V Release 4 for
compatibility with other compilers on those systems:
.Ip "\fB\-G\fR" 4
.IX Item "-G"
Create a shared object.
It is recommended that \fB\-symbolic\fR or \fB\-shared\fR be used instead.
.Ip "\fB\-Qy\fR" 4
.IX Item "-Qy"
Identify the versions of each tool used by the compiler, in a
\&\f(CW\*(C`.ident\*(C'\fR assembler directive in the output.
.Ip "\fB\-Qn\fR" 4
.IX Item "-Qn"
Refrain from adding \f(CW\*(C`.ident\*(C'\fR directives to the output file (this is
the default).
.Ip "\fB\-YP,\fR\fIdirs\fR" 4
.IX Item "-YP,dirs"
Search the directories \fIdirs\fR, and no others, for libraries
specified with \fB\-l\fR.
.Ip "\fB\-Ym,\fR\fIdir\fR" 4
.IX Item "-Ym,dir"
Look in the directory \fIdir\fR to find the M4 preprocessor.
The assembler uses this option.
.PP
.I "TMS320C3x/C4x Options"
.IX Subsection "TMS320C3x/C4x Options"
.PP
These \fB\-m\fR options are defined for TMS320C3x/C4x implementations:
.Ip "\fB\-mcpu=\fR\fIcpu_type\fR" 4
.IX Item "-mcpu=cpu_type"
Set the instruction set, register set, and instruction scheduling
parameters for machine type \fIcpu_type\fR.  Supported values for
\&\fIcpu_type\fR are \fBc30\fR, \fBc31\fR, \fBc32\fR, \fBc40\fR, and
\&\fBc44\fR.  The default is \fBc40\fR to generate code for the
\&\s-1TMS320C40\s0.
.Ip "\fB\-mbig-memory\fR" 4
.IX Item "-mbig-memory"
.PD 0
.Ip "\fB\-mbig\fR" 4
.IX Item "-mbig"
.Ip "\fB\-msmall-memory\fR" 4
.IX Item "-msmall-memory"
.Ip "\fB\-msmall\fR" 4
.IX Item "-msmall"
.PD
Generates code for the big or small memory model.  The small memory
model assumed that all data fits into one 64K word page.  At run-time
the data page (\s-1DP\s0) register must be set to point to the 64K page
containing the .bss and .data program sections.  The big memory model is
the default and requires reloading of the \s-1DP\s0 register for every direct
memory access.
.Ip "\fB\-mbk\fR" 4
.IX Item "-mbk"
.PD 0
.Ip "\fB\-mno-bk\fR" 4
.IX Item "-mno-bk"
.PD
Allow (disallow) allocation of general integer operands into the block
count register \s-1BK\s0.
.Ip "\fB\-mdb\fR" 4
.IX Item "-mdb"
.PD 0
.Ip "\fB\-mno-db\fR" 4
.IX Item "-mno-db"
.PD
Enable (disable) generation of code using decrement and branch,
\&\fIDBcond\fR\|(D), instructions.  This is enabled by default for the C4x.  To be
on the safe side, this is disabled for the C3x, since the maximum
iteration count on the C3x is 2^{23 + 1} (but who iterates loops more than
2^{23} times on the C3x?).  Note that \s-1GCC\s0 will try to reverse a loop so
that it can utilize the decrement and branch instruction, but will give
up if there is more than one memory reference in the loop.  Thus a loop
where the loop counter is decremented can generate slightly more
efficient code, in cases where the \s-1RPTB\s0 instruction cannot be utilized.
.Ip "\fB\-mdp-isr-reload\fR" 4
.IX Item "-mdp-isr-reload"
.PD 0
.Ip "\fB\-mparanoid\fR" 4
.IX Item "-mparanoid"
.PD
Force the \s-1DP\s0 register to be saved on entry to an interrupt service
routine (\s-1ISR\s0), reloaded to point to the data section, and restored on
exit from the \s-1ISR\s0.  This should not be required unless someone has
violated the small memory model by modifying the \s-1DP\s0 register, say within
an object library.
.Ip "\fB\-mmpyi\fR" 4
.IX Item "-mmpyi"
.PD 0
.Ip "\fB\-mno-mpyi\fR" 4
.IX Item "-mno-mpyi"
.PD
For the C3x use the 24\-bit \s-1MPYI\s0 instruction for integer multiplies
instead of a library call to guarantee 32\-bit results.  Note that if one
of the operands is a constant, then the multiplication will be performed
using shifts and adds.  If the \fB\-mmpyi\fR option is not specified for the C3x,
then squaring operations are performed inline instead of a library call.
.Ip "\fB\-mfast-fix\fR" 4
.IX Item "-mfast-fix"
.PD 0
.Ip "\fB\-mno-fast-fix\fR" 4
.IX Item "-mno-fast-fix"
.PD
The C3x/C4x \s-1FIX\s0 instruction to convert a floating point value to an
integer value chooses the nearest integer less than or equal to the
floating point value rather than to the nearest integer.  Thus if the
floating point number is negative, the result will be incorrectly
truncated an additional code is necessary to detect and correct this
case.  This option can be used to disable generation of the additional
code required to correct the result.
.Ip "\fB\-mrptb\fR" 4
.IX Item "-mrptb"
.PD 0
.Ip "\fB\-mno-rptb\fR" 4
.IX Item "-mno-rptb"
.PD
Enable (disable) generation of repeat block sequences using the \s-1RPTB\s0
instruction for zero overhead looping.  The \s-1RPTB\s0 construct is only used
for innermost loops that do not call functions or jump across the loop
boundaries.  There is no advantage having nested \s-1RPTB\s0 loops due to the
overhead required to save and restore the \s-1RC\s0, \s-1RS\s0, and \s-1RE\s0 registers.
This is enabled by default with \fB\-O2\fR.
.Ip "\fB\-mrpts=\fR\fIcount\fR" 4
.IX Item "-mrpts=count"
.PD 0
.Ip "\fB\-mno-rpts\fR" 4
.IX Item "-mno-rpts"
.PD
Enable (disable) the use of the single instruction repeat instruction
\&\s-1RPTS\s0.  If a repeat block contains a single instruction, and the loop
count can be guaranteed to be less than the value \fIcount\fR, \s-1GCC\s0 will
emit a \s-1RPTS\s0 instruction instead of a \s-1RPTB\s0.  If no value is specified,
then a \s-1RPTS\s0 will be emitted even if the loop count cannot be determined
at compile time.  Note that the repeated instruction following \s-1RPTS\s0 does
not have to be reloaded from memory each iteration, thus freeing up the
\&\s-1CPU\s0 buses for operands.  However, since interrupts are blocked by this
instruction, it is disabled by default.
.Ip "\fB\-mloop-unsigned\fR" 4
.IX Item "-mloop-unsigned"
.PD 0
.Ip "\fB\-mno-loop-unsigned\fR" 4
.IX Item "-mno-loop-unsigned"
.PD
The maximum iteration count when using \s-1RPTS\s0 and \s-1RPTB\s0 (and \s-1DB\s0 on the C40)
is 2^{31 + 1} since these instructions test if the iteration count is
negative to terminate the loop.  If the iteration count is unsigned
there is a possibility than the 2^{31 + 1} maximum iteration count may be
exceeded.  This switch allows an unsigned iteration count.
.Ip "\fB\-mti\fR" 4
.IX Item "-mti"
Try to emit an assembler syntax that the \s-1TI\s0 assembler (asm30) is happy
with.  This also enforces compatibility with the \s-1API\s0 employed by the \s-1TI\s0
C3x C compiler.  For example, long doubles are passed as structures
rather than in floating point registers.
.Ip "\fB\-mregparm\fR" 4
.IX Item "-mregparm"
.PD 0
.Ip "\fB\-mmemparm\fR" 4
.IX Item "-mmemparm"
.PD
Generate code that uses registers (stack) for passing arguments to functions.
By default, arguments are passed in registers where possible rather
than by pushing arguments on to the stack.
.Ip "\fB\-mparallel-insns\fR" 4
.IX Item "-mparallel-insns"
.PD 0
.Ip "\fB\-mno-parallel-insns\fR" 4
.IX Item "-mno-parallel-insns"
.PD
Allow the generation of parallel instructions.  This is enabled by
default with \fB\-O2\fR.
.Ip "\fB\-mparallel-mpy\fR" 4
.IX Item "-mparallel-mpy"
.PD 0
.Ip "\fB\-mno-parallel-mpy\fR" 4
.IX Item "-mno-parallel-mpy"
.PD
Allow the generation of MPY||ADD and MPY||SUB parallel instructions,
provided \fB\-mparallel-insns\fR is also specified.  These instructions have
tight register constraints which can pessimize the code generation
of large functions.
.PP
.I "V850 Options"
.IX Subsection "V850 Options"
.PP
These \fB\-m\fR options are defined for V850 implementations:
.Ip "\fB\-mlong-calls\fR" 4
.IX Item "-mlong-calls"
.PD 0
.Ip "\fB\-mno-long-calls\fR" 4
.IX Item "-mno-long-calls"
.PD
Treat all calls as being far away (near).  If calls are assumed to be
far away, the compiler will always load the functions address up into a
register, and call indirect through the pointer.
.Ip "\fB\-mno-ep\fR" 4
.IX Item "-mno-ep"
.PD 0
.Ip "\fB\-mep\fR" 4
.IX Item "-mep"
.PD
Do not optimize (do optimize) basic blocks that use the same index
pointer 4 or more times to copy pointer into the \f(CW\*(C`ep\*(C'\fR register, and
use the shorter \f(CW\*(C`sld\*(C'\fR and \f(CW\*(C`sst\*(C'\fR instructions.  The \fB\-mep\fR
option is on by default if you optimize.
.Ip "\fB\-mno-prolog-function\fR" 4
.IX Item "-mno-prolog-function"
.PD 0
.Ip "\fB\-mprolog-function\fR" 4
.IX Item "-mprolog-function"
.PD
Do not use (do use) external functions to save and restore registers
at the prologue and epilogue of a function.  The external functions
are slower, but use less code space if more than one function saves
the same number of registers.  The \fB\-mprolog-function\fR option
is on by default if you optimize.
.Ip "\fB\-mspace\fR" 4
.IX Item "-mspace"
Try to make the code as small as possible.  At present, this just turns
on the \fB\-mep\fR and \fB\-mprolog-function\fR options.
.Ip "\fB\-mtda=\fR\fIn\fR" 4
.IX Item "-mtda=n"
Put static or global variables whose size is \fIn\fR bytes or less into
the tiny data area that register \f(CW\*(C`ep\*(C'\fR points to.  The tiny data
area can hold up to 256 bytes in total (128 bytes for byte references).
.Ip "\fB\-msda=\fR\fIn\fR" 4
.IX Item "-msda=n"
Put static or global variables whose size is \fIn\fR bytes or less into
the small data area that register \f(CW\*(C`gp\*(C'\fR points to.  The small data
area can hold up to 64 kilobytes.
.Ip "\fB\-mzda=\fR\fIn\fR" 4
.IX Item "-mzda=n"
Put static or global variables whose size is \fIn\fR bytes or less into
the first 32 kilobytes of memory.
.Ip "\fB\-mv850\fR" 4
.IX Item "-mv850"
Specify that the target processor is the V850.
.Ip "\fB\-mbig-switch\fR" 4
.IX Item "-mbig-switch"
Generate code suitable for big switch tables.  Use this option only if
the assembler/linker complain about out of range branches within a switch
table.
.Ip "\fB\-mapp-regs\fR" 4
.IX Item "-mapp-regs"
This option will cause r2 and r5 to be used in the code generated by
the compiler.  This setting is the default.
.Ip "\fB\-mno-app-regs\fR" 4
.IX Item "-mno-app-regs"
This option will cause r2 and r5 to be treated as fixed registers.
.Ip "\fB\-mv850e1\fR" 4
.IX Item "-mv850e1"
Specify that the target processor is the V850E1.  The preprocessor
constants \fB_\|_v850e1_\|_\fR and \fB_\|_v850e_\|_\fR will be defined if
this option is used.
.Ip "\fB\-mv850e\fR" 4
.IX Item "-mv850e"
Specify that the target processor is the V850E.  The preprocessor
constant \fB_\|_v850e_\|_\fR will be defined if this option is used.
.Sp
If neither \fB\-mv850\fR nor \fB\-mv850e\fR nor \fB\-mv850e1\fR
are defined then a default target processor will be chosen and the
relevant \fB_\|_v850*_\|_\fR preprocessor constant will be defined.
.Sp
The preprocessor constants \fB_\|_v850\fR and \fB_\|_v851_\|_\fR are always
defined, regardless of which processor variant is the target.
.Ip "\fB\-mdisable-callt\fR" 4
.IX Item "-mdisable-callt"
This option will suppress generation of the \s-1CALLT\s0 instruction for the
v850e and v850e1 flavors of the v850 architecture.  The default is
\&\fB\-mno-disable-callt\fR which allows the \s-1CALLT\s0 instruction to be used.
.PP
.I "\s-1ARC\s0 Options"
.IX Subsection "ARC Options"
.PP
These options are defined for \s-1ARC\s0 implementations:
.Ip "\fB\-EL\fR" 4
.IX Item "-EL"
Compile code for little endian mode.  This is the default.
.Ip "\fB\-EB\fR" 4
.IX Item "-EB"
Compile code for big endian mode.
.Ip "\fB\-mmangle-cpu\fR" 4
.IX Item "-mmangle-cpu"
Prepend the name of the cpu to all public symbol names.
In multiple-processor systems, there are many \s-1ARC\s0 variants with different
instruction and register set characteristics.  This flag prevents code
compiled for one cpu to be linked with code compiled for another.
No facility exists for handling variants that are ``almost identical''.
This is an all or nothing option.
.Ip "\fB\-mcpu=\fR\fIcpu\fR" 4
.IX Item "-mcpu=cpu"
Compile code for \s-1ARC\s0 variant \fIcpu\fR.
Which variants are supported depend on the configuration.
All variants support \fB\-mcpu=base\fR, this is the default.
.Ip "\fB\-mtext=\fR\fItext-section\fR" 4
.IX Item "-mtext=text-section"
.PD 0
.Ip "\fB\-mdata=\fR\fIdata-section\fR" 4
.IX Item "-mdata=data-section"
.Ip "\fB\-mrodata=\fR\fIreadonly-data-section\fR" 4
.IX Item "-mrodata=readonly-data-section"
.PD
Put functions, data, and readonly data in \fItext-section\fR,
\&\fIdata-section\fR, and \fIreadonly-data-section\fR respectively
by default.  This can be overridden with the \f(CW\*(C`section\*(C'\fR attribute.
.PP
.I "\s-1NS32K\s0 Options"
.IX Subsection "NS32K Options"
.PP
These are the \fB\-m\fR options defined for the 32000 series.  The default
values for these options depends on which style of 32000 was selected when
the compiler was configured; the defaults for the most common choices are
given below.
.Ip "\fB\-m32032\fR" 4
.IX Item "-m32032"
.PD 0
.Ip "\fB\-m32032\fR" 4
.IX Item "-m32032"
.PD
Generate output for a 32032.  This is the default
when the compiler is configured for 32032 and 32016 based systems.
.Ip "\fB\-m32332\fR" 4
.IX Item "-m32332"
.PD 0
.Ip "\fB\-m32332\fR" 4
.IX Item "-m32332"
.PD
Generate output for a 32332.  This is the default
when the compiler is configured for 32332\-based systems.
.Ip "\fB\-m32532\fR" 4
.IX Item "-m32532"
.PD 0
.Ip "\fB\-m32532\fR" 4
.IX Item "-m32532"
.PD
Generate output for a 32532.  This is the default
when the compiler is configured for 32532\-based systems.
.Ip "\fB\-m32081\fR" 4
.IX Item "-m32081"
Generate output containing 32081 instructions for floating point.
This is the default for all systems.
.Ip "\fB\-m32381\fR" 4
.IX Item "-m32381"
Generate output containing 32381 instructions for floating point.  This
also implies \fB\-m32081\fR.  The 32381 is only compatible with the 32332
and 32532 cpus.  This is the default for the pc532\-netbsd configuration.
.Ip "\fB\-mmulti-add\fR" 4
.IX Item "-mmulti-add"
Try and generate multiply-add floating point instructions \f(CW\*(C`polyF\*(C'\fR
and \f(CW\*(C`dotF\*(C'\fR.  This option is only available if the \fB\-m32381\fR
option is in effect.  Using these instructions requires changes to
register allocation which generally has a negative impact on
performance.  This option should only be enabled when compiling code
particularly likely to make heavy use of multiply-add instructions.
.Ip "\fB\-mnomulti-add\fR" 4
.IX Item "-mnomulti-add"
Do not try and generate multiply-add floating point instructions
\&\f(CW\*(C`polyF\*(C'\fR and \f(CW\*(C`dotF\*(C'\fR.  This is the default on all platforms.
.Ip "\fB\-msoft-float\fR" 4
.IX Item "-msoft-float"
Generate output containing library calls for floating point.
\&\fBWarning:\fR the requisite libraries may not be available.
.Ip "\fB\-mieee-compare\fR" 4
.IX Item "-mieee-compare"
.PD 0
.Ip "\fB\-mno-ieee-compare\fR" 4
.IX Item "-mno-ieee-compare"
.PD
Control whether or not the compiler uses \s-1IEEE\s0 floating point
comparisons.  These handle correctly the case where the result of a
comparison is unordered.
\&\fBWarning:\fR the requisite kernel support may not be available.
.Ip "\fB\-mnobitfield\fR" 4
.IX Item "-mnobitfield"
Do not use the bit-field instructions.  On some machines it is faster to
use shifting and masking operations.  This is the default for the pc532.
.Ip "\fB\-mbitfield\fR" 4
.IX Item "-mbitfield"
Do use the bit-field instructions.  This is the default for all platforms
except the pc532.
.Ip "\fB\-mrtd\fR" 4
.IX Item "-mrtd"
Use a different function-calling convention, in which functions
that take a fixed number of arguments return pop their
arguments on return with the \f(CW\*(C`ret\*(C'\fR instruction.
.Sp
This calling convention is incompatible with the one normally
used on Unix, so you cannot use it if you need to call libraries
compiled with the Unix compiler.
.Sp
Also, you must provide function prototypes for all functions that
take variable numbers of arguments (including \f(CW\*(C`printf\*(C'\fR);
otherwise incorrect code will be generated for calls to those
functions.
.Sp
In addition, seriously incorrect code will result if you call a
function with too many arguments.  (Normally, extra arguments are
harmlessly ignored.)
.Sp
This option takes its name from the 680x0 \f(CW\*(C`rtd\*(C'\fR instruction.
.Ip "\fB\-mregparam\fR" 4
.IX Item "-mregparam"
Use a different function-calling convention where the first two arguments
are passed in registers.
.Sp
This calling convention is incompatible with the one normally
used on Unix, so you cannot use it if you need to call libraries
compiled with the Unix compiler.
.Ip "\fB\-mnoregparam\fR" 4
.IX Item "-mnoregparam"
Do not pass any arguments in registers.  This is the default for all
targets.
.Ip "\fB\-msb\fR" 4
.IX Item "-msb"
It is \s-1OK\s0 to use the sb as an index register which is always loaded with
zero.  This is the default for the pc532\-netbsd target.
.Ip "\fB\-mnosb\fR" 4
.IX Item "-mnosb"
The sb register is not available for use or has not been initialized to
zero by the run time system.  This is the default for all targets except
the pc532\-netbsd.  It is also implied whenever \fB\-mhimem\fR or
\&\fB\-fpic\fR is set.
.Ip "\fB\-mhimem\fR" 4
.IX Item "-mhimem"
Many ns32000 series addressing modes use displacements of up to 512MB.
If an address is above 512MB then displacements from zero can not be used.
This option causes code to be generated which can be loaded above 512MB.
This may be useful for operating systems or \s-1ROM\s0 code.
.Ip "\fB\-mnohimem\fR" 4
.IX Item "-mnohimem"
Assume code will be loaded in the first 512MB of virtual address space.
This is the default for all platforms.
.PP
.I "\s-1AVR\s0 Options"
.IX Subsection "AVR Options"
.PP
These options are defined for \s-1AVR\s0 implementations:
.Ip "\fB\-mmcu=\fR\fImcu\fR" 4
.IX Item "-mmcu=mcu"
Specify \s-1ATMEL\s0 \s-1AVR\s0 instruction set or \s-1MCU\s0 type.
.Sp
Instruction set avr1 is for the minimal \s-1AVR\s0 core, not supported by the C
compiler, only for assembler programs (\s-1MCU\s0 types: at90s1200, attiny10,
attiny11, attiny12, attiny15, attiny28).
.Sp
Instruction set avr2 (default) is for the classic \s-1AVR\s0 core with up to
8K program memory space (\s-1MCU\s0 types: at90s2313, at90s2323, attiny22,
at90s2333, at90s2343, at90s4414, at90s4433, at90s4434, at90s8515,
at90c8534, at90s8535).
.Sp
Instruction set avr3 is for the classic \s-1AVR\s0 core with up to 128K program
memory space (\s-1MCU\s0 types: atmega103, atmega603, at43usb320, at76c711).
.Sp
Instruction set avr4 is for the enhanced \s-1AVR\s0 core with up to 8K program
memory space (\s-1MCU\s0 types: atmega8, atmega83, atmega85).
.Sp
Instruction set avr5 is for the enhanced \s-1AVR\s0 core with up to 128K program
memory space (\s-1MCU\s0 types: atmega16, atmega161, atmega163, atmega32, atmega323,
atmega64, atmega128, at43usb355, at94k).
.Ip "\fB\-msize\fR" 4
.IX Item "-msize"
Output instruction sizes to the asm file.
.Ip "\fB\-minit-stack=\fR\fIN\fR" 4
.IX Item "-minit-stack=N"
Specify the initial stack address, which may be a symbol or numeric value,
\&\fB_\|_stack\fR is the default.
.Ip "\fB\-mno-interrupts\fR" 4
.IX Item "-mno-interrupts"
Generated code is not compatible with hardware interrupts.
Code size will be smaller.
.Ip "\fB\-mcall-prologues\fR" 4
.IX Item "-mcall-prologues"
Functions prologues/epilogues expanded as call to appropriate
subroutines.  Code size will be smaller.
.Ip "\fB\-mno-tablejump\fR" 4
.IX Item "-mno-tablejump"
Do not generate tablejump insns which sometimes increase code size.
.Ip "\fB\-mtiny-stack\fR" 4
.IX Item "-mtiny-stack"
Change only the low 8 bits of the stack pointer.
.PP
.I "MCore Options"
.IX Subsection "MCore Options"
.PP
These are the \fB\-m\fR options defined for the Motorola M*Core
processors.
.Ip "\fB\-mhardlit\fR" 4
.IX Item "-mhardlit"
.PD 0
.Ip "\fB\-mno-hardlit\fR" 4
.IX Item "-mno-hardlit"
.PD
Inline constants into the code stream if it can be done in two
instructions or less.
.Ip "\fB\-mdiv\fR" 4
.IX Item "-mdiv"
.PD 0
.Ip "\fB\-mno-div\fR" 4
.IX Item "-mno-div"
.PD
Use the divide instruction.  (Enabled by default).
.Ip "\fB\-mrelax-immediate\fR" 4
.IX Item "-mrelax-immediate"
.PD 0
.Ip "\fB\-mno-relax-immediate\fR" 4
.IX Item "-mno-relax-immediate"
.PD
Allow arbitrary sized immediates in bit operations.
.Ip "\fB\-mwide-bitfields\fR" 4
.IX Item "-mwide-bitfields"
.PD 0
.Ip "\fB\-mno-wide-bitfields\fR" 4
.IX Item "-mno-wide-bitfields"
.PD
Always treat bit-fields as int-sized.
.Ip "\fB\-m4byte-functions\fR" 4
.IX Item "-m4byte-functions"
.PD 0
.Ip "\fB\-mno-4byte-functions\fR" 4
.IX Item "-mno-4byte-functions"
.PD
Force all functions to be aligned to a four byte boundary.
.Ip "\fB\-mcallgraph-data\fR" 4
.IX Item "-mcallgraph-data"
.PD 0
.Ip "\fB\-mno-callgraph-data\fR" 4
.IX Item "-mno-callgraph-data"
.PD
Emit callgraph information.
.Ip "\fB\-mslow-bytes\fR" 4
.IX Item "-mslow-bytes"
.PD 0
.Ip "\fB\-mno-slow-bytes\fR" 4
.IX Item "-mno-slow-bytes"
.PD
Prefer word access when reading byte quantities.
.Ip "\fB\-mlittle-endian\fR" 4
.IX Item "-mlittle-endian"
.PD 0
.Ip "\fB\-mbig-endian\fR" 4
.IX Item "-mbig-endian"
.PD
Generate code for a little endian target.
.Ip "\fB\-m210\fR" 4
.IX Item "-m210"
.PD 0
.Ip "\fB\-m340\fR" 4
.IX Item "-m340"
.PD
Generate code for the 210 processor.
.PP
.I "\s-1IA-64\s0 Options"
.IX Subsection "IA-64 Options"
.PP
These are the \fB\-m\fR options defined for the Intel \s-1IA-64\s0 architecture.
.Ip "\fB\-mbig-endian\fR" 4
.IX Item "-mbig-endian"
Generate code for a big endian target.  This is the default for \s-1HP-UX\s0.
.Ip "\fB\-mlittle-endian\fR" 4
.IX Item "-mlittle-endian"
Generate code for a little endian target.  This is the default for \s-1AIX5\s0
and GNU/Linux.
.Ip "\fB\-mgnu-as\fR" 4
.IX Item "-mgnu-as"
.PD 0
.Ip "\fB\-mno-gnu-as\fR" 4
.IX Item "-mno-gnu-as"
.PD
Generate (or don't) code for the \s-1GNU\s0 assembler.  This is the default.
.Ip "\fB\-mgnu-ld\fR" 4
.IX Item "-mgnu-ld"
.PD 0
.Ip "\fB\-mno-gnu-ld\fR" 4
.IX Item "-mno-gnu-ld"
.PD
Generate (or don't) code for the \s-1GNU\s0 linker.  This is the default.
.Ip "\fB\-mno-pic\fR" 4
.IX Item "-mno-pic"
Generate code that does not use a global pointer register.  The result
is not position independent code, and violates the \s-1IA-64\s0 \s-1ABI\s0.
.Ip "\fB\-mvolatile-asm-stop\fR" 4
.IX Item "-mvolatile-asm-stop"
.PD 0
.Ip "\fB\-mno-volatile-asm-stop\fR" 4
.IX Item "-mno-volatile-asm-stop"
.PD
Generate (or don't) a stop bit immediately before and after volatile asm
statements.
.Ip "\fB\-mb-step\fR" 4
.IX Item "-mb-step"
Generate code that works around Itanium B step errata.
.Ip "\fB\-mregister-names\fR" 4
.IX Item "-mregister-names"
.PD 0
.Ip "\fB\-mno-register-names\fR" 4
.IX Item "-mno-register-names"
.PD
Generate (or don't) \fBin\fR, \fBloc\fR, and \fBout\fR register names for
the stacked registers.  This may make assembler output more readable.
.Ip "\fB\-mno-sdata\fR" 4
.IX Item "-mno-sdata"
.PD 0
.Ip "\fB\-msdata\fR" 4
.IX Item "-msdata"
.PD
Disable (or enable) optimizations that use the small data section.  This may
be useful for working around optimizer bugs.
.Ip "\fB\-mconstant-gp\fR" 4
.IX Item "-mconstant-gp"
Generate code that uses a single constant global pointer value.  This is
useful when compiling kernel code.
.Ip "\fB\-mauto-pic\fR" 4
.IX Item "-mauto-pic"
Generate code that is self-relocatable.  This implies \fB\-mconstant-gp\fR.
This is useful when compiling firmware code.
.Ip "\fB\-minline-float-divide-min-latency\fR" 4
.IX Item "-minline-float-divide-min-latency"
Generate code for inline divides of floating point values
using the minimum latency algorithm.
.Ip "\fB\-minline-float-divide-max-throughput\fR" 4
.IX Item "-minline-float-divide-max-throughput"
Generate code for inline divides of floating point values
using the maximum throughput algorithm.
.Ip "\fB\-minline-int-divide-min-latency\fR" 4
.IX Item "-minline-int-divide-min-latency"
Generate code for inline divides of integer values
using the minimum latency algorithm.
.Ip "\fB\-minline-int-divide-max-throughput\fR" 4
.IX Item "-minline-int-divide-max-throughput"
Generate code for inline divides of integer values
using the maximum throughput algorithm.
.Ip "\fB\-mno-dwarf2\-asm\fR" 4
.IX Item "-mno-dwarf2-asm"
.PD 0
.Ip "\fB\-mdwarf2\-asm\fR" 4
.IX Item "-mdwarf2-asm"
.PD
Don't (or do) generate assembler code for the \s-1DWARF2\s0 line number debugging
info.  This may be useful when not using the \s-1GNU\s0 assembler.
.Ip "\fB\-mfixed-range=\fR\fIregister-range\fR" 4
.IX Item "-mfixed-range=register-range"
Generate code treating the given register range as fixed registers.
A fixed register is one that the register allocator can not use.  This is
useful when compiling kernel code.  A register range is specified as
two registers separated by a dash.  Multiple register ranges can be
specified separated by a comma.
.Ip "\fB\-mearly-stop-bits\fR" 4
.IX Item "-mearly-stop-bits"
.PD 0
.Ip "\fB\-mno-early-stop-bits\fR" 4
.IX Item "-mno-early-stop-bits"
.PD
Allow stop bits to be placed earlier than immediately preceding the
instruction that triggered the stop bit.  This can improve instruction
scheduling, but does not always do so.
.PP
.I "D30V Options"
.IX Subsection "D30V Options"
.PP
These \fB\-m\fR options are defined for D30V implementations:
.Ip "\fB\-mextmem\fR" 4
.IX Item "-mextmem"
Link the \fB.text\fR, \fB.data\fR, \fB.bss\fR, \fB.strings\fR,
\&\fB.rodata\fR, \fB.rodata1\fR, \fB.data1\fR sections into external
memory, which starts at location \f(CW\*(C`0x80000000\*(C'\fR.
.Ip "\fB\-mextmemory\fR" 4
.IX Item "-mextmemory"
Same as the \fB\-mextmem\fR switch.
.Ip "\fB\-monchip\fR" 4
.IX Item "-monchip"
Link the \fB.text\fR section into onchip text memory, which starts at
location \f(CW\*(C`0x0\*(C'\fR.  Also link \fB.data\fR, \fB.bss\fR,
\&\fB.strings\fR, \fB.rodata\fR, \fB.rodata1\fR, \fB.data1\fR sections
into onchip data memory, which starts at location \f(CW\*(C`0x20000000\*(C'\fR.
.Ip "\fB\-mno-asm-optimize\fR" 4
.IX Item "-mno-asm-optimize"
.PD 0
.Ip "\fB\-masm-optimize\fR" 4
.IX Item "-masm-optimize"
.PD
Disable (enable) passing \fB\-O\fR to the assembler when optimizing.
The assembler uses the \fB\-O\fR option to automatically parallelize
adjacent short instructions where possible.
.Ip "\fB\-mbranch-cost=\fR\fIn\fR" 4
.IX Item "-mbranch-cost=n"
Increase the internal costs of branches to \fIn\fR.  Higher costs means
that the compiler will issue more instructions to avoid doing a branch.
The default is 2.
.Ip "\fB\-mcond-exec=\fR\fIn\fR" 4
.IX Item "-mcond-exec=n"
Specify the maximum number of conditionally executed instructions that
replace a branch.  The default is 4.
.PP
.I "S/390 and zSeries Options"
.IX Subsection "S/390 and zSeries Options"
.PP
These are the \fB\-m\fR options defined for the S/390 and zSeries architecture.
.Ip "\fB\-mhard-float\fR" 4
.IX Item "-mhard-float"
.PD 0
.Ip "\fB\-msoft-float\fR" 4
.IX Item "-msoft-float"
.PD
Use (do not use) the hardware floating-point instructions and registers
for floating-point operations.  When \fB\-msoft-float\fR is specified,
functions in \fIlibgcc.a\fR will be used to perform floating-point
operations.  When \fB\-mhard-float\fR is specified, the compiler
generates \s-1IEEE\s0 floating-point instructions.  This is the default.
.Ip "\fB\-mbackchain\fR" 4
.IX Item "-mbackchain"
.PD 0
.Ip "\fB\-mno-backchain\fR" 4
.IX Item "-mno-backchain"
.PD
Generate (or do not generate) code which maintains an explicit
backchain within the stack frame that points to the caller's frame.
This may be needed to allow debugging using tools that do not understand
\&\s-1DWARF-2\s0 call frame information.  The default is not to generate the
backchain.
.Ip "\fB\-msmall-exec\fR" 4
.IX Item "-msmall-exec"
.PD 0
.Ip "\fB\-mno-small-exec\fR" 4
.IX Item "-mno-small-exec"
.PD
Generate (or do not generate) code using the \f(CW\*(C`bras\*(C'\fR instruction
to do subroutine calls.
This only works reliably if the total executable size does not
exceed 64k.  The default is to use the \f(CW\*(C`basr\*(C'\fR instruction instead,
which does not have this limitation.
.Ip "\fB\-m64\fR" 4
.IX Item "-m64"
.PD 0
.Ip "\fB\-m31\fR" 4
.IX Item "-m31"
.PD
When \fB\-m31\fR is specified, generate code compliant to the
GNU/Linux for S/390 \s-1ABI\s0.  When \fB\-m64\fR is specified, generate
code compliant to the GNU/Linux for zSeries \s-1ABI\s0.  This allows \s-1GCC\s0 in
particular to generate 64\-bit instructions.  For the \fBs390\fR
targets, the default is \fB\-m31\fR, while the \fBs390x\fR
targets default to \fB\-m64\fR.
.Ip "\fB\-mzarch\fR" 4
.IX Item "-mzarch"
.PD 0
.Ip "\fB\-mesa\fR" 4
.IX Item "-mesa"
.PD
When \fB\-mzarch\fR is specified, generate code using the
instructions available on z/Architecture.
When \fB\-mesa\fR is specified, generate code using the
instructions available on \s-1ESA/390\s0. Note that \fB\-mesa\fR is
not possible with \fB\-m64\fR.
When generating code compliant to the GNU/Linux for S/390 \s-1ABI\s0,
the default is \fB\-mesa\fR.  When generating code compliant
to the GNU/Linux for zSeries \s-1ABI\s0, the default is \fB\-mzarch\fR.
.Ip "\fB\-mmvcle\fR" 4
.IX Item "-mmvcle"
.PD 0
.Ip "\fB\-mno-mvcle\fR" 4
.IX Item "-mno-mvcle"
.PD
Generate (or do not generate) code using the \f(CW\*(C`mvcle\*(C'\fR instruction
to perform block moves.  When \fB\-mno-mvcle\fR is specified,
use a \f(CW\*(C`mvc\*(C'\fR loop instead.  This is the default.
.Ip "\fB\-mdebug\fR" 4
.IX Item "-mdebug"
.PD 0
.Ip "\fB\-mno-debug\fR" 4
.IX Item "-mno-debug"
.PD
Print (or do not print) additional debug information when compiling.
The default is to not print debug information.
.Ip "\fB\-march=\fR\fIcpu-type\fR" 4
.IX Item "-march=cpu-type"
Generate code that will run on \fIcpu-type\fR, which is the name of a system
representing a certain processor type. Possible values for
\&\fIcpu-type\fR are \fBg5\fR, \fBg6\fR, \fBz900\fR, and \fBz990\fR.
When generating code using the instructions available on z/Architecture,
the default is \fB\-march=z900\fR.  Otherwise, the default is
\&\fB\-march=g5\fR.
.Ip "\fB\-mtune=\fR\fIcpu-type\fR" 4
.IX Item "-mtune=cpu-type"
Tune to \fIcpu-type\fR everything applicable about the generated code,
except for the \s-1ABI\s0 and the set of available instructions.
The list of \fIcpu-type\fR values is the same as for \fB\-march\fR.
The default is the value used for \fB\-march\fR.
.Ip "\fB\-mfused-madd\fR" 4
.IX Item "-mfused-madd"
.PD 0
.Ip "\fB\-mno-fused-madd\fR" 4
.IX Item "-mno-fused-madd"
.PD
Generate code that uses (does not use) the floating point multiply and
accumulate instructions.  These instructions are generated by default if
hardware floating point is used.
.PP
.I "\s-1CRIS\s0 Options"
.IX Subsection "CRIS Options"
.PP
These options are defined specifically for the \s-1CRIS\s0 ports.
.Ip "\fB\-march=\fR\fIarchitecture-type\fR" 4
.IX Item "-march=architecture-type"
.PD 0
.Ip "\fB\-mcpu=\fR\fIarchitecture-type\fR" 4
.IX Item "-mcpu=architecture-type"
.PD
Generate code for the specified architecture.  The choices for
\&\fIarchitecture-type\fR are \fBv3\fR, \fBv8\fR and \fBv10\fR for
respectively \s-1ETRAX\s0\ 4, \s-1ETRAX\s0\ 100, and \s-1ETRAX\s0\ 100\ \s-1LX\s0.
Default is \fBv0\fR except for cris-axis-linux-gnu, where the default is
\&\fBv10\fR.
.Ip "\fB\-mtune=\fR\fIarchitecture-type\fR" 4
.IX Item "-mtune=architecture-type"
Tune to \fIarchitecture-type\fR everything applicable about the generated
code, except for the \s-1ABI\s0 and the set of available instructions.  The
choices for \fIarchitecture-type\fR are the same as for
\&\fB\-march=\fR\fIarchitecture-type\fR.
.Ip "\fB\-mmax-stack-frame=\fR\fIn\fR" 4
.IX Item "-mmax-stack-frame=n"
Warn when the stack frame of a function exceeds \fIn\fR bytes.
.Ip "\fB\-melinux-stacksize=\fR\fIn\fR" 4
.IX Item "-melinux-stacksize=n"
Only available with the \fBcris-axis-aout\fR target.  Arranges for
indications in the program to the kernel loader that the stack of the
program should be set to \fIn\fR bytes.
.Ip "\fB\-metrax4\fR" 4
.IX Item "-metrax4"
.PD 0
.Ip "\fB\-metrax100\fR" 4
.IX Item "-metrax100"
.PD
The options \fB\-metrax4\fR and \fB\-metrax100\fR are synonyms for
\&\fB\-march=v3\fR and \fB\-march=v8\fR respectively.
.Ip "\fB\-mmul-bug-workaround\fR" 4
.IX Item "-mmul-bug-workaround"
.PD 0
.Ip "\fB\-mno-mul-bug-workaround\fR" 4
.IX Item "-mno-mul-bug-workaround"
.PD
Work around a bug in the \f(CW\*(C`muls\*(C'\fR and \f(CW\*(C`mulu\*(C'\fR instructions for \s-1CPU\s0
models where it applies.  This option is active by default.
.Ip "\fB\-mpdebug\fR" 4
.IX Item "-mpdebug"
Enable CRIS-specific verbose debug-related information in the assembly
code.  This option also has the effect to turn off the \fB#NO_APP\fR
formatted-code indicator to the assembler at the beginning of the
assembly file.
.Ip "\fB\-mcc-init\fR" 4
.IX Item "-mcc-init"
Do not use condition-code results from previous instruction; always emit
compare and test instructions before use of condition codes.
.Ip "\fB\-mno-side-effects\fR" 4
.IX Item "-mno-side-effects"
Do not emit instructions with side-effects in addressing modes other than
post-increment.
.Ip "\fB\-mstack-align\fR" 4
.IX Item "-mstack-align"
.PD 0
.Ip "\fB\-mno-stack-align\fR" 4
.IX Item "-mno-stack-align"
.Ip "\fB\-mdata-align\fR" 4
.IX Item "-mdata-align"
.Ip "\fB\-mno-data-align\fR" 4
.IX Item "-mno-data-align"
.Ip "\fB\-mconst-align\fR" 4
.IX Item "-mconst-align"
.Ip "\fB\-mno-const-align\fR" 4
.IX Item "-mno-const-align"
.PD
These options (no-options) arranges (eliminate arrangements) for the
stack-frame, individual data and constants to be aligned for the maximum
single data access size for the chosen \s-1CPU\s0 model.  The default is to
arrange for 32\-bit alignment.  \s-1ABI\s0 details such as structure layout are
not affected by these options.
.Ip "\fB\-m32\-bit\fR" 4
.IX Item "-m32-bit"
.PD 0
.Ip "\fB\-m16\-bit\fR" 4
.IX Item "-m16-bit"
.Ip "\fB\-m8\-bit\fR" 4
.IX Item "-m8-bit"
.PD
Similar to the stack- data- and const-align options above, these options
arrange for stack-frame, writable data and constants to all be 32\-bit,
16\-bit or 8\-bit aligned.  The default is 32\-bit alignment.
.Ip "\fB\-mno-prologue-epilogue\fR" 4
.IX Item "-mno-prologue-epilogue"
.PD 0
.Ip "\fB\-mprologue-epilogue\fR" 4
.IX Item "-mprologue-epilogue"
.PD
With \fB\-mno-prologue-epilogue\fR, the normal function prologue and
epilogue that sets up the stack-frame are omitted and no return
instructions or return sequences are generated in the code.  Use this
option only together with visual inspection of the compiled code: no
warnings or errors are generated when call-saved registers must be saved,
or storage for local variable needs to be allocated.
.Ip "\fB\-mno-gotplt\fR" 4
.IX Item "-mno-gotplt"
.PD 0
.Ip "\fB\-mgotplt\fR" 4
.IX Item "-mgotplt"
.PD
With \fB\-fpic\fR and \fB\-fPIC\fR, don't generate (do generate)
instruction sequences that load addresses for functions from the \s-1PLT\s0 part
of the \s-1GOT\s0 rather than (traditional on other architectures) calls to the
\&\s-1PLT\s0.  The default is \fB\-mgotplt\fR.
.Ip "\fB\-maout\fR" 4
.IX Item "-maout"
Legacy no-op option only recognized with the cris-axis-aout target.
.Ip "\fB\-melf\fR" 4
.IX Item "-melf"
Legacy no-op option only recognized with the cris-axis-elf and
cris-axis-linux-gnu targets.
.Ip "\fB\-melinux\fR" 4
.IX Item "-melinux"
Only recognized with the cris-axis-aout target, where it selects a
GNU/linux-like multilib, include files and instruction set for
\&\fB\-march=v8\fR.
.Ip "\fB\-mlinux\fR" 4
.IX Item "-mlinux"
Legacy no-op option only recognized with the cris-axis-linux-gnu target.
.Ip "\fB\-sim\fR" 4
.IX Item "-sim"
This option, recognized for the cris-axis-aout and cris-axis-elf arranges
to link with input-output functions from a simulator library.  Code,
initialized data and zero-initialized data are allocated consecutively.
.Ip "\fB\-sim2\fR" 4
.IX Item "-sim2"
Like \fB\-sim\fR, but pass linker options to locate initialized data at
0x40000000 and zero-initialized data at 0x80000000.
.PP
.I "\s-1MMIX\s0 Options"
.IX Subsection "MMIX Options"
.PP
These options are defined for the \s-1MMIX:\s0
.Ip "\fB\-mlibfuncs\fR" 4
.IX Item "-mlibfuncs"
.PD 0
.Ip "\fB\-mno-libfuncs\fR" 4
.IX Item "-mno-libfuncs"
.PD
Specify that intrinsic library functions are being compiled, passing all
values in registers, no matter the size.
.Ip "\fB\-mepsilon\fR" 4
.IX Item "-mepsilon"
.PD 0
.Ip "\fB\-mno-epsilon\fR" 4
.IX Item "-mno-epsilon"
.PD
Generate floating-point comparison instructions that compare with respect
to the \f(CW\*(C`rE\*(C'\fR epsilon register.
.Ip "\fB\-mabi=mmixware\fR" 4
.IX Item "-mabi=mmixware"
.PD 0
.Ip "\fB\-mabi=gnu\fR" 4
.IX Item "-mabi=gnu"
.PD
Generate code that passes function parameters and return values that (in
the called function) are seen as registers \f(CW\*(C`$0\*(C'\fR and up, as opposed to
the \s-1GNU\s0 \s-1ABI\s0 which uses global registers \f(CW\*(C`$231\*(C'\fR and up.
.Ip "\fB\-mzero-extend\fR" 4
.IX Item "-mzero-extend"
.PD 0
.Ip "\fB\-mno-zero-extend\fR" 4
.IX Item "-mno-zero-extend"
.PD
When reading data from memory in sizes shorter than 64 bits, use (do not
use) zero-extending load instructions by default, rather than
sign-extending ones.
.Ip "\fB\-mknuthdiv\fR" 4
.IX Item "-mknuthdiv"
.PD 0
.Ip "\fB\-mno-knuthdiv\fR" 4
.IX Item "-mno-knuthdiv"
.PD
Make the result of a division yielding a remainder have the same sign as
the divisor.  With the default, \fB\-mno-knuthdiv\fR, the sign of the
remainder follows the sign of the dividend.  Both methods are
arithmetically valid, the latter being almost exclusively used.
.Ip "\fB\-mtoplevel-symbols\fR" 4
.IX Item "-mtoplevel-symbols"
.PD 0
.Ip "\fB\-mno-toplevel-symbols\fR" 4
.IX Item "-mno-toplevel-symbols"
.PD
Prepend (do not prepend) a \fB:\fR to all global symbols, so the assembly
code can be used with the \f(CW\*(C`PREFIX\*(C'\fR assembly directive.
.Ip "\fB\-melf\fR" 4
.IX Item "-melf"
Generate an executable in the \s-1ELF\s0 format, rather than the default
\&\fBmmo\fR format used by the \fBmmix\fR simulator.
.Ip "\fB\-mbranch-predict\fR" 4
.IX Item "-mbranch-predict"
.PD 0
.Ip "\fB\-mno-branch-predict\fR" 4
.IX Item "-mno-branch-predict"
.PD
Use (do not use) the probable-branch instructions, when static branch
prediction indicates a probable branch.
.Ip "\fB\-mbase-addresses\fR" 4
.IX Item "-mbase-addresses"
.PD 0
.Ip "\fB\-mno-base-addresses\fR" 4
.IX Item "-mno-base-addresses"
.PD
Generate (do not generate) code that uses \fIbase addresses\fR.  Using a
base address automatically generates a request (handled by the assembler
and the linker) for a constant to be set up in a global register.  The
register is used for one or more base address requests within the range 0
to 255 from the value held in the register.  The generally leads to short
and fast code, but the number of different data items that can be
addressed is limited.  This means that a program that uses lots of static
data may require \fB\-mno-base-addresses\fR.
.Ip "\fB\-msingle-exit\fR" 4
.IX Item "-msingle-exit"
.PD 0
.Ip "\fB\-mno-single-exit\fR" 4
.IX Item "-mno-single-exit"
.PD
Force (do not force) generated code to have a single exit point in each
function.
.PP
.I "\s-1PDP-11\s0 Options"
.IX Subsection "PDP-11 Options"
.PP
These options are defined for the \s-1PDP-11:\s0
.Ip "\fB\-mfpu\fR" 4
.IX Item "-mfpu"
Use hardware \s-1FPP\s0 floating point.  This is the default.  (\s-1FIS\s0 floating
point on the \s-1PDP-11/40\s0 is not supported.)
.Ip "\fB\-msoft-float\fR" 4
.IX Item "-msoft-float"
Do not use hardware floating point.
.Ip "\fB\-mac0\fR" 4
.IX Item "-mac0"
Return floating-point results in ac0 (fr0 in Unix assembler syntax).
.Ip "\fB\-mno-ac0\fR" 4
.IX Item "-mno-ac0"
Return floating-point results in memory.  This is the default.
.Ip "\fB\-m40\fR" 4
.IX Item "-m40"
Generate code for a \s-1PDP-11/40\s0.
.Ip "\fB\-m45\fR" 4
.IX Item "-m45"
Generate code for a \s-1PDP-11/45\s0.  This is the default.
.Ip "\fB\-m10\fR" 4
.IX Item "-m10"
Generate code for a \s-1PDP-11/10\s0.
.Ip "\fB\-mbcopy-builtin\fR" 4
.IX Item "-mbcopy-builtin"
Use inline \f(CW\*(C`movstrhi\*(C'\fR patterns for copying memory.  This is the
default.
.Ip "\fB\-mbcopy\fR" 4
.IX Item "-mbcopy"
Do not use inline \f(CW\*(C`movstrhi\*(C'\fR patterns for copying memory.
.Ip "\fB\-mint16\fR" 4
.IX Item "-mint16"
.PD 0
.Ip "\fB\-mno-int32\fR" 4
.IX Item "-mno-int32"
.PD
Use 16\-bit \f(CW\*(C`int\*(C'\fR.  This is the default.
.Ip "\fB\-mint32\fR" 4
.IX Item "-mint32"
.PD 0
.Ip "\fB\-mno-int16\fR" 4
.IX Item "-mno-int16"
.PD
Use 32\-bit \f(CW\*(C`int\*(C'\fR.
.Ip "\fB\-mfloat64\fR" 4
.IX Item "-mfloat64"
.PD 0
.Ip "\fB\-mno-float32\fR" 4
.IX Item "-mno-float32"
.PD
Use 64\-bit \f(CW\*(C`float\*(C'\fR.  This is the default.
.Ip "\fB\-mfloat32\fR" 4
.IX Item "-mfloat32"
.PD 0
.Ip "\fB\-mno-float64\fR" 4
.IX Item "-mno-float64"
.PD
Use 32\-bit \f(CW\*(C`float\*(C'\fR.
.Ip "\fB\-mabshi\fR" 4
.IX Item "-mabshi"
Use \f(CW\*(C`abshi2\*(C'\fR pattern.  This is the default.
.Ip "\fB\-mno-abshi\fR" 4
.IX Item "-mno-abshi"
Do not use \f(CW\*(C`abshi2\*(C'\fR pattern.
.Ip "\fB\-mbranch-expensive\fR" 4
.IX Item "-mbranch-expensive"
Pretend that branches are expensive.  This is for experimenting with
code generation only.
.Ip "\fB\-mbranch-cheap\fR" 4
.IX Item "-mbranch-cheap"
Do not pretend that branches are expensive.  This is the default.
.Ip "\fB\-msplit\fR" 4
.IX Item "-msplit"
Generate code for a system with split I&D.
.Ip "\fB\-mno-split\fR" 4
.IX Item "-mno-split"
Generate code for a system without split I&D.  This is the default.
.Ip "\fB\-munix-asm\fR" 4
.IX Item "-munix-asm"
Use Unix assembler syntax.  This is the default when configured for
\&\fBpdp11\-*\-bsd\fR.
.Ip "\fB\-mdec-asm\fR" 4
.IX Item "-mdec-asm"
Use \s-1DEC\s0 assembler syntax.  This is the default when configured for any
\&\s-1PDP-11\s0 target other than \fBpdp11\-*\-bsd\fR.
.PP
.I "Xstormy16 Options"
.IX Subsection "Xstormy16 Options"
.PP
These options are defined for Xstormy16:
.Ip "\fB\-msim\fR" 4
.IX Item "-msim"
Choose startup files and linker script suitable for the simulator.
.PP
.I "\s-1FRV\s0 Options"
.IX Subsection "FRV Options"
.Ip "\fB\-mgpr-32\fR" 4
.IX Item "-mgpr-32"
Only use the first 32 general purpose registers.
.Ip "\fB\-mgpr-64\fR" 4
.IX Item "-mgpr-64"
Use all 64 general purpose registers.
.Ip "\fB\-mfpr-32\fR" 4
.IX Item "-mfpr-32"
Use only the first 32 floating point registers.
.Ip "\fB\-mfpr-64\fR" 4
.IX Item "-mfpr-64"
Use all 64 floating point registers
.Ip "\fB\-mhard-float\fR" 4
.IX Item "-mhard-float"
Use hardware instructions for floating point operations.
.Ip "\fB\-msoft-float\fR" 4
.IX Item "-msoft-float"
Use library routines for floating point operations.
.Ip "\fB\-malloc-cc\fR" 4
.IX Item "-malloc-cc"
Dynamically allocate condition code registers.
.Ip "\fB\-mfixed-cc\fR" 4
.IX Item "-mfixed-cc"
Do not try to dynamically allocate condition code registers, only
use \f(CW\*(C`icc0\*(C'\fR and \f(CW\*(C`fcc0\*(C'\fR.
.Ip "\fB\-mdword\fR" 4
.IX Item "-mdword"
Change \s-1ABI\s0 to use double word insns.
.Ip "\fB\-mno-dword\fR" 4
.IX Item "-mno-dword"
Do not use double word instructions.
.Ip "\fB\-mdouble\fR" 4
.IX Item "-mdouble"
Use floating point double instructions.
.Ip "\fB\-mno-double\fR" 4
.IX Item "-mno-double"
Do not use floating point double instructions.
.Ip "\fB\-mmedia\fR" 4
.IX Item "-mmedia"
Use media instructions.
.Ip "\fB\-mno-media\fR" 4
.IX Item "-mno-media"
Do not use media instructions.
.Ip "\fB\-mmuladd\fR" 4
.IX Item "-mmuladd"
Use multiply and add/subtract instructions.
.Ip "\fB\-mno-muladd\fR" 4
.IX Item "-mno-muladd"
Do not use multiply and add/subtract instructions.
.Ip "\fB\-mlibrary-pic\fR" 4
.IX Item "-mlibrary-pic"
Enable \s-1PIC\s0 support for building libraries
.Ip "\fB\-macc-4\fR" 4
.IX Item "-macc-4"
Use only the first four media accumulator registers.
.Ip "\fB\-macc-8\fR" 4
.IX Item "-macc-8"
Use all eight media accumulator registers.
.Ip "\fB\-mpack\fR" 4
.IX Item "-mpack"
Pack \s-1VLIW\s0 instructions.
.Ip "\fB\-mno-pack\fR" 4
.IX Item "-mno-pack"
Do not pack \s-1VLIW\s0 instructions.
.Ip "\fB\-mno-eflags\fR" 4
.IX Item "-mno-eflags"
Do not mark \s-1ABI\s0 switches in e_flags.
.Ip "\fB\-mcond-move\fR" 4
.IX Item "-mcond-move"
Enable the use of conditional-move instructions (default).
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.Ip "\fB\-mno-cond-move\fR" 4
.IX Item "-mno-cond-move"
Disable the use of conditional-move instructions.
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.Ip "\fB\-mscc\fR" 4
.IX Item "-mscc"
Enable the use of conditional set instructions (default).
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.Ip "\fB\-mno-scc\fR" 4
.IX Item "-mno-scc"
Disable the use of conditional set instructions.
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.Ip "\fB\-mcond-exec\fR" 4
.IX Item "-mcond-exec"
Enable the use of conditional execution (default).
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.Ip "\fB\-mno-cond-exec\fR" 4
.IX Item "-mno-cond-exec"
Disable the use of conditional execution.
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.Ip "\fB\-mvliw-branch\fR" 4
.IX Item "-mvliw-branch"
Run a pass to pack branches into \s-1VLIW\s0 instructions (default).
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.Ip "\fB\-mno-vliw-branch\fR" 4
.IX Item "-mno-vliw-branch"
Do not run a pass to pack branches into \s-1VLIW\s0 instructions.
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.Ip "\fB\-mmulti-cond-exec\fR" 4
.IX Item "-mmulti-cond-exec"
Enable optimization of \f(CW\*(C`&&\*(C'\fR and \f(CW\*(C`||\*(C'\fR in conditional execution
(default).
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.Ip "\fB\-mno-multi-cond-exec\fR" 4
.IX Item "-mno-multi-cond-exec"
Disable optimization of \f(CW\*(C`&&\*(C'\fR and \f(CW\*(C`||\*(C'\fR in conditional execution.
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.Ip "\fB\-mnested-cond-exec\fR" 4
.IX Item "-mnested-cond-exec"
Enable nested conditional execution optimizations (default).
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.Ip "\fB\-mno-nested-cond-exec\fR" 4
.IX Item "-mno-nested-cond-exec"
Disable nested conditional execution optimizations.
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.Ip "\fB\-mtomcat-stats\fR" 4
.IX Item "-mtomcat-stats"
Cause gas to print out tomcat statistics.
.Ip "\fB\-mcpu=\fR\fIcpu\fR" 4
.IX Item "-mcpu=cpu"
Select the processor type for which to generate code.  Possible values are
\&\fBsimple\fR, \fBtomcat\fR, \fBfr500\fR, \fBfr400\fR, \fBfr300\fR,
\&\fBfrv\fR.
.PP
.I "Xtensa Options"
.IX Subsection "Xtensa Options"
.PP
These options are supported for Xtensa targets:
.Ip "\fB\-mconst16\fR" 4
.IX Item "-mconst16"
.PD 0
.Ip "\fB\-mno-const16\fR" 4
.IX Item "-mno-const16"
.PD
Enable or disable use of \f(CW\*(C`CONST16\*(C'\fR instructions for loading
constant values.  The \f(CW\*(C`CONST16\*(C'\fR instruction is currently not a
standard option from Tensilica.  When enabled, \f(CW\*(C`CONST16\*(C'\fR
instructions are always used in place of the standard \f(CW\*(C`L32R\*(C'\fR
instructions.  The use of \f(CW\*(C`CONST16\*(C'\fR is enabled by default only if
the \f(CW\*(C`L32R\*(C'\fR instruction is not available.
.Ip "\fB\-mfused-madd\fR" 4
.IX Item "-mfused-madd"
.PD 0
.Ip "\fB\-mno-fused-madd\fR" 4
.IX Item "-mno-fused-madd"
.PD
Enable or disable use of fused multiply/add and multiply/subtract
instructions in the floating-point option.  This has no effect if the
floating-point option is not also enabled.  Disabling fused multiply/add
and multiply/subtract instructions forces the compiler to use separate
instructions for the multiply and add/subtract operations.  This may be
desirable in some cases where strict \s-1IEEE\s0 754\-compliant results are
required: the fused multiply add/subtract instructions do not round the
intermediate result, thereby producing results with \fImore\fR bits of
precision than specified by the \s-1IEEE\s0 standard.  Disabling fused multiply
add/subtract instructions also ensures that the program output is not
sensitive to the compiler's ability to combine multiply and add/subtract
operations.
.Ip "\fB\-mtext-section-literals\fR" 4
.IX Item "-mtext-section-literals"
.PD 0
.Ip "\fB\-mno-text-section-literals\fR" 4
.IX Item "-mno-text-section-literals"
.PD
Control the treatment of literal pools.  The default is
\&\fB\-mno-text-section-literals\fR, which places literals in a separate
section in the output file.  This allows the literal pool to be placed
in a data \s-1RAM/ROM\s0, and it also allows the linker to combine literal
pools from separate object files to remove redundant literals and
improve code size.  With \fB\-mtext-section-literals\fR, the literals
are interspersed in the text section in order to keep them as close as
possible to their references.  This may be necessary for large assembly
files.
.Ip "\fB\-mtarget-align\fR" 4
.IX Item "-mtarget-align"
.PD 0
.Ip "\fB\-mno-target-align\fR" 4
.IX Item "-mno-target-align"
.PD
When this option is enabled, \s-1GCC\s0 instructs the assembler to
automatically align instructions to reduce branch penalties at the
expense of some code density.  The assembler attempts to widen density
instructions to align branch targets and the instructions following call
instructions.  If there are not enough preceding safe density
instructions to align a target, no widening will be performed.  The
default is \fB\-mtarget-align\fR.  These options do not affect the
treatment of auto-aligned instructions like \f(CW\*(C`LOOP\*(C'\fR, which the
assembler will always align, either by widening density instructions or
by inserting no-op instructions.
.Ip "\fB\-mlongcalls\fR" 4
.IX Item "-mlongcalls"
.PD 0
.Ip "\fB\-mno-longcalls\fR" 4
.IX Item "-mno-longcalls"
.PD
When this option is enabled, \s-1GCC\s0 instructs the assembler to translate
direct calls to indirect calls unless it can determine that the target
of a direct call is in the range allowed by the call instruction.  This
translation typically occurs for calls to functions in other source
files.  Specifically, the assembler translates a direct \f(CW\*(C`CALL\*(C'\fR
instruction into an \f(CW\*(C`L32R\*(C'\fR followed by a \f(CW\*(C`CALLX\*(C'\fR instruction.
The default is \fB\-mno-longcalls\fR.  This option should be used in
programs where the call target can potentially be out of range.  This
option is implemented in the assembler, not the compiler, so the
assembly code generated by \s-1GCC\s0 will still show direct call
instructions\-\-\-look at the disassembled object code to see the actual
instructions.  Note that the assembler will use an indirect call for
every cross-file call, not just those that really will be out of range.
.Sh "Options for Code Generation Conventions"
.IX Subsection "Options for Code Generation Conventions"
These machine-independent options control the interface conventions
used in code generation.
.PP
Most of them have both positive and negative forms; the negative form
of \fB\-ffoo\fR would be \fB\-fno-foo\fR.  In the table below, only
one of the forms is listed\-\-\-the one which is not the default.  You
can figure out the other form by either removing \fBno-\fR or adding
it.
.Ip "\fB\-fbounds-check\fR" 4
.IX Item "-fbounds-check"
For front-ends that support it, generate additional code to check that
indices used to access arrays are within the declared range.  This is
currently only supported by the Java and Fortran 77 front-ends, where
this option defaults to true and false respectively.
.Ip "\fB\-ftrapv\fR" 4
.IX Item "-ftrapv"
This option generates traps for signed overflow on addition, subtraction,
multiplication operations.
.Ip "\fB\-fwrapv\fR" 4
.IX Item "-fwrapv"
This option instructs the compiler to assume that signed arithmetic
overflow of addition, subtraction and multiplication wraps around
using twos-complement representation.  This flag enables some optimizations
and disables other.  This option is enabled by default for the Java
front-end, as required by the Java language specification.
.Ip "\fB\-fexceptions\fR" 4
.IX Item "-fexceptions"
Enable exception handling.  Generates extra code needed to propagate
exceptions.  For some targets, this implies \s-1GCC\s0 will generate frame
unwind information for all functions, which can produce significant data
size overhead, although it does not affect execution.  If you do not
specify this option, \s-1GCC\s0 will enable it by default for languages like
\&\*(C+ which normally require exception handling, and disable it for
languages like C that do not normally require it.  However, you may need
to enable this option when compiling C code that needs to interoperate
properly with exception handlers written in \*(C+.  You may also wish to
disable this option if you are compiling older \*(C+ programs that don't
use exception handling.
.Ip "\fB\-fnon-call-exceptions\fR" 4
.IX Item "-fnon-call-exceptions"
Generate code that allows trapping instructions to throw exceptions.
Note that this requires platform-specific runtime support that does
not exist everywhere.  Moreover, it only allows \fItrapping\fR
instructions to throw exceptions, i.e. memory references or floating
point instructions.  It does not allow exceptions to be thrown from
arbitrary signal handlers such as \f(CW\*(C`SIGALRM\*(C'\fR.
.Ip "\fB\-funwind-tables\fR" 4
.IX Item "-funwind-tables"
Similar to \fB\-fexceptions\fR, except that it will just generate any needed
static data, but will not affect the generated code in any other way.
You will normally not enable this option; instead, a language processor
that needs this handling would enable it on your behalf.
.Ip "\fB\-fasynchronous-unwind-tables\fR" 4
.IX Item "-fasynchronous-unwind-tables"
Generate unwind table in dwarf2 format, if supported by target machine.  The
table is exact at each instruction boundary, so it can be used for stack
unwinding from asynchronous events (such as debugger or garbage collector).
.Ip "\fB\-fpcc-struct-return\fR" 4
.IX Item "-fpcc-struct-return"
Return ``short'' \f(CW\*(C`struct\*(C'\fR and \f(CW\*(C`union\*(C'\fR values in memory like
longer ones, rather than in registers.  This convention is less
efficient, but it has the advantage of allowing intercallability between
GCC-compiled files and files compiled with other compilers, particularly
the Portable C Compiler (pcc).
.Sp
The precise convention for returning structures in memory depends
on the target configuration macros.
.Sp
Short structures and unions are those whose size and alignment match
that of some integer type.
.Sp
\&\fBWarning:\fR code compiled with the \fB\-fpcc-struct-return\fR
switch is not binary compatible with code compiled with the
\&\fB\-freg-struct-return\fR switch.
Use it to conform to a non-default application binary interface.
.Ip "\fB\-freg-struct-return\fR" 4
.IX Item "-freg-struct-return"
Return \f(CW\*(C`struct\*(C'\fR and \f(CW\*(C`union\*(C'\fR values in registers when possible.
This is more efficient for small structures than
\&\fB\-fpcc-struct-return\fR.
.Sp
If you specify neither \fB\-fpcc-struct-return\fR nor
\&\fB\-freg-struct-return\fR, \s-1GCC\s0 defaults to whichever convention is
standard for the target.  If there is no standard convention, \s-1GCC\s0
defaults to \fB\-fpcc-struct-return\fR, except on targets where \s-1GCC\s0 is
the principal compiler.  In those cases, we can choose the standard, and
we chose the more efficient register return alternative.
.Sp
\&\fBWarning:\fR code compiled with the \fB\-freg-struct-return\fR
switch is not binary compatible with code compiled with the
\&\fB\-fpcc-struct-return\fR switch.
Use it to conform to a non-default application binary interface.
.Ip "\fB\-fshort-enums\fR" 4
.IX Item "-fshort-enums"
Allocate to an \f(CW\*(C`enum\*(C'\fR type only as many bytes as it needs for the
declared range of possible values.  Specifically, the \f(CW\*(C`enum\*(C'\fR type
will be equivalent to the smallest integer type which has enough room.
.Sp
\&\fBWarning:\fR the \fB\-fshort-enums\fR switch causes \s-1GCC\s0 to generate
code that is not binary compatible with code generated without that switch.
Use it to conform to a non-default application binary interface.
.Ip "\fB\-fshort-double\fR" 4
.IX Item "-fshort-double"
Use the same size for \f(CW\*(C`double\*(C'\fR as for \f(CW\*(C`float\*(C'\fR.
.Sp
\&\fBWarning:\fR the \fB\-fshort-double\fR switch causes \s-1GCC\s0 to generate
code that is not binary compatible with code generated without that switch.
Use it to conform to a non-default application binary interface.
.Ip "\fB\-fshort-wchar\fR" 4
.IX Item "-fshort-wchar"
Override the underlying type for \fBwchar_t\fR to be \fBshort
unsigned int\fR instead of the default for the target.  This option is
useful for building programs to run under \s-1WINE\s0.
.Sp
\&\fBWarning:\fR the \fB\-fshort-wchar\fR switch causes \s-1GCC\s0 to generate
code that is not binary compatible with code generated without that switch.
Use it to conform to a non-default application binary interface.
.Ip "\fB\-fshared-data\fR" 4
.IX Item "-fshared-data"
Requests that the data and non-\f(CW\*(C`const\*(C'\fR variables of this
compilation be shared data rather than private data.  The distinction
makes sense only on certain operating systems, where shared data is
shared between processes running the same program, while private data
exists in one copy per process.
.Ip "\fB\-fno-common\fR" 4
.IX Item "-fno-common"
In C, allocate even uninitialized global variables in the data section of the
object file, rather than generating them as common blocks.  This has the
effect that if the same variable is declared (without \f(CW\*(C`extern\*(C'\fR) in
two different compilations, you will get an error when you link them.
The only reason this might be useful is if you wish to verify that the
program will work on other systems which always work this way.
.Ip "\fB\-fno-ident\fR" 4
.IX Item "-fno-ident"
Ignore the \fB#ident\fR directive.
.Ip "\fB\-finhibit-size-directive\fR" 4
.IX Item "-finhibit-size-directive"
Don't output a \f(CW\*(C`.size\*(C'\fR assembler directive, or anything else that
would cause trouble if the function is split in the middle, and the
two halves are placed at locations far apart in memory.  This option is
used when compiling \fIcrtstuff.c\fR; you should not need to use it
for anything else.
.Ip "\fB\-fverbose-asm\fR" 4
.IX Item "-fverbose-asm"
Put extra commentary information in the generated assembly code to
make it more readable.  This option is generally only of use to those
who actually need to read the generated assembly code (perhaps while
debugging the compiler itself).
.Sp
\&\fB\-fno-verbose-asm\fR, the default, causes the
extra information to be omitted and is useful when comparing two assembler
files.
.Ip "\fB\-fpic\fR" 4
.IX Item "-fpic"
Generate position-independent code (\s-1PIC\s0) suitable for use in a shared
library, if supported for the target machine.  Such code accesses all
constant addresses through a global offset table (\s-1GOT\s0).  The dynamic
loader resolves the \s-1GOT\s0 entries when the program starts (the dynamic
loader is not part of \s-1GCC\s0; it is part of the operating system).  If
the \s-1GOT\s0 size for the linked executable exceeds a machine-specific
maximum size, you get an error message from the linker indicating that
\&\fB\-fpic\fR does not work; in that case, recompile with \fB\-fPIC\fR
instead.  (These maximums are 8k on the \s-1SPARC\s0 and 32k
on the m68k and \s-1RS/6000\s0.  The 386 has no such limit.)
.Sp
Position-independent code requires special support, and therefore works
only on certain machines.  For the 386, \s-1GCC\s0 supports \s-1PIC\s0 for System V
but not for the Sun 386i.  Code generated for the \s-1IBM\s0 \s-1RS/6000\s0 is always
position-independent.
.Ip "\fB\-fPIC\fR" 4
.IX Item "-fPIC"
If supported for the target machine, emit position-independent code,
suitable for dynamic linking and avoiding any limit on the size of the
global offset table.  This option makes a difference on the m68k
and the \s-1SPARC\s0.
.Sp
Position-independent code requires special support, and therefore works
only on certain machines.
.Ip "\fB\-fpie\fR" 4
.IX Item "-fpie"
.PD 0
.Ip "\fB\-fPIE\fR" 4
.IX Item "-fPIE"
.PD
These options are similar to \fB\-fpic\fR and \fB\-fPIC\fR, but
generated position independent code can be only linked into executables.
Usually these options are used when \fB\-pie\fR \s-1GCC\s0 option will be
used during linking.
.Ip "\fB\-ffixed-\fR\fIreg\fR" 4
.IX Item "-ffixed-reg"
Treat the register named \fIreg\fR as a fixed register; generated code
should never refer to it (except perhaps as a stack pointer, frame
pointer or in some other fixed role).
.Sp
\&\fIreg\fR must be the name of a register.  The register names accepted
are machine-specific and are defined in the \f(CW\*(C`REGISTER_NAMES\*(C'\fR
macro in the machine description macro file.
.Sp
This flag does not have a negative form, because it specifies a
three-way choice.
.Ip "\fB\-fcall-used-\fR\fIreg\fR" 4
.IX Item "-fcall-used-reg"
Treat the register named \fIreg\fR as an allocable register that is
clobbered by function calls.  It may be allocated for temporaries or
variables that do not live across a call.  Functions compiled this way
will not save and restore the register \fIreg\fR.
.Sp
It is an error to used this flag with the frame pointer or stack pointer.
Use of this flag for other registers that have fixed pervasive roles in
the machine's execution model will produce disastrous results.
.Sp
This flag does not have a negative form, because it specifies a
three-way choice.
.Ip "\fB\-fcall-saved-\fR\fIreg\fR" 4
.IX Item "-fcall-saved-reg"
Treat the register named \fIreg\fR as an allocable register saved by
functions.  It may be allocated even for temporaries or variables that
live across a call.  Functions compiled this way will save and restore
the register \fIreg\fR if they use it.
.Sp
It is an error to used this flag with the frame pointer or stack pointer.
Use of this flag for other registers that have fixed pervasive roles in
the machine's execution model will produce disastrous results.
.Sp
A different sort of disaster will result from the use of this flag for
a register in which function values may be returned.
.Sp
This flag does not have a negative form, because it specifies a
three-way choice.
.Ip "\fB\-fpack-struct\fR" 4
.IX Item "-fpack-struct"
Pack all structure members together without holes.
.Sp
\&\fBWarning:\fR the \fB\-fpack-struct\fR switch causes \s-1GCC\s0 to generate
code that is not binary compatible with code generated without that switch.
Additionally, it makes the code suboptimal.
Use it to conform to a non-default application binary interface.
.Ip "\fB\-finstrument-functions\fR" 4
.IX Item "-finstrument-functions"
Generate instrumentation calls for entry and exit to functions.  Just
after function entry and just before function exit, the following
profiling functions will be called with the address of the current
function and its call site.  (On some platforms,
\&\f(CW\*(C`_\|_builtin_return_address\*(C'\fR does not work beyond the current
function, so the call site information may not be available to the
profiling functions otherwise.)
.Sp
.Vb 4
\&        void __cyg_profile_func_enter (void *this_fn,
\&                                       void *call_site);
\&        void __cyg_profile_func_exit  (void *this_fn,
\&                                       void *call_site);
.Ve
The first argument is the address of the start of the current function,
which may be looked up exactly in the symbol table.
.Sp
This currently disables function inlining.  This restriction is
expected to be removed in future releases.
.Sp
A function may be given the attribute \f(CW\*(C`no_instrument_function\*(C'\fR, in
which case this instrumentation will not be done.  This can be used, for
example, for the profiling functions listed above, high-priority
interrupt routines, and any functions from which the profiling functions
cannot safely be called (perhaps signal handlers, if the profiling
routines generate output or allocate memory).
.Ip "\fB\-fstack-check\fR" 4
.IX Item "-fstack-check"
Generate code to verify that you do not go beyond the boundary of the
stack.  You should specify this flag if you are running in an
environment with multiple threads, but only rarely need to specify it in
a single-threaded environment since stack overflow is automatically
detected on nearly all systems if there is only one stack.
.Sp
Note that this switch does not actually cause checking to be done; the
operating system must do that.  The switch causes generation of code
to ensure that the operating system sees the stack being extended.
.Ip "\fB\-fstack-limit-register=\fR\fIreg\fR" 4
.IX Item "-fstack-limit-register=reg"
.PD 0
.Ip "\fB\-fstack-limit-symbol=\fR\fIsym\fR" 4
.IX Item "-fstack-limit-symbol=sym"
.Ip "\fB\-fno-stack-limit\fR" 4
.IX Item "-fno-stack-limit"
.PD
Generate code to ensure that the stack does not grow beyond a certain value,
either the value of a register or the address of a symbol.  If the stack
would grow beyond the value, a signal is raised.  For most targets,
the signal is raised before the stack overruns the boundary, so
it is possible to catch the signal without taking special precautions.
.Sp
For instance, if the stack starts at absolute address \fB0x80000000\fR
and grows downwards, you can use the flags
\&\fB\-fstack-limit-symbol=_\|_stack_limit\fR and
\&\fB\-Wl,\-\-defsym,_\|_stack_limit=0x7ffe0000\fR to enforce a stack limit
of 128KB.  Note that this may only work with the \s-1GNU\s0 linker.
.Ip "\fB\-fargument-alias\fR" 4
.IX Item "-fargument-alias"
.PD 0
.Ip "\fB\-fargument-noalias\fR" 4
.IX Item "-fargument-noalias"
.Ip "\fB\-fargument-noalias-global\fR" 4
.IX Item "-fargument-noalias-global"
.PD
Specify the possible relationships among parameters and between
parameters and global data.
.Sp
\&\fB\-fargument-alias\fR specifies that arguments (parameters) may
alias each other and may alias global storage.\fB\-fargument-noalias\fR specifies that arguments do not alias
each other, but may alias global storage.\fB\-fargument-noalias-global\fR specifies that arguments do not
alias each other and do not alias global storage.
.Sp
Each language will automatically use whatever option is required by
the language standard.  You should not need to use these options yourself.
.Ip "\fB\-fleading-underscore\fR" 4
.IX Item "-fleading-underscore"
This option and its counterpart, \fB\-fno-leading-underscore\fR, forcibly
change the way C symbols are represented in the object file.  One use
is to help link with legacy assembly code.
.Sp
\&\fBWarning:\fR the \fB\-fleading-underscore\fR switch causes \s-1GCC\s0 to
generate code that is not binary compatible with code generated without that
switch.  Use it to conform to a non-default application binary interface.
Not all targets provide complete support for this switch.
.Ip "\fB\-ftls-model=\fR\fImodel\fR" 4
.IX Item "-ftls-model=model"
Alter the thread-local storage model to be used.
The \fImodel\fR argument should be one of \f(CW\*(C`global\-dynamic\*(C'\fR,
\&\f(CW\*(C`local\-dynamic\*(C'\fR, \f(CW\*(C`initial\-exec\*(C'\fR or \f(CW\*(C`local\-exec\*(C'\fR.
.Sp
The default without \fB\-fpic\fR is \f(CW\*(C`initial\-exec\*(C'\fR; with
\&\fB\-fpic\fR the default is \f(CW\*(C`global\-dynamic\*(C'\fR.
.SH "ENVIRONMENT"
.IX Header "ENVIRONMENT"
This section describes several environment variables that affect how \s-1GCC\s0
operates.  Some of them work by specifying directories or prefixes to use
when searching for various kinds of files.  Some are used to specify other
aspects of the compilation environment.
.PP
Note that you can also specify places to search using options such as
\&\fB\-B\fR, \fB\-I\fR and \fB\-L\fR.  These
take precedence over places specified using environment variables, which
in turn take precedence over those specified by the configuration of \s-1GCC\s0.
.Ip "\fB\s-1LANG\s0\fR" 4
.IX Item "LANG"
.PD 0
.Ip "\fB\s-1LC_CTYPE\s0\fR" 4
.IX Item "LC_CTYPE"
.Ip "\fB\s-1LC_MESSAGES\s0\fR" 4
.IX Item "LC_MESSAGES"
.Ip "\fB\s-1LC_ALL\s0\fR" 4
.IX Item "LC_ALL"
.PD
These environment variables control the way that \s-1GCC\s0 uses
localization information that allow \s-1GCC\s0 to work with different
national conventions.  \s-1GCC\s0 inspects the locale categories
\&\fB\s-1LC_CTYPE\s0\fR and \fB\s-1LC_MESSAGES\s0\fR if it has been configured to do
so.  These locale categories can be set to any value supported by your
installation.  A typical value is \fBen_UK\fR for English in the United
Kingdom.
.Sp
The \fB\s-1LC_CTYPE\s0\fR environment variable specifies character
classification.  \s-1GCC\s0 uses it to determine the character boundaries in
a string; this is needed for some multibyte encodings that contain quote
and escape characters that would otherwise be interpreted as a string
end or escape.
.Sp
The \fB\s-1LC_MESSAGES\s0\fR environment variable specifies the language to
use in diagnostic messages.
.Sp
If the \fB\s-1LC_ALL\s0\fR environment variable is set, it overrides the value
of \fB\s-1LC_CTYPE\s0\fR and \fB\s-1LC_MESSAGES\s0\fR; otherwise, \fB\s-1LC_CTYPE\s0\fR
and \fB\s-1LC_MESSAGES\s0\fR default to the value of the \fB\s-1LANG\s0\fR
environment variable.  If none of these variables are set, \s-1GCC\s0
defaults to traditional C English behavior.
.Ip "\fB\s-1TMPDIR\s0\fR" 4
.IX Item "TMPDIR"
If \fB\s-1TMPDIR\s0\fR is set, it specifies the directory to use for temporary
files.  \s-1GCC\s0 uses temporary files to hold the output of one stage of
compilation which is to be used as input to the next stage: for example,
the output of the preprocessor, which is the input to the compiler
proper.
.Ip "\fB\s-1GCC_EXEC_PREFIX\s0\fR" 4
.IX Item "GCC_EXEC_PREFIX"
If \fB\s-1GCC_EXEC_PREFIX\s0\fR is set, it specifies a prefix to use in the
names of the subprograms executed by the compiler.  No slash is added
when this prefix is combined with the name of a subprogram, but you can
specify a prefix that ends with a slash if you wish.
.Sp
If \fB\s-1GCC_EXEC_PREFIX\s0\fR is not set, \s-1GCC\s0 will attempt to figure out
an appropriate prefix to use based on the pathname it was invoked with.
.Sp
If \s-1GCC\s0 cannot find the subprogram using the specified prefix, it
tries looking in the usual places for the subprogram.
.Sp
The default value of \fB\s-1GCC_EXEC_PREFIX\s0\fR is
\&\fI\fIprefix\fI/lib/gcc/\fR where \fIprefix\fR is the value
of \f(CW\*(C`prefix\*(C'\fR when you ran the \fIconfigure\fR script.
.Sp
Other prefixes specified with \fB\-B\fR take precedence over this prefix.
.Sp
This prefix is also used for finding files such as \fIcrt0.o\fR that are
used for linking.
.Sp
In addition, the prefix is used in an unusual way in finding the
directories to search for header files.  For each of the standard
directories whose name normally begins with \fB/usr/local/lib/gcc\fR
(more precisely, with the value of \fB\s-1GCC_INCLUDE_DIR\s0\fR), \s-1GCC\s0 tries
replacing that beginning with the specified prefix to produce an
alternate directory name.  Thus, with \fB\-Bfoo/\fR, \s-1GCC\s0 will search
\&\fIfoo/bar\fR where it would normally search \fI/usr/local/lib/bar\fR.
These alternate directories are searched first; the standard directories
come next.
.Ip "\fB\s-1COMPILER_PATH\s0\fR" 4
.IX Item "COMPILER_PATH"
The value of \fB\s-1COMPILER_PATH\s0\fR is a colon-separated list of
directories, much like \fB\s-1PATH\s0\fR.  \s-1GCC\s0 tries the directories thus
specified when searching for subprograms, if it can't find the
subprograms using \fB\s-1GCC_EXEC_PREFIX\s0\fR.
.Ip "\fB\s-1LIBRARY_PATH\s0\fR" 4
.IX Item "LIBRARY_PATH"
The value of \fB\s-1LIBRARY_PATH\s0\fR is a colon-separated list of
directories, much like \fB\s-1PATH\s0\fR.  When configured as a native compiler,
\&\s-1GCC\s0 tries the directories thus specified when searching for special
linker files, if it can't find them using \fB\s-1GCC_EXEC_PREFIX\s0\fR.  Linking
using \s-1GCC\s0 also uses these directories when searching for ordinary
libraries for the \fB\-l\fR option (but directories specified with
\&\fB\-L\fR come first).
.Ip "\fB\s-1LANG\s0\fR" 4
.IX Item "LANG"
This variable is used to pass locale information to the compiler.  One way in
which this information is used is to determine the character set to be used
when character literals, string literals and comments are parsed in C and \*(C+.
When the compiler is configured to allow multibyte characters,
the following values for \fB\s-1LANG\s0\fR are recognized:
.RS 4
.Ip "\fBC-JIS\fR" 4
.IX Item "C-JIS"
Recognize \s-1JIS\s0 characters.
.Ip "\fBC-SJIS\fR" 4
.IX Item "C-SJIS"
Recognize \s-1SJIS\s0 characters.
.Ip "\fBC-EUCJP\fR" 4
.IX Item "C-EUCJP"
Recognize \s-1EUCJP\s0 characters.
.RE
.RS 4
.Sp
If \fB\s-1LANG\s0\fR is not defined, or if it has some other value, then the
compiler will use mblen and mbtowc as defined by the default locale to
recognize and translate multibyte characters.
.RE
.PP
Some additional environments variables affect the behavior of the
preprocessor.
.Ip "\fB\s-1CPATH\s0\fR" 4
.IX Item "CPATH"
.PD 0
.Ip "\fBC_INCLUDE_PATH\fR" 4
.IX Item "C_INCLUDE_PATH"
.Ip "\fB\s-1CPLUS_INCLUDE_PATH\s0\fR" 4
.IX Item "CPLUS_INCLUDE_PATH"
.Ip "\fB\s-1OBJC_INCLUDE_PATH\s0\fR" 4
.IX Item "OBJC_INCLUDE_PATH"
.PD
Each variable's value is a list of directories separated by a special
character, much like \fB\s-1PATH\s0\fR, in which to look for header files.
The special character, \f(CW\*(C`PATH_SEPARATOR\*(C'\fR, is target-dependent and
determined at \s-1GCC\s0 build time.  For Microsoft Windows-based targets it is a
semicolon, and for almost all other targets it is a colon.
.Sp
\&\fB\s-1CPATH\s0\fR specifies a list of directories to be searched as if
specified with \fB\-I\fR, but after any paths given with \fB\-I\fR
options on the command line.  This environment variable is used
regardless of which language is being preprocessed.
.Sp
The remaining environment variables apply only when preprocessing the
particular language indicated.  Each specifies a list of directories
to be searched as if specified with \fB\-isystem\fR, but after any
paths given with \fB\-isystem\fR options on the command line.
.Sp
In all these variables, an empty element instructs the compiler to
search its current working directory.  Empty elements can appear at the
beginning or end of a path.  For instance, if the value of
\&\fB\s-1CPATH\s0\fR is \f(CW\*(C`:/special/include\*(C'\fR, that has the same
effect as \fB\-I.\ \-I/special/include\fR.
.Ip "\fB\s-1DEPENDENCIES_OUTPUT\s0\fR" 4
.IX Item "DEPENDENCIES_OUTPUT"
If this variable is set, its value specifies how to output
dependencies for Make based on the non-system header files processed
by the compiler.  System header files are ignored in the dependency
output.
.Sp
The value of \fB\s-1DEPENDENCIES_OUTPUT\s0\fR can be just a file name, in
which case the Make rules are written to that file, guessing the target
name from the source file name.  Or the value can have the form
\&\fIfile\fR\fB \fR\fItarget\fR, in which case the rules are written to
file \fIfile\fR using \fItarget\fR as the target name.
.Sp
In other words, this environment variable is equivalent to combining
the options \fB\-MM\fR and \fB\-MF\fR,
with an optional \fB\-MT\fR switch too.
.Ip "\fB\s-1SUNPRO_DEPENDENCIES\s0\fR" 4
.IX Item "SUNPRO_DEPENDENCIES"
This variable is the same as \fB\s-1DEPENDENCIES_OUTPUT\s0\fR (see above),
except that system header files are not ignored, so it implies
\&\fB\-M\fR rather than \fB\-MM\fR.  However, the dependence on the
main input file is omitted.
.SH "BUGS"
.IX Header "BUGS"
For instructions on reporting bugs, see
<\fBhttp://gcc.gnu.org/bugs.html\fR>.  Use of the \fBgccbug\fR
script to report bugs is recommended.
.SH "FOOTNOTES"
.IX Header "FOOTNOTES"
.Ip "1." 4
On some systems, \fBgcc \-shared\fR
needs to build supplementary stub code for constructors to work.  On
multi-libbed systems, \fBgcc \-shared\fR must select the correct support
libraries to link against.  Failing to supply the correct flags may lead
to subtle defects.  Supplying them in cases where they are not necessary
is innocuous.
.SH "SEE ALSO"
.IX Header "SEE ALSO"
\&\fIgpl\fR\|(7), \fIgfdl\fR\|(7), \fIfsf-funding\fR\|(7),
\&\fIcpp\fR\|(1), \fIgcov\fR\|(1), \fIg77\fR\|(1), \fIas\fR\|(1), \fIld\fR\|(1), \fIgdb\fR\|(1), \fIadb\fR\|(1), \fIdbx\fR\|(1), \fIsdb\fR\|(1)
and the Info entries for \fIgcc\fR, \fIcpp\fR, \fIg77\fR, \fIas\fR,
\&\fIld\fR, \fIbinutils\fR and \fIgdb\fR.
.SH "AUTHOR"
.IX Header "AUTHOR"
See the Info entry for \fBgcc\fR, or
<\fBhttp://gcc.gnu.org/onlinedocs/gcc/Contributors.html\fR>,
for contributors to \s-1GCC\s0.
.SH "COPYRIGHT"
.IX Header "COPYRIGHT"
Copyright (c) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997,
1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
.PP
Permission is granted to copy, distribute and/or modify this document
under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.2 or
any later version published by the Free Software Foundation; with the
Invariant Sections being ``\s-1GNU\s0 General Public License'' and ``Funding
Free Software'', the Front-Cover texts being (a) (see below), and with
the Back-Cover Texts being (b) (see below).  A copy of the license is
included in the \fIgfdl\fR\|(7) man page.
.PP
(a) The \s-1FSF\s0's Front-Cover Text is:
.PP
.Vb 1
\&     A GNU Manual
.Ve
(b) The \s-1FSF\s0's Back-Cover Text is:
.PP
.Vb 3
\&     You have freedom to copy and modify this GNU Manual, like GNU
\&     software.  Copies published by the Free Software Foundation raise
\&     funds for GNU development.
.Ve