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1 /* Copyright (C) 2002, 2003, 2004 Free Software Foundation, Inc.
3 This file is part of GCC.
5 GCC is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2, or (at your option)
8 any later version.
10 GCC is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with GCC; see the file COPYING. If not, write to
17 the Free Software Foundation, 59 Temple Place - Suite 330,
18 Boston, MA 02111-1307, USA. */
20 /* As a special exception, if you include this header file into source
21 files compiled by GCC, this header file does not by itself cause
22 the resulting executable to be covered by the GNU General Public
23 License. This exception does not however invalidate any other
24 reasons why the executable file might be covered by the GNU General
25 Public License. */
27 /* Implemented from the specification included in the Intel C++ Compiler
28 User Guide and Reference, version 8.0. */
30 #ifndef _XMMINTRIN_H_INCLUDED
31 #define _XMMINTRIN_H_INCLUDED
33 #ifndef __SSE__
35 #else
37 /* We need type definitions from the MMX header file. */
38 #include <mmintrin.h>
40 /* The data type intended for user use. */
43 /* Internal data types for implementing the intrinsics. */
46 /* Create a selector for use with the SHUFPS instruction. */
47 #define _MM_SHUFFLE(fp3,fp2,fp1,fp0) \
48 (((fp3) << 6) | ((fp2) << 4) | ((fp1) << 2) | (fp0))
50 /* Constants for use with _mm_prefetch. */
51 enum _mm_hint
52 {
57 };
59 /* Bits in the MXCSR. */
60 #define _MM_EXCEPT_MASK 0x003f
61 #define _MM_EXCEPT_INVALID 0x0001
62 #define _MM_EXCEPT_DENORM 0x0002
63 #define _MM_EXCEPT_DIV_ZERO 0x0004
64 #define _MM_EXCEPT_OVERFLOW 0x0008
65 #define _MM_EXCEPT_UNDERFLOW 0x0010
66 #define _MM_EXCEPT_INEXACT 0x0020
68 #define _MM_MASK_MASK 0x1f80
69 #define _MM_MASK_INVALID 0x0080
70 #define _MM_MASK_DENORM 0x0100
71 #define _MM_MASK_DIV_ZERO 0x0200
72 #define _MM_MASK_OVERFLOW 0x0400
73 #define _MM_MASK_UNDERFLOW 0x0800
74 #define _MM_MASK_INEXACT 0x1000
76 #define _MM_ROUND_MASK 0x6000
77 #define _MM_ROUND_NEAREST 0x0000
78 #define _MM_ROUND_DOWN 0x2000
79 #define _MM_ROUND_UP 0x4000
80 #define _MM_ROUND_TOWARD_ZERO 0x6000
82 #define _MM_FLUSH_ZERO_MASK 0x8000
83 #define _MM_FLUSH_ZERO_ON 0x8000
84 #define _MM_FLUSH_ZERO_OFF 0x0000
86 /* Perform the respective operation on the lower SPFP (single-precision
87 floating-point) values of A and B; the upper three SPFP values are
88 passed through from A. */
90 static __inline __m128
92 {
94 }
96 static __inline __m128
98 {
100 }
102 static __inline __m128
104 {
106 }
108 static __inline __m128
110 {
112 }
114 static __inline __m128
116 {
118 }
120 static __inline __m128
122 {
124 }
126 static __inline __m128
128 {
130 }
132 static __inline __m128
134 {
136 }
138 static __inline __m128
140 {
142 }
144 /* Perform the respective operation on the four SPFP values in A and B. */
146 static __inline __m128
148 {
150 }
152 static __inline __m128
154 {
156 }
158 static __inline __m128
160 {
162 }
164 static __inline __m128
166 {
168 }
170 static __inline __m128
172 {
174 }
176 static __inline __m128
178 {
180 }
182 static __inline __m128
184 {
186 }
188 static __inline __m128
190 {
192 }
194 static __inline __m128
196 {
198 }
200 /* Perform logical bit-wise operations on 128-bit values. */
202 static __inline __m128
204 {
206 }
208 static __inline __m128
210 {
212 }
214 static __inline __m128
216 {
218 }
220 static __inline __m128
222 {
224 }
226 /* Perform a comparison on the lower SPFP values of A and B. If the
227 comparison is true, place a mask of all ones in the result, otherwise a
228 mask of zeros. The upper three SPFP values are passed through from A. */
230 static __inline __m128
232 {
234 }
236 static __inline __m128
238 {
240 }
242 static __inline __m128
244 {
246 }
248 static __inline __m128
250 {
255 __A));
256 }
258 static __inline __m128
260 {
265 __A));
266 }
268 static __inline __m128
270 {
272 }
274 static __inline __m128
276 {
278 }
280 static __inline __m128
282 {
284 }
286 static __inline __m128
288 {
293 __A));
294 }
296 static __inline __m128
298 {
303 __A));
304 }
306 static __inline __m128
308 {
310 }
312 static __inline __m128
314 {
316 }
318 /* Perform a comparison on the four SPFP values of A and B. For each
319 element, if the comparison is true, place a mask of all ones in the
320 result, otherwise a mask of zeros. */
322 static __inline __m128
324 {
326 }
328 static __inline __m128
330 {
332 }
334 static __inline __m128
336 {
338 }
340 static __inline __m128
342 {
344 }
346 static __inline __m128
348 {
350 }
352 static __inline __m128
354 {
356 }
358 static __inline __m128
360 {
362 }
364 static __inline __m128
366 {
368 }
370 static __inline __m128
372 {
374 }
376 static __inline __m128
378 {
380 }
382 static __inline __m128
384 {
386 }
388 static __inline __m128
390 {
392 }
394 /* Compare the lower SPFP values of A and B and return 1 if true
395 and 0 if false. */
399 {
401 }
405 {
407 }
411 {
413 }
417 {
419 }
423 {
425 }
429 {
431 }
435 {
437 }
441 {
443 }
447 {
449 }
453 {
455 }
459 {
461 }
465 {
467 }
469 /* Convert the lower SPFP value to a 32-bit integer according to the current
470 rounding mode. */
473 {
475 }
479 {
481 }
483 #ifdef __x86_64__
484 /* Convert the lower SPFP value to a 32-bit integer according to the current
485 rounding mode. */
488 {
490 }
491 #endif
493 /* Convert the two lower SPFP values to 32-bit integers according to the
494 current rounding mode. Return the integers in packed form. */
495 static __inline __m64
497 {
499 }
501 static __inline __m64
503 {
505 }
507 /* Truncate the lower SPFP value to a 32-bit integer. */
510 {
512 }
516 {
518 }
520 #ifdef __x86_64__
521 /* Truncate the lower SPFP value to a 32-bit integer. */
524 {
526 }
527 #endif
529 /* Truncate the two lower SPFP values to 32-bit integers. Return the
530 integers in packed form. */
531 static __inline __m64
533 {
535 }
537 static __inline __m64
539 {
541 }
543 /* Convert B to a SPFP value and insert it as element zero in A. */
544 static __inline __m128
546 {
548 }
550 static __inline __m128
552 {
554 }
556 #ifdef __x86_64__
557 /* Convert B to a SPFP value and insert it as element zero in A. */
558 static __inline __m128
560 {
562 }
563 #endif
565 /* Convert the two 32-bit values in B to SPFP form and insert them
566 as the two lower elements in A. */
567 static __inline __m128
569 {
571 }
573 static __inline __m128
575 {
577 }
579 /* Convert the four signed 16-bit values in A to SPFP form. */
580 static __inline __m128
582 {
583 __v4hi __sign;
585 __v4sf __r;
587 /* This comparison against zero gives us a mask that can be used to
588 fill in the missing sign bits in the unpack operations below, so
589 that we get signed values after unpacking. */
593 /* Convert the four words to doublewords. */
597 /* Convert the doublewords to floating point two at a time. */
604 }
606 /* Convert the four unsigned 16-bit values in A to SPFP form. */
607 static __inline __m128
609 {
612 __v4sf __r;
614 /* Convert the four words to doublewords. */
618 /* Convert the doublewords to floating point two at a time. */
625 }
627 /* Convert the low four signed 8-bit values in A to SPFP form. */
628 static __inline __m128
630 {
631 __v8qi __sign;
633 /* This comparison against zero gives us a mask that can be used to
634 fill in the missing sign bits in the unpack operations below, so
635 that we get signed values after unpacking. */
639 /* Convert the four low bytes to words. */
643 }
645 /* Convert the low four unsigned 8-bit values in A to SPFP form. */
646 static __inline __m128
648 {
652 }
654 /* Convert the four signed 32-bit values in A and B to SPFP form. */
655 static __inline __m128
657 {
662 }
664 /* Convert the four SPFP values in A to four signed 16-bit integers. */
665 static __inline __m64
667 {
673 }
675 /* Convert the four SPFP values in A to four signed 8-bit integers. */
676 static __inline __m64
678 {
682 }
684 /* Selects four specific SPFP values from A and B based on MASK. */
685 #if 0
686 static __inline __m128
688 {
690 }
691 #else
692 #define _mm_shuffle_ps(A, B, MASK) \
693 ((__m128) __builtin_ia32_shufps ((__v4sf)(A), (__v4sf)(B), (MASK)))
694 #endif
697 /* Selects and interleaves the upper two SPFP values from A and B. */
698 static __inline __m128
700 {
702 }
704 /* Selects and interleaves the lower two SPFP values from A and B. */
705 static __inline __m128
707 {
709 }
711 /* Sets the upper two SPFP values with 64-bits of data loaded from P;
712 the lower two values are passed through from A. */
713 static __inline __m128
715 {
717 }
719 /* Stores the upper two SPFP values of A into P. */
722 {
724 }
726 /* Moves the upper two values of B into the lower two values of A. */
727 static __inline __m128
729 {
731 }
733 /* Moves the lower two values of B into the upper two values of A. */
734 static __inline __m128
736 {
738 }
740 /* Sets the lower two SPFP values with 64-bits of data loaded from P;
741 the upper two values are passed through from A. */
742 static __inline __m128
744 {
746 }
748 /* Stores the lower two SPFP values of A into P. */
751 {
753 }
755 /* Creates a 4-bit mask from the most significant bits of the SPFP values. */
758 {
760 }
762 /* Return the contents of the control register. */
765 {
767 }
769 /* Read exception bits from the control register. */
772 {
774 }
778 {
780 }
784 {
786 }
790 {
792 }
794 /* Set the control register to I. */
797 {
799 }
801 /* Set exception bits in the control register. */
804 {
806 }
810 {
812 }
816 {
818 }
822 {
824 }
826 /* Create a vector with element 0 as *P and the rest zero. */
827 static __inline __m128
829 {
831 }
833 /* Create a vector with all four elements equal to *P. */
834 static __inline __m128
836 {
839 }
841 static __inline __m128
843 {
845 }
847 /* Load four SPFP values from P. The address must be 16-byte aligned. */
848 static __inline __m128
850 {
852 }
854 /* Load four SPFP values from P. The address need not be 16-byte aligned. */
855 static __inline __m128
857 {
859 }
861 /* Load four SPFP values in reverse order. The address must be aligned. */
862 static __inline __m128
864 {
867 }
869 /* Create a vector with element 0 as F and the rest zero. */
870 static __inline __m128
872 {
874 }
876 /* Create a vector with all four elements equal to F. */
877 static __inline __m128
879 {
882 }
884 static __inline __m128
886 {
888 }
890 /* Create the vector [Z Y X W]. */
891 static __inline __m128
893 {
895 }
897 /* Create the vector [W X Y Z]. */
898 static __inline __m128
900 {
902 }
904 /* Create a vector of zeros. */
905 static __inline __m128
907 {
909 }
911 /* Stores the lower SPFP value. */
914 {
916 }
918 /* Store the lower SPFP value across four words. */
921 {
925 }
929 {
931 }
933 /* Store four SPFP values. The address must be 16-byte aligned. */
936 {
938 }
940 /* Store four SPFP values. The address need not be 16-byte aligned. */
943 {
945 }
947 /* Store four SPFP values in reverse order. The address must be aligned. */
950 {
954 }
956 /* Sets the low SPFP value of A from the low value of B. */
957 static __inline __m128
959 {
961 }
963 /* Extracts one of the four words of A. The selector N must be immediate. */
964 #if 0
967 {
969 }
973 {
975 }
976 #else
977 #define _mm_extract_pi16(A, N) \
978 __builtin_ia32_pextrw ((__v4hi)(A), (N))
979 #define _m_pextrw(A, N) _mm_extract_pi16((A), (N))
980 #endif
982 /* Inserts word D into one of four words of A. The selector N must be
983 immediate. */
984 #if 0
985 static __inline __m64
987 {
989 }
991 static __inline __m64
993 {
995 }
996 #else
997 #define _mm_insert_pi16(A, D, N) \
998 ((__m64) __builtin_ia32_pinsrw ((__v4hi)(A), (D), (N)))
999 #define _m_pinsrw(A, D, N) _mm_insert_pi16((A), (D), (N))
1000 #endif
1002 /* Compute the element-wise maximum of signed 16-bit values. */
1003 static __inline __m64
1005 {
1007 }
1009 static __inline __m64
1011 {
1013 }
1015 /* Compute the element-wise maximum of unsigned 8-bit values. */
1016 static __inline __m64
1018 {
1020 }
1022 static __inline __m64
1024 {
1026 }
1028 /* Compute the element-wise minimum of signed 16-bit values. */
1029 static __inline __m64
1031 {
1033 }
1035 static __inline __m64
1037 {
1039 }
1041 /* Compute the element-wise minimum of unsigned 8-bit values. */
1042 static __inline __m64
1044 {
1046 }
1048 static __inline __m64
1050 {
1052 }
1054 /* Create an 8-bit mask of the signs of 8-bit values. */
1057 {
1059 }
1063 {
1065 }
1067 /* Multiply four unsigned 16-bit values in A by four unsigned 16-bit values
1068 in B and produce the high 16 bits of the 32-bit results. */
1069 static __inline __m64
1071 {
1073 }
1075 static __inline __m64
1077 {
1079 }
1081 /* Return a combination of the four 16-bit values in A. The selector
1082 must be an immediate. */
1083 #if 0
1084 static __inline __m64
1086 {
1088 }
1090 static __inline __m64
1092 {
1094 }
1095 #else
1096 #define _mm_shuffle_pi16(A, N) \
1097 ((__m64) __builtin_ia32_pshufw ((__v4hi)(A), (N)))
1098 #define _m_pshufw(A, N) _mm_shuffle_pi16 ((A), (N))
1099 #endif
1101 /* Conditionally store byte elements of A into P. The high bit of each
1102 byte in the selector N determines whether the corresponding byte from
1103 A is stored. */
1106 {
1108 }
1112 {
1114 }
1116 /* Compute the rounded averages of the unsigned 8-bit values in A and B. */
1117 static __inline __m64
1119 {
1121 }
1123 static __inline __m64
1125 {
1127 }
1129 /* Compute the rounded averages of the unsigned 16-bit values in A and B. */
1130 static __inline __m64
1132 {
1134 }
1136 static __inline __m64
1138 {
1140 }
1142 /* Compute the sum of the absolute differences of the unsigned 8-bit
1143 values in A and B. Return the value in the lower 16-bit word; the
1144 upper words are cleared. */
1145 static __inline __m64
1147 {
1149 }
1151 static __inline __m64
1153 {
1155 }
1157 /* Loads one cache line from address P to a location "closer" to the
1158 processor. The selector I specifies the type of prefetch operation. */
1159 #if 0
1162 {
1164 }
1165 #else
1166 #define _mm_prefetch(P, I) \
1167 __builtin_prefetch ((P), 0, (I))
1168 #endif
1170 /* Stores the data in A to the address P without polluting the caches. */
1173 {
1175 }
1177 /* Likewise. The address must be 16-byte aligned. */
1180 {
1182 }
1184 /* Guarantees that every preceding store is globally visible before
1185 any subsequent store. */
1188 {
1190 }
1192 /* The execution of the next instruction is delayed by an implementation
1193 specific amount of time. The instruction does not modify the
1194 architectural state. */
1197 {
1199 }
1201 /* Transpose the 4x4 matrix composed of row[0-3]. */
1202 #define _MM_TRANSPOSE4_PS(row0, row1, row2, row3) \
1203 do { \
1204 __v4sf __r0 = (row0), __r1 = (row1), __r2 = (row2), __r3 = (row3); \
1205 __v4sf __t0 = __builtin_ia32_shufps (__r0, __r1, 0x44); \
1206 __v4sf __t2 = __builtin_ia32_shufps (__r0, __r1, 0xEE); \
1207 __v4sf __t1 = __builtin_ia32_shufps (__r2, __r3, 0x44); \
1208 __v4sf __t3 = __builtin_ia32_shufps (__r2, __r3, 0xEE); \
1209 (row0) = __builtin_ia32_shufps (__t0, __t1, 0x88); \
1210 (row1) = __builtin_ia32_shufps (__t0, __t1, 0xDD); \
1211 (row2) = __builtin_ia32_shufps (__t2, __t3, 0x88); \
1212 (row3) = __builtin_ia32_shufps (__t2, __t3, 0xDD); \
1213 } while (0)
1215 /* For backward source compatibility. */
1216 #include <emmintrin.h>