cpudetect.c

   1 #include "config.h"
   2 #include "cpudetect.h"
   3 #include "mp_msg.h"
   4
   5 CpuCaps gCpuCaps;
   6
   7 #ifdef HAVE_MALLOC_H
   8 #include <malloc.h>
   9 #endif
  10 #include <stdlib.h>
  11
  12 #if defined(ARCH_X86) || defined(ARCH_X86_64)
  13
  14 #include <stdio.h>
  15 #include <string.h>
  16
  17 #if defined (__NetBSD__) || defined(__OpenBSD__)
  18 #include <sys/param.h>
  19 #include <sys/sysctl.h>
  20 #include <machine/cpu.h>
  21 #endif
  22
  23 #if defined(__FreeBSD__) || defined(__DragonFly__)
  24 #include <sys/types.h>
  25 #include <sys/sysctl.h>
  26 #endif
  27
  28 #ifdef __linux__
  29 #include <signal.h>
  30 #endif
  31
  32 #ifdef WIN32
  33 #include <windows.h>
  34 #endif
  35
  36 //#define X86_FXSR_MAGIC
  37 /* Thanks to the FreeBSD project for some of this cpuid code, and
  38  * help understanding how to use it.  Thanks to the Mesa
  39  * team for SSE support detection and more cpu detect code.
  40  */
  41
  42 /* I believe this code works.  However, it has only been used on a PII and PIII */
  43
  44 static void check_os_katmai_support( void );
  45
  46 #if 1
  47 // return TRUE if cpuid supported
  48 static int has_cpuid()
  49 {
  50         long a, c;
  51
  52 // code from libavcodec:
  53     __asm__ __volatile__ (
  54                           /* See if CPUID instruction is supported ... */
  55                           /* ... Get copies of EFLAGS into eax and ecx */
  56                           "pushf\n\t"
  57                           "pop %0\n\t"
  58                           "mov %0, %1\n\t"
  59
  60                           /* ... Toggle the ID bit in one copy and store */
  61                           /*     to the EFLAGS reg */
  62                           "xor $0x200000, %0\n\t"
  63                           "push %0\n\t"
  64                           "popf\n\t"
  65
  66                           /* ... Get the (hopefully modified) EFLAGS */
  67                           "pushf\n\t"
  68                           "pop %0\n\t"
  69                           : "=a" (a), "=c" (c)
  70                           :
  71                           : "cc"
  72                           );
  73
  74         return (a!=c);
  75 }
  76 #endif
  77
  78 static void
  79 do_cpuid(unsigned int ax, unsigned int *p)
  80 {
  81 #if 0
  82         __asm __volatile(
  83         "cpuid;"
  84         : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
  85         :  "0" (ax)
  86         );
  87 #else
  88 // code from libavcodec:
  89     __asm __volatile
  90         ("mov %%"REG_b", %%"REG_S"\n\t"
  91          "cpuid\n\t"
  92          "xchg %%"REG_b", %%"REG_S
  93          : "=a" (p[0]), "=S" (p[1]),
  94            "=c" (p[2]), "=d" (p[3])
  95          : "0" (ax));
  96 #endif
  97
  98 }
  99
 100 void GetCpuCaps( CpuCaps *caps)
 101 {
 102         unsigned int regs[4];
 103         unsigned int regs2[4];
 104
 105         memset(caps, 0, sizeof(*caps));
 106         caps->isX86=1;
 107         caps->cl_size=32; /* default */
 108         if (!has_cpuid()) {
 109             mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n");
 110             return;
 111         }
 112         do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
 113         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s  max cpuid level: %d\n",
 114                         (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
 115         if (regs[0]>=0x00000001)
 116         {
 117                 char *tmpstr;
 118                 unsigned cl_size;
 119
 120                 do_cpuid(0x00000001, regs2);
 121
 122                 caps->cpuType=(regs2[0] >> 8)&0xf;
 123
 124 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and
 125 // System Instructions, Table 3-2: Effective family computation, page 120.
 126                 if(caps->cpuType==0xf){
 127                     // use extended family (P4, IA64, K8)
 128                     caps->cpuType=0xf+((regs2[0]>>20)&255);
 129                 }
 130                 caps->cpuStepping=regs2[0] & 0xf;
 131
 132                 // general feature flags:
 133                 caps->hasTSC  = (regs2[3] & (1 << 8  )) >>  8; // 0x0000010
 134                 caps->hasMMX  = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 135                 caps->hasSSE  = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
 136                 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
 137                 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
 138                 cl_size = ((regs2[1] >> 8) & 0xFF)*8;
 139                 if(cl_size) caps->cl_size = cl_size;
 140
 141                 tmpstr=GetCpuFriendlyName(regs, regs2);
 142                 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: %s ",tmpstr);
 143                 free(tmpstr);
 144                 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"(Family: %d, Stepping: %d)\n",
 145                     caps->cpuType, caps->cpuStepping);
 146
 147         }
 148         do_cpuid(0x80000000, regs);
 149         if (regs[0]>=0x80000001) {
 150                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
 151                 do_cpuid(0x80000001, regs2);
 152                 caps->hasMMX  |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 153                 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
 154                 caps->has3DNow    = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
 155                 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
 156         }
 157         if(regs[0]>=0x80000006)
 158         {
 159                 do_cpuid(0x80000006, regs2);
 160                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF);
 161                 caps->cl_size  = regs2[2] & 0xFF;
 162         }
 163         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"Detected cache-line size is %u bytes\n",caps->cl_size);
 164 #if 0
 165         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
 166                 gCpuCaps.hasMMX,
 167                 gCpuCaps.hasMMX2,
 168                 gCpuCaps.hasSSE,
 169                 gCpuCaps.hasSSE2,
 170                 gCpuCaps.has3DNow,
 171                 gCpuCaps.has3DNowExt );
 172 #endif
 173
 174                 /* FIXME: Does SSE2 need more OS support, too? */
 175 #if defined(__linux__) || defined(__FreeBSD__) || defined(__NetBSD__) || defined(__CYGWIN__) || defined(__OpenBSD__) || defined(__DragonFly__)
 176                 if (caps->hasSSE)
 177                         check_os_katmai_support();
 178                 if (!caps->hasSSE)
 179                         caps->hasSSE2 = 0;
 180 #else
 181                 caps->hasSSE=0;
 182                 caps->hasSSE2 = 0;
 183 #endif
 184 //              caps->has3DNow=1;
 185 //              caps->hasMMX2 = 0;
 186 //              caps->hasMMX = 0;
 187
 188 #ifndef HAVE_MMX
 189         if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n");
 190         caps->hasMMX=0;
 191 #endif
 192 #ifndef HAVE_MMX2
 193         if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n");
 194         caps->hasMMX2=0;
 195 #endif
 196 #ifndef HAVE_SSE
 197         if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n");
 198         caps->hasSSE=0;
 199 #endif
 200 #ifndef HAVE_SSE2
 201         if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n");
 202         caps->hasSSE2=0;
 203 #endif
 204 #ifndef HAVE_3DNOW
 205         if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n");
 206         caps->has3DNow=0;
 207 #endif
 208 #ifndef HAVE_3DNOWEX
 209         if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n");
 210         caps->has3DNowExt=0;
 211 #endif
 212 }
 213
 214
 215 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */
 216 #define CPUID_EXTMODEL  ((regs2[0] >> 16)&0x0F) /* 19..16 */
 217 #define CPUID_TYPE              ((regs2[0] >> 12)&0x04) /* 13..12 */
 218 #define CPUID_FAMILY    ((regs2[0] >>  8)&0x0F) /* 11..08 */
 219 #define CPUID_MODEL             ((regs2[0] >>  4)&0x0F) /* 07..04 */
 220 #define CPUID_STEPPING  ((regs2[0] >>  0)&0x0F) /* 03..00 */
 221
 222 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
 223 #include "cputable.h" /* get cpuname and cpuvendors */
 224         char vendor[17];
 225         char *retname;
 226         int i;
 227
 228         if (NULL==(retname=(char*)malloc(256))) {
 229                 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n");
 230                 exit(1);
 231         }
 232
 233         sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
 234
 235         for(i=0; i<MAX_VENDORS; i++){
 236                 if(!strcmp(cpuvendors[i].string,vendor)){
 237                         if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){
 238                                 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]);
 239                         } else {
 240                                 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY);
 241                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name);
 242                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor:   %s\n",cpuvendors[i].string);
 243                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type:     %d\n",CPUID_TYPE);
 244                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family:   %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY);
 245                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model:    %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL);
 246                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING);
 247                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name"
 248                                        "to the MPlayer-Developers, so we can add it to the list!\n");
 249                         }
 250                 }
 251         }
 252         retname[255] = 0;
 253
 254         //printf("Detected CPU: %s\n", retname);
 255         return retname;
 256 }
 257
 258 #undef CPUID_EXTFAMILY
 259 #undef CPUID_EXTMODEL
 260 #undef CPUID_TYPE
 261 #undef CPUID_FAMILY
 262 #undef CPUID_MODEL
 263 #undef CPUID_STEPPING
 264
 265
 266 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
 267 static void sigill_handler_sse( int signal, struct sigcontext sc )
 268 {
 269    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 270
 271    /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
 272     * instructions are 3 bytes long.  We must increment the instruction
 273     * pointer manually to avoid repeated execution of the offending
 274     * instruction.
 275     *
 276     * If the SIGILL is caused by a divide-by-zero when unmasked
 277     * exceptions aren't supported, the SIMD FPU status and control
 278     * word will be restored at the end of the test, so we don't need
 279     * to worry about doing it here.  Besides, we may not be able to...
 280     */
 281    sc.eip += 3;
 282
 283    gCpuCaps.hasSSE=0;
 284 }
 285
 286 static void sigfpe_handler_sse( int signal, struct sigcontext sc )
 287 {
 288    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGFPE, " );
 289
 290    if ( sc.fpstate->magic != 0xffff ) {
 291       /* Our signal context has the extended FPU state, so reset the
 292        * divide-by-zero exception mask and clear the divide-by-zero
 293        * exception bit.
 294        */
 295       sc.fpstate->mxcsr |= 0x00000200;
 296       sc.fpstate->mxcsr &= 0xfffffffb;
 297    } else {
 298       /* If we ever get here, we're completely hosed.
 299        */
 300       mp_msg(MSGT_CPUDETECT,MSGL_V, "\n\n" );
 301       mp_msg(MSGT_CPUDETECT,MSGL_V, "SSE enabling test failed badly!" );
 302    }
 303 }
 304 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */
 305
 306 #ifdef WIN32
 307 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep)
 308 {
 309    if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){
 310       mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 311       ep->ContextRecord->Eip +=3;
 312       gCpuCaps.hasSSE=0;
 313           return EXCEPTION_CONTINUE_EXECUTION;
 314    }
 315    return EXCEPTION_CONTINUE_SEARCH;
 316 }
 317 #endif /* WIN32 */
 318
 319 /* If we're running on a processor that can do SSE, let's see if we
 320  * are allowed to or not.  This will catch 2.4.0 or later kernels that
 321  * haven't been configured for a Pentium III but are running on one,
 322  * and RedHat patched 2.2 kernels that have broken exception handling
 323  * support for user space apps that do SSE.
 324  */
 325 static void check_os_katmai_support( void )
 326 {
 327 #ifdef ARCH_X86_64
 328    gCpuCaps.hasSSE=1;
 329    gCpuCaps.hasSSE2=1;
 330 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 331    int has_sse=0, ret;
 332    size_t len=sizeof(has_sse);
 333
 334    ret = sysctlbyname("hw.instruction_sse", &has_sse, &len, NULL, 0);
 335    if (ret || !has_sse)
 336       gCpuCaps.hasSSE=0;
 337
 338 #elif defined(__NetBSD__) || defined (__OpenBSD__)
 339 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
 340    int has_sse, has_sse2, ret, mib[2];
 341    size_t varlen;
 342
 343    mib[0] = CTL_MACHDEP;
 344    mib[1] = CPU_SSE;
 345    varlen = sizeof(has_sse);
 346
 347    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 348    ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0);
 349    if (ret < 0 || !has_sse) {
 350       gCpuCaps.hasSSE=0;
 351       mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 352    } else {
 353       gCpuCaps.hasSSE=1;
 354       mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" );
 355    }
 356
 357    mib[1] = CPU_SSE2;
 358    varlen = sizeof(has_sse2);
 359    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " );
 360    ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0);
 361    if (ret < 0 || !has_sse2) {
 362       gCpuCaps.hasSSE2=0;
 363       mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 364    } else {
 365       gCpuCaps.hasSSE2=1;
 366       mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" );
 367    }
 368 #else
 369    gCpuCaps.hasSSE = 0;
 370    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" );
 371 #endif
 372 #elif defined(WIN32)
 373    LPTOP_LEVEL_EXCEPTION_FILTER exc_fil;
 374    if ( gCpuCaps.hasSSE ) {
 375       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 376       exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse);
 377       __asm __volatile ("xorps %xmm0, %xmm0");
 378       SetUnhandledExceptionFilter(exc_fil);
 379       if ( gCpuCaps.hasSSE ) mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
 380       else mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 381    }
 382 #elif defined(__linux__)
 383 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
 384    struct sigaction saved_sigill;
 385    struct sigaction saved_sigfpe;
 386
 387    /* Save the original signal handlers.
 388     */
 389    sigaction( SIGILL, NULL, &saved_sigill );
 390    sigaction( SIGFPE, NULL, &saved_sigfpe );
 391
 392    signal( SIGILL, (void (*)(int))sigill_handler_sse );
 393    signal( SIGFPE, (void (*)(int))sigfpe_handler_sse );
 394
 395    /* Emulate test for OSFXSR in CR4.  The OS will set this bit if it
 396     * supports the extended FPU save and restore required for SSE.  If
 397     * we execute an SSE instruction on a PIII and get a SIGILL, the OS
 398     * doesn't support Streaming SIMD Exceptions, even if the processor
 399     * does.
 400     */
 401    if ( gCpuCaps.hasSSE ) {
 402       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 403
 404 //      __asm __volatile ("xorps %%xmm0, %%xmm0");
 405       __asm __volatile ("xorps %xmm0, %xmm0");
 406
 407       if ( gCpuCaps.hasSSE ) {
 408          mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
 409       } else {
 410          mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 411       }
 412    }
 413
 414    /* Emulate test for OSXMMEXCPT in CR4.  The OS will set this bit if
 415     * it supports unmasked SIMD FPU exceptions.  If we unmask the
 416     * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS
 417     * doesn't support unmasked SIMD FPU exceptions.  If we get a SIGFPE
 418     * as expected, we're okay but we need to clean up after it.
 419     *
 420     * Are we being too stringent in our requirement that the OS support
 421     * unmasked exceptions?  Certain RedHat 2.2 kernels enable SSE by
 422     * setting CR4.OSFXSR but don't support unmasked exceptions.  Win98
 423     * doesn't even support them.  We at least know the user-space SSE
 424     * support is good in kernels that do support unmasked exceptions,
 425     * and therefore to be safe I'm going to leave this test in here.
 426     */
 427    if ( gCpuCaps.hasSSE ) {
 428       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE unmasked exceptions... " );
 429
 430 //      test_os_katmai_exception_support();
 431
 432       if ( gCpuCaps.hasSSE ) {
 433          mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
 434       } else {
 435          mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 436       }
 437    }
 438
 439    /* Restore the original signal handlers.
 440     */
 441    sigaction( SIGILL, &saved_sigill, NULL );
 442    sigaction( SIGFPE, &saved_sigfpe, NULL );
 443
 444    /* If we've gotten to here and the XMM CPUID bit is still set, we're
 445     * safe to go ahead and hook out the SSE code throughout Mesa.
 446     */
 447    if ( gCpuCaps.hasSSE ) {
 448       mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE passed.\n" );
 449    } else {
 450       mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE failed!\n" );
 451    }
 452 #else
 453    /* We can't use POSIX signal handling to test the availability of
 454     * SSE, so we disable it by default.
 455     */
 456    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" );
 457    gCpuCaps.hasSSE=0;
 458 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */
 459 #else
 460    /* Do nothing on other platforms for now.
 461     */
 462    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" );
 463    gCpuCaps.hasSSE=0;
 464 #endif /* __linux__ */
 465 }
 466 #else /* ARCH_X86 || ARCH_X86_64 */
 467
 468 #ifdef SYS_DARWIN
 469 #include <sys/sysctl.h>
 470 #else
 471 #include <signal.h>
 472 #include <setjmp.h>
 473
 474 static sigjmp_buf jmpbuf;
 475 static volatile sig_atomic_t canjump = 0;
 476
 477 static void sigill_handler (int sig)
 478 {
 479     if (!canjump) {
 480         signal (sig, SIG_DFL);
 481         raise (sig);
 482     }
 483
 484     canjump = 0;
 485     siglongjmp (jmpbuf, 1);
 486 }
 487 #endif
 488
 489 void GetCpuCaps( CpuCaps *caps)
 490 {
 491         caps->cpuType=0;
 492         caps->cpuStepping=0;
 493         caps->hasMMX=0;
 494         caps->hasMMX2=0;
 495         caps->has3DNow=0;
 496         caps->has3DNowExt=0;
 497         caps->hasSSE=0;
 498         caps->hasSSE2=0;
 499         caps->isX86=0;
 500         caps->hasAltiVec = 0;
 501 #ifdef HAVE_ALTIVEC
 502 #ifdef SYS_DARWIN
 503 /*
 504   rip-off from ffmpeg altivec detection code.
 505   this code also appears on Apple's AltiVec pages.
 506  */
 507         {
 508                 int sels[2] = {CTL_HW, HW_VECTORUNIT};
 509                 int has_vu = 0;
 510                 size_t len = sizeof(has_vu);
 511                 int err;
 512
 513                 err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
 514
 515                 if (err == 0)
 516                         if (has_vu != 0)
 517                                 caps->hasAltiVec = 1;
 518         }
 519 #else /* SYS_DARWIN */
 520 /* no Darwin, do it the brute-force way */
 521 /* this is borrowed from the libmpeg2 library */
 522         {
 523           signal (SIGILL, sigill_handler);
 524           if (sigsetjmp (jmpbuf, 1)) {
 525             signal (SIGILL, SIG_DFL);
 526           } else {
 527             canjump = 1;
 528
 529             asm volatile ("mtspr 256, %0\n\t"
 530                           "vand %%v0, %%v0, %%v0"
 531                           :
 532                           : "r" (-1));
 533
 534             signal (SIGILL, SIG_DFL);
 535             caps->hasAltiVec = 1;
 536           }
 537         }
 538 #endif /* SYS_DARWIN */
 539         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not "));
 540 #endif /* HAVE_ALTIVEC */
 541
 542 #ifdef ARCH_IA64
 543         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Intel Itanium\n");
 544 #endif
 545
 546 #ifdef ARCH_SPARC
 547         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Sun Sparc\n");
 548 #endif
 549
 550 #ifdef ARCH_ARMV4L
 551         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: ARM\n");
 552 #endif
 553
 554 #ifdef ARCH_POWERPC
 555         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: PowerPC\n");
 556 #endif
 557
 558 #ifdef ARCH_ALPHA
 559         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Digital Alpha\n");
 560 #endif
 561
 562 #ifdef ARCH_SGI_MIPS
 563         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: SGI MIPS\n");
 564 #endif
 565
 566 #ifdef ARCH_PA_RISC
 567         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Hewlett-Packard PA-RISC\n");
 568 #endif
 569
 570 #ifdef ARCH_S390
 571         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390\n");
 572 #endif
 573
 574 #ifdef ARCH_S390X
 575         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390X\n");
 576 #endif
 577
 578 #ifdef ARCH_VAX
 579         mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Digital VAX\n" );
 580 #endif
 581 }
 582 #endif /* !ARCH_X86 */