firmware/target/arm/as3525/sd-as3525v2.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 Daniel Ankers
  11  * Copyright © 2008-2009 Rafaël Carré
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19  * KIND, either express or implied.
  20  *
  21  ****************************************************************************/
  22
  23 #include "config.h" /* for HAVE_MULTIVOLUME */
  24 #include "fat.h"
  25 #include "thread.h"
  26 #include "gcc_extensions.h"
  27 #include "led.h"
  28 #include "sdmmc.h"
  29 #include "system.h"
  30 #include "kernel.h"
  31 #include "cpu.h"
  32 #include <stdio.h>
  33 #include <stdlib.h>
  34 #include <string.h>
  35 #include "as3525v2.h"
  36 #include "pl081.h"  /* DMA controller */
  37 #include "dma-target.h" /* DMA request lines */
  38 #include "clock-target.h"
  39 #include "panic.h"
  40 #include "stdbool.h"
  41 #include "ata_idle_notify.h"
  42 #include "sd.h"
  43 #include "usb.h"
  44
  45 #ifdef HAVE_HOTSWAP
  46 #include "disk.h"
  47 #endif
  48
  49 #if defined(SANSA_FUZEV2)
  50 #include "backlight-target.h"
  51 #endif
  52
  53 #include "lcd.h"
  54 #include <stdarg.h>
  55 #include "sysfont.h"
  56
  57 #define     INTERNAL_AS3525  0   /* embedded SD card */
  58 #define     SD_SLOT_AS3525   1   /* SD slot if present */
  59
  60 /* Clipv2 Clip+ and Fuzev2 OF all occupy the same size */
  61 #define AMS_OF_SIZE 0xf000
  62
  63 /* command flags */
  64 #define MCI_NO_RESP     (0<<0)
  65 #define MCI_RESP        (1<<0)
  66 #define MCI_LONG_RESP   (1<<1)
  67 #define MCI_ACMD        (1<<2)
  68
  69 /* controller registers */
  70 #define SD_BASE 0xC6070000
  71
  72 #define SD_REG(x)       (*(volatile unsigned long *) (SD_BASE+x))
  73
  74 #define MCI_CTRL        SD_REG(0x00)
  75
  76 /* control bits */
  77 #define CTRL_RESET      (1<<0)
  78 #define FIFO_RESET      (1<<1)
  79 #define DMA_RESET       (1<<2)
  80 #define INT_ENABLE      (1<<4)
  81 #define DMA_ENABLE      (1<<5)
  82 #define READ_WAIT       (1<<6)
  83 #define SEND_IRQ_RESP   (1<<7)
  84 #define ABRT_READ_DATA  (1<<8)
  85 #define SEND_CCSD       (1<<9)
  86 #define SEND_AS_CCSD    (1<<10)
  87 #define EN_OD_PULLUP    (1<<24)
  88
  89
  90 #define MCI_PWREN       SD_REG(0x04)    /* power enable */
  91
  92 #define PWR_CRD_0       (1<<0)
  93 #define PWR_CRD_1       (1<<1)
  94 #define PWR_CRD_2       (1<<2)
  95 #define PWR_CRD_3       (1<<3)
  96
  97 #define MCI_CLKDIV      SD_REG(0x08)    /* clock divider */
  98 /* CLK_DIV_0 :    bits 7:0
  99  * CLK_DIV_1 :    bits 15:8
 100  * CLK_DIV_2 :    bits 23:16
 101  * CLK_DIV_3 :    bits 31:24
 102  */
 103
 104 #define MCI_CLKSRC      SD_REG(0x0C)    /* clock source */
 105 /* CLK_SRC_CRD0:  bits 1:0
 106  * CLK_SRC_CRD1:  bits 3:2
 107  * CLK_SRC_CRD2:  bits 5:4
 108  * CLK_SRC_CRD3:  bits 7:6
 109  */
 110
 111 #define MCI_CLKENA      SD_REG(0x10)    /* clock enable */
 112
 113 #define CCLK_ENA_CRD0   (1<<0)
 114 #define CCLK_ENA_CRD1   (1<<1)
 115 #define CCLK_ENA_CRD2   (1<<2)
 116 #define CCLK_ENA_CRD3   (1<<3)
 117 #define CCLK_LP_CRD0    (1<<16)         /* LP --> Low Power Mode? */
 118 #define CCLK_LP_CRD1    (1<<17)
 119 #define CCLK_LP_CRD2    (1<<18)
 120 #define CCLK_LP_CRD3    (1<<19)
 121
 122 #define MCI_TMOUT       SD_REG(0x14)    /* timeout */
 123 /* response timeout bits 0:7
 124  * data timeout bits     8:31
 125  */
 126
 127 #define MCI_CTYPE       SD_REG(0x18)    /* card type */
 128                                         /* 1 bit per card, set = wide bus */
 129 #define WIDTH4_CRD0     (1<<0)
 130 #define WIDTH4_CRD1     (1<<1)
 131 #define WIDTH4_CRD2     (1<<2)
 132 #define WIDTH4_CRD3     (1<<3)
 133
 134 #define MCI_BLKSIZ      SD_REG(0x1C)    /* block size  bits 0:15*/
 135 #define MCI_BYTCNT      SD_REG(0x20)    /* byte count  bits 0:31*/
 136 #define MCI_MASK        SD_REG(0x24)    /* interrupt mask */
 137
 138
 139
 140 #define MCI_ARGUMENT    SD_REG(0x28)
 141 #define MCI_COMMAND     SD_REG(0x2C)
 142
 143 /* command bits (bits 5:0 are the command index) */
 144 #define CMD_RESP_EXP_BIT        (1<<6)
 145 #define CMD_RESP_LENGTH_BIT     (1<<7)
 146 #define CMD_CHECK_CRC_BIT       (1<<8)
 147 #define CMD_DATA_EXP_BIT        (1<<9)
 148 #define CMD_RW_BIT              (1<<10)
 149 #define CMD_TRANSMODE_BIT       (1<<11)
 150 #define CMD_SENT_AUTO_STOP_BIT  (1<<12)
 151 #define CMD_WAIT_PRV_DAT_BIT    (1<<13)
 152 #define CMD_ABRT_CMD_BIT        (1<<14)
 153 #define CMD_SEND_INIT_BIT       (1<<15)
 154 #define CMD_CARD_NO(x)          ((x)<<16)         /* 5 bits wide  */
 155 #define CMD_SEND_CLK_ONLY       (1<<21)
 156 #define CMD_READ_CEATA          (1<<22)
 157 #define CMD_CCS_EXPECTED        (1<<23)
 158 #define CMD_DONE_BIT            (1<<31)
 159
 160 #define TRANSFER_CMD  (cmd == SD_READ_MULTIPLE_BLOCK ||   \
 161                        cmd == SD_WRITE_MULTIPLE_BLOCK)
 162
 163 #define MCI_RESP0       SD_REG(0x30)
 164 #define MCI_RESP1       SD_REG(0x34)
 165 #define MCI_RESP2       SD_REG(0x38)
 166 #define MCI_RESP3       SD_REG(0x3C)
 167
 168 #define MCI_MASK_STATUS SD_REG(0x40)    /* masked interrupt status */
 169 #define MCI_RAW_STATUS  SD_REG(0x44)    /* raw interrupt status, also used as
 170                                          * status clear */
 171
 172 /* interrupt bits */                /* C D E   (Cmd) (Data) (End) */
 173 #define MCI_INT_CRDDET  (1<<0)      /*          card detect */
 174 #define MCI_INT_RE      (1<<1)      /* x         response error */
 175 #define MCI_INT_CD      (1<<2)      /*     x     command done */
 176 #define MCI_INT_DTO     (1<<3)      /*     x     data transfer over */
 177 #define MCI_INT_TXDR    (1<<4)      /*          tx fifo data request */
 178 #define MCI_INT_RXDR    (1<<5)      /*          rx fifo data request */
 179 #define MCI_INT_RCRC    (1<<6)      /* x         response crc error */
 180 #define MCI_INT_DCRC    (1<<7)      /*   x       data crc error */
 181 #define MCI_INT_RTO     (1<<8)      /* x         response timeout */
 182 #define MCI_INT_DRTO    (1<<9)      /*   x       data read timeout */
 183 #define MCI_INT_HTO     (1<<10)     /*   x       data starv timeout */
 184 #define MCI_INT_FRUN    (1<<11)     /*   x       fifo over/underrun */
 185 #define MCI_INT_HLE     (1<<12)     /* x x        hw locked while error */
 186 #define MCI_INT_SBE     (1<<13)     /*   x       start bit error */
 187 #define MCI_INT_ACD     (1<<14)     /*          auto command done */
 188 #define MCI_INT_EBE     (1<<15)     /*   x       end bit error */
 189 #define MCI_INT_SDIO    (0xf<<16)
 190
 191 /*
 192  *  STATUS register
 193  *  & 0xBA80    = MCI_INT_DCRC | MCI_INT_DRTO | MCI_INT_FRUN | \
 194  *                  MCI_INT_HLE | MCI_INT_SBE | MCI_INT_EBE
 195  *  & 8         = MCI_INT_DTO
 196  *  & 0x428     = MCI_INT_DTO | MCI_INT_RXDR | MCI_INT_HTO
 197  *  & 0x418     = MCI_INT_DTO | MCI_INT_TXDR | MCI_INT_HTO
 198  */
 199
 200 #define MCI_CMD_ERROR    \
 201          (MCI_INT_RE   | \
 202           MCI_INT_RCRC | \
 203           MCI_INT_RTO  | \
 204           MCI_INT_HLE)
 205
 206 #define MCI_DATA_ERROR    \
 207         ( MCI_INT_DCRC  | \
 208           MCI_INT_DRTO  | \
 209           MCI_INT_HTO   | \
 210           MCI_INT_FRUN  | \
 211           MCI_INT_HLE   | \
 212           MCI_INT_SBE   | \
 213           MCI_INT_EBE)
 214
 215 #define MCI_STATUS      SD_REG(0x48)
 216
 217 #define FIFO_RX_WM              (1<<0)
 218 #define FIFO_TX_WM              (1<<1)
 219 #define FIFO_EMPTY              (1<<2)
 220 #define FIFO_FULL               (1<<3)
 221 #define CMD_FSM_STATE_B0        (1<<4)
 222 #define CMD_FSM_STATE_B1        (1<<5)
 223 #define CMD_FSM_STATE_B2        (1<<6)
 224 #define CMD_FSM_STATE_B3        (1<<7)
 225 #define DATA_3_STAT             (1<<8)
 226 #define DATA_BUSY               (1<<9)
 227 #define DATA_STAT_MC_BUSY       (1<<10)
 228 #define RESP_IDX_B0             (1<<11)
 229 #define RESP_IDX_B1             (1<<12)
 230 #define RESP_IDX_B2             (1<<13)
 231 #define RESP_IDX_B3             (1<<14)
 232 #define RESP_IDX_B4             (1<<15)
 233 #define RESP_IDX_B5             (1<<16)
 234 #define FIFO_CNT_B00            (1<<17)
 235 #define FIFO_CNT_B01            (1<<18)
 236 #define FIFO_CNT_B02            (1<<19)
 237 #define FIFO_CNT_B03            (1<<20)
 238 #define FIFO_CNT_B04            (1<<21)
 239 #define FIFO_CNT_B05            (1<<22)
 240 #define FIFO_CNT_B06            (1<<23)
 241 #define FIFO_CNT_B07            (1<<24)
 242 #define FIFO_CNT_B08            (1<<25)
 243 #define FIFO_CNT_B09            (1<<26)
 244 #define FIFO_CNT_B10            (1<<27)
 245 #define FIFO_CNT_B11            (1<<28)
 246 #define FIFO_CNT_B12            (1<<29)
 247 #define DMA_ACK                 (1<<30)
 248 #define START_CMD               (1<<31)
 249
 250 #define MCI_FIFOTH      SD_REG(0x4C)    /* FIFO threshold */
 251 /* TX watermark :    bits 11:0
 252  * RX watermark :    bits 27:16
 253  * DMA MTRANS SIZE : bits 30:28
 254  * bits 31, 15:12 : unused
 255  */
 256 #define MCI_FIFOTH_MASK 0x8000f000
 257
 258 #define MCI_CDETECT     SD_REG(0x50)    /* card detect */
 259
 260 #define CDETECT_CRD_0   (1<<0)
 261 #define CDETECT_CRD_1   (1<<1)
 262 #define CDETECT_CRD_2   (1<<2)
 263 #define CDETECT_CRD_3   (1<<3)
 264
 265 #define MCI_WRTPRT      SD_REG(0x54)    /* write protect */
 266 #define MCI_GPIO        SD_REG(0x58)
 267 #define MCI_TCBCNT      SD_REG(0x5C)    /* transferred CIU byte count (card)*/
 268 #define MCI_TBBCNT      SD_REG(0x60)    /* transferred host/DMA to/from bytes (FIFO)*/
 269 #define MCI_DEBNCE      SD_REG(0x64)    /* card detect debounce  bits 23:0*/
 270 #define MCI_USRID       SD_REG(0x68)    /* user id */
 271 #define MCI_VERID       SD_REG(0x6C)    /* version id */
 272
 273 #define MCI_HCON        SD_REG(0x70)    /* hardware config */
 274 /* bit  0       : card type
 275  * bits 5:1     : maximum card index
 276  * bit  6       : BUS TYPE
 277  * bits 9:7     : DATA WIDTH
 278  * bits 15:10   : ADDR WIDTH
 279  * bits 17:16   : DMA IF
 280  * bits 20:18   : DMA WIDTH
 281  * bit  21      : FIFO RAM INSIDE
 282  * bit  22      : IMPL HOLD REG
 283  * bit  23      : SET CLK FALSE
 284  * bits 25:24   : MAX CLK DIV IDX
 285  * bit  26      : AREA OPTIM
 286  */
 287
 288 #define MCI_BMOD        SD_REG(0x80)    /* bus mode */
 289 /* bit  0       : SWR
 290  * bit  1       : FB
 291  * bits 6:2     : DSL
 292  * bit  7       : DE
 293  * bit  10:8    : PBL
 294  */
 295
 296 #define MCI_PLDMND      SD_REG(0x84)    /* poll demand */
 297 #define MCI_DBADDR      SD_REG(0x88)    /* descriptor base address */
 298 #define MCI_IDSTS       SD_REG(0x8C)    /* internal DMAC status */
 299 /* bit  0       : TI
 300  * bit  1       : RI
 301  * bit  2       : FBE
 302  * bit  3       : unused
 303  * bit  4       : DU
 304  * bit  5       : CES
 305  * bits 7:6     : unused
 306  * bits 8       : NIS
 307  * bit  9       : AIS
 308  * bits 12:10   : EB
 309  * bits 16:13   : FSM
 310  */
 311
 312 #define MCI_IDINTEN     SD_REG(0x90)    /* internal DMAC interrupt enable */
 313 /* bit  0       : TI
 314  * bit  1       : RI
 315  * bit  2       : FBE
 316  * bit  3       : unused
 317  * bit  4       : DU
 318  * bit  5       : CES
 319  * bits 7:6     : unused
 320  * bits 8       : NI
 321  * bit  9       : AI
 322  */
 323 #define MCI_DSCADDR     SD_REG(0x94)    /* current host descriptor address */
 324 #define MCI_BUFADDR     SD_REG(0x98)    /* current host buffer address */
 325
 326 #define MCI_FIFO        ((unsigned long *) (SD_BASE+0x100))
 327
 328 #define UNALIGNED_NUM_SECTORS 10
 329 static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32)));   /* align on cache line size */
 330 static unsigned char *uncached_buffer = AS3525_UNCACHED_ADDR(&aligned_buffer[0]);
 331
 332 static tCardInfo card_info[NUM_DRIVES];
 333
 334 /* for compatibility */
 335 static long last_disk_activity = -1;
 336
 337 static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
 338 static const char         sd_thread_name[] = "ata/sd";
 339 static struct mutex       sd_mtx SHAREDBSS_ATTR;
 340 static struct event_queue sd_queue;
 341 #ifndef BOOTLOADER
 342 bool sd_enabled = false;
 343 #endif
 344
 345 static struct semaphore transfer_completion_signal;
 346 static struct semaphore command_completion_signal;
 347 static volatile bool retry;
 348 static volatile int cmd_error;
 349
 350 #if defined(HAVE_MULTIDRIVE)
 351 #define EXT_SD_BITS (1<<2)
 352 #endif
 353
 354 static inline void mci_delay(void) { udelay(1000); }
 355
 356 void INT_NAND(void)
 357 {
 358     MCI_CTRL &= ~INT_ENABLE;
 359     /* use raw status here as we need to check some Ints that are masked */
 360     const int status = MCI_RAW_STATUS;
 361
 362     MCI_RAW_STATUS = status;    /* clear status */
 363
 364     if(status & MCI_DATA_ERROR)
 365         retry = true;
 366
 367     if( status & (MCI_INT_DTO|MCI_DATA_ERROR))
 368         semaphore_release(&transfer_completion_signal);
 369
 370     cmd_error = status & MCI_CMD_ERROR;
 371
 372     if(status & MCI_INT_CD)
 373         semaphore_release(&command_completion_signal);
 374
 375     MCI_CTRL |= INT_ENABLE;
 376 }
 377
 378 static inline bool card_detect_target(void)
 379 {
 380 #if defined(HAVE_MULTIDRIVE)
 381 #if defined(SANSA_FUZEV2)
 382     return GPIOA_PIN(2);
 383 #elif defined(SANSA_CLIPPLUS)
 384     return !(GPIOA_PIN(2));
 385 #else
 386 #error "microSD pin not defined for your target"
 387 #endif
 388 #else
 389     return false;
 390 #endif
 391 }
 392
 393 static bool send_cmd(const int drive, const int cmd, const int arg, const int flags,
 394         unsigned long *response)
 395 {
 396     int card_no;
 397
 398     if ((flags & MCI_ACMD) && /* send SD_APP_CMD first */
 399         !send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_RESP, response))
 400         return false;
 401
 402 #if defined(HAVE_MULTIDRIVE)
 403     if(sd_present(SD_SLOT_AS3525))
 404         GPIOB_PIN(5) = (1-drive) << 5;
 405 #endif
 406
 407     MCI_ARGUMENT = arg;
 408
 409 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS)
 410     if (amsv2_variant == 1)
 411         card_no = 1 << 16;
 412     else
 413 #endif
 414         card_no = CMD_CARD_NO(drive);
 415
 416     /* Construct MCI_COMMAND  */
 417     MCI_COMMAND =
 418       /*b5:0*/    cmd
 419       /*b6  */  | ((flags & MCI_RESP)                ? CMD_RESP_EXP_BIT:      0)
 420       /*b7  */  | ((flags & MCI_LONG_RESP)           ? CMD_RESP_LENGTH_BIT:   0)
 421       /*b8      | CMD_CHECK_CRC_BIT       unused  */
 422       /*b9  */  | (TRANSFER_CMD                      ? CMD_DATA_EXP_BIT:      0)
 423       /*b10 */  | ((cmd == SD_WRITE_MULTIPLE_BLOCK)  ? CMD_RW_BIT:            0)
 424       /*b11     | CMD_TRANSMODE_BIT       unused  */
 425       /*b12     | CMD_SENT_AUTO_STOP_BIT  unused  */
 426       /*b13 */  | (TRANSFER_CMD                      ? CMD_WAIT_PRV_DAT_BIT:  0)
 427       /*b14     | CMD_ABRT_CMD_BIT        unused  */
 428       /*b15     | CMD_SEND_INIT_BIT       unused  */
 429    /*b20:16 */  |                                      card_no
 430       /*b21     | CMD_SEND_CLK_ONLY       unused  */
 431       /*b22     | CMD_READ_CEATA          unused  */
 432       /*b23     | CMD_CCS_EXPECTED        unused  */
 433       /*b31 */  |                                      CMD_DONE_BIT;
 434
 435 #if defined(SANSA_FUZEV2)
 436     if (amsv2_variant == 0)
 437     {
 438         extern int buttonlight_is_on;
 439         if(buttonlight_is_on)
 440             _buttonlight_on();
 441         else
 442             _buttonlight_off();
 443     }
 444 #endif
 445     semaphore_wait(&command_completion_signal, TIMEOUT_BLOCK);
 446
 447     /*  Handle command responses & errors */
 448     if(flags & MCI_RESP)
 449     {
 450         if(cmd_error & (MCI_INT_RCRC | MCI_INT_RTO))
 451             return false;
 452
 453         if(flags & MCI_LONG_RESP)
 454         {
 455             response[0] = MCI_RESP3;
 456             response[1] = MCI_RESP2;
 457             response[2] = MCI_RESP1;
 458             response[3] = MCI_RESP0;
 459         }
 460         else
 461             response[0] = MCI_RESP0;
 462     }
 463     return true;
 464 }
 465
 466 static int sd_wait_for_tran_state(const int drive)
 467 {
 468     unsigned long response;
 469     unsigned int timeout = current_tick + 5*HZ;
 470     int cmd_retry = 10;
 471
 472     while (1)
 473     {
 474         while (!send_cmd(drive, SD_SEND_STATUS, card_info[drive].rca, MCI_RESP,
 475                          &response) && cmd_retry > 0)
 476         {
 477             cmd_retry--;
 478         }
 479
 480         if (cmd_retry <= 0)
 481             return -1;
 482
 483         if (((response >> 9) & 0xf) == SD_TRAN)
 484             return 0;
 485
 486         if(TIME_AFTER(current_tick, timeout))
 487             return -10 * ((response >> 9) & 0xf);
 488
 489         last_disk_activity = current_tick;
 490     }
 491 }
 492
 493
 494 static int sd_init_card(const int drive)
 495 {
 496     unsigned long response;
 497     long init_timeout;
 498     bool sd_v2 = false;
 499
 500     card_info[drive].rca = 0;
 501
 502     /*  assume 24 MHz clock / 60 = 400 kHz  */
 503     MCI_CLKDIV = (MCI_CLKDIV & ~(0xFF)) | 0x3C;    /* CLK_DIV_0 : bits 7:0  */
 504
 505     /* 100 - 400kHz clock required for Identification Mode  */
 506     /*  Start of Card Identification Mode ************************************/
 507
 508     /* CMD0 Go Idle  */
 509     if(!send_cmd(drive, SD_GO_IDLE_STATE, 0, MCI_NO_RESP, NULL))
 510         return -1;
 511     mci_delay();
 512
 513     /* CMD8 Check for v2 sd card.  Must be sent before using ACMD41
 514       Non v2 cards will not respond to this command*/
 515     if(send_cmd(drive, SD_SEND_IF_COND, 0x1AA, MCI_RESP, &response))
 516         if((response & 0xFFF) == 0x1AA)
 517             sd_v2 = true;
 518
 519     /* timeout for initialization is 1sec, from SD Specification 2.00 */
 520     init_timeout = current_tick + HZ;
 521
 522     do {
 523         /* this timeout is the only valid error for this loop*/
 524         if(TIME_AFTER(current_tick, init_timeout))
 525             return -2;
 526
 527          /* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */
 528         if(!send_cmd(drive, SD_APP_OP_COND, (0x00FF8000 | (sd_v2 ? 1<<30 : 0)),
 529                         MCI_ACMD|MCI_RESP, &card_info[drive].ocr))
 530             return -3;
 531     } while(!(card_info[drive].ocr & (1<<31)) );
 532
 533     /* CMD2 send CID */
 534     if(!send_cmd(drive, SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP, card_info[drive].cid))
 535         return -4;
 536
 537     /* CMD3 send RCA */
 538     if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info[drive].rca))
 539         return -5;
 540
 541 #ifdef HAVE_MULTIDRIVE
 542     /* Make sure we have 2 unique rca numbers */
 543     if(card_info[INTERNAL_AS3525].rca == card_info[SD_SLOT_AS3525].rca)
 544         if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info[drive].rca))
 545             return -6;
 546 #endif
 547     /*  End of Card Identification Mode   ************************************/
 548
 549     if (sd_v2)
 550     {
 551         /* Attempt to switch cards to HS timings, non HS cards just ignore this */
 552         /*  CMD7 w/rca: Select card to put it in TRAN state */
 553         if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_NO_RESP, NULL))
 554             return -7;
 555
 556         if(sd_wait_for_tran_state(drive))
 557             return -8;
 558
 559         /* CMD6 */
 560         if(!send_cmd(drive, SD_SWITCH_FUNC, 0x80fffff1, MCI_NO_RESP, NULL))
 561             return -9;
 562
 563         /* This delay is a bit of a hack, but seems to fix card detection
 564            problems with some SD cards (particularly 16 GB and bigger cards).
 565            Preferably we should handle this properly instead of using a delay,
 566            see also FS#11870. */
 567         sleep(HZ/10);
 568
 569         /*  We need to go back to STBY state now so we can read csd */
 570         /*  CMD7 w/rca=0:  Deselect card to put it in STBY state */
 571         if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_NO_RESP, NULL))
 572             return -10;
 573     }
 574
 575     /* CMD9 send CSD */
 576     if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
 577                  MCI_RESP|MCI_LONG_RESP, card_info[drive].csd))
 578         return -11;
 579
 580     /* Another delay hack, see FS#11798 */
 581     mci_delay();
 582
 583     sd_parse_csd(&card_info[drive]);
 584
 585     if(drive == INTERNAL_AS3525) /* The OF is stored in the first blocks */
 586         card_info[INTERNAL_AS3525].numblocks -= AMS_OF_SIZE;
 587
 588     /*  Card back to full speed  */
 589     MCI_CLKDIV &= ~(0xFF);    /* CLK_DIV_0 : bits 7:0 = 0x00 */
 590
 591     /*  CMD7 w/rca: Select card to put it in TRAN state */
 592     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_NO_RESP, NULL))
 593         return -12;
 594
 595 #ifndef BOOTLOADER
 596     /*  Switch to to 4 bit widebus mode  */
 597     if(sd_wait_for_tran_state(drive) < 0)
 598         return -13;
 599     /* ACMD6  */
 600     if(!send_cmd(drive, SD_SET_BUS_WIDTH, 2, MCI_ACMD|MCI_NO_RESP, NULL))
 601         return -15;
 602     mci_delay();
 603     /* ACMD42  */
 604     if(!send_cmd(drive, SD_SET_CLR_CARD_DETECT, 0, MCI_ACMD|MCI_NO_RESP, NULL))
 605         return -17;
 606
 607     /* Now that card is widebus make controller aware */
 608 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS)
 609     if (amsv2_variant == 1)
 610         MCI_CTYPE |= 1<<1;
 611     else
 612 #endif
 613         MCI_CTYPE |= (1<<drive);
 614
 615 #endif /* ! BOOTLOADER */
 616
 617     /*  Set low power mode  */
 618 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS)
 619     if (amsv2_variant == 1)
 620         MCI_CLKENA |= 1<<16;
 621     else
 622 #endif
 623         MCI_CLKENA |= 1<<(drive + 16);
 624
 625     card_info[drive].initialized = 1;
 626
 627     return 0;
 628 }
 629
 630 static void sd_thread(void) NORETURN_ATTR;
 631 static void sd_thread(void)
 632 {
 633     struct queue_event ev;
 634     bool idle_notified = false;
 635
 636     while (1)
 637     {
 638         queue_wait_w_tmo(&sd_queue, &ev, HZ);
 639
 640         switch ( ev.id )
 641         {
 642 #ifdef HAVE_HOTSWAP
 643         case SYS_HOTSWAP_INSERTED:
 644         case SYS_HOTSWAP_EXTRACTED:
 645         {
 646             int microsd_init = 1;
 647             fat_lock();          /* lock-out FAT activity first -
 648                                     prevent deadlocking via disk_mount that
 649                                     would cause a reverse-order attempt with
 650                                     another thread */
 651             mutex_lock(&sd_mtx); /* lock-out card activity - direct calls
 652                                     into driver that bypass the fat cache */
 653
 654             /* We now have exclusive control of fat cache and ata */
 655
 656             disk_unmount(SD_SLOT_AS3525);     /* release "by force", ensure file
 657                                     descriptors aren't leaked and any busy
 658                                     ones are invalid if mounting */
 659             /* Force card init for new card, re-init for re-inserted one or
 660              * clear if the last attempt to init failed with an error. */
 661             card_info[SD_SLOT_AS3525].initialized = 0;
 662
 663             if (ev.id == SYS_HOTSWAP_INSERTED)
 664             {
 665                 sd_enable(true);
 666                 microsd_init = sd_init_card(SD_SLOT_AS3525);
 667                 if (microsd_init < 0) /* initialisation failed */
 668                     panicf("microSD init failed : %d", microsd_init);
 669
 670                 microsd_init = disk_mount(SD_SLOT_AS3525); /* 0 if fail */
 671             }
 672
 673             /*
 674              * Mount succeeded, or this was an EXTRACTED event,
 675              * in both cases notify the system about the changed filesystems
 676              */
 677             if (microsd_init)
 678                 queue_broadcast(SYS_FS_CHANGED, 0);
 679
 680             sd_enable(false);
 681
 682             /* Access is now safe */
 683             mutex_unlock(&sd_mtx);
 684             fat_unlock();
 685             }
 686             break;
 687 #endif
 688         case SYS_TIMEOUT:
 689             if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
 690             {
 691                 idle_notified = false;
 692             }
 693             else if (!idle_notified)
 694             {
 695                 call_storage_idle_notifys(false);
 696                 idle_notified = true;
 697             }
 698             break;
 699
 700         case SYS_USB_CONNECTED:
 701             usb_acknowledge(SYS_USB_CONNECTED_ACK);
 702             /* Wait until the USB cable is extracted again */
 703             usb_wait_for_disconnect(&sd_queue);
 704
 705             break;
 706         }
 707     }
 708 }
 709
 710 static void init_controller(void)
 711 {
 712     int hcon_numcards = ((MCI_HCON>>1) & 0x1F) + 1;
 713     int card_mask = (1 << hcon_numcards) - 1;
 714     int pwr_mask;
 715
 716 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS)
 717     if (amsv2_variant == 1)
 718         pwr_mask = 1 << 1;
 719     else
 720 #endif
 721         pwr_mask = card_mask;
 722
 723     MCI_PWREN &= ~pwr_mask;             /*  power off all cards  */
 724     MCI_PWREN = pwr_mask;               /*  power up cards  */
 725
 726     MCI_CTRL |= CTRL_RESET;
 727     while(MCI_CTRL & CTRL_RESET)
 728         ;
 729
 730     MCI_RAW_STATUS = 0xffffffff;        /* Clear all MCI Interrupts  */
 731
 732     MCI_TMOUT = 0xffffffff;             /*  data b31:8, response b7:0 */
 733
 734     MCI_CTYPE = 0x0;                    /*  all cards 1 bit bus for now */
 735
 736     MCI_CLKENA = card_mask;             /*  Enables card clocks  */
 737
 738     MCI_ARGUMENT = 0;
 739     MCI_COMMAND = CMD_DONE_BIT|CMD_SEND_CLK_ONLY|CMD_WAIT_PRV_DAT_BIT;
 740     while(MCI_COMMAND & CMD_DONE_BIT)
 741         ;
 742
 743     MCI_DEBNCE = 0xfffff;               /* default value */
 744
 745     /* Rx watermark = 63(sd reads)  Tx watermark = 128 (sd writes) */
 746     MCI_FIFOTH = (MCI_FIFOTH & MCI_FIFOTH_MASK) | 0x503f0080;
 747
 748 /*  RCRC & RTO interrupts should be set together with the CD interrupt but
 749  *  in practice sometimes incorrectly precede the CD interrupt.  If we leave
 750  *  them masked for now we can check them in the isr by reading raw status when
 751  *  the CD int is triggered.
 752  */
 753     MCI_MASK |= (MCI_DATA_ERROR | MCI_INT_DTO | MCI_INT_CD);
 754
 755     MCI_CTRL |= INT_ENABLE | DMA_ENABLE;
 756
 757     MCI_BLKSIZ = SD_BLOCK_SIZE;
 758 }
 759
 760 int sd_init(void)
 761 {
 762     int ret;
 763
 764     bitset32(&CGU_PERI, CGU_MCI_CLOCK_ENABLE);
 765
 766     CGU_IDE =   (1<<7)          /* AHB interface enable */
 767             |   (AS3525_IDE_DIV << 2)
 768             |   1;              /* clock source = PLLA */
 769
 770     CGU_MEMSTICK =  (1<<7)      /* interface enable */
 771                  |  (AS3525_MS_DIV << 2)
 772                  |  1;          /* clock source = PLLA */
 773
 774     CGU_SDSLOT = (1<<7)         /* interface enable */
 775                | (AS3525_SDSLOT_DIV << 2)
 776                | 1;             /* clock source = PLLA */
 777
 778     semaphore_init(&transfer_completion_signal, 1, 0);
 779     semaphore_init(&command_completion_signal, 1, 0);
 780
 781 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS)
 782     if (amsv2_variant == 1)
 783         GPIOB_DIR |= 1 << 5;
 784 #endif
 785
 786 #ifdef HAVE_MULTIDRIVE
 787     /* clear previous irq */
 788     GPIOA_IC = EXT_SD_BITS;
 789     /* enable edge detecting */
 790     GPIOA_IS &= ~EXT_SD_BITS;
 791     /* detect both raising and falling edges */
 792     GPIOA_IBE |= EXT_SD_BITS;
 793     /* enable the card detect interrupt */
 794     GPIOA_IE |= EXT_SD_BITS;
 795 #endif /* HAVE_MULTIDRIVE */
 796
 797 #ifndef SANSA_CLIPV2
 798     /* Configure XPD for SD-MCI interface */
 799     bitset32(&CCU_IO, 1<<2);
 800 #endif
 801
 802     VIC_INT_ENABLE = INTERRUPT_NAND;
 803
 804     init_controller();
 805     ret = sd_init_card(INTERNAL_AS3525);
 806     if(ret < 0)
 807         return ret;
 808
 809     /* init mutex */
 810     mutex_init(&sd_mtx);
 811
 812     queue_init(&sd_queue, true);
 813     create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
 814             sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
 815
 816 #ifndef BOOTLOADER
 817     sd_enabled = true;
 818     sd_enable(false);
 819 #endif
 820     return 0;
 821 }
 822
 823 static int sd_transfer_sectors(IF_MD2(int drive,) unsigned long start,
 824                                 int count, void* buf, bool write)
 825 {
 826     int ret = 0;
 827 #ifndef HAVE_MULTIDRIVE
 828     const int drive = 0;
 829 #endif
 830     bool aligned = !((uintptr_t)buf & (CACHEALIGN_SIZE - 1));
 831     int const retry_all_max = 1;
 832     int retry_all = 0;
 833     int const retry_data_max = 100; /* Generous, methinks */
 834     int retry_data;
 835
 836     mutex_lock(&sd_mtx);
 837 #ifndef BOOTLOADER
 838     sd_enable(true);
 839     led(true);
 840 #endif
 841
 842     if(count < 0) /* XXX: why is it signed ? */
 843     {
 844         ret = -18;
 845         goto sd_transfer_error_no_dma;
 846     }
 847
 848     if((start+count) > card_info[drive].numblocks)
 849     {
 850         ret = -19;
 851         goto sd_transfer_error_no_dma;
 852     }
 853
 854     /* skip SanDisk OF */
 855     if (drive == INTERNAL_AS3525)
 856         start += AMS_OF_SIZE;
 857
 858     /* no need for complete retry on main, just SD */
 859     if (drive == SD_SLOT_AS3525)
 860         retry_all = retry_all_max;
 861
 862 sd_transfer_retry_with_reinit:
 863     if (card_info[drive].initialized <= 0)
 864     {
 865         ret = sd_init_card(drive);
 866         if (!(card_info[drive].initialized))
 867             goto sd_transfer_error_no_dma;
 868     }
 869
 870     /*  CMD7 w/rca: Select card to put it in TRAN state */
 871     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_NO_RESP, NULL))
 872     {
 873         ret = -20;
 874         goto sd_transfer_error_no_dma;
 875     }
 876
 877     dma_retain();
 878
 879     if(aligned)
 880     {   /* direct transfer, indirect is always uncached */
 881         if(write)
 882             commit_dcache_range(buf, count * SECTOR_SIZE);
 883         else
 884             discard_dcache_range(buf, count * SECTOR_SIZE);
 885     }
 886
 887     const int cmd = write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
 888     retry_data = retry_data_max;
 889
 890     while (1)
 891     {
 892         void *dma_buf;
 893         unsigned int transfer = count;
 894
 895         last_disk_activity = current_tick;
 896
 897         if(aligned)
 898         {
 899             dma_buf = AS3525_PHYSICAL_ADDR(buf);
 900         }
 901         else
 902         {
 903             dma_buf = AS3525_PHYSICAL_ADDR(&aligned_buffer[0]);
 904             if(transfer > UNALIGNED_NUM_SECTORS)
 905                 transfer = UNALIGNED_NUM_SECTORS;
 906
 907             if(write)
 908                 memcpy(uncached_buffer, buf, transfer * SD_BLOCK_SIZE);
 909         }
 910
 911         /* Interrupt handler might set this to true during transfer */
 912         retry = false;
 913
 914         MCI_BYTCNT = transfer * SD_BLOCK_SIZE;
 915
 916         ret = sd_wait_for_tran_state(drive);
 917         if (ret < 0)
 918         {
 919             ret -= 25;
 920             goto sd_transfer_error;
 921         }
 922
 923         int arg = start;
 924         if(!(card_info[drive].ocr & (1<<30))) /* not SDHC */
 925             arg *= SD_BLOCK_SIZE;
 926
 927         if(write)
 928             dma_enable_channel(0, dma_buf, MCI_FIFO, DMA_PERI_SD,
 929                 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
 930         else
 931             dma_enable_channel(0, MCI_FIFO, dma_buf, DMA_PERI_SD,
 932                 DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL);
 933
 934         unsigned long dummy; /* if we don't ask for a response, writing fails */
 935         if(!send_cmd(drive, cmd, arg, MCI_RESP, &dummy))
 936         {
 937             ret = -21;
 938             goto sd_transfer_error;
 939         }
 940
 941         semaphore_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 942
 943         last_disk_activity = current_tick;
 944
 945         if(write)
 946         {
 947             /* wait for the card to exit programming state */
 948             while(MCI_STATUS & DATA_BUSY) ;
 949         }
 950
 951         if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_NO_RESP, NULL))
 952         {
 953             ret = -22;
 954             goto sd_transfer_error;
 955         }
 956
 957         if(!retry)
 958         {
 959             if(!write && !aligned)
 960                 memcpy(buf, uncached_buffer, transfer * SD_BLOCK_SIZE);
 961             buf += transfer * SD_BLOCK_SIZE;
 962             start += transfer;
 963             count -= transfer;
 964
 965             if (count > 0)
 966                 continue;
 967         }
 968         else   /*  reset controller if we had an error  */
 969         {
 970             MCI_CTRL |= (FIFO_RESET|DMA_RESET);
 971             while(MCI_CTRL & (FIFO_RESET|DMA_RESET))
 972                 ;
 973             if (--retry_data >= 0)
 974                 continue;
 975         }
 976
 977         break;
 978     }
 979
 980     dma_release();
 981
 982     /* CMD lines are separate, not common, so we need to actively deselect */
 983     /*  CMD7 w/rca =0 : deselects card & puts it in STBY state */
 984     if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_NO_RESP, NULL))
 985     {
 986         ret = -23;
 987         goto sd_transfer_error;
 988     }
 989
 990     while (1)
 991     {
 992 #ifndef BOOTLOADER
 993         sd_enable(false);
 994         led(false);
 995 #endif
 996         mutex_unlock(&sd_mtx);
 997         return ret;
 998
 999 sd_transfer_error:
1000         dma_release();
1001
1002 sd_transfer_error_no_dma:
1003         card_info[drive].initialized = 0;
1004
1005         /* .initialized might have been >= 0 but now stale if the ata sd thread
1006          * isn't handling an insert because of USB */
1007         if (--retry_all >= 0)
1008             goto sd_transfer_retry_with_reinit;
1009     }
1010 }
1011
1012 int sd_read_sectors(IF_MD2(int drive,) unsigned long start, int count,
1013                     void* buf)
1014 {
1015     return sd_transfer_sectors(IF_MD2(drive,) start, count, buf, false);
1016 }
1017
1018 int sd_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
1019                      const void* buf)
1020 {
1021 #if defined(BOOTLOADER) /* we don't need write support in bootloader */
1022 #ifdef HAVE_MULTIDRIVE
1023     (void) drive;
1024 #endif
1025     (void) start;
1026     (void) count;
1027     (void) buf;
1028     return -1;
1029 #else
1030     return sd_transfer_sectors(IF_MD2(drive,) start, count, (void*)buf, true);
1031 #endif /* defined(BOOTLOADER) */
1032 }
1033
1034 #ifndef BOOTLOADER
1035 long sd_last_disk_activity(void)
1036 {
1037     return last_disk_activity;
1038 }
1039
1040 void sd_enable(bool on)
1041 {
1042     if (on)
1043     {
1044         bitset32(&CGU_PERI, CGU_MCI_CLOCK_ENABLE);
1045         CGU_IDE |= (1<<7);                  /* AHB interface enable */
1046         CGU_MEMSTICK |= (1<<7);             /* interface enable */
1047         CGU_SDSLOT |= (1<<7);               /* interface enable */
1048     }
1049     else
1050     {
1051         CGU_SDSLOT &= ~(1<<7);              /* interface enable */
1052         CGU_MEMSTICK &= ~(1<<7);            /* interface enable */
1053         CGU_IDE &= ~(1<<7);                 /* AHB interface enable */
1054         bitclr32(&CGU_PERI, CGU_MCI_CLOCK_ENABLE);
1055     }
1056 }
1057
1058 tCardInfo *card_get_info_target(int card_no)
1059 {
1060     return &card_info[card_no];
1061 }
1062 #endif /* BOOTLOADER */
1063
1064 #ifdef HAVE_HOTSWAP
1065 bool sd_removable(IF_MD_NONVOID(int drive))
1066 {
1067     return (drive==1);
1068 }
1069
1070 bool sd_present(IF_MD_NONVOID(int drive))
1071 {
1072     return (drive == 0) ? true : card_detect_target();
1073 }
1074
1075 static int sd1_oneshot_callback(struct timeout *tmo)
1076 {
1077     (void)tmo;
1078
1079     /* This is called only if the state was stable for 300ms - check state
1080      * and post appropriate event. */
1081     if (card_detect_target())
1082     {
1083         queue_broadcast(SYS_HOTSWAP_INSERTED, 0);
1084     }
1085     else
1086         queue_broadcast(SYS_HOTSWAP_EXTRACTED, 0);
1087
1088     return 0;
1089 }
1090
1091 void sd_gpioa_isr(void)
1092 {
1093     static struct timeout sd1_oneshot;
1094     if (GPIOA_MIS & EXT_SD_BITS)
1095         timeout_register(&sd1_oneshot, sd1_oneshot_callback, (3*HZ/10), 0);
1096     /* acknowledge interrupt */
1097     GPIOA_IC = EXT_SD_BITS;
1098 }
1099 #endif /* HAVE_HOTSWAP */
1100
1101 #ifdef CONFIG_STORAGE_MULTI
1102 int sd_num_drives(int first_drive)
1103 {
1104     /* We don't care which logical drive number(s) we have been assigned */
1105     (void)first_drive;
1106
1107     return NUM_DRIVES;
1108 }
1109 #endif /* CONFIG_STORAGE_MULTI */