1 /***************************************************************************
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
10 * Copyright (C) 2002 Randy D. Wood
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
20 ****************************************************************************/
24 #ifdef HAVE_REMOTE_LCD
25 #include "lcd-remote.h"
36 #include "core_alloc.h"
41 #include "crc32-mi4.h"
42 #undef FIRMWARE_OFFSET_FILE_CRC
43 #undef FIRMWARE_OFFSET_FILE_DATA
44 #define FIRMWARE_OFFSET_FILE_CRC 0xC
45 #define FIRMWARE_OFFSET_FILE_DATA 0x200
48 #if !defined(IRIVER_IFP7XX_SERIES)
49 /* FIX: this doesn't work on iFP */
51 #define IRQ0_EDGE_TRIGGER 0x80
53 static int rolo_handle
;
55 /* Handle the COP properly - it needs to jump to a function outside SDRAM while
56 * the new firmware is being loaded, and then jump to the start of SDRAM
57 * TODO: Use the mailboxes built into the PP processor for this
61 volatile unsigned char IDATA_ATTR cpu_message
= 0;
62 volatile unsigned char IDATA_ATTR cpu_reply
= 0;
63 extern int cop_idlestackbegin
[];
65 void rolo_restart_cop(void) ICODE_ATTR
;
66 void rolo_restart_cop(void)
68 if (CURRENT_CORE
== CPU
)
70 /* There should be free thread slots aplenty */
71 create_thread(rolo_restart_cop
, cop_idlestackbegin
, IDLE_STACK_SIZE
,
72 0, "rolo COP" IF_PRIO(, PRIORITY_REALTIME
)
79 /* Invalidate cache */
80 commit_discard_idcache();
83 CACHE_CTL
= CACHE_CTL_DISABLE
;
85 /* Tell the main core that we're ready to reload */
88 /* Wait while RoLo loads the image into SDRAM */
89 /* TODO: Accept checksum failure gracefully */
90 while(cpu_message
!= 1);
92 /* Acknowledge the CPU and then reload */
100 #endif /* NUM_CORES > 1 */
103 static void rolo_error(const char *text
)
105 rolo_handle
= core_free(rolo_handle
);
107 lcd_puts(0, 0, "ROLO error:");
108 lcd_puts_scroll(0, 1, text
);
116 #if CONFIG_CPU == SH7034 || CONFIG_CPU == IMX31L
117 /* these are in assembler file "descramble.S" for SH7034 */
118 extern unsigned short descramble(const unsigned char* source
,
119 unsigned char* dest
, int length
);
120 /* this is in firmware/target/arm/imx31/rolo_restart.c for IMX31 */
121 extern void rolo_restart(const unsigned char* source
, unsigned char* dest
,
125 /* explicitly put this code in iram, ICODE_ATTR is defined to be null for some
126 targets that are low on iram, like the gigabeat F/X */
127 void rolo_restart(const unsigned char* source
, unsigned char* dest
,
128 long length
) __attribute__ ((section(".icode")));
129 void rolo_restart(const unsigned char* source
, unsigned char* dest
,
133 unsigned char* localdest
= dest
;
135 /* This is the equivalent of a call to memcpy() but this must be done from
136 iram to avoid overwriting itself and we don't want to depend on memcpy()
137 always being in iram */
138 for(i
= 0;i
< length
;i
++)
139 *localdest
++ = *source
++;
141 #if defined(CPU_COLDFIRE)
143 "movec.l %0,%%vbr \n"
144 "move.l (%0)+,%%sp \n"
149 #elif defined(CPU_PP)
153 commit_discard_idcache();
156 CACHE_CTL
= CACHE_CTL_DISABLE
;
158 /* Reset the memory mapping registers to zero */
160 volatile unsigned long *mmap_reg
;
161 for (mmap_reg
= &MMAP_FIRST
; mmap_reg
<= &MMAP_LAST
; mmap_reg
++)
166 /* Tell the COP it's safe to continue rebooting */
169 /* Wait for the COP to tell us it is rebooting */
170 while(cpu_reply
!= 2);
178 #elif defined(CPU_ARM)
179 /* Flush and invalidate caches */
180 commit_discard_idcache();
185 #elif defined(CPU_MIPS)
186 __dcache_writeback_all();
195 /* This is assigned in the linker control file */
196 extern unsigned long loadaddress
;
198 /***************************************************************************
200 * Name: rolo_load_app(char *filename,int scrambled)
201 * Filename must be a fully defined filename including the path and extension
203 ***************************************************************************/
204 int rolo_load(const char* filename
)
208 #if defined(CPU_COLDFIRE) || defined(CPU_ARM) || defined(CPU_MIPS)
209 #if !defined(MI4_FORMAT)
212 unsigned long checksum
,file_checksum
;
215 unsigned short checksum
,file_checksum
;
217 unsigned char* ramstart
= (void*)&loadaddress
;
218 unsigned char* filebuf
;
222 lcd_puts(0, 0, "ROLO...");
223 lcd_puts(0, 1, "Loading");
225 #ifdef HAVE_REMOTE_LCD
226 lcd_remote_clear_display();
227 lcd_remote_puts(0, 0, "ROLO...");
228 lcd_remote_puts(0, 1, "Loading");
234 fd
= open(filename
, O_RDONLY
);
236 rolo_error("File not found");
240 length
= filesize(fd
) - FIRMWARE_OFFSET_FILE_DATA
;
242 /* get the system buffer. release only in case of error, otherwise
243 * we don't return anyway */
244 rolo_handle
= core_alloc_maximum("rolo", &filebuf_size
, NULL
);
245 filebuf
= core_get_data(rolo_handle
);
247 #if CONFIG_CPU != SH7034
248 /* Read and save checksum */
249 lseek(fd
, FIRMWARE_OFFSET_FILE_CRC
, SEEK_SET
);
250 if (read(fd
, &file_checksum
, 4) != 4) {
251 rolo_error("Error Reading checksum");
255 #if !defined(MI4_FORMAT)
256 /* Rockbox checksums are big-endian */
257 file_checksum
= betoh32(file_checksum
);
260 #if defined(CPU_PP) && NUM_CORES > 1
261 lcd_puts(0, 2, "Waiting for coprocessor...");
264 /* Wait for COP to be in safe code */
265 while(cpu_reply
!= 1);
270 lseek(fd
, FIRMWARE_OFFSET_FILE_DATA
, SEEK_SET
);
272 /* this shouldn't happen, but well */
273 if ((long)filebuf_size
< length
)
275 rolo_error("File too big");
279 if (read(fd
, filebuf
, length
) != length
) {
280 rolo_error("Error Reading File");
285 /* Check CRC32 to see if we have a valid file */
286 chksum_crc32gentab();
287 checksum
= chksum_crc32 (filebuf
, length
);
289 checksum
= MODEL_NUMBER
;
291 for(i
= 0;i
< length
;i
++) {
292 checksum
+= filebuf
[i
];
296 /* Verify checksum against file header */
297 if (checksum
!= file_checksum
) {
298 rolo_error("Checksum Error");
302 #ifdef HAVE_STORAGE_FLUSH
303 lcd_puts(0, 1, "Flushing storage buffers");
308 lcd_puts(0, 1, "Executing");
310 #ifdef HAVE_REMOTE_LCD
311 lcd_remote_puts(0, 1, "Executing");
316 #if CONFIG_CPU != IMX31L /* We're not finished yet */
318 /* Should do these together since some ARM version should never have
319 * FIQ disabled and not IRQ (imx31 errata). */
320 disable_interrupt(IRQ_FIQ_STATUS
);
322 /* Some targets have a higher disable level than HIGEST_IRQ_LEVEL */
323 set_irq_level(DISABLE_INTERRUPTS
);
325 #endif /* CONFIG_CPU == IMX31L */
327 #else /* CONFIG_CPU == SH7034 */
328 /* Read file length from header and compare to real file length */
329 lseek(fd
, FIRMWARE_OFFSET_FILE_LENGTH
, SEEK_SET
);
330 if(read(fd
, &file_length
, 4) != 4) {
331 rolo_error("Error Reading File Length");
334 if (length
!= file_length
) {
335 rolo_error("File length mismatch");
339 /* Read and save checksum */
340 lseek(fd
, FIRMWARE_OFFSET_FILE_CRC
, SEEK_SET
);
341 if (read(fd
, &file_checksum
, 2) != 2) {
342 rolo_error("Error Reading checksum");
345 lseek(fd
, FIRMWARE_OFFSET_FILE_DATA
, SEEK_SET
);
347 /* verify that file can be read and descrambled */
348 if ((size_t)((2*length
)+4) >= filebuf_size
) {
349 rolo_error("Not enough room to load file");
353 if (read(fd
, &filebuf
[length
], length
) != (int)length
) {
354 rolo_error("Error Reading File");
358 lcd_puts(0, 1, "Descramble");
361 checksum
= descramble(filebuf
+ length
, filebuf
, length
);
363 /* Verify checksum against file header */
364 if (checksum
!= file_checksum
) {
365 rolo_error("Checksum Error");
369 #ifdef HAVE_STORAGE_FLUSH
370 lcd_puts(0, 1, "Flushing ");
375 lcd_puts(0, 1, "Executing ");
378 set_irq_level(HIGHEST_IRQ_LEVEL
);
380 /* Calling these 2 initialization routines was necessary to get the
381 the origional Archos version of the firmware to load and execute. */
382 system_init(); /* Initialize system for restart */
383 i2c_init(); /* Init i2c bus - it seems like a good idea */
384 ICR
= IRQ0_EDGE_TRIGGER
; /* Make IRQ0 edge triggered */
385 TSTR
= 0xE0; /* disable all timers */
386 /* model-specific de-init, needed when flashed */
387 /* Especially the Archos software is picky about this */
388 #if defined(ARCHOS_RECORDER) || defined(ARCHOS_RECORDERV2) || \
389 defined(ARCHOS_FMRECORDER)
393 rolo_restart(filebuf
, ramstart
, length
);
395 return 0; /* this is never reached */
396 (void)checksum
; (void)file_checksum
;
398 #else /* !defined(IRIVER_IFP7XX_SERIES) */
399 int rolo_load(const char* filename
)
406 #endif /* !defined(IRIVER_IFP7XX_SERIES) */