firmware/export/s5l8702.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id: s5l8700.h 28791 2010-12-11 09:39:33Z Buschel $
   9  *
  10  * Copyright (C) 2008 by Marcoen Hirschberg, Bart van Adrichem
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #ifndef __S5L8702_H__
  23 #define __S5L8702_H__
  24
  25 #include <inttypes.h>
  26
  27 #define REG8_PTR_T  volatile uint8_t *
  28 #define REG16_PTR_T volatile uint16_t *
  29 #define REG32_PTR_T volatile uint32_t *
  30
  31 #define TIMER_FREQ  54000000
  32
  33 #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
  34
  35 #define DRAM_ORIG 0x08000000
  36 #define IRAM_ORIG 0
  37
  38 #define DRAM_SIZE (MEMORYSIZE * 0x100000)
  39 #define IRAM_SIZE 0x40000
  40
  41 #define TTB_SIZE                  0x4000
  42 #define TTB_BASE_ADDR             (DRAM_ORIG + DRAM_SIZE - TTB_SIZE)
  43
  44 /////SYSTEM CONTROLLER/////
  45 #define CLKCON0      (*((volatile uint32_t*)(0x3C500000)))
  46 #define CLKCON1      (*((volatile uint32_t*)(0x3C500004)))
  47 #define CLKCON2      (*((volatile uint32_t*)(0x3C500008)))
  48 #define CLKCON3      (*((volatile uint32_t*)(0x3C50000C)))
  49 #define CLKCON4      (*((volatile uint32_t*)(0x3C500010)))
  50 #define CLKCON5      (*((volatile uint32_t*)(0x3C500014)))
  51 #define PLL0PMS      (*((volatile uint32_t*)(0x3C500020)))
  52 #define PLL1PMS      (*((volatile uint32_t*)(0x3C500024)))
  53 #define PLL2PMS      (*((volatile uint32_t*)(0x3C500028)))
  54 #define PLL0LCNT     (*((volatile uint32_t*)(0x3C500030)))
  55 #define PLL1LCNT     (*((volatile uint32_t*)(0x3C500034)))
  56 #define PLL2LCNT     (*((volatile uint32_t*)(0x3C500038)))
  57 #define PLLLOCK      (*((volatile uint32_t*)(0x3C500040)))
  58 #define PLLMODE      (*((volatile uint32_t*)(0x3C500044)))
  59 #define PWRCON(i)    (*((uint32_t volatile*)(0x3C500000 \
  60                                            + ((i) == 4 ? 0x6C : \
  61                                              ((i) == 3 ? 0x68 : \
  62                                              ((i) == 2 ? 0x58 : \
  63                                              ((i) == 1 ? 0x4C : \
  64                                                          0x48)))))))
  65
  66
  67 /////TIMER/////
  68 #define TACON        (*((uint32_t volatile*)(0x3C700000)))
  69 #define TACMD        (*((uint32_t volatile*)(0x3C700004)))
  70 #define TADATA0      (*((uint32_t volatile*)(0x3C700008)))
  71 #define TADATA1      (*((uint32_t volatile*)(0x3C70000C)))
  72 #define TAPRE        (*((uint32_t volatile*)(0x3C700010)))
  73 #define TACNT        (*((uint32_t volatile*)(0x3C700014)))
  74 #define TBCON        (*((uint32_t volatile*)(0x3C700020)))
  75 #define TBCMD        (*((uint32_t volatile*)(0x3C700024)))
  76 #define TBDATA0      (*((uint32_t volatile*)(0x3C700028)))
  77 #define TBDATA1      (*((uint32_t volatile*)(0x3C70002C)))
  78 #define TBPRE        (*((uint32_t volatile*)(0x3C700030)))
  79 #define TBCNT        (*((uint32_t volatile*)(0x3C700034)))
  80 #define TCCON        (*((uint32_t volatile*)(0x3C700040)))
  81 #define TCCMD        (*((uint32_t volatile*)(0x3C700044)))
  82 #define TCDATA0      (*((uint32_t volatile*)(0x3C700048)))
  83 #define TCDATA1      (*((uint32_t volatile*)(0x3C70004C)))
  84 #define TCPRE        (*((uint32_t volatile*)(0x3C700050)))
  85 #define TCCNT        (*((uint32_t volatile*)(0x3C700054)))
  86 #define TDCON        (*((uint32_t volatile*)(0x3C700060)))
  87 #define TDCMD        (*((uint32_t volatile*)(0x3C700064)))
  88 #define TDDATA0      (*((uint32_t volatile*)(0x3C700068)))
  89 #define TDDATA1      (*((uint32_t volatile*)(0x3C70006C)))
  90 #define TDPRE        (*((uint32_t volatile*)(0x3C700070)))
  91 #define TDCNT        (*((uint32_t volatile*)(0x3C700074)))
  92 #define TECON        (*((uint32_t volatile*)(0x3C7000A0)))
  93 #define TECMD        (*((uint32_t volatile*)(0x3C7000A4)))
  94 #define TEDATA0      (*((uint32_t volatile*)(0x3C7000A8)))
  95 #define TEDATA1      (*((uint32_t volatile*)(0x3C7000AC)))
  96 #define TEPRE        (*((uint32_t volatile*)(0x3C7000B0)))
  97 #define TECNT        (*((uint32_t volatile*)(0x3C7000B4)))
  98 #define TFCON        (*((uint32_t volatile*)(0x3C7000C0)))
  99 #define TFCMD        (*((uint32_t volatile*)(0x3C7000C4)))
 100 #define TFDATA0      (*((uint32_t volatile*)(0x3C7000C8)))
 101 #define TFDATA1      (*((uint32_t volatile*)(0x3C7000CC)))
 102 #define TFPRE        (*((uint32_t volatile*)(0x3C7000D0)))
 103 #define TFCNT        (*((uint32_t volatile*)(0x3C7000D4)))
 104 #define TGCON        (*((uint32_t volatile*)(0x3C7000E0)))
 105 #define TGCMD        (*((uint32_t volatile*)(0x3C7000E4)))
 106 #define TGDATA0      (*((uint32_t volatile*)(0x3C7000E8)))
 107 #define TGDATA1      (*((uint32_t volatile*)(0x3C7000EC)))
 108 #define TGPRE        (*((uint32_t volatile*)(0x3C7000F0)))
 109 #define TGCNT        (*((uint32_t volatile*)(0x3C7000F4)))
 110 #define THCON        (*((uint32_t volatile*)(0x3C700100)))
 111 #define THCMD        (*((uint32_t volatile*)(0x3C700104)))
 112 #define THDATA0      (*((uint32_t volatile*)(0x3C700108)))
 113 #define THDATA1      (*((uint32_t volatile*)(0x3C70010C)))
 114 #define THPRE        (*((uint32_t volatile*)(0x3C700110)))
 115 #define THCNT        (*((uint32_t volatile*)(0x3C700114)))
 116 #define USEC_TIMER   TECNT
 117
 118
 119 /////USB/////
 120 #define OTGBASE 0x38400000
 121 #define PHYBASE 0x3C400000
 122 #define SYNOPSYSOTG_CLOCK 0
 123 #define SYNOPSYSOTG_AHBCFG 0x2B
 124
 125
 126 /////I2C/////
 127 #define IICCON(bus)  (*((uint32_t volatile*)(0x3C600000 + 0x300000 * (bus))))
 128 #define IICSTAT(bus) (*((uint32_t volatile*)(0x3C600004 + 0x300000 * (bus))))
 129 #define IICADD(bus)  (*((uint32_t volatile*)(0x3C600008 + 0x300000 * (bus))))
 130 #define IICDS(bus)   (*((uint32_t volatile*)(0x3C60000C + 0x300000 * (bus))))
 131
 132
 133 /////INTERRUPT CONTROLLERS/////
 134 #define VICIRQSTATUS(v)       (*((uint32_t volatile*)(0x38E00000 + 0x1000 * (v))))
 135 #define VICFIQSTATUS(v)       (*((uint32_t volatile*)(0x38E00004 + 0x1000 * (v))))
 136 #define VICRAWINTR(v)         (*((uint32_t volatile*)(0x38E00008 + 0x1000 * (v))))
 137 #define VICINTSELECT(v)       (*((uint32_t volatile*)(0x38E0000C + 0x1000 * (v))))
 138 #define VICINTENABLE(v)       (*((uint32_t volatile*)(0x38E00010 + 0x1000 * (v))))
 139 #define VICINTENCLEAR(v)      (*((uint32_t volatile*)(0x38E00014 + 0x1000 * (v))))
 140 #define VICSOFTINT(v)         (*((uint32_t volatile*)(0x38E00018 + 0x1000 * (v))))
 141 #define VICSOFTINTCLEAR(v)    (*((uint32_t volatile*)(0x38E0001C + 0x1000 * (v))))
 142 #define VICPROTECTION(v)      (*((uint32_t volatile*)(0x38E00020 + 0x1000 * (v))))
 143 #define VICSWPRIORITYMASK(v)  (*((uint32_t volatile*)(0x38E00024 + 0x1000 * (v))))
 144 #define VICPRIORITYDAISY(v)   (*((uint32_t volatile*)(0x38E00028 + 0x1000 * (v))))
 145 #define VICVECTADDR(v, i)     (*((uint32_t volatile*)(0x38E00100 + 0x1000 * (v) + 4 * (i))))
 146 #define VICVECTPRIORITY(v, i) (*((uint32_t volatile*)(0x38E00200 + 0x1000 * (v) + 4 * (i))))
 147 #define VICADDRESS(v)         (*((const void* volatile*)(0x38E00F00 + 0x1000 * (v))))
 148 #define VIC0IRQSTATUS         (*((uint32_t volatile*)(0x38E00000)))
 149 #define VIC0FIQSTATUS         (*((uint32_t volatile*)(0x38E00004)))
 150 #define VIC0RAWINTR           (*((uint32_t volatile*)(0x38E00008)))
 151 #define VIC0INTSELECT         (*((uint32_t volatile*)(0x38E0000C)))
 152 #define VIC0INTENABLE         (*((uint32_t volatile*)(0x38E00010)))
 153 #define VIC0INTENCLEAR        (*((uint32_t volatile*)(0x38E00014)))
 154 #define VIC0SOFTINT           (*((uint32_t volatile*)(0x38E00018)))
 155 #define VIC0SOFTINTCLEAR      (*((uint32_t volatile*)(0x38E0001C)))
 156 #define VIC0PROTECTION        (*((uint32_t volatile*)(0x38E00020)))
 157 #define VIC0SWPRIORITYMASK    (*((uint32_t volatile*)(0x38E00024)))
 158 #define VIC0PRIORITYDAISY     (*((uint32_t volatile*)(0x38E00028)))
 159 #define VIC0VECTADDR(i)       (*((const void* volatile*)(0x38E00100 + 4 * (i))))
 160 #define VIC0VECTADDR0         (*((const void* volatile*)(0x38E00100)))
 161 #define VIC0VECTADDR1         (*((const void* volatile*)(0x38E00104)))
 162 #define VIC0VECTADDR2         (*((const void* volatile*)(0x38E00108)))
 163 #define VIC0VECTADDR3         (*((const void* volatile*)(0x38E0010C)))
 164 #define VIC0VECTADDR4         (*((const void* volatile*)(0x38E00110)))
 165 #define VIC0VECTADDR5         (*((const void* volatile*)(0x38E00114)))
 166 #define VIC0VECTADDR6         (*((const void* volatile*)(0x38E00118)))
 167 #define VIC0VECTADDR7         (*((const void* volatile*)(0x38E0011C)))
 168 #define VIC0VECTADDR8         (*((const void* volatile*)(0x38E00120)))
 169 #define VIC0VECTADDR9         (*((const void* volatile*)(0x38E00124)))
 170 #define VIC0VECTADDR10        (*((const void* volatile*)(0x38E00128)))
 171 #define VIC0VECTADDR11        (*((const void* volatile*)(0x38E0012C)))
 172 #define VIC0VECTADDR12        (*((const void* volatile*)(0x38E00130)))
 173 #define VIC0VECTADDR13        (*((const void* volatile*)(0x38E00134)))
 174 #define VIC0VECTADDR14        (*((const void* volatile*)(0x38E00138)))
 175 #define VIC0VECTADDR15        (*((const void* volatile*)(0x38E0013C)))
 176 #define VIC0VECTADDR16        (*((const void* volatile*)(0x38E00140)))
 177 #define VIC0VECTADDR17        (*((const void* volatile*)(0x38E00144)))
 178 #define VIC0VECTADDR18        (*((const void* volatile*)(0x38E00148)))
 179 #define VIC0VECTADDR19        (*((const void* volatile*)(0x38E0014C)))
 180 #define VIC0VECTADDR20        (*((const void* volatile*)(0x38E00150)))
 181 #define VIC0VECTADDR21        (*((const void* volatile*)(0x38E00154)))
 182 #define VIC0VECTADDR22        (*((const void* volatile*)(0x38E00158)))
 183 #define VIC0VECTADDR23        (*((const void* volatile*)(0x38E0015C)))
 184 #define VIC0VECTADDR24        (*((const void* volatile*)(0x38E00160)))
 185 #define VIC0VECTADDR25        (*((const void* volatile*)(0x38E00164)))
 186 #define VIC0VECTADDR26        (*((const void* volatile*)(0x38E00168)))
 187 #define VIC0VECTADDR27        (*((const void* volatile*)(0x38E0016C)))
 188 #define VIC0VECTADDR28        (*((const void* volatile*)(0x38E00170)))
 189 #define VIC0VECTADDR29        (*((const void* volatile*)(0x38E00174)))
 190 #define VIC0VECTADDR30        (*((const void* volatile*)(0x38E00178)))
 191 #define VIC0VECTADDR31        (*((const void* volatile*)(0x38E0017C)))
 192 #define VIC0VECTPRIORITY(i)   (*((uint32_t volatile*)(0x38E00200 + 4 * (i))))
 193 #define VIC0VECTPRIORITY0     (*((uint32_t volatile*)(0x38E00200)))
 194 #define VIC0VECTPRIORITY1     (*((uint32_t volatile*)(0x38E00204)))
 195 #define VIC0VECTPRIORITY2     (*((uint32_t volatile*)(0x38E00208)))
 196 #define VIC0VECTPRIORITY3     (*((uint32_t volatile*)(0x38E0020C)))
 197 #define VIC0VECTPRIORITY4     (*((uint32_t volatile*)(0x38E00210)))
 198 #define VIC0VECTPRIORITY5     (*((uint32_t volatile*)(0x38E00214)))
 199 #define VIC0VECTPRIORITY6     (*((uint32_t volatile*)(0x38E00218)))
 200 #define VIC0VECTPRIORITY7     (*((uint32_t volatile*)(0x38E0021C)))
 201 #define VIC0VECTPRIORITY8     (*((uint32_t volatile*)(0x38E00220)))
 202 #define VIC0VECTPRIORITY9     (*((uint32_t volatile*)(0x38E00224)))
 203 #define VIC0VECTPRIORITY10    (*((uint32_t volatile*)(0x38E00228)))
 204 #define VIC0VECTPRIORITY11    (*((uint32_t volatile*)(0x38E0022C)))
 205 #define VIC0VECTPRIORITY12    (*((uint32_t volatile*)(0x38E00230)))
 206 #define VIC0VECTPRIORITY13    (*((uint32_t volatile*)(0x38E00234)))
 207 #define VIC0VECTPRIORITY14    (*((uint32_t volatile*)(0x38E00238)))
 208 #define VIC0VECTPRIORITY15    (*((uint32_t volatile*)(0x38E0023C)))
 209 #define VIC0VECTPRIORITY16    (*((uint32_t volatile*)(0x38E00240)))
 210 #define VIC0VECTPRIORITY17    (*((uint32_t volatile*)(0x38E00244)))
 211 #define VIC0VECTPRIORITY18    (*((uint32_t volatile*)(0x38E00248)))
 212 #define VIC0VECTPRIORITY19    (*((uint32_t volatile*)(0x38E0024C)))
 213 #define VIC0VECTPRIORITY20    (*((uint32_t volatile*)(0x38E00250)))
 214 #define VIC0VECTPRIORITY21    (*((uint32_t volatile*)(0x38E00254)))
 215 #define VIC0VECTPRIORITY22    (*((uint32_t volatile*)(0x38E00258)))
 216 #define VIC0VECTPRIORITY23    (*((uint32_t volatile*)(0x38E0025C)))
 217 #define VIC0VECTPRIORITY24    (*((uint32_t volatile*)(0x38E00260)))
 218 #define VIC0VECTPRIORITY25    (*((uint32_t volatile*)(0x38E00264)))
 219 #define VIC0VECTPRIORITY26    (*((uint32_t volatile*)(0x38E00268)))
 220 #define VIC0VECTPRIORITY27    (*((uint32_t volatile*)(0x38E0026C)))
 221 #define VIC0VECTPRIORITY28    (*((uint32_t volatile*)(0x38E00270)))
 222 #define VIC0VECTPRIORITY29    (*((uint32_t volatile*)(0x38E00274)))
 223 #define VIC0VECTPRIORITY30    (*((uint32_t volatile*)(0x38E00278)))
 224 #define VIC0VECTPRIORITY31    (*((uint32_t volatile*)(0x38E0027C)))
 225 #define VIC0ADDRESS           (*((void* volatile*)(0x38E00F00)))
 226 #define VIC1IRQSTATUS         (*((uint32_t volatile*)(0x38E01000)))
 227 #define VIC1FIQSTATUS         (*((uint32_t volatile*)(0x38E01004)))
 228 #define VIC1RAWINTR           (*((uint32_t volatile*)(0x38E01008)))
 229 #define VIC1INTSELECT         (*((uint32_t volatile*)(0x38E0100C)))
 230 #define VIC1INTENABLE         (*((uint32_t volatile*)(0x38E01010)))
 231 #define VIC1INTENCLEAR        (*((uint32_t volatile*)(0x38E01014)))
 232 #define VIC1SOFTINT           (*((uint32_t volatile*)(0x38E01018)))
 233 #define VIC1SOFTINTCLEAR      (*((uint32_t volatile*)(0x38E0101C)))
 234 #define VIC1PROTECTION        (*((uint32_t volatile*)(0x38E01020)))
 235 #define VIC1SWPRIORITYMASK    (*((uint32_t volatile*)(0x38E01024)))
 236 #define VIC1PRIORITYDAISY     (*((uint32_t volatile*)(0x38E01028)))
 237 #define VIC1VECTADDR(i)       (*((const void* volatile*)(0x38E01100 + 4 * (i))))
 238 #define VIC1VECTADDR0         (*((const void* volatile*)(0x38E01100)))
 239 #define VIC1VECTADDR1         (*((const void* volatile*)(0x38E01104)))
 240 #define VIC1VECTADDR2         (*((const void* volatile*)(0x38E01108)))
 241 #define VIC1VECTADDR3         (*((const void* volatile*)(0x38E0110C)))
 242 #define VIC1VECTADDR4         (*((const void* volatile*)(0x38E01110)))
 243 #define VIC1VECTADDR5         (*((const void* volatile*)(0x38E01114)))
 244 #define VIC1VECTADDR6         (*((const void* volatile*)(0x38E01118)))
 245 #define VIC1VECTADDR7         (*((const void* volatile*)(0x38E0111C)))
 246 #define VIC1VECTADDR8         (*((const void* volatile*)(0x38E01120)))
 247 #define VIC1VECTADDR9         (*((const void* volatile*)(0x38E01124)))
 248 #define VIC1VECTADDR10        (*((const void* volatile*)(0x38E01128)))
 249 #define VIC1VECTADDR11        (*((const void* volatile*)(0x38E0112C)))
 250 #define VIC1VECTADDR12        (*((const void* volatile*)(0x38E01130)))
 251 #define VIC1VECTADDR13        (*((const void* volatile*)(0x38E01134)))
 252 #define VIC1VECTADDR14        (*((const void* volatile*)(0x38E01138)))
 253 #define VIC1VECTADDR15        (*((const void* volatile*)(0x38E0113C)))
 254 #define VIC1VECTADDR16        (*((const void* volatile*)(0x38E01140)))
 255 #define VIC1VECTADDR17        (*((const void* volatile*)(0x38E01144)))
 256 #define VIC1VECTADDR18        (*((const void* volatile*)(0x38E01148)))
 257 #define VIC1VECTADDR19        (*((const void* volatile*)(0x38E0114C)))
 258 #define VIC1VECTADDR20        (*((const void* volatile*)(0x38E01150)))
 259 #define VIC1VECTADDR21        (*((const void* volatile*)(0x38E01154)))
 260 #define VIC1VECTADDR22        (*((const void* volatile*)(0x38E01158)))
 261 #define VIC1VECTADDR23        (*((const void* volatile*)(0x38E0115C)))
 262 #define VIC1VECTADDR24        (*((const void* volatile*)(0x38E01160)))
 263 #define VIC1VECTADDR25        (*((const void* volatile*)(0x38E01164)))
 264 #define VIC1VECTADDR26        (*((const void* volatile*)(0x38E01168)))
 265 #define VIC1VECTADDR27        (*((const void* volatile*)(0x38E0116C)))
 266 #define VIC1VECTADDR28        (*((const void* volatile*)(0x38E01170)))
 267 #define VIC1VECTADDR29        (*((const void* volatile*)(0x38E01174)))
 268 #define VIC1VECTADDR30        (*((const void* volatile*)(0x38E01178)))
 269 #define VIC1VECTADDR31        (*((const void* volatile*)(0x38E0117C)))
 270 #define VIC1VECTPRIORITY(i)   (*((uint32_t volatile*)(0x38E01200 + 4 * (i))))
 271 #define VIC1VECTPRIORITY0     (*((uint32_t volatile*)(0x38E01200)))
 272 #define VIC1VECTPRIORITY1     (*((uint32_t volatile*)(0x38E01204)))
 273 #define VIC1VECTPRIORITY2     (*((uint32_t volatile*)(0x38E01208)))
 274 #define VIC1VECTPRIORITY3     (*((uint32_t volatile*)(0x38E0120C)))
 275 #define VIC1VECTPRIORITY4     (*((uint32_t volatile*)(0x38E01210)))
 276 #define VIC1VECTPRIORITY5     (*((uint32_t volatile*)(0x38E01214)))
 277 #define VIC1VECTPRIORITY6     (*((uint32_t volatile*)(0x38E01218)))
 278 #define VIC1VECTPRIORITY7     (*((uint32_t volatile*)(0x38E0121C)))
 279 #define VIC1VECTPRIORITY8     (*((uint32_t volatile*)(0x38E01220)))
 280 #define VIC1VECTPRIORITY9     (*((uint32_t volatile*)(0x38E01224)))
 281 #define VIC1VECTPRIORITY10    (*((uint32_t volatile*)(0x38E01228)))
 282 #define VIC1VECTPRIORITY11    (*((uint32_t volatile*)(0x38E0122C)))
 283 #define VIC1VECTPRIORITY12    (*((uint32_t volatile*)(0x38E01230)))
 284 #define VIC1VECTPRIORITY13    (*((uint32_t volatile*)(0x38E01234)))
 285 #define VIC1VECTPRIORITY14    (*((uint32_t volatile*)(0x38E01238)))
 286 #define VIC1VECTPRIORITY15    (*((uint32_t volatile*)(0x38E0123C)))
 287 #define VIC1VECTPRIORITY16    (*((uint32_t volatile*)(0x38E01240)))
 288 #define VIC1VECTPRIORITY17    (*((uint32_t volatile*)(0x38E01244)))
 289 #define VIC1VECTPRIORITY18    (*((uint32_t volatile*)(0x38E01248)))
 290 #define VIC1VECTPRIORITY19    (*((uint32_t volatile*)(0x38E0124C)))
 291 #define VIC1VECTPRIORITY20    (*((uint32_t volatile*)(0x38E01250)))
 292 #define VIC1VECTPRIORITY21    (*((uint32_t volatile*)(0x38E01254)))
 293 #define VIC1VECTPRIORITY22    (*((uint32_t volatile*)(0x38E01258)))
 294 #define VIC1VECTPRIORITY23    (*((uint32_t volatile*)(0x38E0125C)))
 295 #define VIC1VECTPRIORITY24    (*((uint32_t volatile*)(0x38E01260)))
 296 #define VIC1VECTPRIORITY25    (*((uint32_t volatile*)(0x38E01264)))
 297 #define VIC1VECTPRIORITY26    (*((uint32_t volatile*)(0x38E01268)))
 298 #define VIC1VECTPRIORITY27    (*((uint32_t volatile*)(0x38E0126C)))
 299 #define VIC1VECTPRIORITY28    (*((uint32_t volatile*)(0x38E01270)))
 300 #define VIC1VECTPRIORITY29    (*((uint32_t volatile*)(0x38E01274)))
 301 #define VIC1VECTPRIORITY30    (*((uint32_t volatile*)(0x38E01278)))
 302 #define VIC1VECTPRIORITY31    (*((uint32_t volatile*)(0x38E0127C)))
 303 #define VIC1ADDRESS           (*((void* volatile*)(0x38E01F00)))
 304
 305
 306 /////GPIO/////
 307 #define PCON(i)       (*((uint32_t volatile*)(0x3cf00000 + ((i) << 5))))
 308 #define PDAT(i)       (*((uint32_t volatile*)(0x3cf00004 + ((i) << 5))))
 309 #define PUNA(i)       (*((uint32_t volatile*)(0x3cf00008 + ((i) << 5))))
 310 #define PUNB(i)       (*((uint32_t volatile*)(0x3cf0000c + ((i) << 5))))
 311 #define PCON0         (*((uint32_t volatile*)(0x3cf00000)))
 312 #define PDAT0         (*((uint32_t volatile*)(0x3cf00004)))
 313 #define PCON1         (*((uint32_t volatile*)(0x3cf00020)))
 314 #define PDAT1         (*((uint32_t volatile*)(0x3cf00024)))
 315 #define PCON2         (*((uint32_t volatile*)(0x3cf00040)))
 316 #define PDAT2         (*((uint32_t volatile*)(0x3cf00044)))
 317 #define PCON3         (*((uint32_t volatile*)(0x3cf00060)))
 318 #define PDAT3         (*((uint32_t volatile*)(0x3cf00064)))
 319 #define PCON4         (*((uint32_t volatile*)(0x3cf00080)))
 320 #define PDAT4         (*((uint32_t volatile*)(0x3cf00084)))
 321 #define PCON5         (*((uint32_t volatile*)(0x3cf000a0)))
 322 #define PDAT5         (*((uint32_t volatile*)(0x3cf000a4)))
 323 #define PCON6         (*((uint32_t volatile*)(0x3cf000c0)))
 324 #define PDAT6         (*((uint32_t volatile*)(0x3cf000c4)))
 325 #define PCON7         (*((uint32_t volatile*)(0x3cf000e0)))
 326 #define PDAT7         (*((uint32_t volatile*)(0x3cf000e4)))
 327 #define PCON8         (*((uint32_t volatile*)(0x3cf00100)))
 328 #define PDAT8         (*((uint32_t volatile*)(0x3cf00104)))
 329 #define PCON9         (*((uint32_t volatile*)(0x3cf00120)))
 330 #define PDAT9         (*((uint32_t volatile*)(0x3cf00124)))
 331 #define PCONA         (*((uint32_t volatile*)(0x3cf00140)))
 332 #define PDATA         (*((uint32_t volatile*)(0x3cf00144)))
 333 #define PCONB         (*((uint32_t volatile*)(0x3cf00160)))
 334 #define PDATB         (*((uint32_t volatile*)(0x3cf00164)))
 335 #define PCONC         (*((uint32_t volatile*)(0x3cf00180)))
 336 #define PDATC         (*((uint32_t volatile*)(0x3cf00184)))
 337 #define PCOND         (*((uint32_t volatile*)(0x3cf001a0)))
 338 #define PDATD         (*((uint32_t volatile*)(0x3cf001a4)))
 339 #define PCONE         (*((uint32_t volatile*)(0x3cf001c0)))
 340 #define PDATE         (*((uint32_t volatile*)(0x3cf001c4)))
 341 #define PCONF         (*((uint32_t volatile*)(0x3cf001e0)))
 342 #define PDATF         (*((uint32_t volatile*)(0x3cf001e4)))
 343 #define GPIOCMD       (*((uint32_t volatile*)(0x3cf00200)))
 344
 345
 346 /////SPI/////
 347 #define SPIBASE(i)      ((i) == 2 ? 0x3d200000 : \
 348                          (i) == 1 ? 0x3ce00000 : \
 349                                     0x3c300000)
 350 #define SPICLKGATE(i)   ((i) == 2 ? 0x2f : \
 351                          (i) == 1 ? 0x2b : \
 352                                     0x22)
 353 #define SPIDMA(i)       ((i) == 2 ? 0xd : \
 354                          (i) == 1 ? 0xf : \
 355                                     0x5)
 356 #define SPICTRL(i)    (*((uint32_t volatile*)(SPIBASE(i))))
 357 #define SPISETUP(i)   (*((uint32_t volatile*)(SPIBASE(i) + 0x4)))
 358 #define SPISTATUS(i)  (*((uint32_t volatile*)(SPIBASE(i) + 0x8)))
 359 #define SPIUNKREG1(i) (*((uint32_t volatile*)(SPIBASE(i) + 0xc)))
 360 #define SPITXDATA(i)  (*((uint32_t volatile*)(SPIBASE(i) + 0x10)))
 361 #define SPIRXDATA(i)  (*((uint32_t volatile*)(SPIBASE(i) + 0x20)))
 362 #define SPICLKDIV(i)  (*((uint32_t volatile*)(SPIBASE(i) + 0x30)))
 363 #define SPIRXLIMIT(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x34)))
 364 #define SPIUNKREG3(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x38)))
 365
 366
 367 /////AES/////
 368 #define AESCONTROL    (*((uint32_t volatile*)(0x38c00000)))
 369 #define AESGO         (*((uint32_t volatile*)(0x38c00004)))
 370 #define AESUNKREG0    (*((uint32_t volatile*)(0x38c00008)))
 371 #define AESSTATUS     (*((uint32_t volatile*)(0x38c0000c)))
 372 #define AESUNKREG1    (*((uint32_t volatile*)(0x38c00010)))
 373 #define AESKEYLEN     (*((uint32_t volatile*)(0x38c00014)))
 374 #define AESOUTSIZE    (*((uint32_t volatile*)(0x38c00018)))
 375 #define AESOUTADDR    (*((void* volatile*)(0x38c00020)))
 376 #define AESINSIZE     (*((uint32_t volatile*)(0x38c00024)))
 377 #define AESINADDR     (*((const void* volatile*)(0x38c00028)))
 378 #define AESAUXSIZE    (*((uint32_t volatile*)(0x38c0002c)))
 379 #define AESAUXADDR    (*((void* volatile*)(0x38c00030)))
 380 #define AESSIZE3      (*((uint32_t volatile*)(0x38c00034)))
 381 #define AESKEY          ((uint32_t volatile*)(0x38c0004c))
 382 #define AESTYPE       (*((uint32_t volatile*)(0x38c0006c)))
 383 #define AESIV           ((uint32_t volatile*)(0x38c00074))
 384 #define AESTYPE2      (*((uint32_t volatile*)(0x38c00088)))
 385 #define AESUNKREG2    (*((uint32_t volatile*)(0x38c0008c)))
 386
 387
 388 /////SHA1/////
 389 #define SHA1CONFIG    (*((uint32_t volatile*)(0x38000000)))
 390 #define SHA1RESET     (*((uint32_t volatile*)(0x38000004)))
 391 #define SHA1RESULT      ((uint32_t volatile*)(0x38000020))
 392 #define SHA1DATAIN      ((uint32_t volatile*)(0x38000040))
 393
 394
 395 /////DMA/////
 396 #ifndef ASM
 397 struct dma_lli
 398 {
 399     const void* srcaddr;
 400     void* dstaddr;
 401     const struct dma_lli* nextlli;
 402     uint32_t control;
 403 };
 404 #endif
 405 #define DMACINTSTS(d)       (*((uint32_t volatile*)(0x38200000 + 0x1700000 * (d))))
 406 #define DMACINTTCSTS(d)     (*((uint32_t volatile*)(0x38200004 + 0x1700000 * (d))))
 407 #define DMACINTTCCLR(d)     (*((uint32_t volatile*)(0x38200008 + 0x1700000 * (d))))
 408 #define DMACINTERRSTS(d)    (*((uint32_t volatile*)(0x3820000c + 0x1700000 * (d))))
 409 #define DMACINTERRCLR(d)    (*((uint32_t volatile*)(0x38200010 + 0x1700000 * (d))))
 410 #define DMACRAWINTTCSTS(d)  (*((uint32_t volatile*)(0x38200014 + 0x1700000 * (d))))
 411 #define DMACRAWINTERRSTS(d) (*((uint32_t volatile*)(0x38200018 + 0x1700000 * (d))))
 412 #define DMACENABLEDCHANS(d) (*((uint32_t volatile*)(0x3820001c + 0x1700000 * (d))))
 413 #define DMACSOFTBREQ(d)     (*((uint32_t volatile*)(0x38200020 + 0x1700000 * (d))))
 414 #define DMACSOFTSREQ(d)     (*((uint32_t volatile*)(0x38200024 + 0x1700000 * (d))))
 415 #define DMACSOFTLBREQ(d)    (*((uint32_t volatile*)(0x38200028 + 0x1700000 * (d))))
 416 #define DMACSOFTLSREQ(d)    (*((uint32_t volatile*)(0x3820002c + 0x1700000 * (d))))
 417 #define DMACCONFIG(d)       (*((uint32_t volatile*)(0x38200030 + 0x1700000 * (d))))
 418 #define DMACSYNC(d)         (*((uint32_t volatile*)(0x38200034 + 0x1700000 * (d))))
 419 #define DMACCLLI(d, c)      (*((struct dma_lli volatile*)(0x38200100 + 0x1700000 * (d) + 0x20 * (c))))
 420 #define DMACCSRCADDR(d, c)  (*((const void* volatile*)(0x38200100 + 0x1700000 * (d) + 0x20 * (c))))
 421 #define DMACCDESTADDR(d, c) (*((void* volatile*)(0x38200104 + 0x1700000 * (d) + 0x20 * (c))))
 422 #define DMACCNEXTLLI(d, c)  (*((const void* volatile*)(0x38200108 + 0x1700000 * (d) + 0x20 * (c))))
 423 #define DMACCCONTROL(d, c)  (*((uint32_t volatile*)(0x3820010c + 0x1700000 * (d) + 0x20 * (c))))
 424 #define DMACCCONFIG(d, c)   (*((uint32_t volatile*)(0x38200110 + 0x1700000 * (d) + 0x20 * (c))))
 425 #define DMAC0INTSTS         (*((uint32_t volatile*)(0x38200000)))
 426 #define DMAC0INTTCSTS       (*((uint32_t volatile*)(0x38200004)))
 427 #define DMAC0INTTCCLR       (*((uint32_t volatile*)(0x38200008)))
 428 #define DMAC0INTERRSTS      (*((uint32_t volatile*)(0x3820000c)))
 429 #define DMAC0INTERRCLR      (*((uint32_t volatile*)(0x38200010)))
 430 #define DMAC0RAWINTTCSTS    (*((uint32_t volatile*)(0x38200014)))
 431 #define DMAC0RAWINTERRSTS   (*((uint32_t volatile*)(0x38200018)))
 432 #define DMAC0ENABLEDCHANS   (*((uint32_t volatile*)(0x3820001c)))
 433 #define DMAC0SOFTBREQ       (*((uint32_t volatile*)(0x38200020)))
 434 #define DMAC0SOFTSREQ       (*((uint32_t volatile*)(0x38200024)))
 435 #define DMAC0SOFTLBREQ      (*((uint32_t volatile*)(0x38200028)))
 436 #define DMAC0SOFTLSREQ      (*((uint32_t volatile*)(0x3820002c)))
 437 #define DMAC0CONFIG         (*((uint32_t volatile*)(0x38200030)))
 438 #define DMAC0SYNC           (*((uint32_t volatile*)(0x38200034)))
 439 #define DMAC0CLLI(c)        (*((struct dma_lli volatile*)(0x38200100 + 0x20 * (c))))
 440 #define DMAC0CSRCADDR(c)    (*((const void* volatile*)(0x38200100 + 0x20 * (c))))
 441 #define DMAC0CDESTADDR(c)   (*((void* volatile*)(0x38200104 + 0x20 * (c))))
 442 #define DMAC0CNEXTLLI(c)    (*((const void* volatile*)(0x38200108 + 0x20 * (c))))
 443 #define DMAC0CCONTROL(c)    (*((uint32_t volatile*)(0x3820010c + 0x20 * (c))))
 444 #define DMAC0CCONFIG(c)     (*((uint32_t volatile*)(0x38200110 + 0x20 * (c))))
 445 #define DMAC0C0LLI          (*((struct dma_lli volatile*)(0x38200100)))
 446 #define DMAC0C0SRCADDR      (*((const void* volatile*)(0x38200100)))
 447 #define DMAC0C0DESTADDR     (*((void* volatile*)(0x38200104)))
 448 #define DMAC0C0NEXTLLI      (*((const struct dma_lli* volatile*)(0x38200108)))
 449 #define DMAC0C0CONTROL      (*((uint32_t volatile*)(0x3820010c)))
 450 #define DMAC0C0CONFIG       (*((uint32_t volatile*)(0x38200110)))
 451 #define DMAC0C1LLI          (*((struct dma_lli volatile*)(0x38200120)))
 452 #define DMAC0C1SRCADDR      (*((const void* volatile*)(0x38200120)))
 453 #define DMAC0C1DESTADDR     (*((void* volatile*)(0x38200124)))
 454 #define DMAC0C1NEXTLLI      (*((const struct dma_lli* volatile*)(0x38200128)))
 455 #define DMAC0C1CONTROL      (*((uint32_t volatile*)(0x3820012c)))
 456 #define DMAC0C1CONFIG       (*((uint32_t volatile*)(0x38200130)))
 457 #define DMAC0C2LLI          (*((struct dma_lli volatile*)(0x38200140)))
 458 #define DMAC0C2SRCADDR      (*((const void* volatile*)(0x38200140)))
 459 #define DMAC0C2DESTADDR     (*((void* volatile*)(0x38200144)))
 460 #define DMAC0C2NEXTLLI      (*((const struct dma_lli* volatile*)(0x38200148)))
 461 #define DMAC0C2CONTROL      (*((uint32_t volatile*)(0x3820014c)))
 462 #define DMAC0C2CONFIG       (*((uint32_t volatile*)(0x38200150)))
 463 #define DMAC0C3LLI          (*((struct dma_lli volatile*)(0x38200160)))
 464 #define DMAC0C3SRCADDR      (*((const void* volatile*)(0x38200160)))
 465 #define DMAC0C3DESTADDR     (*((void* volatile*)(0x38200164)))
 466 #define DMAC0C3NEXTLLI      (*((const struct dma_lli* volatile*)(0x38200168)))
 467 #define DMAC0C3CONTROL      (*((uint32_t volatile*)(0x3820016c)))
 468 #define DMAC0C3CONFIG       (*((uint32_t volatile*)(0x38200170)))
 469 #define DMAC0C4LLI          (*((struct dma_lli volatile*)(0x38200180)))
 470 #define DMAC0C4SRCADDR      (*((const void* volatile*)(0x38200180)))
 471 #define DMAC0C4DESTADDR     (*((void* volatile*)(0x38200184)))
 472 #define DMAC0C4NEXTLLI      (*((const struct dma_lli* volatile*)(0x38200188)))
 473 #define DMAC0C4CONTROL      (*((uint32_t volatile*)(0x3820018c)))
 474 #define DMAC0C4CONFIG       (*((uint32_t volatile*)(0x38200190)))
 475 #define DMAC0C5LLI          (*((struct dma_lli volatile*)(0x382001a0)))
 476 #define DMAC0C5SRCADDR      (*((const void* volatile*)(0x382001a0)))
 477 #define DMAC0C5DESTADDR     (*((void* volatile*)(0x382001a4)))
 478 #define DMAC0C5NEXTLLI      (*((const struct dma_lli* volatile*)(0x382001a8)))
 479 #define DMAC0C5CONTROL      (*((uint32_t volatile*)(0x382001ac)))
 480 #define DMAC0C5CONFIG       (*((uint32_t volatile*)(0x382001b0)))
 481 #define DMAC0C6LLI          (*((struct dma_lli volatile*)(0x382001c0)))
 482 #define DMAC0C6SRCADDR      (*((const void* volatile*)(0x382001c0)))
 483 #define DMAC0C6DESTADDR     (*((void* volatile*)(0x382001c4)))
 484 #define DMAC0C6NEXTLLI      (*((const struct dma_lli* volatile*)(0x382001c8)))
 485 #define DMAC0C6CONTROL      (*((uint32_t volatile*)(0x382001cc)))
 486 #define DMAC0C6CONFIG       (*((uint32_t volatile*)(0x382001d0)))
 487 #define DMAC0C7LLI          (*((struct dma_lli volatile*)(0x382001e0)))
 488 #define DMAC0C7SRCADDR      (*((const void* volatile*)(0x382001e0)))
 489 #define DMAC0C7DESTADDR     (*((void* volatile*)(0x382001e4)))
 490 #define DMAC0C7NEXTLLI      (*((const struct dma_lli* volatile*)(0x382001e8)))
 491 #define DMAC0C7CONTROL      (*((uint32_t volatile*)(0x382001ec)))
 492 #define DMAC0C7CONFIG       (*((uint32_t volatile*)(0x382001f0)))
 493 #define DMAC1INTSTS         (*((uint32_t volatile*)(0x39900000)))
 494 #define DMAC1INTTCSTS       (*((uint32_t volatile*)(0x39900004)))
 495 #define DMAC1INTTCCLR       (*((uint32_t volatile*)(0x39900008)))
 496 #define DMAC1INTERRSTS      (*((uint32_t volatile*)(0x3990000c)))
 497 #define DMAC1INTERRCLR      (*((uint32_t volatile*)(0x39900010)))
 498 #define DMAC1RAWINTTCSTS    (*((uint32_t volatile*)(0x39900014)))
 499 #define DMAC1RAWINTERRSTS   (*((uint32_t volatile*)(0x39900018)))
 500 #define DMAC1ENABLEDCHANS   (*((uint32_t volatile*)(0x3990001c)))
 501 #define DMAC1SOFTBREQ       (*((uint32_t volatile*)(0x39900020)))
 502 #define DMAC1SOFTSREQ       (*((uint32_t volatile*)(0x39900024)))
 503 #define DMAC1SOFTLBREQ      (*((uint32_t volatile*)(0x39900028)))
 504 #define DMAC1SOFTLSREQ      (*((uint32_t volatile*)(0x3990002c)))
 505 #define DMAC1CONFIG         (*((uint32_t volatile*)(0x39900030)))
 506 #define DMAC1SYNC           (*((uint32_t volatile*)(0x39900034)))
 507 #define DMAC1CLLI(c)        (*((struct dma_lli volatile*)(0x39900100 + 0x20 * (c))))
 508 #define DMAC1CSRCADDR(c)    (*((const void* volatile*)(0x39900100 + 0x20 * (c))))
 509 #define DMAC1CDESTADDR(c)   (*((void* volatile*)(0x39900104 + 0x20 * (c))))
 510 #define DMAC1CNEXTLLI(c)    (*((const void* volatile*)(0x39900108 + 0x20 * (c))))
 511 #define DMAC1CCONTROL(c)    (*((uint32_t volatile*)(0x3990010c + 0x20 * (c))))
 512 #define DMAC1CCONFIG(c)     (*((uint32_t volatile*)(0x39900110 + 0x20 * (c))))
 513 #define DMAC1C0LLI          (*((struct dma_lli volatile*)(0x39900100)))
 514 #define DMAC1C0SRCADDR      (*((const void* volatile*)(0x39900100)))
 515 #define DMAC1C0DESTADDR     (*((void* volatile*)(0x39900104)))
 516 #define DMAC1C0NEXTLLI      (*((const struct dma_lli* volatile*)(0x39900108)))
 517 #define DMAC1C0CONTROL      (*((uint32_t volatile*)(0x3990010c)))
 518 #define DMAC1C0CONFIG       (*((uint32_t volatile*)(0x39900110)))
 519 #define DMAC1C1LLI          (*((struct dma_lli volatile*)(0x39900120)))
 520 #define DMAC1C1SRCADDR      (*((const void* volatile*)(0x39900120)))
 521 #define DMAC1C1DESTADDR     (*((void* volatile*)(0x39900124)))
 522 #define DMAC1C1NEXTLLI      (*((const struct dma_lli* volatile*)(0x39900128)))
 523 #define DMAC1C1CONTROL      (*((uint32_t volatile*)(0x3990012c)))
 524 #define DMAC1C1CONFIG       (*((uint32_t volatile*)(0x39900130)))
 525 #define DMAC1C2LLI          (*((struct dma_lli volatile*)(0x39900140)))
 526 #define DMAC1C2SRCADDR      (*((const void* volatile*)(0x39900140)))
 527 #define DMAC1C2DESTADDR     (*((void* volatile*)(0x39900144)))
 528 #define DMAC1C2NEXTLLI      (*((const struct dma_lli* volatile*)(0x39900148)))
 529 #define DMAC1C2CONTROL      (*((uint32_t volatile*)(0x3990014c)))
 530 #define DMAC1C2CONFIG       (*((uint32_t volatile*)(0x39900150)))
 531 #define DMAC1C3LLI          (*((struct dma_lli volatile*)(0x39900160)))
 532 #define DMAC1C3SRCADDR      (*((const void* volatile*)(0x39900160)))
 533 #define DMAC1C3DESTADDR     (*((void* volatile*)(0x39900164)))
 534 #define DMAC1C3NEXTLLI      (*((volatile void**)(0x39900168)))
 535 #define DMAC1C3CONTROL      (*((uint32_t volatile*)(0x3990016c)))
 536 #define DMAC1C3CONFIG       (*((uint32_t volatile*)(0x39900170)))
 537 #define DMAC1C4LLI          (*((struct dma_lli volatile*)(0x39900180)))
 538 #define DMAC1C4SRCADDR      (*((const void* volatile*)(0x39900180)))
 539 #define DMAC1C4DESTADDR     (*((void* volatile*)(0x39900184)))
 540 #define DMAC1C4NEXTLLI      (*((const struct dma_lli* volatile*)(0x39900188)))
 541 #define DMAC1C4CONTROL      (*((uint32_t volatile*)(0x3990018c)))
 542 #define DMAC1C4CONFIG       (*((uint32_t volatile*)(0x39900190)))
 543 #define DMAC1C5LLI          (*((struct dma_lli volatile*)(0x399001a0)))
 544 #define DMAC1C5SRCADDR      (*((const void* volatile*)(0x399001a0)))
 545 #define DMAC1C5DESTADDR     (*((void* volatile*)(0x399001a4)))
 546 #define DMAC1C5NEXTLLI      (*((const struct dma_lli* volatile*)(0x399001a8)))
 547 #define DMAC1C5CONTROL      (*((uint32_t volatile*)(0x399001ac)))
 548 #define DMAC1C5CONFIG       (*((uint32_t volatile*)(0x399001b0)))
 549 #define DMAC1C6LLI          (*((struct dma_lli volatile*)(0x399001c0)))
 550 #define DMAC1C6SRCADDR      (*((const void* volatile*)(0x399001c0)))
 551 #define DMAC1C6DESTADDR     (*((void* volatile*)(0x399001c4)))
 552 #define DMAC1C6NEXTLLI      (*((const struct dma_lli* volatile*)(0x399001c8)))
 553 #define DMAC1C6CONTROL      (*((uint32_t volatile*)(0x399001cc)))
 554 #define DMAC1C6CONFIG       (*((uint32_t volatile*)(0x399001d0)))
 555 #define DMAC1C7LLI          (*((struct dma_lli volatile*)(0x399001e0)))
 556 #define DMAC1C7SRCADDR      (*((const void* volatile*)(0x399001e0)))
 557 #define DMAC1C7DESTADDR     (*((void* volatile*)(0x399001e4)))
 558 #define DMAC1C7NEXTLLI      (*((const struct dma_lli* volatile*)(0x399001e8)))
 559 #define DMAC1C7CONTROL      (*((uint32_t volatile*)(0x399001ec)))
 560 #define DMAC1C7CONFIG       (*((uint32_t volatile*)(0x399001f0)))
 561
 562
 563 /////LCD/////
 564 #define LCD_BASE   (0x38300000)
 565 #define LCD_WCMD   (*((uint32_t volatile*)(0x38300004)))
 566 #define LCD_STATUS (*((uint32_t volatile*)(0x3830001c)))
 567 #define LCD_WDATA  (*((uint32_t volatile*)(0x38300040)))
 568
 569
 570 /////ATA/////
 571 #define ATA_CONTROL         (*((uint32_t volatile*)(0x38700000)))
 572 #define ATA_STATUS          (*((uint32_t volatile*)(0x38700004)))
 573 #define ATA_COMMAND         (*((uint32_t volatile*)(0x38700008)))
 574 #define ATA_SWRST           (*((uint32_t volatile*)(0x3870000c)))
 575 #define ATA_IRQ             (*((uint32_t volatile*)(0x38700010)))
 576 #define ATA_IRQ_MASK        (*((uint32_t volatile*)(0x38700014)))
 577 #define ATA_CFG             (*((uint32_t volatile*)(0x38700018)))
 578 #define ATA_MDMA_TIME       (*((uint32_t volatile*)(0x38700028)))
 579 #define ATA_PIO_TIME        (*((uint32_t volatile*)(0x3870002c)))
 580 #define ATA_UDMA_TIME       (*((uint32_t volatile*)(0x38700030)))
 581 #define ATA_XFR_NUM         (*((uint32_t volatile*)(0x38700034)))
 582 #define ATA_XFR_CNT         (*((uint32_t volatile*)(0x38700038)))
 583 #define ATA_TBUF_START      (*((void* volatile*)(0x3870003c)))
 584 #define ATA_TBUF_SIZE       (*((uint32_t volatile*)(0x38700040)))
 585 #define ATA_SBUF_START      (*((void* volatile*)(0x38700044)))
 586 #define ATA_SBUF_SIZE       (*((uint32_t volatile*)(0x38700048)))
 587 #define ATA_CADR_TBUF       (*((void* volatile*)(0x3870004c)))
 588 #define ATA_CADR_SBUF       (*((void* volatile*)(0x38700050)))
 589 #define ATA_PIO_DTR         (*((uint32_t volatile*)(0x38700054)))
 590 #define ATA_PIO_FED         (*((uint32_t volatile*)(0x38700058)))
 591 #define ATA_PIO_SCR         (*((uint32_t volatile*)(0x3870005c)))
 592 #define ATA_PIO_LLR         (*((uint32_t volatile*)(0x38700060)))
 593 #define ATA_PIO_LMR         (*((uint32_t volatile*)(0x38700064)))
 594 #define ATA_PIO_LHR         (*((uint32_t volatile*)(0x38700068)))
 595 #define ATA_PIO_DVR         (*((uint32_t volatile*)(0x3870006c)))
 596 #define ATA_PIO_CSD         (*((uint32_t volatile*)(0x38700070)))
 597 #define ATA_PIO_DAD         (*((uint32_t volatile*)(0x38700074)))
 598 #define ATA_PIO_READY       (*((uint32_t volatile*)(0x38700078)))
 599 #define ATA_PIO_RDATA       (*((uint32_t volatile*)(0x3870007c)))
 600 #define ATA_BUS_FIFO_STATUS (*((uint32_t volatile*)(0x38700080)))
 601 #define ATA_FIFO_STATUS     (*((uint32_t volatile*)(0x38700084)))
 602 #define ATA_DMA_ADDR        (*((void* volatile*)(0x38700088)))
 603
 604
 605 /////SDCI/////
 606 #define SDCI_CTRL     (*((uint32_t volatile*)(0x38b00000)))
 607 #define SDCI_DCTRL    (*((uint32_t volatile*)(0x38b00004)))
 608 #define SDCI_CMD      (*((uint32_t volatile*)(0x38b00008)))
 609 #define SDCI_ARGU     (*((uint32_t volatile*)(0x38b0000c)))
 610 #define SDCI_STATE    (*((uint32_t volatile*)(0x38b00010)))
 611 #define SDCI_STAC     (*((uint32_t volatile*)(0x38b00014)))
 612 #define SDCI_DSTA     (*((uint32_t volatile*)(0x38b00018)))
 613 #define SDCI_FSTA     (*((uint32_t volatile*)(0x38b0001c)))
 614 #define SDCI_RESP0    (*((uint32_t volatile*)(0x38b00020)))
 615 #define SDCI_RESP1    (*((uint32_t volatile*)(0x38b00024)))
 616 #define SDCI_RESP2    (*((uint32_t volatile*)(0x38b00028)))
 617 #define SDCI_RESP3    (*((uint32_t volatile*)(0x38b0002c)))
 618 #define SDCI_CDIV     (*((uint32_t volatile*)(0x38b00030)))
 619 #define SDCI_SDIO_CSR (*((uint32_t volatile*)(0x38b00034)))
 620 #define SDCI_IRQ      (*((uint32_t volatile*)(0x38b00038)))
 621 #define SDCI_IRQ_MASK (*((uint32_t volatile*)(0x38b0003c)))
 622 #define SDCI_DATA     (*((uint32_t volatile*)(0x38b00040)))
 623 #define SDCI_DMAADDR  (*((void* volatile*)(0x38b00044)))
 624 #define SDCI_DMASIZE  (*((uint32_t volatile*)(0x38b00048)))
 625 #define SDCI_DMACOUNT (*((uint32_t volatile*)(0x38b0004c)))
 626 #define SDCI_RESET    (*((uint32_t volatile*)(0x38b0006c)))
 627
 628 #define SDCI_CTRL_SDCIEN BIT(0)
 629 #define SDCI_CTRL_CARD_TYPE_MASK BIT(1)
 630 #define SDCI_CTRL_CARD_TYPE_SD 0
 631 #define SDCI_CTRL_CARD_TYPE_MMC BIT(1)
 632 #define SDCI_CTRL_BUS_WIDTH_MASK BITRANGE(2, 3)
 633 #define SDCI_CTRL_BUS_WIDTH_1BIT 0
 634 #define SDCI_CTRL_BUS_WIDTH_4BIT BIT(2)
 635 #define SDCI_CTRL_BUS_WIDTH_8BIT BIT(3)
 636 #define SDCI_CTRL_DMA_EN BIT(4)
 637 #define SDCI_CTRL_L_ENDIAN BIT(5)
 638 #define SDCI_CTRL_DMA_REQ_CON_MASK BIT(6)
 639 #define SDCI_CTRL_DMA_REQ_CON_NEMPTY 0
 640 #define SDCI_CTRL_DMA_REQ_CON_FULL BIT(6)
 641 #define SDCI_CTRL_CLK_SEL_MASK BIT(7)
 642 #define SDCI_CTRL_CLK_SEL_PCLK 0
 643 #define SDCI_CTRL_CLK_SEL_SDCLK BIT(7)
 644 #define SDCI_CTRL_BIT_8 BIT(8)
 645 #define SDCI_CTRL_BIT_14 BIT(14)
 646
 647 #define SDCI_DCTRL_TXFIFORST BIT(0)
 648 #define SDCI_DCTRL_RXFIFORST BIT(1)
 649 #define SDCI_DCTRL_TRCONT_MASK BITRANGE(4, 5)
 650 #define SDCI_DCTRL_TRCONT_TX BIT(4)
 651 #define SDCI_DCTRL_BUS_TEST_MASK BITRANGE(6, 7)
 652 #define SDCI_DCTRL_BUS_TEST_TX BIT(6)
 653 #define SDCI_DCTRL_BUS_TEST_RX BIT(7)
 654
 655 #define SDCI_CDIV_CLKDIV_MASK BITRANGE(0, 7)
 656 #define SDCI_CDIV_CLKDIV(x) ((x) >> 1)
 657 #define SDCI_CDIV_CLKDIV_2 BIT(0)
 658 #define SDCI_CDIV_CLKDIV_4 BIT(1)
 659 #define SDCI_CDIV_CLKDIV_8 BIT(2)
 660 #define SDCI_CDIV_CLKDIV_16 BIT(3)
 661 #define SDCI_CDIV_CLKDIV_32 BIT(4)
 662 #define SDCI_CDIV_CLKDIV_64 BIT(5)
 663 #define SDCI_CDIV_CLKDIV_128 BIT(6)
 664 #define SDCI_CDIV_CLKDIV_256 BIT(7)
 665
 666 #define SDCI_CMD_CMD_NUM_MASK BITRANGE(0, 5)
 667 #define SDCI_CMD_CMD_NUM_SHIFT 0
 668 #define SDCI_CMD_CMD_NUM(x) (x)
 669 #define SDCI_CMD_CMD_TYPE_MASK BITRANGE(6, 7)
 670 #define SDCI_CMD_CMD_TYPE_BC 0
 671 #define SDCI_CMD_CMD_TYPE_BCR BIT(6)
 672 #define SDCI_CMD_CMD_TYPE_AC BIT(7)
 673 #define SDCI_CMD_CMD_TYPE_ADTC (BIT(6) | BIT(7))
 674 #define SDCI_CMD_CMD_RD_WR BIT(8)
 675 #define SDCI_CMD_RES_TYPE_MASK BITRANGE(16, 18)
 676 #define SDCI_CMD_RES_TYPE_NONE 0
 677 #define SDCI_CMD_RES_TYPE_R1 BIT(16)
 678 #define SDCI_CMD_RES_TYPE_R2 BIT(17)
 679 #define SDCI_CMD_RES_TYPE_R3 (BIT(16) | BIT(17))
 680 #define SDCI_CMD_RES_TYPE_R4 BIT(18)
 681 #define SDCI_CMD_RES_TYPE_R5 (BIT(16) | BIT(18))
 682 #define SDCI_CMD_RES_TYPE_R6 (BIT(17) | BIT(18))
 683 #define SDCI_CMD_RES_BUSY BIT(19)
 684 #define SDCI_CMD_RES_SIZE_MASK BIT(20)
 685 #define SDCI_CMD_RES_SIZE_48 0
 686 #define SDCI_CMD_RES_SIZE_136 BIT(20)
 687 #define SDCI_CMD_NCR_NID_MASK BIT(21)
 688 #define SDCI_CMD_NCR_NID_NCR 0
 689 #define SDCI_CMD_NCR_NID_NID BIT(21)
 690 #define SDCI_CMD_CMDSTR BIT(31)
 691
 692 #define SDCI_STATE_DAT_STATE_MASK BITRANGE(0, 3)
 693 #define SDCI_STATE_DAT_STATE_IDLE 0
 694 #define SDCI_STATE_DAT_STATE_DAT_RCV BIT(0)
 695 #define SDCI_STATE_DAT_STATE_CRC_RCV BIT(1)
 696 #define SDCI_STATE_DAT_STATE_DAT_END (BIT(0) | BIT(1))
 697 #define SDCI_STATE_DAT_STATE_DAT_SET BIT(2)
 698 #define SDCI_STATE_DAT_STATE_DAT_OUT (BIT(0) | BIT(2))
 699 #define SDCI_STATE_DAT_STATE_CRC_TIME (BIT(1) | BIT(2))
 700 #define SDCI_STATE_DAT_STATE_CRC_OUT (BIT(0) | BIT(1) | BIT(2))
 701 #define SDCI_STATE_DAT_STATE_ENDB_OUT BIT(3)
 702 #define SDCI_STATE_DAT_STATE_ENDB_STOD (BIT(0) | BIT(3))
 703 #define SDCI_STATE_DAT_STATE_DAT_CRCR (BIT(1) | BIT(3))
 704 #define SDCI_STATE_DAT_STATE_CARD_PRG (BIT(0) | BIT(1) | BIT(3))
 705 #define SDCI_STATE_DAT_STATE_DAT_BUSY (BIT(2) | BIT(3))
 706 #define SDCI_STATE_CMD_STATE_MASK (BIT(4) | BIT(5) | BIT(6))
 707 #define SDCI_STATE_CMD_STATE_CMD_IDLE 0
 708 #define SDCI_STATE_CMD_STATE_CMD_CMDO BIT(4)
 709 #define SDCI_STATE_CMD_STATE_CMD_CRCO BIT(5)
 710 #define SDCI_STATE_CMD_STATE_CMD_TOUT (BIT(4) | BIT(5))
 711 #define SDCI_STATE_CMD_STATE_CMD_RESR BIT(6)
 712 #define SDCI_STATE_CMD_STATE_CMD_INTV (BIT(4) | BIT(6))
 713
 714 #define SDCI_STAC_CLR_CMDEND BIT(2)
 715 #define SDCI_STAC_CLR_BIT_3 BIT(3)
 716 #define SDCI_STAC_CLR_RESEND BIT(4)
 717 #define SDCI_STAC_CLR_DATEND BIT(6)
 718 #define SDCI_STAC_CLR_DAT_CRCEND BIT(7)
 719 #define SDCI_STAC_CLR_CRC_STAEND BIT(8)
 720 #define SDCI_STAC_CLR_RESTOUTE BIT(15)
 721 #define SDCI_STAC_CLR_RESENDE BIT(16)
 722 #define SDCI_STAC_CLR_RESINDE BIT(17)
 723 #define SDCI_STAC_CLR_RESCRCE BIT(18)
 724 #define SDCI_STAC_CLR_WR_DATCRCE BIT(22)
 725 #define SDCI_STAC_CLR_RD_DATCRCE BIT(23)
 726 #define SDCI_STAC_CLR_RD_DATENDE0 BIT(24)
 727 #define SDCI_STAC_CLR_RD_DATENDE1 BIT(25)
 728 #define SDCI_STAC_CLR_RD_DATENDE2 BIT(26)
 729 #define SDCI_STAC_CLR_RD_DATENDE3 BIT(27)
 730 #define SDCI_STAC_CLR_RD_DATENDE4 BIT(28)
 731 #define SDCI_STAC_CLR_RD_DATENDE5 BIT(29)
 732 #define SDCI_STAC_CLR_RD_DATENDE6 BIT(30)
 733 #define SDCI_STAC_CLR_RD_DATENDE7 BIT(31)
 734
 735 #define SDCI_DSTA_CMDRDY BIT(0)
 736 #define SDCI_DSTA_CMDPRO BIT(1)
 737 #define SDCI_DSTA_CMDEND BIT(2)
 738 #define SDCI_DSTA_RESPRO BIT(3)
 739 #define SDCI_DSTA_RESEND BIT(4)
 740 #define SDCI_DSTA_DATPRO BIT(5)
 741 #define SDCI_DSTA_DATEND BIT(6)
 742 #define SDCI_DSTA_DAT_CRCEND BIT(7)
 743 #define SDCI_DSTA_CRC_STAEND BIT(8)
 744 #define SDCI_DSTA_DAT_BUSY BIT(9)
 745 #define SDCI_DSTA_SDCLK_HOLD BIT(12)
 746 #define SDCI_DSTA_DAT0_STATUS BIT(13)
 747 #define SDCI_DSTA_WP_DECT_INPUT BIT(14)
 748 #define SDCI_DSTA_RESTOUTE BIT(15)
 749 #define SDCI_DSTA_RESENDE BIT(16)
 750 #define SDCI_DSTA_RESINDE BIT(17)
 751 #define SDCI_DSTA_RESCRCE BIT(18)
 752 #define SDCI_DSTA_WR_CRC_STATUS_MASK BITRANGE(19, 21)
 753 #define SDCI_DSTA_WR_CRC_STATUS_OK BIT(20)
 754 #define SDCI_DSTA_WR_CRC_STATUS_TXERR (BIT(19) | BIT(21))
 755 #define SDCI_DSTA_WR_CRC_STATUS_CARDERR (BIT(19) | BIT(20) | BIT(21))
 756 #define SDCI_DSTA_WR_DATCRCE BIT(22)
 757 #define SDCI_DSTA_RD_DATCRCE BIT(23)
 758 #define SDCI_DSTA_RD_DATENDE0 BIT(24)
 759 #define SDCI_DSTA_RD_DATENDE1 BIT(25)
 760 #define SDCI_DSTA_RD_DATENDE2 BIT(26)
 761 #define SDCI_DSTA_RD_DATENDE3 BIT(27)
 762 #define SDCI_DSTA_RD_DATENDE4 BIT(28)
 763 #define SDCI_DSTA_RD_DATENDE5 BIT(29)
 764 #define SDCI_DSTA_RD_DATENDE6 BIT(30)
 765 #define SDCI_DSTA_RD_DATENDE7 BIT(31)
 766
 767 #define SDCI_FSTA_RX_FIFO_EMPTY BIT(0)
 768 #define SDCI_FSTA_RX_FIFO_FULL BIT(1)
 769 #define SDCI_FSTA_TX_FIFO_EMPTY BIT(2)
 770 #define SDCI_FSTA_TX_FIFO_FULL BIT(3)
 771
 772 #define SDCI_SDIO_CSR_SDIO_RW_EN BIT(0)
 773 #define SDCI_SDIO_CSR_SDIO_INT_EN BIT(1)
 774 #define SDCI_SDIO_CSR_SDIO_RW_REQ BIT(2)
 775 #define SDCI_SDIO_CSR_SDIO_RW_STOP BIT(3)
 776 #define SDCI_SDIO_CSR_SDIO_INT_PERIOD_MASK BIT(4)
 777 #define SDCI_SDIO_CSR_SDIO_INT_PERIOD_MORE 0
 778 #define SDCI_SDIO_CSR_SDIO_INT_PERIOD_XACT BIT(4)
 779
 780 #define SDCI_IRQ_DAT_DONE_INT BIT(0)
 781 #define SDCI_IRQ_IOCARD_IRQ_INT BIT(1)
 782 #define SDCI_IRQ_READ_WAIT_INT BIT(2)
 783
 784 #define SDCI_IRQ_MASK_MASK_DAT_DONE_INT BIT(0)
 785 #define SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT BIT(1)
 786 #define SDCI_IRQ_MASK_MASK_READ_WAIT_INT BIT(2)
 787
 788
 789 /////CLICKWHEEL/////
 790 #define WHEEL00      (*((uint32_t volatile*)(0x3C200000)))
 791 #define WHEEL04      (*((uint32_t volatile*)(0x3C200004)))
 792 #define WHEEL08      (*((uint32_t volatile*)(0x3C200008)))
 793 #define WHEEL0C      (*((uint32_t volatile*)(0x3C20000C)))
 794 #define WHEEL10      (*((uint32_t volatile*)(0x3C200010)))
 795 #define WHEELINT     (*((uint32_t volatile*)(0x3C200014)))
 796 #define WHEELRX      (*((uint32_t volatile*)(0x3C200018)))
 797 #define WHEELTX      (*((uint32_t volatile*)(0x3C20001C)))
 798
 799
 800 /////I2S/////
 801 #define I2SCLKCON           (*((volatile uint32_t*)(0x3CA00000)))
 802 #define I2STXCON            (*((volatile uint32_t*)(0x3CA00004)))
 803 #define I2STXCOM            (*((volatile uint32_t*)(0x3CA00008)))
 804 #define I2STXDB0            (*((volatile uint32_t*)(0x3CA00010)))
 805 #define I2SRXCON            (*((volatile uint32_t*)(0x3CA00030)))
 806 #define I2SRXCOM            (*((volatile uint32_t*)(0x3CA00034)))
 807 #define I2SRXDB             (*((volatile uint32_t*)(0x3CA00038)))
 808 #define I2SSTATUS           (*((volatile uint32_t*)(0x3CA0003C)))
 809 #define I2S40               (*((volatile uint32_t*)(0x3CA00040)))
 810
 811
 812 /////CLOCK GATES/////
 813 #define CLOCKGATE_USB_1 2
 814 #define CLOCKGATE_USB_2 35
 815
 816
 817 /////INTERRUPTS/////
 818 #define IRQ_TIMER 8
 819 #define IRQ_USB_FUNC 19
 820 #define IRQ_DMAC(d) 16 + d
 821 #define IRQ_DMAC0 16
 822 #define IRQ_DMAC1 17
 823 #define IRQ_WHEEL 23
 824 #define IRQ_ATA 29
 825 #define IRQ_MMC 44
 826
 827
 828 #endif
 829