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update madwifi
[linux-2.6/zen-sources.git] / drivers / net / wireless / madwifi / ath / if_ath_hal_extensions.h
blobb9ee1375ad301e90893e3e8c5f90d4f18e0a5e12
1 /*-
2 * Copyright (c) 2007 Michael Taylor
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 * 3. Neither the names of the above-listed copyright holders nor the names
16 * of any contributors may be used to endorse or promote products derived
17 * from this software without specific prior written permission.
18 *
19 * Alternatively, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") version 2 as published by the Free
21 * Software Foundation.
22 *
23 * NO WARRANTY
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGES.
35 *
36 * $Id: foo mtaylor $
37 */
38
39 /* This file provides some wrapper functions that invoke functions in
40 * if_ath_hal.h. Since all the functions in the generated file, if_ath_hal.h
41 * have locks to protect them... no further locking is required in these
42 * additional helper functions. Mostly these just provide a series of nicknames
43 * for specific sets of arguments to HAL functions that are commonly needed. */
44
45 #ifndef _IF_ATH_HAL_EXTENSIONS_H_
46 #define _IF_ATH_HAL_EXTENSIONS_H_
47
48 #include <linux/types.h>
49
50 #define AR5K_PHY_AGCSIZE 0x9850
51 #define AR5K_PHY_AGCSIZE_DESIRED 0x0ff00000
52 #define AR5K_PHY_AGCSIZE_DESIRED_S 20
53
54 #define AR5K_PHY_SIG 0x9858
55 #define AR5K_PHY_SIG_FIRSTEP 0x0003f000
56 #define AR5K_PHY_SIG_FIRSTEP_S 12
57 #define AR5K_PHY_SIG_FIRPWR 0x03fc0000
58 #define AR5K_PHY_SIG_FIRPWR_S 18
59
60 #define AR5K_PHY_AGCCOARSE 0x985c
61 #define AR5K_PHY_AGCCOARSE_LO 0x00007f80
62 #define AR5K_PHY_AGCCOARSE_LO_S 7
63 #define AR5K_PHY_AGCCOARSE_HI 0x003f8000
64 #define AR5K_PHY_AGCCOARSE_HI_S 15
65
66 #define AR5K_PHY_WEAK_OFDM_HIGH 0x9868
67 #define AR5K_PHY_WEAK_OFDM_HIGH_M1 0x00fe0000
68 #define AR5K_PHY_WEAK_OFDM_HIGH_M1_S 17
69 #define AR5K_PHY_WEAK_OFDM_HIGH_M2 0x7f000000
70 #define AR5K_PHY_WEAK_OFDM_HIGH_M2_S 24
71 #define AR5K_PHY_WEAK_OFDM_HIGH_M2_COUNT 0x0000001f
72 #define AR5K_PHY_WEAK_OFDM_HIGH_M2_COUNT_S 0
73
74 #define AR5K_PHY_WEAK_OFDM_HIGH_M1_OFF 127
75 #define AR5K_PHY_WEAK_OFDM_HIGH_M1_ON 77
76
77 #define AR5K_PHY_WEAK_OFDM_HIGH_M2_OFF 127
78 #define AR5K_PHY_WEAK_OFDM_HIGH_M2_ON 64
79
80 #define AR5K_PHY_WEAK_OFDM_HIGH_M2_COUNT_OFF 31
81 #define AR5K_PHY_WEAK_OFDM_HIGH_M2_COUNT_ON 16
82
83 /* NB: comparing defaults for these registers vs. patent, it appears this
84 * is baseband processor stuff from table 2. */
85 #define AR5K_PHY_WEAK_OFDM_LOW 0x986c
86 #define AR5K_PHY_WEAK_OFDM_LOW_M1 0x001fc000
87 #define AR5K_PHY_WEAK_OFDM_LOW_M1_S 14
88 #define AR5K_PHY_WEAK_OFDM_LOW_M2 0x0fe00000
89 #define AR5K_PHY_WEAK_OFDM_LOW_M2_S 21
90 #define AR5K_PHY_WEAK_OFDM_LOW_M2_COUNT 0x00003f00
91 #define AR5K_PHY_WEAK_OFDM_LOW_M2_COUNT_S 8
92 #define AR5K_PHY_WEAK_OFDM_LOW_SELFCOR 0x00000001
93 #define AR5K_PHY_WEAK_OFDM_LOW_SELFCOR_S 0
94
95 #define AR5K_PHY_WEAK_OFDM_LOW_M1_OFF 127
96 #define AR5K_PHY_WEAK_OFDM_LOW_M1_ON 50
97
98 #define AR5K_PHY_WEAK_OFDM_LOW_M2_OFF 127
99 #define AR5K_PHY_WEAK_OFDM_LOW_M2_ON 40
100
101 #define AR5K_PHY_WEAK_OFDM_LOW_M2_COUNT_OFF 63
102 #define AR5K_PHY_WEAK_OFDM_LOW_M2_COUNT_ON 48
103
104 #define AR5K_PHY_WEAK_OFDM_LOW_SELFCOR_OFF 0
105 #define AR5K_PHY_WEAK_OFDM_LOW_SELFCOR_ON 1
106
107 #define AR5K_PHY_SPUR 0x9924
108 #define AR5K_PHY_SPUR_THRESH 0x000000fe
109 #define AR5K_PHY_SPUR_THRESH_S 1
110
111 #define AR5K_PHY_WEAK_CCK 0xa208
112 #define AR5K_PHY_WEAK_CCK_THRESH 0x0000000f
113 #define AR5K_PHY_WEAK_CCK_THRESH_S 0
114
115 #define AR5K_PHY_WEAK_CCK_THRESH_ON 6
116 #define AR5K_PHY_WEAK_CCK_THRESH_OFF 8
117
118 #define DEFAULT_AR5K_PHY_AGCSIZE_DESIRED -34
119 #define DEFAULT_AR5K_PHY_AGCCOARSE_HI -18
120 #define DEFAULT_AR5K_PHY_AGCCOARSE_LO -52
121 #define DEFAULT_AR5K_PHY_SIG_FIRPWR -70
122
123 /* NB: I can never make up my mind which is right. */
124 #define DEFAULT_ENABLE_AR5K_PHY_WEAK_OFDM_11BG 1
125 #define DEFAULT_ENABLE_AR5K_PHY_WEAK_OFDM_11A 1
126
127 #define IS_CHAN_ANY(ah) \
128 (((struct ieee80211com *)ah->ah_sc)->ic_bsschan == IEEE80211_CHAN_ANYC)
129
130 #define IS_BG_OR_ANY(ah) \
131 (IS_CHAN_ANY(ah) || (!(ieee80211_chan2mode(((struct ieee80211com *)ah->ah_sc)->ic_bsschan) & \
132 (IEEE80211_MODE_11A | IEEE80211_MODE_TURBO_A))))
133
134 #define DEFAULT_ENABLE_AR5K_PHY_WEAK_OFDM (IS_BG_OR_ANY(ah) ? \
135 DEFAULT_ENABLE_AR5K_PHY_WEAK_OFDM_11BG : \
136 DEFAULT_ENABLE_AR5K_PHY_WEAK_OFDM_11A \
137 )
138
139 #define DEFAULT_ENABLE_AR5K_PHY_WEAK_OFDM_HIGH DEFAULT_ENABLE_AR5K_PHY_WEAK_OFDM
140 #define DEFAULT_ENABLE_AR5K_PHY_WEAK_OFDM_LOW DEFAULT_ENABLE_AR5K_PHY_WEAK_OFDM
141 #define DEFAULT_ENABLE_AR5K_PHY_WEAK_CCK 0
142
143 #define DEFAULT_AR5K_PHY_SPUR_THRESH 2
144 #define DEFAULT_AR5K_PHY_SIG_FIRSTEP 0
145
146 /*
147 * Transmit configuration register
148 */
149 #define AR5K_TXCFG 0x0030 /* Register Address */
150 #define AR5K_TXCFG_SDMAMR 0x00000007 /* DMA size */
151 #define AR5K_TXCFG_SDMAMR_S 0
152
153 /*
154 * Receive configuration register
155 */
156 #define AR5K_RXCFG 0x0034 /* Register Address */
157 #define AR5K_RXCFG_SDMAMW 0x00000007 /* DMA size */
158 #define AR5K_RXCFG_SDMAMW_S 0
159
160 /*
161 * Second station id register (MAC address in upper 16 bits)
162 */
163 #define AR5K_STA_ID1 0x8004 /* Register Address */
164 #define AR5K_STA_ID1_AP 0x00010000 /* Set AP mode */
165 #define AR5K_STA_ID1_ADHOC 0x00020000 /* Set Ad-Hoc mode */
166 #define AR5K_STA_ID1_PWR_SV 0x00040000 /* Power save reporting (?) */
167 #define AR5K_STA_ID1_NO_KEYSRCH 0x00080000 /* No key search */
168 #define AR5K_STA_ID1_NO_PSPOLL 0x00100000 /* No power save polling [5210] */
169 #define AR5K_STA_ID1_PCF_5211 0x00100000 /* Enable PCF on [5211+] */
170 #define AR5K_STA_ID1_PCF_5210 0x00200000 /* Enable PCF on [5210] */
171 #define AR5K_STA_ID1_PCF (ah->ah_version == AR5K_AR5210 ? \
172 AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211)
173 #define AR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000 /* Use default antenna */
174 #define AR5K_STA_ID1_DESC_ANTENNA 0x00400000 /* Update antenna from descriptor */
175 #define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000 /* Use default antenna for RTS (?) */
176 #define AR5K_STA_ID1_ACKCTS_6MB 0x01000000 /* Use 6Mbit/s for ACK/CTS (?) */
177 #define AR5K_STA_ID1_BASE_RATE_11B 0x02000000 /* Use 11b base rate (for ACK/CTS ?) [5211+] */
178
179 /*
180 * PCU beacon control register
181 */
182 #define AR5K_BEACON_5210 0x8024
183 #define AR5K_BEACON_5211 0x8020
184
185 /*
186 * Next beacon time register
187 */
188 #define AR5K_TIMER0_5210 0x802c
189 #define AR5K_TIMER0_5211 0x8028
190 /*
191 * Next DMA beacon alert register
192 */
193 #define AR5K_TIMER1_5210 0x8030
194 #define AR5K_TIMER1_5211 0x802c
195
196 /*
197 * Next software beacon alert register
198 */
199 #define AR5K_TIMER2_5210 0x8034
200 #define AR5K_TIMER2_5211 0x8030
201
202 /*
203 * Next ATIM window time register
204 */
205 #define AR5K_TIMER3_5210 0x8038
206 #define AR5K_TIMER3_5211 0x8034
207
208
209 enum ath5k_srev_type {
210 AR5K_VERSION_VER,
211 AR5K_VERSION_RAD,
212 };
213
214 struct ath5k_srev_name {
215 const char *sr_name;
216 enum ath5k_srev_type sr_type;
217 u_int sr_val;
218 };
219
220 #define AR5K_SREV_UNKNOWN 0xffff
221
222 #define AR5K_SREV_VER_AR5210 0x00
223 #define AR5K_SREV_VER_AR5311 0x10
224 #define AR5K_SREV_VER_AR5311A 0x20
225 #define AR5K_SREV_VER_AR5311B 0x30
226 #define AR5K_SREV_VER_AR5211 0x40
227 #define AR5K_SREV_VER_AR5212 0x50
228 #define AR5K_SREV_VER_AR5213 0x55
229 #define AR5K_SREV_VER_AR5213A 0x59
230 #define AR5K_SREV_VER_AR2413 0x78
231 #define AR5K_SREV_VER_AR2414 0x79
232 #define AR5K_SREV_VER_AR2424 0xa0 /* PCI-E */
233 #define AR5K_SREV_VER_AR5424 0xa3 /* PCI-E */
234 #define AR5K_SREV_VER_AR5413 0xa4
235 #define AR5K_SREV_VER_AR5414 0xa5
236 #define AR5K_SREV_VER_AR5416 0xc0 /* PCI-E */
237 #define AR5K_SREV_VER_AR5418 0xca /* PCI-E */
238 #define AR5K_SREV_VER_AR2425 0xe2 /* PCI-E */
239
240 #define AR5K_SREV_RAD_5110 0x00
241 #define AR5K_SREV_RAD_5111 0x10
242 #define AR5K_SREV_RAD_5111A 0x15
243 #define AR5K_SREV_RAD_2111 0x20
244 #define AR5K_SREV_RAD_5112 0x30
245 #define AR5K_SREV_RAD_5112A 0x35
246 #define AR5K_SREV_RAD_2112 0x40
247 #define AR5K_SREV_RAD_2112A 0x45
248 #define AR5K_SREV_RAD_SC0 0x56 /* Found on 2413/2414 */
249 #define AR5K_SREV_RAD_SC1 0x63 /* Found on 5413/5414 */
250 #define AR5K_SREV_RAD_SC2 0xa2 /* Found on 2424-5/5424 */
251 #define AR5K_SREV_RAD_5133 0xc0 /* MIMO found on 5418 */
252
253 #define ATH_SREV_FROM_AH(_ah) ((_ah)->ah_macVersion << 4 | (_ah)->ah_macRev)
254
255 /*
256 * DMA size definitions (2^(n+2))
257 */
258 enum ath5k_dmasize {
259 AR5K_DMASIZE_4B = 0,
260 AR5K_DMASIZE_8B,
261 AR5K_DMASIZE_16B,
262 AR5K_DMASIZE_32B,
263 AR5K_DMASIZE_64B,
264 AR5K_DMASIZE_128B,
265 AR5K_DMASIZE_256B,
266 AR5K_DMASIZE_512B
267 };
268
269
270 int ath_set_ack_bitrate(struct ath_softc *sc, int);
271 int ar_device(int devid);
272 const char * ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val);
273 void ath_hw_beacon_stop(struct ath_softc *sc);
274 int ath_hw_check_atim(struct ath_softc *sc, int window, int intval);
275
276 static inline unsigned long field_width(unsigned long mask, unsigned long shift)
277 {
278 unsigned long r = 0;
279 unsigned long x = mask >> shift;
280 if ( 0 == mask ) return 0;
281 #if BITS_PER_LONG >= 64
282 if ( x & (~0UL<<32) ) { x >>= 32; r += 32; }
283 #endif
284 if ( x & 0xffff0000 ) { x >>= 16; r += 16; }
285 if ( x & 0x0000ff00 ) { x >>= 8; r += 8; }
286 if ( x & 0x000000f0 ) { x >>= 4; r += 4; }
287 if ( x & 0x0000000c ) { x >>= 2; r += 2; }
288 if ( x & 0x00000002 ) { r += 1; }
289 return r+1;
290 }
291
292 static inline u_int32_t get_field(struct ath_hal *ah, u_int32_t reg, u_int32_t mask, u_int32_t shift, int is_signed) {
293 unsigned long x = ((OS_REG_READ(ah, reg) & mask) >> shift);
294 if (is_signed) {
295 unsigned long c =(-1) << (field_width(mask, shift)-1);
296 return (x + c) ^ c;
297 }
298 return x;
299 }
300
301 static inline void set_field(struct ath_hal *ah, u_int32_t reg, u_int32_t mask, u_int32_t shift, u_int32_t value) {
302 OS_REG_WRITE(ah, reg,
303 (OS_REG_READ(ah, reg) & ~mask) |
304 ((value << shift) & mask));
305 }
306
307 static inline u_int32_t field_eq(struct ath_hal *ah, u_int32_t reg,
308 u_int32_t mask, u_int32_t shift,
309 u_int32_t value, int is_signed) {
310 return (get_field(ah, reg, mask, shift, is_signed) & (mask >> shift)) ==
311 (value & (mask >> shift));
312 }
313
314 static inline void override_warning(struct ath_hal *ah, const char *name,
315 u_int32_t reg, u_int32_t mask,
316 u_int32_t shift, u_int32_t expected, int is_signed) {
317
318 if (!field_eq(ah, reg, mask, shift, expected, is_signed))
319 printk("%s: Correcting 0x%04x[%s] from 0x%x (%d) to 0x%x (%d).\n",
320 SC_DEV_NAME(ah->ah_sc),
321 reg,
322 name,
323 (get_field(ah, reg, mask, shift, is_signed) & (mask >> shift)),
324 get_field(ah, reg, mask, shift, is_signed),
325 (expected & (mask >> shift)), /* not sign extended */
326 expected);
327 #if 0 /* NB: For checking to see if HAL is fixed or not */
328 else {
329 printk("%s: Keeping 0x%04x[%s] - 0x%x (%d).\n",
330 SC_DEV_NAME(ah->ah_sc),
331 reg,
332 name,
333 (get_field(ah, reg, mask, shift, is_signed) & (mask >> shift)),
334 get_field(ah, reg, mask, shift, is_signed));
335 }
336 #endif
337 }
338
339 static inline void verification_warning(struct ath_hal *ah, const char *name,
340 u_int32_t reg, u_int32_t mask,
341 u_int32_t shift, u_int32_t expected, int is_signed) {
342
343 int ret = field_eq(ah, reg, mask, shift, expected, is_signed);
344 if (!ret) {
345 printk("%s: %s verification of %s default value "
346 "[found=0x%x (%d) expected=0x%x (%d)].\n",
347 SC_DEV_NAME(ah->ah_sc),
348 (ret ? "PASSED" : "FAILED"),
349 name,
350 (get_field(ah, reg, mask, shift, is_signed) & (mask >> shift)),
351 get_field(ah, reg, mask, shift, is_signed),
352 (expected & (mask >> shift)), /* not sign extended */
353 expected);
354 ath_hal_print_decoded_register(ah, NULL, reg,
355 OS_REG_READ(ah, reg), OS_REG_READ(ah, reg), 0);
356 }
357 }
358
359 #define GET_FIELD(ah, __reg, __mask, __signed) \
360 get_field(ah, __reg, __mask, __mask ## _S, __signed)
361 #define SET_FIELD(ah, __reg, __mask, __value) \
362 set_field(ah, __reg, __mask, __mask ## _S, __value);
363 #define FIELD_EQ(ah, __reg, __mask, __value, __signed) \
364 field_eq(ah, __reg, __mask, __mask ## _S, __value, __signed)
365
366 #if 0 /* NB: These are working at this point, and HAL tweaks them a lot */
367 #define OVERRIDE_WARNING(ah, __reg, __mask, __expected, __signed) \
368 override_warning(ah, #__mask, __reg, __mask, __mask ## _S, __expected, __signed)
369 #else
370 #define OVERRIDE_WARNING(ah, __reg, __mask, __expected, __signed)
371 #endif
372
373 #define VERIFICATION_WARNING(ah, __reg, __mask, __signed) \
374 verification_warning(ah, #__mask, __reg, __mask, __mask ## _S, DEFAULT_ ## __mask, __signed)
375 #define VERIFICATION_WARNING_SW(ah, __reg, __mask, __signed) \
376 verification_warning(ah, #__mask, __reg, __mask, __mask ## _S, DEFAULT_ENABLE_ ## __reg ? __mask ## _ON : __mask ## _OFF, __signed)
377
378 static inline void ath_hal_set_noise_immunity(struct ath_hal *ah,
379 int agc_desired_size,
380 int agc_coarse_hi,
381 int agc_coarse_lo,
382 int sig_firpwr)
383 {
384 ATH_HAL_LOCK_IRQ(ah->ah_sc);
385 ath_hal_set_function(__func__);
386 ath_hal_set_device(SC_DEV_NAME(ah->ah_sc));
387
388 #if 0 /* NB: These are working at this point, and HAL tweaks them a lot */
389 OVERRIDE_WARNING(ah, AR5K_PHY_AGCSIZE, AR5K_PHY_AGCSIZE_DESIRED, agc_desired_size, 1);
390 OVERRIDE_WARNING(ah, AR5K_PHY_AGCCOARSE, AR5K_PHY_AGCCOARSE_LO, agc_coarse_lo, 1);
391 OVERRIDE_WARNING(ah, AR5K_PHY_AGCCOARSE, AR5K_PHY_AGCCOARSE_HI, agc_coarse_hi, 1);
392 OVERRIDE_WARNING(ah, AR5K_PHY_SIG, AR5K_PHY_SIG_FIRPWR, sig_firpwr, 1);
393 #endif
394
395 SET_FIELD(ah, AR5K_PHY_AGCSIZE, AR5K_PHY_AGCSIZE_DESIRED, agc_desired_size);
396 SET_FIELD(ah, AR5K_PHY_AGCCOARSE, AR5K_PHY_AGCCOARSE_LO, agc_coarse_lo);
397 SET_FIELD(ah, AR5K_PHY_AGCCOARSE, AR5K_PHY_AGCCOARSE_HI, agc_coarse_hi);
398 SET_FIELD(ah, AR5K_PHY_SIG, AR5K_PHY_SIG_FIRPWR, sig_firpwr);
399
400 ath_hal_set_function(NULL);
401 ath_hal_set_device(NULL);
402 ATH_HAL_UNLOCK_IRQ(ah->ah_sc);
403 }
404
405 static inline void ath_hal_set_ofdm_weak_det(struct ath_hal *ah,
406 int low_m1, int low_m2, int low_m2_count, int low_self_corr,
407 int high_m1, int high_m2, int high_m2_count)
408 {
409 ATH_HAL_LOCK_IRQ(ah->ah_sc);
410 ath_hal_set_function(__func__);
411 ath_hal_set_device(SC_DEV_NAME(ah->ah_sc));
412
413 OVERRIDE_WARNING(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_M1, low_m1, 0);
414 OVERRIDE_WARNING(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_M2, low_m2, 0);
415 OVERRIDE_WARNING(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_M2_COUNT, low_m2_count, 0);
416 OVERRIDE_WARNING(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_SELFCOR, low_self_corr, 0);
417 OVERRIDE_WARNING(ah, AR5K_PHY_WEAK_OFDM_HIGH, AR5K_PHY_WEAK_OFDM_HIGH_M1, high_m1, 0);
418 OVERRIDE_WARNING(ah, AR5K_PHY_WEAK_OFDM_HIGH, AR5K_PHY_WEAK_OFDM_HIGH_M2, high_m2, 0);
419 OVERRIDE_WARNING(ah, AR5K_PHY_WEAK_OFDM_HIGH, AR5K_PHY_WEAK_OFDM_HIGH_M2_COUNT, high_m2_count, 0);
420
421 SET_FIELD(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_M1, low_m1);
422 SET_FIELD(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_M2, low_m2);
423 SET_FIELD(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_M2_COUNT, low_m2_count);
424 SET_FIELD(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_SELFCOR, low_self_corr);
425 SET_FIELD(ah, AR5K_PHY_WEAK_OFDM_HIGH, AR5K_PHY_WEAK_OFDM_HIGH_M1, high_m1);
426 SET_FIELD(ah, AR5K_PHY_WEAK_OFDM_HIGH, AR5K_PHY_WEAK_OFDM_HIGH_M2, high_m2);
427 SET_FIELD(ah, AR5K_PHY_WEAK_OFDM_HIGH, AR5K_PHY_WEAK_OFDM_HIGH_M2_COUNT, high_m2_count);
428
429 ath_hal_set_function(NULL);
430 ath_hal_set_device(NULL);
431 ATH_HAL_UNLOCK_IRQ(ah->ah_sc);
432 }
433
434 static inline void ath_hal_set_cck_weak_det(struct ath_hal *ah, int thresh)
435 {
436 ATH_HAL_LOCK_IRQ(ah->ah_sc);
437 ath_hal_set_function(__func__);
438 ath_hal_set_device(SC_DEV_NAME(ah->ah_sc));
439
440 OVERRIDE_WARNING(ah, AR5K_PHY_WEAK_CCK, AR5K_PHY_WEAK_CCK_THRESH, thresh, 0);
441
442 SET_FIELD(ah, AR5K_PHY_WEAK_CCK, AR5K_PHY_WEAK_CCK_THRESH, thresh);
443
444 ath_hal_set_function(NULL);
445 ath_hal_set_device(NULL);
446 ATH_HAL_UNLOCK_IRQ(ah->ah_sc);
447 }
448
449 static inline void ath_hal_set_sig_firstep(struct ath_hal *ah, int firstep)
450 {
451 ATH_HAL_LOCK_IRQ(ah->ah_sc);
452 ath_hal_set_function(__func__);
453 ath_hal_set_device(SC_DEV_NAME(ah->ah_sc));
454
455 OVERRIDE_WARNING(ah, AR5K_PHY_SIG, AR5K_PHY_SIG_FIRSTEP, firstep, 0);
456
457 SET_FIELD(ah, AR5K_PHY_SIG, AR5K_PHY_SIG_FIRSTEP, firstep);
458
459 ath_hal_set_function(NULL);
460 ath_hal_set_device(NULL);
461 ATH_HAL_UNLOCK_IRQ(ah->ah_sc);
462 }
463
464 static inline void ath_hal_set_spur_immunity(struct ath_hal *ah, int thresh)
465 {
466 ATH_HAL_LOCK_IRQ(ah->ah_sc);
467 ath_hal_set_function(__func__);
468 ath_hal_set_device(SC_DEV_NAME(ah->ah_sc));
469
470 OVERRIDE_WARNING(ah, AR5K_PHY_SPUR, AR5K_PHY_SPUR_THRESH, thresh, 0);
471
472 SET_FIELD(ah, AR5K_PHY_SPUR, AR5K_PHY_SPUR_THRESH, thresh);
473
474 ath_hal_set_function(NULL);
475 ath_hal_set_device(NULL);
476 ATH_HAL_UNLOCK_IRQ(ah->ah_sc);
477 }
478
479 static inline void ath_hal_restore_default_noise_immunity(struct ath_hal *ah) {
480
481 ath_hal_set_noise_immunity(ah,
482 DEFAULT_AR5K_PHY_AGCSIZE_DESIRED,
483 DEFAULT_AR5K_PHY_AGCCOARSE_HI,
484 DEFAULT_AR5K_PHY_AGCCOARSE_LO,
485 DEFAULT_AR5K_PHY_SIG_FIRPWR);
486 }
487
488 static inline void ath_hal_enable_ofdm_weak_det(struct ath_hal *ah, int enable) {
489 if (enable)
490 ath_hal_set_ofdm_weak_det(ah,
491 AR5K_PHY_WEAK_OFDM_LOW_M1_ON,
492 AR5K_PHY_WEAK_OFDM_LOW_M2_ON,
493 AR5K_PHY_WEAK_OFDM_LOW_M2_COUNT_ON,
494 AR5K_PHY_WEAK_OFDM_LOW_SELFCOR_ON,
495 AR5K_PHY_WEAK_OFDM_HIGH_M1_ON,
496 AR5K_PHY_WEAK_OFDM_HIGH_M2_ON,
497 AR5K_PHY_WEAK_OFDM_HIGH_M2_COUNT_ON);
498 else
499 ath_hal_set_ofdm_weak_det(ah,
500 AR5K_PHY_WEAK_OFDM_LOW_M1_OFF,
501 AR5K_PHY_WEAK_OFDM_LOW_M2_OFF,
502 AR5K_PHY_WEAK_OFDM_LOW_M2_COUNT_OFF,
503 AR5K_PHY_WEAK_OFDM_LOW_SELFCOR_OFF,
504 AR5K_PHY_WEAK_OFDM_HIGH_M1_OFF,
505 AR5K_PHY_WEAK_OFDM_HIGH_M2_OFF,
506 AR5K_PHY_WEAK_OFDM_HIGH_M2_COUNT_OFF);
507 }
508
509 static inline void ath_hal_enable_cck_weak_det(struct ath_hal *ah, int enable) {
510 ath_hal_set_cck_weak_det(ah, enable
511 ? AR5K_PHY_WEAK_CCK_THRESH_ON
512 : AR5K_PHY_WEAK_CCK_THRESH_OFF);
513 }
514
515 static inline void ath_hal_restore_default_ofdm_weak_det(struct ath_hal *ah) {
516 ath_hal_enable_ofdm_weak_det(ah, DEFAULT_ENABLE_AR5K_PHY_WEAK_OFDM);
517 }
518
519 static inline void ath_hal_restore_default_cck_weak_det(struct ath_hal *ah) {
520 ath_hal_enable_cck_weak_det(ah, DEFAULT_ENABLE_AR5K_PHY_WEAK_CCK);
521 }
522
523 static inline void ath_hal_restore_default_sig_firstep(struct ath_hal *ah) {
524
525 ath_hal_set_sig_firstep(ah,
526 DEFAULT_AR5K_PHY_SIG_FIRSTEP);
527 }
528
529 static inline void ath_hal_restore_default_spur_immunity(struct ath_hal *ah) {
530
531 ath_hal_set_spur_immunity(ah,
532 DEFAULT_AR5K_PHY_SPUR_THRESH);
533 }
534
535 static inline void ath_hal_restore_default_intmit(struct ath_hal *ah) {
536 ath_hal_restore_default_noise_immunity(ah);
537 ath_hal_restore_default_ofdm_weak_det(ah);
538 ath_hal_restore_default_cck_weak_det(ah);
539 ath_hal_restore_default_sig_firstep(ah);
540 ath_hal_restore_default_spur_immunity(ah);
541
542 }
543
544 static inline void ath_hal_verify_default_intmit(struct ath_hal *ah) {
545 /* Just a list of all the fields above, for sanity checks... */
546 VERIFICATION_WARNING(ah, AR5K_PHY_AGCSIZE, AR5K_PHY_AGCSIZE_DESIRED, 1);
547 VERIFICATION_WARNING(ah, AR5K_PHY_AGCCOARSE, AR5K_PHY_AGCCOARSE_LO, 1);
548 VERIFICATION_WARNING(ah, AR5K_PHY_AGCCOARSE, AR5K_PHY_AGCCOARSE_HI, 1);
549 VERIFICATION_WARNING(ah, AR5K_PHY_SIG, AR5K_PHY_SIG_FIRPWR, 1);
550 VERIFICATION_WARNING_SW(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_M1, 0);
551 VERIFICATION_WARNING_SW(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_M2, 0);
552 VERIFICATION_WARNING_SW(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_M2_COUNT, 0);
553 VERIFICATION_WARNING_SW(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_SELFCOR, 0);
554 VERIFICATION_WARNING_SW(ah, AR5K_PHY_WEAK_OFDM_HIGH, AR5K_PHY_WEAK_OFDM_HIGH_M1, 0);
555 VERIFICATION_WARNING_SW(ah, AR5K_PHY_WEAK_OFDM_HIGH, AR5K_PHY_WEAK_OFDM_HIGH_M2, 0);
556 VERIFICATION_WARNING_SW(ah, AR5K_PHY_WEAK_OFDM_HIGH, AR5K_PHY_WEAK_OFDM_HIGH_M2_COUNT, 0);
557 VERIFICATION_WARNING_SW(ah, AR5K_PHY_WEAK_CCK, AR5K_PHY_WEAK_CCK_THRESH, 0);
558 VERIFICATION_WARNING(ah, AR5K_PHY_SIG, AR5K_PHY_SIG_FIRSTEP, 0);
559 VERIFICATION_WARNING(ah, AR5K_PHY_SPUR, AR5K_PHY_SPUR_THRESH, 0);
560 }
561
562 static inline void ath_hal_set_dmasize_pcie(struct ath_hal *ah) {
563 SET_FIELD(ah, AR5K_TXCFG, AR5K_TXCFG_SDMAMR, AR5K_DMASIZE_128B);
564 SET_FIELD(ah, AR5K_RXCFG, AR5K_RXCFG_SDMAMW, AR5K_DMASIZE_128B);
565 }
566
567 #endif /* _IF_ATH_HAL_EXTENSIONS_H_ */
Stable & featurefull patchset based on Linus's git branch