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[linux-2.6/zen-sources.git] / drivers / net / sundance.c
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1 /* sundance.c: A Linux device driver for the Sundance ST201 "Alta". */
2 /*
3 Written 1999-2000 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 The author may be reached as becker@scyld.com, or C/O
13 Scyld Computing Corporation
14 410 Severn Ave., Suite 210
15 Annapolis MD 21403
16
17 Support and updates available at
18 http://www.scyld.com/network/sundance.html
19 [link no longer provides useful info -jgarzik]
20 Archives of the mailing list are still available at
21 http://www.beowulf.org/pipermail/netdrivers/
22
23 */
24
25 #define DRV_NAME "sundance"
26 #define DRV_VERSION "1.2"
27 #define DRV_RELDATE "11-Sep-2006"
28
29
30 /* The user-configurable values.
31 These may be modified when a driver module is loaded.*/
32 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
33 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
34 Typical is a 64 element hash table based on the Ethernet CRC. */
35 static const int multicast_filter_limit = 32;
36
37 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
38 Setting to > 1518 effectively disables this feature.
39 This chip can receive into offset buffers, so the Alpha does not
40 need a copy-align. */
41 static int rx_copybreak;
42 static int flowctrl=1;
43
44 /* media[] specifies the media type the NIC operates at.
45 autosense Autosensing active media.
46 10mbps_hd 10Mbps half duplex.
47 10mbps_fd 10Mbps full duplex.
48 100mbps_hd 100Mbps half duplex.
49 100mbps_fd 100Mbps full duplex.
50 0 Autosensing active media.
51 1 10Mbps half duplex.
52 2 10Mbps full duplex.
53 3 100Mbps half duplex.
54 4 100Mbps full duplex.
55 */
56 #define MAX_UNITS 8
57 static char *media[MAX_UNITS];
58
59
60 /* Operational parameters that are set at compile time. */
61
62 /* Keep the ring sizes a power of two for compile efficiency.
63 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
64 Making the Tx ring too large decreases the effectiveness of channel
65 bonding and packet priority, and more than 128 requires modifying the
66 Tx error recovery.
67 Large receive rings merely waste memory. */
68 #define TX_RING_SIZE 32
69 #define TX_QUEUE_LEN (TX_RING_SIZE - 1) /* Limit ring entries actually used. */
70 #define RX_RING_SIZE 64
71 #define RX_BUDGET 32
72 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct netdev_desc)
73 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct netdev_desc)
74
75 /* Operational parameters that usually are not changed. */
76 /* Time in jiffies before concluding the transmitter is hung. */
77 #define TX_TIMEOUT (4*HZ)
78 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
79
80 /* Include files, designed to support most kernel versions 2.0.0 and later. */
81 #include <linux/module.h>
82 #include <linux/kernel.h>
83 #include <linux/string.h>
84 #include <linux/timer.h>
85 #include <linux/errno.h>
86 #include <linux/ioport.h>
87 #include <linux/slab.h>
88 #include <linux/interrupt.h>
89 #include <linux/pci.h>
90 #include <linux/netdevice.h>
91 #include <linux/etherdevice.h>
92 #include <linux/skbuff.h>
93 #include <linux/init.h>
94 #include <linux/bitops.h>
95 #include <asm/uaccess.h>
96 #include <asm/processor.h> /* Processor type for cache alignment. */
97 #include <asm/io.h>
98 #include <linux/delay.h>
99 #include <linux/spinlock.h>
100 #ifndef _COMPAT_WITH_OLD_KERNEL
101 #include <linux/crc32.h>
102 #include <linux/ethtool.h>
103 #include <linux/mii.h>
104 #else
105 #include "crc32.h"
106 #include "ethtool.h"
107 #include "mii.h"
108 #include "compat.h"
109 #endif
110
111 /* These identify the driver base version and may not be removed. */
112 static char version[] =
113 KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker\n";
114
115 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
116 MODULE_DESCRIPTION("Sundance Alta Ethernet driver");
117 MODULE_LICENSE("GPL");
118
119 module_param(debug, int, 0);
120 module_param(rx_copybreak, int, 0);
121 module_param_array(media, charp, NULL, 0);
122 module_param(flowctrl, int, 0);
123 MODULE_PARM_DESC(debug, "Sundance Alta debug level (0-5)");
124 MODULE_PARM_DESC(rx_copybreak, "Sundance Alta copy breakpoint for copy-only-tiny-frames");
125 MODULE_PARM_DESC(flowctrl, "Sundance Alta flow control [0|1]");
126
127 /*
128 Theory of Operation
129
130 I. Board Compatibility
131
132 This driver is designed for the Sundance Technologies "Alta" ST201 chip.
133
134 II. Board-specific settings
135
136 III. Driver operation
137
138 IIIa. Ring buffers
139
140 This driver uses two statically allocated fixed-size descriptor lists
141 formed into rings by a branch from the final descriptor to the beginning of
142 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
143 Some chips explicitly use only 2^N sized rings, while others use a
144 'next descriptor' pointer that the driver forms into rings.
145
146 IIIb/c. Transmit/Receive Structure
147
148 This driver uses a zero-copy receive and transmit scheme.
149 The driver allocates full frame size skbuffs for the Rx ring buffers at
150 open() time and passes the skb->data field to the chip as receive data
151 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
152 a fresh skbuff is allocated and the frame is copied to the new skbuff.
153 When the incoming frame is larger, the skbuff is passed directly up the
154 protocol stack. Buffers consumed this way are replaced by newly allocated
155 skbuffs in a later phase of receives.
156
157 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
158 using a full-sized skbuff for small frames vs. the copying costs of larger
159 frames. New boards are typically used in generously configured machines
160 and the underfilled buffers have negligible impact compared to the benefit of
161 a single allocation size, so the default value of zero results in never
162 copying packets. When copying is done, the cost is usually mitigated by using
163 a combined copy/checksum routine. Copying also preloads the cache, which is
164 most useful with small frames.
165
166 A subtle aspect of the operation is that the IP header at offset 14 in an
167 ethernet frame isn't longword aligned for further processing.
168 Unaligned buffers are permitted by the Sundance hardware, so
169 frames are received into the skbuff at an offset of "+2", 16-byte aligning
170 the IP header.
171
172 IIId. Synchronization
173
174 The driver runs as two independent, single-threaded flows of control. One
175 is the send-packet routine, which enforces single-threaded use by the
176 dev->tbusy flag. The other thread is the interrupt handler, which is single
177 threaded by the hardware and interrupt handling software.
178
179 The send packet thread has partial control over the Tx ring and 'dev->tbusy'
180 flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
181 queue slot is empty, it clears the tbusy flag when finished otherwise it sets
182 the 'lp->tx_full' flag.
183
184 The interrupt handler has exclusive control over the Rx ring and records stats
185 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
186 empty by incrementing the dirty_tx mark. Iff the 'lp->tx_full' flag is set, it
187 clears both the tx_full and tbusy flags.
188
189 IV. Notes
190
191 IVb. References
192
193 The Sundance ST201 datasheet, preliminary version.
194 The Kendin KS8723 datasheet, preliminary version.
195 The ICplus IP100 datasheet, preliminary version.
196 http://www.scyld.com/expert/100mbps.html
197 http://www.scyld.com/expert/NWay.html
198
199 IVc. Errata
200
201 */
202
203 /* Work-around for Kendin chip bugs. */
204 #ifndef CONFIG_SUNDANCE_MMIO
205 #define USE_IO_OPS 1
206 #endif
207
208 static const struct pci_device_id sundance_pci_tbl[] = {
209 { 0x1186, 0x1002, 0x1186, 0x1002, 0, 0, 0 },
210 { 0x1186, 0x1002, 0x1186, 0x1003, 0, 0, 1 },
211 { 0x1186, 0x1002, 0x1186, 0x1012, 0, 0, 2 },
212 { 0x1186, 0x1002, 0x1186, 0x1040, 0, 0, 3 },
213 { 0x1186, 0x1002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
214 { 0x13F0, 0x0201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 },
215 { 0x13F0, 0x0200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6 },
216 { }
217 };
218 MODULE_DEVICE_TABLE(pci, sundance_pci_tbl);
219
220 enum {
221 netdev_io_size = 128
222 };
223
224 struct pci_id_info {
225 const char *name;
226 };
227 static const struct pci_id_info pci_id_tbl[] __devinitdata = {
228 {"D-Link DFE-550TX FAST Ethernet Adapter"},
229 {"D-Link DFE-550FX 100Mbps Fiber-optics Adapter"},
230 {"D-Link DFE-580TX 4 port Server Adapter"},
231 {"D-Link DFE-530TXS FAST Ethernet Adapter"},
232 {"D-Link DL10050-based FAST Ethernet Adapter"},
233 {"Sundance Technology Alta"},
234 {"IC Plus Corporation IP100A FAST Ethernet Adapter"},
235 { } /* terminate list. */
236 };
237
238 /* This driver was written to use PCI memory space, however x86-oriented
239 hardware often uses I/O space accesses. */
240
241 /* Offsets to the device registers.
242 Unlike software-only systems, device drivers interact with complex hardware.
243 It's not useful to define symbolic names for every register bit in the
244 device. The name can only partially document the semantics and make
245 the driver longer and more difficult to read.
246 In general, only the important configuration values or bits changed
247 multiple times should be defined symbolically.
248 */
249 enum alta_offsets {
250 DMACtrl = 0x00,
251 TxListPtr = 0x04,
252 TxDMABurstThresh = 0x08,
253 TxDMAUrgentThresh = 0x09,
254 TxDMAPollPeriod = 0x0a,
255 RxDMAStatus = 0x0c,
256 RxListPtr = 0x10,
257 DebugCtrl0 = 0x1a,
258 DebugCtrl1 = 0x1c,
259 RxDMABurstThresh = 0x14,
260 RxDMAUrgentThresh = 0x15,
261 RxDMAPollPeriod = 0x16,
262 LEDCtrl = 0x1a,
263 ASICCtrl = 0x30,
264 EEData = 0x34,
265 EECtrl = 0x36,
266 FlashAddr = 0x40,
267 FlashData = 0x44,
268 TxStatus = 0x46,
269 TxFrameId = 0x47,
270 DownCounter = 0x18,
271 IntrClear = 0x4a,
272 IntrEnable = 0x4c,
273 IntrStatus = 0x4e,
274 MACCtrl0 = 0x50,
275 MACCtrl1 = 0x52,
276 StationAddr = 0x54,
277 MaxFrameSize = 0x5A,
278 RxMode = 0x5c,
279 MIICtrl = 0x5e,
280 MulticastFilter0 = 0x60,
281 MulticastFilter1 = 0x64,
282 RxOctetsLow = 0x68,
283 RxOctetsHigh = 0x6a,
284 TxOctetsLow = 0x6c,
285 TxOctetsHigh = 0x6e,
286 TxFramesOK = 0x70,
287 RxFramesOK = 0x72,
288 StatsCarrierError = 0x74,
289 StatsLateColl = 0x75,
290 StatsMultiColl = 0x76,
291 StatsOneColl = 0x77,
292 StatsTxDefer = 0x78,
293 RxMissed = 0x79,
294 StatsTxXSDefer = 0x7a,
295 StatsTxAbort = 0x7b,
296 StatsBcastTx = 0x7c,
297 StatsBcastRx = 0x7d,
298 StatsMcastTx = 0x7e,
299 StatsMcastRx = 0x7f,
300 /* Aliased and bogus values! */
301 RxStatus = 0x0c,
302 };
303 enum ASICCtrl_HiWord_bit {
304 GlobalReset = 0x0001,
305 RxReset = 0x0002,
306 TxReset = 0x0004,
307 DMAReset = 0x0008,
308 FIFOReset = 0x0010,
309 NetworkReset = 0x0020,
310 HostReset = 0x0040,
311 ResetBusy = 0x0400,
312 };
313
314 /* Bits in the interrupt status/mask registers. */
315 enum intr_status_bits {
316 IntrSummary=0x0001, IntrPCIErr=0x0002, IntrMACCtrl=0x0008,
317 IntrTxDone=0x0004, IntrRxDone=0x0010, IntrRxStart=0x0020,
318 IntrDrvRqst=0x0040,
319 StatsMax=0x0080, LinkChange=0x0100,
320 IntrTxDMADone=0x0200, IntrRxDMADone=0x0400,
321 };
322
323 /* Bits in the RxMode register. */
324 enum rx_mode_bits {
325 AcceptAllIPMulti=0x20, AcceptMultiHash=0x10, AcceptAll=0x08,
326 AcceptBroadcast=0x04, AcceptMulticast=0x02, AcceptMyPhys=0x01,
327 };
328 /* Bits in MACCtrl. */
329 enum mac_ctrl0_bits {
330 EnbFullDuplex=0x20, EnbRcvLargeFrame=0x40,
331 EnbFlowCtrl=0x100, EnbPassRxCRC=0x200,
332 };
333 enum mac_ctrl1_bits {
334 StatsEnable=0x0020, StatsDisable=0x0040, StatsEnabled=0x0080,
335 TxEnable=0x0100, TxDisable=0x0200, TxEnabled=0x0400,
336 RxEnable=0x0800, RxDisable=0x1000, RxEnabled=0x2000,
337 };
338
339 /* The Rx and Tx buffer descriptors. */
340 /* Note that using only 32 bit fields simplifies conversion to big-endian
341 architectures. */
342 struct netdev_desc {
343 __le32 next_desc;
344 __le32 status;
345 struct desc_frag { __le32 addr, length; } frag[1];
346 };
347
348 /* Bits in netdev_desc.status */
349 enum desc_status_bits {
350 DescOwn=0x8000,
351 DescEndPacket=0x4000,
352 DescEndRing=0x2000,
353 LastFrag=0x80000000,
354 DescIntrOnTx=0x8000,
355 DescIntrOnDMADone=0x80000000,
356 DisableAlign = 0x00000001,
357 };
358
359 #define PRIV_ALIGN 15 /* Required alignment mask */
360 /* Use __attribute__((aligned (L1_CACHE_BYTES))) to maintain alignment
361 within the structure. */
362 #define MII_CNT 4
363 struct netdev_private {
364 /* Descriptor rings first for alignment. */
365 struct netdev_desc *rx_ring;
366 struct netdev_desc *tx_ring;
367 struct sk_buff* rx_skbuff[RX_RING_SIZE];
368 struct sk_buff* tx_skbuff[TX_RING_SIZE];
369 dma_addr_t tx_ring_dma;
370 dma_addr_t rx_ring_dma;
371 struct net_device_stats stats;
372 struct timer_list timer; /* Media monitoring timer. */
373 /* Frequently used values: keep some adjacent for cache effect. */
374 spinlock_t lock;
375 spinlock_t rx_lock; /* Group with Tx control cache line. */
376 int msg_enable;
377 int chip_id;
378 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
379 unsigned int rx_buf_sz; /* Based on MTU+slack. */
380 struct netdev_desc *last_tx; /* Last Tx descriptor used. */
381 unsigned int cur_tx, dirty_tx;
382 /* These values are keep track of the transceiver/media in use. */
383 unsigned int flowctrl:1;
384 unsigned int default_port:4; /* Last dev->if_port value. */
385 unsigned int an_enable:1;
386 unsigned int speed;
387 struct tasklet_struct rx_tasklet;
388 struct tasklet_struct tx_tasklet;
389 int budget;
390 int cur_task;
391 /* Multicast and receive mode. */
392 spinlock_t mcastlock; /* SMP lock multicast updates. */
393 u16 mcast_filter[4];
394 /* MII transceiver section. */
395 struct mii_if_info mii_if;
396 int mii_preamble_required;
397 unsigned char phys[MII_CNT]; /* MII device addresses, only first one used. */
398 struct pci_dev *pci_dev;
399 void __iomem *base;
400 };
401
402 /* The station address location in the EEPROM. */
403 #define EEPROM_SA_OFFSET 0x10
404 #define DEFAULT_INTR (IntrRxDMADone | IntrPCIErr | \
405 IntrDrvRqst | IntrTxDone | StatsMax | \
406 LinkChange)
407
408 static int change_mtu(struct net_device *dev, int new_mtu);
409 static int eeprom_read(void __iomem *ioaddr, int location);
410 static int mdio_read(struct net_device *dev, int phy_id, int location);
411 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
412 static int mdio_wait_link(struct net_device *dev, int wait);
413 static int netdev_open(struct net_device *dev);
414 static void check_duplex(struct net_device *dev);
415 static void netdev_timer(unsigned long data);
416 static void tx_timeout(struct net_device *dev);
417 static void init_ring(struct net_device *dev);
418 static int start_tx(struct sk_buff *skb, struct net_device *dev);
419 static int reset_tx (struct net_device *dev);
420 static irqreturn_t intr_handler(int irq, void *dev_instance);
421 static void rx_poll(unsigned long data);
422 static void tx_poll(unsigned long data);
423 static void refill_rx (struct net_device *dev);
424 static void netdev_error(struct net_device *dev, int intr_status);
425 static void netdev_error(struct net_device *dev, int intr_status);
426 static void set_rx_mode(struct net_device *dev);
427 static int __set_mac_addr(struct net_device *dev);
428 static struct net_device_stats *get_stats(struct net_device *dev);
429 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
430 static int netdev_close(struct net_device *dev);
431 static const struct ethtool_ops ethtool_ops;
432
433 static void sundance_reset(struct net_device *dev, unsigned long reset_cmd)
434 {
435 struct netdev_private *np = netdev_priv(dev);
436 void __iomem *ioaddr = np->base + ASICCtrl;
437 int countdown;
438
439 /* ST201 documentation states ASICCtrl is a 32bit register */
440 iowrite32 (reset_cmd | ioread32 (ioaddr), ioaddr);
441 /* ST201 documentation states reset can take up to 1 ms */
442 countdown = 10 + 1;
443 while (ioread32 (ioaddr) & (ResetBusy << 16)) {
444 if (--countdown == 0) {
445 printk(KERN_WARNING "%s : reset not completed !!\n", dev->name);
446 break;
447 }
448 udelay(100);
449 }
450 }
451
452 static int __devinit sundance_probe1 (struct pci_dev *pdev,
453 const struct pci_device_id *ent)
454 {
455 struct net_device *dev;
456 struct netdev_private *np;
457 static int card_idx;
458 int chip_idx = ent->driver_data;
459 int irq;
460 int i;
461 void __iomem *ioaddr;
462 u16 mii_ctl;
463 void *ring_space;
464 dma_addr_t ring_dma;
465 #ifdef USE_IO_OPS
466 int bar = 0;
467 #else
468 int bar = 1;
469 #endif
470 int phy, phy_end, phy_idx = 0;
471 DECLARE_MAC_BUF(mac);
472
473 /* when built into the kernel, we only print version if device is found */
474 #ifndef MODULE
475 static int printed_version;
476 if (!printed_version++)
477 printk(version);
478 #endif
479
480 if (pci_enable_device(pdev))
481 return -EIO;
482 pci_set_master(pdev);
483
484 irq = pdev->irq;
485
486 dev = alloc_etherdev(sizeof(*np));
487 if (!dev)
488 return -ENOMEM;
489 SET_NETDEV_DEV(dev, &pdev->dev);
490
491 if (pci_request_regions(pdev, DRV_NAME))
492 goto err_out_netdev;
493
494 ioaddr = pci_iomap(pdev, bar, netdev_io_size);
495 if (!ioaddr)
496 goto err_out_res;
497
498 for (i = 0; i < 3; i++)
499 ((__le16 *)dev->dev_addr)[i] =
500 cpu_to_le16(eeprom_read(ioaddr, i + EEPROM_SA_OFFSET));
501 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
502
503 dev->base_addr = (unsigned long)ioaddr;
504 dev->irq = irq;
505
506 np = netdev_priv(dev);
507 np->base = ioaddr;
508 np->pci_dev = pdev;
509 np->chip_id = chip_idx;
510 np->msg_enable = (1 << debug) - 1;
511 spin_lock_init(&np->lock);
512 tasklet_init(&np->rx_tasklet, rx_poll, (unsigned long)dev);
513 tasklet_init(&np->tx_tasklet, tx_poll, (unsigned long)dev);
514
515 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
516 if (!ring_space)
517 goto err_out_cleardev;
518 np->tx_ring = (struct netdev_desc *)ring_space;
519 np->tx_ring_dma = ring_dma;
520
521 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
522 if (!ring_space)
523 goto err_out_unmap_tx;
524 np->rx_ring = (struct netdev_desc *)ring_space;
525 np->rx_ring_dma = ring_dma;
526
527 np->mii_if.dev = dev;
528 np->mii_if.mdio_read = mdio_read;
529 np->mii_if.mdio_write = mdio_write;
530 np->mii_if.phy_id_mask = 0x1f;
531 np->mii_if.reg_num_mask = 0x1f;
532
533 /* The chip-specific entries in the device structure. */
534 dev->open = &netdev_open;
535 dev->hard_start_xmit = &start_tx;
536 dev->stop = &netdev_close;
537 dev->get_stats = &get_stats;
538 dev->set_multicast_list = &set_rx_mode;
539 dev->do_ioctl = &netdev_ioctl;
540 SET_ETHTOOL_OPS(dev, &ethtool_ops);
541 dev->tx_timeout = &tx_timeout;
542 dev->watchdog_timeo = TX_TIMEOUT;
543 dev->change_mtu = &change_mtu;
544 pci_set_drvdata(pdev, dev);
545
546 i = register_netdev(dev);
547 if (i)
548 goto err_out_unmap_rx;
549
550 printk(KERN_INFO "%s: %s at %p, %s, IRQ %d.\n",
551 dev->name, pci_id_tbl[chip_idx].name, ioaddr,
552 print_mac(mac, dev->dev_addr), irq);
553
554 np->phys[0] = 1; /* Default setting */
555 np->mii_preamble_required++;
556
557 /*
558 * It seems some phys doesn't deal well with address 0 being accessed
559 * first
560 */
561 if (sundance_pci_tbl[np->chip_id].device == 0x0200) {
562 phy = 0;
563 phy_end = 31;
564 } else {
565 phy = 1;
566 phy_end = 32; /* wraps to zero, due to 'phy & 0x1f' */
567 }
568 for (; phy <= phy_end && phy_idx < MII_CNT; phy++) {
569 int phyx = phy & 0x1f;
570 int mii_status = mdio_read(dev, phyx, MII_BMSR);
571 if (mii_status != 0xffff && mii_status != 0x0000) {
572 np->phys[phy_idx++] = phyx;
573 np->mii_if.advertising = mdio_read(dev, phyx, MII_ADVERTISE);
574 if ((mii_status & 0x0040) == 0)
575 np->mii_preamble_required++;
576 printk(KERN_INFO "%s: MII PHY found at address %d, status "
577 "0x%4.4x advertising %4.4x.\n",
578 dev->name, phyx, mii_status, np->mii_if.advertising);
579 }
580 }
581 np->mii_preamble_required--;
582
583 if (phy_idx == 0) {
584 printk(KERN_INFO "%s: No MII transceiver found, aborting. ASIC status %x\n",
585 dev->name, ioread32(ioaddr + ASICCtrl));
586 goto err_out_unregister;
587 }
588
589 np->mii_if.phy_id = np->phys[0];
590
591 /* Parse override configuration */
592 np->an_enable = 1;
593 if (card_idx < MAX_UNITS) {
594 if (media[card_idx] != NULL) {
595 np->an_enable = 0;
596 if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
597 strcmp (media[card_idx], "4") == 0) {
598 np->speed = 100;
599 np->mii_if.full_duplex = 1;
600 } else if (strcmp (media[card_idx], "100mbps_hd") == 0
601 || strcmp (media[card_idx], "3") == 0) {
602 np->speed = 100;
603 np->mii_if.full_duplex = 0;
604 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
605 strcmp (media[card_idx], "2") == 0) {
606 np->speed = 10;
607 np->mii_if.full_duplex = 1;
608 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
609 strcmp (media[card_idx], "1") == 0) {
610 np->speed = 10;
611 np->mii_if.full_duplex = 0;
612 } else {
613 np->an_enable = 1;
614 }
615 }
616 if (flowctrl == 1)
617 np->flowctrl = 1;
618 }
619
620 /* Fibre PHY? */
621 if (ioread32 (ioaddr + ASICCtrl) & 0x80) {
622 /* Default 100Mbps Full */
623 if (np->an_enable) {
624 np->speed = 100;
625 np->mii_if.full_duplex = 1;
626 np->an_enable = 0;
627 }
628 }
629 /* Reset PHY */
630 mdio_write (dev, np->phys[0], MII_BMCR, BMCR_RESET);
631 mdelay (300);
632 /* If flow control enabled, we need to advertise it.*/
633 if (np->flowctrl)
634 mdio_write (dev, np->phys[0], MII_ADVERTISE, np->mii_if.advertising | 0x0400);
635 mdio_write (dev, np->phys[0], MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART);
636 /* Force media type */
637 if (!np->an_enable) {
638 mii_ctl = 0;
639 mii_ctl |= (np->speed == 100) ? BMCR_SPEED100 : 0;
640 mii_ctl |= (np->mii_if.full_duplex) ? BMCR_FULLDPLX : 0;
641 mdio_write (dev, np->phys[0], MII_BMCR, mii_ctl);
642 printk (KERN_INFO "Override speed=%d, %s duplex\n",
643 np->speed, np->mii_if.full_duplex ? "Full" : "Half");
644
645 }
646
647 /* Perhaps move the reset here? */
648 /* Reset the chip to erase previous misconfiguration. */
649 if (netif_msg_hw(np))
650 printk("ASIC Control is %x.\n", ioread32(ioaddr + ASICCtrl));
651 sundance_reset(dev, 0x00ff << 16);
652 if (netif_msg_hw(np))
653 printk("ASIC Control is now %x.\n", ioread32(ioaddr + ASICCtrl));
654
655 card_idx++;
656 return 0;
657
658 err_out_unregister:
659 unregister_netdev(dev);
660 err_out_unmap_rx:
661 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
662 err_out_unmap_tx:
663 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
664 err_out_cleardev:
665 pci_set_drvdata(pdev, NULL);
666 pci_iounmap(pdev, ioaddr);
667 err_out_res:
668 pci_release_regions(pdev);
669 err_out_netdev:
670 free_netdev (dev);
671 return -ENODEV;
672 }
673
674 static int change_mtu(struct net_device *dev, int new_mtu)
675 {
676 if ((new_mtu < 68) || (new_mtu > 8191)) /* Set by RxDMAFrameLen */
677 return -EINVAL;
678 if (netif_running(dev))
679 return -EBUSY;
680 dev->mtu = new_mtu;
681 return 0;
682 }
683
684 #define eeprom_delay(ee_addr) ioread32(ee_addr)
685 /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. */
686 static int __devinit eeprom_read(void __iomem *ioaddr, int location)
687 {
688 int boguscnt = 10000; /* Typical 1900 ticks. */
689 iowrite16(0x0200 | (location & 0xff), ioaddr + EECtrl);
690 do {
691 eeprom_delay(ioaddr + EECtrl);
692 if (! (ioread16(ioaddr + EECtrl) & 0x8000)) {
693 return ioread16(ioaddr + EEData);
694 }
695 } while (--boguscnt > 0);
696 return 0;
697 }
698
699 /* MII transceiver control section.
700 Read and write the MII registers using software-generated serial
701 MDIO protocol. See the MII specifications or DP83840A data sheet
702 for details.
703
704 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
705 met by back-to-back 33Mhz PCI cycles. */
706 #define mdio_delay() ioread8(mdio_addr)
707
708 enum mii_reg_bits {
709 MDIO_ShiftClk=0x0001, MDIO_Data=0x0002, MDIO_EnbOutput=0x0004,
710 };
711 #define MDIO_EnbIn (0)
712 #define MDIO_WRITE0 (MDIO_EnbOutput)
713 #define MDIO_WRITE1 (MDIO_Data | MDIO_EnbOutput)
714
715 /* Generate the preamble required for initial synchronization and
716 a few older transceivers. */
717 static void mdio_sync(void __iomem *mdio_addr)
718 {
719 int bits = 32;
720
721 /* Establish sync by sending at least 32 logic ones. */
722 while (--bits >= 0) {
723 iowrite8(MDIO_WRITE1, mdio_addr);
724 mdio_delay();
725 iowrite8(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr);
726 mdio_delay();
727 }
728 }
729
730 static int mdio_read(struct net_device *dev, int phy_id, int location)
731 {
732 struct netdev_private *np = netdev_priv(dev);
733 void __iomem *mdio_addr = np->base + MIICtrl;
734 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
735 int i, retval = 0;
736
737 if (np->mii_preamble_required)
738 mdio_sync(mdio_addr);
739
740 /* Shift the read command bits out. */
741 for (i = 15; i >= 0; i--) {
742 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
743
744 iowrite8(dataval, mdio_addr);
745 mdio_delay();
746 iowrite8(dataval | MDIO_ShiftClk, mdio_addr);
747 mdio_delay();
748 }
749 /* Read the two transition, 16 data, and wire-idle bits. */
750 for (i = 19; i > 0; i--) {
751 iowrite8(MDIO_EnbIn, mdio_addr);
752 mdio_delay();
753 retval = (retval << 1) | ((ioread8(mdio_addr) & MDIO_Data) ? 1 : 0);
754 iowrite8(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
755 mdio_delay();
756 }
757 return (retval>>1) & 0xffff;
758 }
759
760 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
761 {
762 struct netdev_private *np = netdev_priv(dev);
763 void __iomem *mdio_addr = np->base + MIICtrl;
764 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value;
765 int i;
766
767 if (np->mii_preamble_required)
768 mdio_sync(mdio_addr);
769
770 /* Shift the command bits out. */
771 for (i = 31; i >= 0; i--) {
772 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
773
774 iowrite8(dataval, mdio_addr);
775 mdio_delay();
776 iowrite8(dataval | MDIO_ShiftClk, mdio_addr);
777 mdio_delay();
778 }
779 /* Clear out extra bits. */
780 for (i = 2; i > 0; i--) {
781 iowrite8(MDIO_EnbIn, mdio_addr);
782 mdio_delay();
783 iowrite8(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
784 mdio_delay();
785 }
786 return;
787 }
788
789 static int mdio_wait_link(struct net_device *dev, int wait)
790 {
791 int bmsr;
792 int phy_id;
793 struct netdev_private *np;
794
795 np = netdev_priv(dev);
796 phy_id = np->phys[0];
797
798 do {
799 bmsr = mdio_read(dev, phy_id, MII_BMSR);
800 if (bmsr & 0x0004)
801 return 0;
802 mdelay(1);
803 } while (--wait > 0);
804 return -1;
805 }
806
807 static int netdev_open(struct net_device *dev)
808 {
809 struct netdev_private *np = netdev_priv(dev);
810 void __iomem *ioaddr = np->base;
811 unsigned long flags;
812 int i;
813
814 /* Do we need to reset the chip??? */
815
816 i = request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev);
817 if (i)
818 return i;
819
820 if (netif_msg_ifup(np))
821 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
822 dev->name, dev->irq);
823 init_ring(dev);
824
825 iowrite32(np->rx_ring_dma, ioaddr + RxListPtr);
826 /* The Tx list pointer is written as packets are queued. */
827
828 /* Initialize other registers. */
829 __set_mac_addr(dev);
830 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
831 iowrite16(dev->mtu + 18, ioaddr + MaxFrameSize);
832 #else
833 iowrite16(dev->mtu + 14, ioaddr + MaxFrameSize);
834 #endif
835 if (dev->mtu > 2047)
836 iowrite32(ioread32(ioaddr + ASICCtrl) | 0x0C, ioaddr + ASICCtrl);
837
838 /* Configure the PCI bus bursts and FIFO thresholds. */
839
840 if (dev->if_port == 0)
841 dev->if_port = np->default_port;
842
843 spin_lock_init(&np->mcastlock);
844
845 set_rx_mode(dev);
846 iowrite16(0, ioaddr + IntrEnable);
847 iowrite16(0, ioaddr + DownCounter);
848 /* Set the chip to poll every N*320nsec. */
849 iowrite8(100, ioaddr + RxDMAPollPeriod);
850 iowrite8(127, ioaddr + TxDMAPollPeriod);
851 /* Fix DFE-580TX packet drop issue */
852 if (np->pci_dev->revision >= 0x14)
853 iowrite8(0x01, ioaddr + DebugCtrl1);
854 netif_start_queue(dev);
855
856 spin_lock_irqsave(&np->lock, flags);
857 reset_tx(dev);
858 spin_unlock_irqrestore(&np->lock, flags);
859
860 iowrite16 (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1);
861
862 if (netif_msg_ifup(np))
863 printk(KERN_DEBUG "%s: Done netdev_open(), status: Rx %x Tx %x "
864 "MAC Control %x, %4.4x %4.4x.\n",
865 dev->name, ioread32(ioaddr + RxStatus), ioread8(ioaddr + TxStatus),
866 ioread32(ioaddr + MACCtrl0),
867 ioread16(ioaddr + MACCtrl1), ioread16(ioaddr + MACCtrl0));
868
869 /* Set the timer to check for link beat. */
870 init_timer(&np->timer);
871 np->timer.expires = jiffies + 3*HZ;
872 np->timer.data = (unsigned long)dev;
873 np->timer.function = &netdev_timer; /* timer handler */
874 add_timer(&np->timer);
875
876 /* Enable interrupts by setting the interrupt mask. */
877 iowrite16(DEFAULT_INTR, ioaddr + IntrEnable);
878
879 return 0;
880 }
881
882 static void check_duplex(struct net_device *dev)
883 {
884 struct netdev_private *np = netdev_priv(dev);
885 void __iomem *ioaddr = np->base;
886 int mii_lpa = mdio_read(dev, np->phys[0], MII_LPA);
887 int negotiated = mii_lpa & np->mii_if.advertising;
888 int duplex;
889
890 /* Force media */
891 if (!np->an_enable || mii_lpa == 0xffff) {
892 if (np->mii_if.full_duplex)
893 iowrite16 (ioread16 (ioaddr + MACCtrl0) | EnbFullDuplex,
894 ioaddr + MACCtrl0);
895 return;
896 }
897
898 /* Autonegotiation */
899 duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040;
900 if (np->mii_if.full_duplex != duplex) {
901 np->mii_if.full_duplex = duplex;
902 if (netif_msg_link(np))
903 printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d "
904 "negotiated capability %4.4x.\n", dev->name,
905 duplex ? "full" : "half", np->phys[0], negotiated);
906 iowrite16(ioread16(ioaddr + MACCtrl0) | duplex ? 0x20 : 0, ioaddr + MACCtrl0);
907 }
908 }
909
910 static void netdev_timer(unsigned long data)
911 {
912 struct net_device *dev = (struct net_device *)data;
913 struct netdev_private *np = netdev_priv(dev);
914 void __iomem *ioaddr = np->base;
915 int next_tick = 10*HZ;
916
917 if (netif_msg_timer(np)) {
918 printk(KERN_DEBUG "%s: Media selection timer tick, intr status %4.4x, "
919 "Tx %x Rx %x.\n",
920 dev->name, ioread16(ioaddr + IntrEnable),
921 ioread8(ioaddr + TxStatus), ioread32(ioaddr + RxStatus));
922 }
923 check_duplex(dev);
924 np->timer.expires = jiffies + next_tick;
925 add_timer(&np->timer);
926 }
927
928 static void tx_timeout(struct net_device *dev)
929 {
930 struct netdev_private *np = netdev_priv(dev);
931 void __iomem *ioaddr = np->base;
932 unsigned long flag;
933
934 netif_stop_queue(dev);
935 tasklet_disable(&np->tx_tasklet);
936 iowrite16(0, ioaddr + IntrEnable);
937 printk(KERN_WARNING "%s: Transmit timed out, TxStatus %2.2x "
938 "TxFrameId %2.2x,"
939 " resetting...\n", dev->name, ioread8(ioaddr + TxStatus),
940 ioread8(ioaddr + TxFrameId));
941
942 {
943 int i;
944 for (i=0; i<TX_RING_SIZE; i++) {
945 printk(KERN_DEBUG "%02x %08llx %08x %08x(%02x) %08x %08x\n", i,
946 (unsigned long long)(np->tx_ring_dma + i*sizeof(*np->tx_ring)),
947 le32_to_cpu(np->tx_ring[i].next_desc),
948 le32_to_cpu(np->tx_ring[i].status),
949 (le32_to_cpu(np->tx_ring[i].status) >> 2) & 0xff,
950 le32_to_cpu(np->tx_ring[i].frag[0].addr),
951 le32_to_cpu(np->tx_ring[i].frag[0].length));
952 }
953 printk(KERN_DEBUG "TxListPtr=%08x netif_queue_stopped=%d\n",
954 ioread32(np->base + TxListPtr),
955 netif_queue_stopped(dev));
956 printk(KERN_DEBUG "cur_tx=%d(%02x) dirty_tx=%d(%02x)\n",
957 np->cur_tx, np->cur_tx % TX_RING_SIZE,
958 np->dirty_tx, np->dirty_tx % TX_RING_SIZE);
959 printk(KERN_DEBUG "cur_rx=%d dirty_rx=%d\n", np->cur_rx, np->dirty_rx);
960 printk(KERN_DEBUG "cur_task=%d\n", np->cur_task);
961 }
962 spin_lock_irqsave(&np->lock, flag);
963
964 /* Stop and restart the chip's Tx processes . */
965 reset_tx(dev);
966 spin_unlock_irqrestore(&np->lock, flag);
967
968 dev->if_port = 0;
969
970 dev->trans_start = jiffies;
971 np->stats.tx_errors++;
972 if (np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
973 netif_wake_queue(dev);
974 }
975 iowrite16(DEFAULT_INTR, ioaddr + IntrEnable);
976 tasklet_enable(&np->tx_tasklet);
977 }
978
979
980 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
981 static void init_ring(struct net_device *dev)
982 {
983 struct netdev_private *np = netdev_priv(dev);
984 int i;
985
986 np->cur_rx = np->cur_tx = 0;
987 np->dirty_rx = np->dirty_tx = 0;
988 np->cur_task = 0;
989
990 np->rx_buf_sz = (dev->mtu <= 1520 ? PKT_BUF_SZ : dev->mtu + 16);
991
992 /* Initialize all Rx descriptors. */
993 for (i = 0; i < RX_RING_SIZE; i++) {
994 np->rx_ring[i].next_desc = cpu_to_le32(np->rx_ring_dma +
995 ((i+1)%RX_RING_SIZE)*sizeof(*np->rx_ring));
996 np->rx_ring[i].status = 0;
997 np->rx_ring[i].frag[0].length = 0;
998 np->rx_skbuff[i] = NULL;
999 }
1000
1001 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1002 for (i = 0; i < RX_RING_SIZE; i++) {
1003 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
1004 np->rx_skbuff[i] = skb;
1005 if (skb == NULL)
1006 break;
1007 skb->dev = dev; /* Mark as being used by this device. */
1008 skb_reserve(skb, 2); /* 16 byte align the IP header. */
1009 np->rx_ring[i].frag[0].addr = cpu_to_le32(
1010 pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz,
1011 PCI_DMA_FROMDEVICE));
1012 np->rx_ring[i].frag[0].length = cpu_to_le32(np->rx_buf_sz | LastFrag);
1013 }
1014 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1015
1016 for (i = 0; i < TX_RING_SIZE; i++) {
1017 np->tx_skbuff[i] = NULL;
1018 np->tx_ring[i].status = 0;
1019 }
1020 return;
1021 }
1022
1023 static void tx_poll (unsigned long data)
1024 {
1025 struct net_device *dev = (struct net_device *)data;
1026 struct netdev_private *np = netdev_priv(dev);
1027 unsigned head = np->cur_task % TX_RING_SIZE;
1028 struct netdev_desc *txdesc =
1029 &np->tx_ring[(np->cur_tx - 1) % TX_RING_SIZE];
1030
1031 /* Chain the next pointer */
1032 for (; np->cur_tx - np->cur_task > 0; np->cur_task++) {
1033 int entry = np->cur_task % TX_RING_SIZE;
1034 txdesc = &np->tx_ring[entry];
1035 if (np->last_tx) {
1036 np->last_tx->next_desc = cpu_to_le32(np->tx_ring_dma +
1037 entry*sizeof(struct netdev_desc));
1038 }
1039 np->last_tx = txdesc;
1040 }
1041 /* Indicate the latest descriptor of tx ring */
1042 txdesc->status |= cpu_to_le32(DescIntrOnTx);
1043
1044 if (ioread32 (np->base + TxListPtr) == 0)
1045 iowrite32 (np->tx_ring_dma + head * sizeof(struct netdev_desc),
1046 np->base + TxListPtr);
1047 return;
1048 }
1049
1050 static int
1051 start_tx (struct sk_buff *skb, struct net_device *dev)
1052 {
1053 struct netdev_private *np = netdev_priv(dev);
1054 struct netdev_desc *txdesc;
1055 unsigned entry;
1056
1057 /* Calculate the next Tx descriptor entry. */
1058 entry = np->cur_tx % TX_RING_SIZE;
1059 np->tx_skbuff[entry] = skb;
1060 txdesc = &np->tx_ring[entry];
1061
1062 txdesc->next_desc = 0;
1063 txdesc->status = cpu_to_le32 ((entry << 2) | DisableAlign);
1064 txdesc->frag[0].addr = cpu_to_le32 (pci_map_single (np->pci_dev, skb->data,
1065 skb->len,
1066 PCI_DMA_TODEVICE));
1067 txdesc->frag[0].length = cpu_to_le32 (skb->len | LastFrag);
1068
1069 /* Increment cur_tx before tasklet_schedule() */
1070 np->cur_tx++;
1071 mb();
1072 /* Schedule a tx_poll() task */
1073 tasklet_schedule(&np->tx_tasklet);
1074
1075 /* On some architectures: explicitly flush cache lines here. */
1076 if (np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 1
1077 && !netif_queue_stopped(dev)) {
1078 /* do nothing */
1079 } else {
1080 netif_stop_queue (dev);
1081 }
1082 dev->trans_start = jiffies;
1083 if (netif_msg_tx_queued(np)) {
1084 printk (KERN_DEBUG
1085 "%s: Transmit frame #%d queued in slot %d.\n",
1086 dev->name, np->cur_tx, entry);
1087 }
1088 return 0;
1089 }
1090
1091 /* Reset hardware tx and free all of tx buffers */
1092 static int
1093 reset_tx (struct net_device *dev)
1094 {
1095 struct netdev_private *np = netdev_priv(dev);
1096 void __iomem *ioaddr = np->base;
1097 struct sk_buff *skb;
1098 int i;
1099 int irq = in_interrupt();
1100
1101 /* Reset tx logic, TxListPtr will be cleaned */
1102 iowrite16 (TxDisable, ioaddr + MACCtrl1);
1103 sundance_reset(dev, (NetworkReset|FIFOReset|DMAReset|TxReset) << 16);
1104
1105 /* free all tx skbuff */
1106 for (i = 0; i < TX_RING_SIZE; i++) {
1107 np->tx_ring[i].next_desc = 0;
1108
1109 skb = np->tx_skbuff[i];
1110 if (skb) {
1111 pci_unmap_single(np->pci_dev,
1112 le32_to_cpu(np->tx_ring[i].frag[0].addr),
1113 skb->len, PCI_DMA_TODEVICE);
1114 if (irq)
1115 dev_kfree_skb_irq (skb);
1116 else
1117 dev_kfree_skb (skb);
1118 np->tx_skbuff[i] = NULL;
1119 np->stats.tx_dropped++;
1120 }
1121 }
1122 np->cur_tx = np->dirty_tx = 0;
1123 np->cur_task = 0;
1124
1125 np->last_tx = NULL;
1126 iowrite8(127, ioaddr + TxDMAPollPeriod);
1127
1128 iowrite16 (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1);
1129 return 0;
1130 }
1131
1132 /* The interrupt handler cleans up after the Tx thread,
1133 and schedule a Rx thread work */
1134 static irqreturn_t intr_handler(int irq, void *dev_instance)
1135 {
1136 struct net_device *dev = (struct net_device *)dev_instance;
1137 struct netdev_private *np = netdev_priv(dev);
1138 void __iomem *ioaddr = np->base;
1139 int hw_frame_id;
1140 int tx_cnt;
1141 int tx_status;
1142 int handled = 0;
1143 int i;
1144
1145
1146 do {
1147 int intr_status = ioread16(ioaddr + IntrStatus);
1148 iowrite16(intr_status, ioaddr + IntrStatus);
1149
1150 if (netif_msg_intr(np))
1151 printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n",
1152 dev->name, intr_status);
1153
1154 if (!(intr_status & DEFAULT_INTR))
1155 break;
1156
1157 handled = 1;
1158
1159 if (intr_status & (IntrRxDMADone)) {
1160 iowrite16(DEFAULT_INTR & ~(IntrRxDone|IntrRxDMADone),
1161 ioaddr + IntrEnable);
1162 if (np->budget < 0)
1163 np->budget = RX_BUDGET;
1164 tasklet_schedule(&np->rx_tasklet);
1165 }
1166 if (intr_status & (IntrTxDone | IntrDrvRqst)) {
1167 tx_status = ioread16 (ioaddr + TxStatus);
1168 for (tx_cnt=32; tx_status & 0x80; --tx_cnt) {
1169 if (netif_msg_tx_done(np))
1170 printk
1171 ("%s: Transmit status is %2.2x.\n",
1172 dev->name, tx_status);
1173 if (tx_status & 0x1e) {
1174 if (netif_msg_tx_err(np))
1175 printk("%s: Transmit error status %4.4x.\n",
1176 dev->name, tx_status);
1177 np->stats.tx_errors++;
1178 if (tx_status & 0x10)
1179 np->stats.tx_fifo_errors++;
1180 if (tx_status & 0x08)
1181 np->stats.collisions++;
1182 if (tx_status & 0x04)
1183 np->stats.tx_fifo_errors++;
1184 if (tx_status & 0x02)
1185 np->stats.tx_window_errors++;
1186
1187 /*
1188 ** This reset has been verified on
1189 ** DFE-580TX boards ! phdm@macqel.be.
1190 */
1191 if (tx_status & 0x10) { /* TxUnderrun */
1192 /* Restart Tx FIFO and transmitter */
1193 sundance_reset(dev, (NetworkReset|FIFOReset|TxReset) << 16);
1194 /* No need to reset the Tx pointer here */
1195 }
1196 /* Restart the Tx. Need to make sure tx enabled */
1197 i = 10;
1198 do {
1199 iowrite16(ioread16(ioaddr + MACCtrl1) | TxEnable, ioaddr + MACCtrl1);
1200 if (ioread16(ioaddr + MACCtrl1) & TxEnabled)
1201 break;
1202 mdelay(1);
1203 } while (--i);
1204 }
1205 /* Yup, this is a documentation bug. It cost me *hours*. */
1206 iowrite16 (0, ioaddr + TxStatus);
1207 if (tx_cnt < 0) {
1208 iowrite32(5000, ioaddr + DownCounter);
1209 break;
1210 }
1211 tx_status = ioread16 (ioaddr + TxStatus);
1212 }
1213 hw_frame_id = (tx_status >> 8) & 0xff;
1214 } else {
1215 hw_frame_id = ioread8(ioaddr + TxFrameId);
1216 }
1217
1218 if (np->pci_dev->revision >= 0x14) {
1219 spin_lock(&np->lock);
1220 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
1221 int entry = np->dirty_tx % TX_RING_SIZE;
1222 struct sk_buff *skb;
1223 int sw_frame_id;
1224 sw_frame_id = (le32_to_cpu(
1225 np->tx_ring[entry].status) >> 2) & 0xff;
1226 if (sw_frame_id == hw_frame_id &&
1227 !(le32_to_cpu(np->tx_ring[entry].status)
1228 & 0x00010000))
1229 break;
1230 if (sw_frame_id == (hw_frame_id + 1) %
1231 TX_RING_SIZE)
1232 break;
1233 skb = np->tx_skbuff[entry];
1234 /* Free the original skb. */
1235 pci_unmap_single(np->pci_dev,
1236 le32_to_cpu(np->tx_ring[entry].frag[0].addr),
1237 skb->len, PCI_DMA_TODEVICE);
1238 dev_kfree_skb_irq (np->tx_skbuff[entry]);
1239 np->tx_skbuff[entry] = NULL;
1240 np->tx_ring[entry].frag[0].addr = 0;
1241 np->tx_ring[entry].frag[0].length = 0;
1242 }
1243 spin_unlock(&np->lock);
1244 } else {
1245 spin_lock(&np->lock);
1246 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
1247 int entry = np->dirty_tx % TX_RING_SIZE;
1248 struct sk_buff *skb;
1249 if (!(le32_to_cpu(np->tx_ring[entry].status)
1250 & 0x00010000))
1251 break;
1252 skb = np->tx_skbuff[entry];
1253 /* Free the original skb. */
1254 pci_unmap_single(np->pci_dev,
1255 le32_to_cpu(np->tx_ring[entry].frag[0].addr),
1256 skb->len, PCI_DMA_TODEVICE);
1257 dev_kfree_skb_irq (np->tx_skbuff[entry]);
1258 np->tx_skbuff[entry] = NULL;
1259 np->tx_ring[entry].frag[0].addr = 0;
1260 np->tx_ring[entry].frag[0].length = 0;
1261 }
1262 spin_unlock(&np->lock);
1263 }
1264
1265 if (netif_queue_stopped(dev) &&
1266 np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
1267 /* The ring is no longer full, clear busy flag. */
1268 netif_wake_queue (dev);
1269 }
1270 /* Abnormal error summary/uncommon events handlers. */
1271 if (intr_status & (IntrPCIErr | LinkChange | StatsMax))
1272 netdev_error(dev, intr_status);
1273 } while (0);
1274 if (netif_msg_intr(np))
1275 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1276 dev->name, ioread16(ioaddr + IntrStatus));
1277 return IRQ_RETVAL(handled);
1278 }
1279
1280 static void rx_poll(unsigned long data)
1281 {
1282 struct net_device *dev = (struct net_device *)data;
1283 struct netdev_private *np = netdev_priv(dev);
1284 int entry = np->cur_rx % RX_RING_SIZE;
1285 int boguscnt = np->budget;
1286 void __iomem *ioaddr = np->base;
1287 int received = 0;
1288
1289 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1290 while (1) {
1291 struct netdev_desc *desc = &(np->rx_ring[entry]);
1292 u32 frame_status = le32_to_cpu(desc->status);
1293 int pkt_len;
1294
1295 if (--boguscnt < 0) {
1296 goto not_done;
1297 }
1298 if (!(frame_status & DescOwn))
1299 break;
1300 pkt_len = frame_status & 0x1fff; /* Chip omits the CRC. */
1301 if (netif_msg_rx_status(np))
1302 printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n",
1303 frame_status);
1304 if (frame_status & 0x001f4000) {
1305 /* There was a error. */
1306 if (netif_msg_rx_err(np))
1307 printk(KERN_DEBUG " netdev_rx() Rx error was %8.8x.\n",
1308 frame_status);
1309 np->stats.rx_errors++;
1310 if (frame_status & 0x00100000) np->stats.rx_length_errors++;
1311 if (frame_status & 0x00010000) np->stats.rx_fifo_errors++;
1312 if (frame_status & 0x00060000) np->stats.rx_frame_errors++;
1313 if (frame_status & 0x00080000) np->stats.rx_crc_errors++;
1314 if (frame_status & 0x00100000) {
1315 printk(KERN_WARNING "%s: Oversized Ethernet frame,"
1316 " status %8.8x.\n",
1317 dev->name, frame_status);
1318 }
1319 } else {
1320 struct sk_buff *skb;
1321 #ifndef final_version
1322 if (netif_msg_rx_status(np))
1323 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d"
1324 ", bogus_cnt %d.\n",
1325 pkt_len, boguscnt);
1326 #endif
1327 /* Check if the packet is long enough to accept without copying
1328 to a minimally-sized skbuff. */
1329 if (pkt_len < rx_copybreak
1330 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1331 skb_reserve(skb, 2); /* 16 byte align the IP header */
1332 pci_dma_sync_single_for_cpu(np->pci_dev,
1333 le32_to_cpu(desc->frag[0].addr),
1334 np->rx_buf_sz,
1335 PCI_DMA_FROMDEVICE);
1336
1337 skb_copy_to_linear_data(skb, np->rx_skbuff[entry]->data, pkt_len);
1338 pci_dma_sync_single_for_device(np->pci_dev,
1339 le32_to_cpu(desc->frag[0].addr),
1340 np->rx_buf_sz,
1341 PCI_DMA_FROMDEVICE);
1342 skb_put(skb, pkt_len);
1343 } else {
1344 pci_unmap_single(np->pci_dev,
1345 le32_to_cpu(desc->frag[0].addr),
1346 np->rx_buf_sz,
1347 PCI_DMA_FROMDEVICE);
1348 skb_put(skb = np->rx_skbuff[entry], pkt_len);
1349 np->rx_skbuff[entry] = NULL;
1350 }
1351 skb->protocol = eth_type_trans(skb, dev);
1352 /* Note: checksum -> skb->ip_summed = CHECKSUM_UNNECESSARY; */
1353 netif_rx(skb);
1354 dev->last_rx = jiffies;
1355 }
1356 entry = (entry + 1) % RX_RING_SIZE;
1357 received++;
1358 }
1359 np->cur_rx = entry;
1360 refill_rx (dev);
1361 np->budget -= received;
1362 iowrite16(DEFAULT_INTR, ioaddr + IntrEnable);
1363 return;
1364
1365 not_done:
1366 np->cur_rx = entry;
1367 refill_rx (dev);
1368 if (!received)
1369 received = 1;
1370 np->budget -= received;
1371 if (np->budget <= 0)
1372 np->budget = RX_BUDGET;
1373 tasklet_schedule(&np->rx_tasklet);
1374 return;
1375 }
1376
1377 static void refill_rx (struct net_device *dev)
1378 {
1379 struct netdev_private *np = netdev_priv(dev);
1380 int entry;
1381 int cnt = 0;
1382
1383 /* Refill the Rx ring buffers. */
1384 for (;(np->cur_rx - np->dirty_rx + RX_RING_SIZE) % RX_RING_SIZE > 0;
1385 np->dirty_rx = (np->dirty_rx + 1) % RX_RING_SIZE) {
1386 struct sk_buff *skb;
1387 entry = np->dirty_rx % RX_RING_SIZE;
1388 if (np->rx_skbuff[entry] == NULL) {
1389 skb = dev_alloc_skb(np->rx_buf_sz);
1390 np->rx_skbuff[entry] = skb;
1391 if (skb == NULL)
1392 break; /* Better luck next round. */
1393 skb->dev = dev; /* Mark as being used by this device. */
1394 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1395 np->rx_ring[entry].frag[0].addr = cpu_to_le32(
1396 pci_map_single(np->pci_dev, skb->data,
1397 np->rx_buf_sz, PCI_DMA_FROMDEVICE));
1398 }
1399 /* Perhaps we need not reset this field. */
1400 np->rx_ring[entry].frag[0].length =
1401 cpu_to_le32(np->rx_buf_sz | LastFrag);
1402 np->rx_ring[entry].status = 0;
1403 cnt++;
1404 }
1405 return;
1406 }
1407 static void netdev_error(struct net_device *dev, int intr_status)
1408 {
1409 struct netdev_private *np = netdev_priv(dev);
1410 void __iomem *ioaddr = np->base;
1411 u16 mii_ctl, mii_advertise, mii_lpa;
1412 int speed;
1413
1414 if (intr_status & LinkChange) {
1415 if (mdio_wait_link(dev, 10) == 0) {
1416 printk(KERN_INFO "%s: Link up\n", dev->name);
1417 if (np->an_enable) {
1418 mii_advertise = mdio_read(dev, np->phys[0],
1419 MII_ADVERTISE);
1420 mii_lpa = mdio_read(dev, np->phys[0], MII_LPA);
1421 mii_advertise &= mii_lpa;
1422 printk(KERN_INFO "%s: Link changed: ",
1423 dev->name);
1424 if (mii_advertise & ADVERTISE_100FULL) {
1425 np->speed = 100;
1426 printk("100Mbps, full duplex\n");
1427 } else if (mii_advertise & ADVERTISE_100HALF) {
1428 np->speed = 100;
1429 printk("100Mbps, half duplex\n");
1430 } else if (mii_advertise & ADVERTISE_10FULL) {
1431 np->speed = 10;
1432 printk("10Mbps, full duplex\n");
1433 } else if (mii_advertise & ADVERTISE_10HALF) {
1434 np->speed = 10;
1435 printk("10Mbps, half duplex\n");
1436 } else
1437 printk("\n");
1438
1439 } else {
1440 mii_ctl = mdio_read(dev, np->phys[0], MII_BMCR);
1441 speed = (mii_ctl & BMCR_SPEED100) ? 100 : 10;
1442 np->speed = speed;
1443 printk(KERN_INFO "%s: Link changed: %dMbps ,",
1444 dev->name, speed);
1445 printk("%s duplex.\n",
1446 (mii_ctl & BMCR_FULLDPLX) ?
1447 "full" : "half");
1448 }
1449 check_duplex(dev);
1450 if (np->flowctrl && np->mii_if.full_duplex) {
1451 iowrite16(ioread16(ioaddr + MulticastFilter1+2) | 0x0200,
1452 ioaddr + MulticastFilter1+2);
1453 iowrite16(ioread16(ioaddr + MACCtrl0) | EnbFlowCtrl,
1454 ioaddr + MACCtrl0);
1455 }
1456 netif_carrier_on(dev);
1457 } else {
1458 printk(KERN_INFO "%s: Link down\n", dev->name);
1459 netif_carrier_off(dev);
1460 }
1461 }
1462 if (intr_status & StatsMax) {
1463 get_stats(dev);
1464 }
1465 if (intr_status & IntrPCIErr) {
1466 printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n",
1467 dev->name, intr_status);
1468 /* We must do a global reset of DMA to continue. */
1469 }
1470 }
1471
1472 static struct net_device_stats *get_stats(struct net_device *dev)
1473 {
1474 struct netdev_private *np = netdev_priv(dev);
1475 void __iomem *ioaddr = np->base;
1476 int i;
1477
1478 /* We should lock this segment of code for SMP eventually, although
1479 the vulnerability window is very small and statistics are
1480 non-critical. */
1481 /* The chip only need report frame silently dropped. */
1482 np->stats.rx_missed_errors += ioread8(ioaddr + RxMissed);
1483 np->stats.tx_packets += ioread16(ioaddr + TxFramesOK);
1484 np->stats.rx_packets += ioread16(ioaddr + RxFramesOK);
1485 np->stats.collisions += ioread8(ioaddr + StatsLateColl);
1486 np->stats.collisions += ioread8(ioaddr + StatsMultiColl);
1487 np->stats.collisions += ioread8(ioaddr + StatsOneColl);
1488 np->stats.tx_carrier_errors += ioread8(ioaddr + StatsCarrierError);
1489 ioread8(ioaddr + StatsTxDefer);
1490 for (i = StatsTxDefer; i <= StatsMcastRx; i++)
1491 ioread8(ioaddr + i);
1492 np->stats.tx_bytes += ioread16(ioaddr + TxOctetsLow);
1493 np->stats.tx_bytes += ioread16(ioaddr + TxOctetsHigh) << 16;
1494 np->stats.rx_bytes += ioread16(ioaddr + RxOctetsLow);
1495 np->stats.rx_bytes += ioread16(ioaddr + RxOctetsHigh) << 16;
1496
1497 return &np->stats;
1498 }
1499
1500 static void set_rx_mode(struct net_device *dev)
1501 {
1502 struct netdev_private *np = netdev_priv(dev);
1503 void __iomem *ioaddr = np->base;
1504 u16 mc_filter[4]; /* Multicast hash filter */
1505 u32 rx_mode;
1506 int i;
1507
1508 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1509 memset(mc_filter, 0xff, sizeof(mc_filter));
1510 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptAll | AcceptMyPhys;
1511 } else if ((dev->mc_count > multicast_filter_limit)
1512 || (dev->flags & IFF_ALLMULTI)) {
1513 /* Too many to match, or accept all multicasts. */
1514 memset(mc_filter, 0xff, sizeof(mc_filter));
1515 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1516 } else if (dev->mc_count) {
1517 struct dev_mc_list *mclist;
1518 int bit;
1519 int index;
1520 int crc;
1521 memset (mc_filter, 0, sizeof (mc_filter));
1522 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1523 i++, mclist = mclist->next) {
1524 crc = ether_crc_le (ETH_ALEN, mclist->dmi_addr);
1525 for (index=0, bit=0; bit < 6; bit++, crc <<= 1)
1526 if (crc & 0x80000000) index |= 1 << bit;
1527 mc_filter[index/16] |= (1 << (index % 16));
1528 }
1529 rx_mode = AcceptBroadcast | AcceptMultiHash | AcceptMyPhys;
1530 } else {
1531 iowrite8(AcceptBroadcast | AcceptMyPhys, ioaddr + RxMode);
1532 return;
1533 }
1534 if (np->mii_if.full_duplex && np->flowctrl)
1535 mc_filter[3] |= 0x0200;
1536
1537 for (i = 0; i < 4; i++)
1538 iowrite16(mc_filter[i], ioaddr + MulticastFilter0 + i*2);
1539 iowrite8(rx_mode, ioaddr + RxMode);
1540 }
1541
1542 static int __set_mac_addr(struct net_device *dev)
1543 {
1544 struct netdev_private *np = netdev_priv(dev);
1545 u16 addr16;
1546
1547 addr16 = (dev->dev_addr[0] | (dev->dev_addr[1] << 8));
1548 iowrite16(addr16, np->base + StationAddr);
1549 addr16 = (dev->dev_addr[2] | (dev->dev_addr[3] << 8));
1550 iowrite16(addr16, np->base + StationAddr+2);
1551 addr16 = (dev->dev_addr[4] | (dev->dev_addr[5] << 8));
1552 iowrite16(addr16, np->base + StationAddr+4);
1553 return 0;
1554 }
1555
1556 static int check_if_running(struct net_device *dev)
1557 {
1558 if (!netif_running(dev))
1559 return -EINVAL;
1560 return 0;
1561 }
1562
1563 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1564 {
1565 struct netdev_private *np = netdev_priv(dev);
1566 strcpy(info->driver, DRV_NAME);
1567 strcpy(info->version, DRV_VERSION);
1568 strcpy(info->bus_info, pci_name(np->pci_dev));
1569 }
1570
1571 static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1572 {
1573 struct netdev_private *np = netdev_priv(dev);
1574 spin_lock_irq(&np->lock);
1575 mii_ethtool_gset(&np->mii_if, ecmd);
1576 spin_unlock_irq(&np->lock);
1577 return 0;
1578 }
1579
1580 static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1581 {
1582 struct netdev_private *np = netdev_priv(dev);
1583 int res;
1584 spin_lock_irq(&np->lock);
1585 res = mii_ethtool_sset(&np->mii_if, ecmd);
1586 spin_unlock_irq(&np->lock);
1587 return res;
1588 }
1589
1590 static int nway_reset(struct net_device *dev)
1591 {
1592 struct netdev_private *np = netdev_priv(dev);
1593 return mii_nway_restart(&np->mii_if);
1594 }
1595
1596 static u32 get_link(struct net_device *dev)
1597 {
1598 struct netdev_private *np = netdev_priv(dev);
1599 return mii_link_ok(&np->mii_if);
1600 }
1601
1602 static u32 get_msglevel(struct net_device *dev)
1603 {
1604 struct netdev_private *np = netdev_priv(dev);
1605 return np->msg_enable;
1606 }
1607
1608 static void set_msglevel(struct net_device *dev, u32 val)
1609 {
1610 struct netdev_private *np = netdev_priv(dev);
1611 np->msg_enable = val;
1612 }
1613
1614 static const struct ethtool_ops ethtool_ops = {
1615 .begin = check_if_running,
1616 .get_drvinfo = get_drvinfo,
1617 .get_settings = get_settings,
1618 .set_settings = set_settings,
1619 .nway_reset = nway_reset,
1620 .get_link = get_link,
1621 .get_msglevel = get_msglevel,
1622 .set_msglevel = set_msglevel,
1623 };
1624
1625 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1626 {
1627 struct netdev_private *np = netdev_priv(dev);
1628 int rc;
1629
1630 if (!netif_running(dev))
1631 return -EINVAL;
1632
1633 spin_lock_irq(&np->lock);
1634 rc = generic_mii_ioctl(&np->mii_if, if_mii(rq), cmd, NULL);
1635 spin_unlock_irq(&np->lock);
1636
1637 return rc;
1638 }
1639
1640 static int netdev_close(struct net_device *dev)
1641 {
1642 struct netdev_private *np = netdev_priv(dev);
1643 void __iomem *ioaddr = np->base;
1644 struct sk_buff *skb;
1645 int i;
1646
1647 /* Wait and kill tasklet */
1648 tasklet_kill(&np->rx_tasklet);
1649 tasklet_kill(&np->tx_tasklet);
1650 np->cur_tx = 0;
1651 np->dirty_tx = 0;
1652 np->cur_task = 0;
1653 np->last_tx = NULL;
1654
1655 netif_stop_queue(dev);
1656
1657 if (netif_msg_ifdown(np)) {
1658 printk(KERN_DEBUG "%s: Shutting down ethercard, status was Tx %2.2x "
1659 "Rx %4.4x Int %2.2x.\n",
1660 dev->name, ioread8(ioaddr + TxStatus),
1661 ioread32(ioaddr + RxStatus), ioread16(ioaddr + IntrStatus));
1662 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1663 dev->name, np->cur_tx, np->dirty_tx, np->cur_rx, np->dirty_rx);
1664 }
1665
1666 /* Disable interrupts by clearing the interrupt mask. */
1667 iowrite16(0x0000, ioaddr + IntrEnable);
1668
1669 /* Disable Rx and Tx DMA for safely release resource */
1670 iowrite32(0x500, ioaddr + DMACtrl);
1671
1672 /* Stop the chip's Tx and Rx processes. */
1673 iowrite16(TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl1);
1674
1675 for (i = 2000; i > 0; i--) {
1676 if ((ioread32(ioaddr + DMACtrl) & 0xc000) == 0)
1677 break;
1678 mdelay(1);
1679 }
1680
1681 iowrite16(GlobalReset | DMAReset | FIFOReset | NetworkReset,
1682 ioaddr +ASICCtrl + 2);
1683
1684 for (i = 2000; i > 0; i--) {
1685 if ((ioread16(ioaddr + ASICCtrl +2) & ResetBusy) == 0)
1686 break;
1687 mdelay(1);
1688 }
1689
1690 #ifdef __i386__
1691 if (netif_msg_hw(np)) {
1692 printk("\n"KERN_DEBUG" Tx ring at %8.8x:\n",
1693 (int)(np->tx_ring_dma));
1694 for (i = 0; i < TX_RING_SIZE; i++)
1695 printk(" #%d desc. %4.4x %8.8x %8.8x.\n",
1696 i, np->tx_ring[i].status, np->tx_ring[i].frag[0].addr,
1697 np->tx_ring[i].frag[0].length);
1698 printk("\n"KERN_DEBUG " Rx ring %8.8x:\n",
1699 (int)(np->rx_ring_dma));
1700 for (i = 0; i < /*RX_RING_SIZE*/4 ; i++) {
1701 printk(KERN_DEBUG " #%d desc. %4.4x %4.4x %8.8x\n",
1702 i, np->rx_ring[i].status, np->rx_ring[i].frag[0].addr,
1703 np->rx_ring[i].frag[0].length);
1704 }
1705 }
1706 #endif /* __i386__ debugging only */
1707
1708 free_irq(dev->irq, dev);
1709
1710 del_timer_sync(&np->timer);
1711
1712 /* Free all the skbuffs in the Rx queue. */
1713 for (i = 0; i < RX_RING_SIZE; i++) {
1714 np->rx_ring[i].status = 0;
1715 skb = np->rx_skbuff[i];
1716 if (skb) {
1717 pci_unmap_single(np->pci_dev,
1718 le32_to_cpu(np->rx_ring[i].frag[0].addr),
1719 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1720 dev_kfree_skb(skb);
1721 np->rx_skbuff[i] = NULL;
1722 }
1723 np->rx_ring[i].frag[0].addr = cpu_to_le32(0xBADF00D0); /* poison */
1724 }
1725 for (i = 0; i < TX_RING_SIZE; i++) {
1726 np->tx_ring[i].next_desc = 0;
1727 skb = np->tx_skbuff[i];
1728 if (skb) {
1729 pci_unmap_single(np->pci_dev,
1730 le32_to_cpu(np->tx_ring[i].frag[0].addr),
1731 skb->len, PCI_DMA_TODEVICE);
1732 dev_kfree_skb(skb);
1733 np->tx_skbuff[i] = NULL;
1734 }
1735 }
1736
1737 return 0;
1738 }
1739
1740 static void __devexit sundance_remove1 (struct pci_dev *pdev)
1741 {
1742 struct net_device *dev = pci_get_drvdata(pdev);
1743
1744 if (dev) {
1745 struct netdev_private *np = netdev_priv(dev);
1746
1747 unregister_netdev(dev);
1748 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring,
1749 np->rx_ring_dma);
1750 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring,
1751 np->tx_ring_dma);
1752 pci_iounmap(pdev, np->base);
1753 pci_release_regions(pdev);
1754 free_netdev(dev);
1755 pci_set_drvdata(pdev, NULL);
1756 }
1757 }
1758
1759 static struct pci_driver sundance_driver = {
1760 .name = DRV_NAME,
1761 .id_table = sundance_pci_tbl,
1762 .probe = sundance_probe1,
1763 .remove = __devexit_p(sundance_remove1),
1764 };
1765
1766 static int __init sundance_init(void)
1767 {
1768 /* when a module, this is printed whether or not devices are found in probe */
1769 #ifdef MODULE
1770 printk(version);
1771 #endif
1772 return pci_register_driver(&sundance_driver);
1773 }
1774
1775 static void __exit sundance_exit(void)
1776 {
1777 pci_unregister_driver(&sundance_driver);
1778 }
1779
1780 module_init(sundance_init);
1781 module_exit(sundance_exit);
1782
1783
Stable & featurefull patchset based on Linus's git branch