?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
remove malta-mtd.c and fix MAINTAINERS
[linux-2.6/zen-sources.git] / drivers / net / 8139too.c
blob63f906b04899de12271baa196bc7b424d0c067f8
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define DRV_NAME "8139too"
93 #define DRV_VERSION "0.9.28"
94
95
96 #include <linux/module.h>
97 #include <linux/kernel.h>
98 #include <linux/compiler.h>
99 #include <linux/pci.h>
100 #include <linux/init.h>
101 #include <linux/netdevice.h>
102 #include <linux/etherdevice.h>
103 #include <linux/rtnetlink.h>
104 #include <linux/delay.h>
105 #include <linux/ethtool.h>
106 #include <linux/mii.h>
107 #include <linux/completion.h>
108 #include <linux/crc32.h>
109 #include <linux/io.h>
110 #include <linux/uaccess.h>
111 #include <asm/irq.h>
112
113 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
114 #define PFX DRV_NAME ": "
115
116 /* Default Message level */
117 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
118 NETIF_MSG_PROBE | \
119 NETIF_MSG_LINK)
120
121
122 /* define to 1, 2 or 3 to enable copious debugging info */
123 #define RTL8139_DEBUG 0
124
125 /* define to 1 to disable lightweight runtime debugging checks */
126 #undef RTL8139_NDEBUG
127
128
129 #if RTL8139_DEBUG
130 /* note: prints function name for you */
131 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__ , ## args)
132 #else
133 # define DPRINTK(fmt, args...)
134 #endif
135
136 #ifdef RTL8139_NDEBUG
137 # define assert(expr) do {} while (0)
138 #else
139 # define assert(expr) \
140 if(unlikely(!(expr))) { \
141 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
142 #expr, __FILE__, __func__, __LINE__); \
143 }
144 #endif
145
146
147 /* A few user-configurable values. */
148 /* media options */
149 #define MAX_UNITS 8
150 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
151 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
152
153 /* Whether to use MMIO or PIO. Default to MMIO. */
154 #ifdef CONFIG_8139TOO_PIO
155 static int use_io = 1;
156 #else
157 static int use_io = 0;
158 #endif
159
160 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
161 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
162 static int multicast_filter_limit = 32;
163
164 /* bitmapped message enable number */
165 static int debug = -1;
166
167 /*
168 * Receive ring size
169 * Warning: 64K ring has hardware issues and may lock up.
170 */
171 #if defined(CONFIG_SH_DREAMCAST)
172 #define RX_BUF_IDX 0 /* 8K ring */
173 #else
174 #define RX_BUF_IDX 2 /* 32K ring */
175 #endif
176 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
177 #define RX_BUF_PAD 16
178 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
179
180 #if RX_BUF_LEN == 65536
181 #define RX_BUF_TOT_LEN RX_BUF_LEN
182 #else
183 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
184 #endif
185
186 /* Number of Tx descriptor registers. */
187 #define NUM_TX_DESC 4
188
189 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
190 #define MAX_ETH_FRAME_SIZE 1536
191
192 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
193 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
194 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
195
196 /* PCI Tuning Parameters
197 Threshold is bytes transferred to chip before transmission starts. */
198 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
199
200 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
201 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
202 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
203 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
204 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
205
206 /* Operational parameters that usually are not changed. */
207 /* Time in jiffies before concluding the transmitter is hung. */
208 #define TX_TIMEOUT (6*HZ)
209
210
211 enum {
212 HAS_MII_XCVR = 0x010000,
213 HAS_CHIP_XCVR = 0x020000,
214 HAS_LNK_CHNG = 0x040000,
215 };
216
217 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
218 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
219 #define RTL_MIN_IO_SIZE 0x80
220 #define RTL8139B_IO_SIZE 256
221
222 #define RTL8129_CAPS HAS_MII_XCVR
223 #define RTL8139_CAPS (HAS_CHIP_XCVR|HAS_LNK_CHNG)
224
225 typedef enum {
226 RTL8139 = 0,
227 RTL8129,
228 } board_t;
229
230
231 /* indexed by board_t, above */
232 static const struct {
233 const char *name;
234 u32 hw_flags;
235 } board_info[] __devinitdata = {
236 { "RealTek RTL8139", RTL8139_CAPS },
237 { "RealTek RTL8129", RTL8129_CAPS },
238 };
239
240
241 static struct pci_device_id rtl8139_pci_tbl[] = {
242 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
257 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
259 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
260 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
261
262 #ifdef CONFIG_SH_SECUREEDGE5410
263 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
264 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
265 #endif
266 #ifdef CONFIG_8139TOO_8129
267 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
268 #endif
269
270 /* some crazy cards report invalid vendor ids like
271 * 0x0001 here. The other ids are valid and constant,
272 * so we simply don't match on the main vendor id.
273 */
274 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
275 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
276 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
277
278 {0,}
279 };
280 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
281
282 static struct {
283 const char str[ETH_GSTRING_LEN];
284 } ethtool_stats_keys[] = {
285 { "early_rx" },
286 { "tx_buf_mapped" },
287 { "tx_timeouts" },
288 { "rx_lost_in_ring" },
289 };
290
291 /* The rest of these values should never change. */
292
293 /* Symbolic offsets to registers. */
294 enum RTL8139_registers {
295 MAC0 = 0, /* Ethernet hardware address. */
296 MAR0 = 8, /* Multicast filter. */
297 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
298 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
299 RxBuf = 0x30,
300 ChipCmd = 0x37,
301 RxBufPtr = 0x38,
302 RxBufAddr = 0x3A,
303 IntrMask = 0x3C,
304 IntrStatus = 0x3E,
305 TxConfig = 0x40,
306 RxConfig = 0x44,
307 Timer = 0x48, /* A general-purpose counter. */
308 RxMissed = 0x4C, /* 24 bits valid, write clears. */
309 Cfg9346 = 0x50,
310 Config0 = 0x51,
311 Config1 = 0x52,
312 TimerInt = 0x54,
313 MediaStatus = 0x58,
314 Config3 = 0x59,
315 Config4 = 0x5A, /* absent on RTL-8139A */
316 HltClk = 0x5B,
317 MultiIntr = 0x5C,
318 TxSummary = 0x60,
319 BasicModeCtrl = 0x62,
320 BasicModeStatus = 0x64,
321 NWayAdvert = 0x66,
322 NWayLPAR = 0x68,
323 NWayExpansion = 0x6A,
324 /* Undocumented registers, but required for proper operation. */
325 FIFOTMS = 0x70, /* FIFO Control and test. */
326 CSCR = 0x74, /* Chip Status and Configuration Register. */
327 PARA78 = 0x78,
328 FlashReg = 0xD4, /* Communication with Flash ROM, four bytes. */
329 PARA7c = 0x7c, /* Magic transceiver parameter register. */
330 Config5 = 0xD8, /* absent on RTL-8139A */
331 };
332
333 enum ClearBitMasks {
334 MultiIntrClear = 0xF000,
335 ChipCmdClear = 0xE2,
336 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
337 };
338
339 enum ChipCmdBits {
340 CmdReset = 0x10,
341 CmdRxEnb = 0x08,
342 CmdTxEnb = 0x04,
343 RxBufEmpty = 0x01,
344 };
345
346 /* Interrupt register bits, using my own meaningful names. */
347 enum IntrStatusBits {
348 PCIErr = 0x8000,
349 PCSTimeout = 0x4000,
350 RxFIFOOver = 0x40,
351 RxUnderrun = 0x20,
352 RxOverflow = 0x10,
353 TxErr = 0x08,
354 TxOK = 0x04,
355 RxErr = 0x02,
356 RxOK = 0x01,
357
358 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
359 };
360
361 enum TxStatusBits {
362 TxHostOwns = 0x2000,
363 TxUnderrun = 0x4000,
364 TxStatOK = 0x8000,
365 TxOutOfWindow = 0x20000000,
366 TxAborted = 0x40000000,
367 TxCarrierLost = 0x80000000,
368 };
369 enum RxStatusBits {
370 RxMulticast = 0x8000,
371 RxPhysical = 0x4000,
372 RxBroadcast = 0x2000,
373 RxBadSymbol = 0x0020,
374 RxRunt = 0x0010,
375 RxTooLong = 0x0008,
376 RxCRCErr = 0x0004,
377 RxBadAlign = 0x0002,
378 RxStatusOK = 0x0001,
379 };
380
381 /* Bits in RxConfig. */
382 enum rx_mode_bits {
383 AcceptErr = 0x20,
384 AcceptRunt = 0x10,
385 AcceptBroadcast = 0x08,
386 AcceptMulticast = 0x04,
387 AcceptMyPhys = 0x02,
388 AcceptAllPhys = 0x01,
389 };
390
391 /* Bits in TxConfig. */
392 enum tx_config_bits {
393 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
394 TxIFGShift = 24,
395 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
396 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
397 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
398 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
399
400 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
401 TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */
402 TxClearAbt = (1 << 0), /* Clear abort (WO) */
403 TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */
404 TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */
405
406 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
407 };
408
409 /* Bits in Config1 */
410 enum Config1Bits {
411 Cfg1_PM_Enable = 0x01,
412 Cfg1_VPD_Enable = 0x02,
413 Cfg1_PIO = 0x04,
414 Cfg1_MMIO = 0x08,
415 LWAKE = 0x10, /* not on 8139, 8139A */
416 Cfg1_Driver_Load = 0x20,
417 Cfg1_LED0 = 0x40,
418 Cfg1_LED1 = 0x80,
419 SLEEP = (1 << 1), /* only on 8139, 8139A */
420 PWRDN = (1 << 0), /* only on 8139, 8139A */
421 };
422
423 /* Bits in Config3 */
424 enum Config3Bits {
425 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
426 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
427 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
428 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
429 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
430 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
431 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
432 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
433 };
434
435 /* Bits in Config4 */
436 enum Config4Bits {
437 LWPTN = (1 << 2), /* not on 8139, 8139A */
438 };
439
440 /* Bits in Config5 */
441 enum Config5Bits {
442 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
443 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
444 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
445 Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */
446 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
447 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
448 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
449 };
450
451 enum RxConfigBits {
452 /* rx fifo threshold */
453 RxCfgFIFOShift = 13,
454 RxCfgFIFONone = (7 << RxCfgFIFOShift),
455
456 /* Max DMA burst */
457 RxCfgDMAShift = 8,
458 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
459
460 /* rx ring buffer length */
461 RxCfgRcv8K = 0,
462 RxCfgRcv16K = (1 << 11),
463 RxCfgRcv32K = (1 << 12),
464 RxCfgRcv64K = (1 << 11) | (1 << 12),
465
466 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
467 RxNoWrap = (1 << 7),
468 };
469
470 /* Twister tuning parameters from RealTek.
471 Completely undocumented, but required to tune bad links on some boards. */
472 enum CSCRBits {
473 CSCR_LinkOKBit = 0x0400,
474 CSCR_LinkChangeBit = 0x0800,
475 CSCR_LinkStatusBits = 0x0f000,
476 CSCR_LinkDownOffCmd = 0x003c0,
477 CSCR_LinkDownCmd = 0x0f3c0,
478 };
479
480 enum Cfg9346Bits {
481 Cfg9346_Lock = 0x00,
482 Cfg9346_Unlock = 0xC0,
483 };
484
485 typedef enum {
486 CH_8139 = 0,
487 CH_8139_K,
488 CH_8139A,
489 CH_8139A_G,
490 CH_8139B,
491 CH_8130,
492 CH_8139C,
493 CH_8100,
494 CH_8100B_8139D,
495 CH_8101,
496 } chip_t;
497
498 enum chip_flags {
499 HasHltClk = (1 << 0),
500 HasLWake = (1 << 1),
501 };
502
503 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
504 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
505 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
506
507 /* directly indexed by chip_t, above */
508 static const struct {
509 const char *name;
510 u32 version; /* from RTL8139C/RTL8139D docs */
511 u32 flags;
512 } rtl_chip_info[] = {
513 { "RTL-8139",
514 HW_REVID(1, 0, 0, 0, 0, 0, 0),
515 HasHltClk,
516 },
517
518 { "RTL-8139 rev K",
519 HW_REVID(1, 1, 0, 0, 0, 0, 0),
520 HasHltClk,
521 },
522
523 { "RTL-8139A",
524 HW_REVID(1, 1, 1, 0, 0, 0, 0),
525 HasHltClk, /* XXX undocumented? */
526 },
527
528 { "RTL-8139A rev G",
529 HW_REVID(1, 1, 1, 0, 0, 1, 0),
530 HasHltClk, /* XXX undocumented? */
531 },
532
533 { "RTL-8139B",
534 HW_REVID(1, 1, 1, 1, 0, 0, 0),
535 HasLWake,
536 },
537
538 { "RTL-8130",
539 HW_REVID(1, 1, 1, 1, 1, 0, 0),
540 HasLWake,
541 },
542
543 { "RTL-8139C",
544 HW_REVID(1, 1, 1, 0, 1, 0, 0),
545 HasLWake,
546 },
547
548 { "RTL-8100",
549 HW_REVID(1, 1, 1, 1, 0, 1, 0),
550 HasLWake,
551 },
552
553 { "RTL-8100B/8139D",
554 HW_REVID(1, 1, 1, 0, 1, 0, 1),
555 HasHltClk /* XXX undocumented? */
556 | HasLWake,
557 },
558
559 { "RTL-8101",
560 HW_REVID(1, 1, 1, 0, 1, 1, 1),
561 HasLWake,
562 },
563 };
564
565 struct rtl_extra_stats {
566 unsigned long early_rx;
567 unsigned long tx_buf_mapped;
568 unsigned long tx_timeouts;
569 unsigned long rx_lost_in_ring;
570 };
571
572 struct rtl8139_private {
573 void __iomem *mmio_addr;
574 int drv_flags;
575 struct pci_dev *pci_dev;
576 u32 msg_enable;
577 struct napi_struct napi;
578 struct net_device *dev;
579
580 unsigned char *rx_ring;
581 unsigned int cur_rx; /* RX buf index of next pkt */
582 dma_addr_t rx_ring_dma;
583
584 unsigned int tx_flag;
585 unsigned long cur_tx;
586 unsigned long dirty_tx;
587 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
588 unsigned char *tx_bufs; /* Tx bounce buffer region. */
589 dma_addr_t tx_bufs_dma;
590
591 signed char phys[4]; /* MII device addresses. */
592
593 /* Twister tune state. */
594 char twistie, twist_row, twist_col;
595
596 unsigned int watchdog_fired : 1;
597 unsigned int default_port : 4; /* Last dev->if_port value. */
598 unsigned int have_thread : 1;
599
600 spinlock_t lock;
601 spinlock_t rx_lock;
602
603 chip_t chipset;
604 u32 rx_config;
605 struct rtl_extra_stats xstats;
606
607 struct delayed_work thread;
608
609 struct mii_if_info mii;
610 unsigned int regs_len;
611 unsigned long fifo_copy_timeout;
612 };
613
614 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
615 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
616 MODULE_LICENSE("GPL");
617 MODULE_VERSION(DRV_VERSION);
618
619 module_param(use_io, int, 0);
620 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO");
621 module_param(multicast_filter_limit, int, 0);
622 module_param_array(media, int, NULL, 0);
623 module_param_array(full_duplex, int, NULL, 0);
624 module_param(debug, int, 0);
625 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
626 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
627 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
628 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
629
630 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
631 static int rtl8139_open (struct net_device *dev);
632 static int mdio_read (struct net_device *dev, int phy_id, int location);
633 static void mdio_write (struct net_device *dev, int phy_id, int location,
634 int val);
635 static void rtl8139_start_thread(struct rtl8139_private *tp);
636 static void rtl8139_tx_timeout (struct net_device *dev);
637 static void rtl8139_init_ring (struct net_device *dev);
638 static int rtl8139_start_xmit (struct sk_buff *skb,
639 struct net_device *dev);
640 #ifdef CONFIG_NET_POLL_CONTROLLER
641 static void rtl8139_poll_controller(struct net_device *dev);
642 #endif
643 static int rtl8139_poll(struct napi_struct *napi, int budget);
644 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);
645 static int rtl8139_close (struct net_device *dev);
646 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
647 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
648 static void rtl8139_set_rx_mode (struct net_device *dev);
649 static void __set_rx_mode (struct net_device *dev);
650 static void rtl8139_hw_start (struct net_device *dev);
651 static void rtl8139_thread (struct work_struct *work);
652 static void rtl8139_tx_timeout_task(struct work_struct *work);
653 static const struct ethtool_ops rtl8139_ethtool_ops;
654
655 /* write MMIO register, with flush */
656 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
657 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
658 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
659 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
660
661 /* write MMIO register */
662 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
663 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
664 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
665
666 /* read MMIO register */
667 #define RTL_R8(reg) ioread8 (ioaddr + (reg))
668 #define RTL_R16(reg) ioread16 (ioaddr + (reg))
669 #define RTL_R32(reg) ((unsigned long) ioread32 (ioaddr + (reg)))
670
671
672 static const u16 rtl8139_intr_mask =
673 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
674 TxErr | TxOK | RxErr | RxOK;
675
676 static const u16 rtl8139_norx_intr_mask =
677 PCIErr | PCSTimeout | RxUnderrun |
678 TxErr | TxOK | RxErr ;
679
680 #if RX_BUF_IDX == 0
681 static const unsigned int rtl8139_rx_config =
682 RxCfgRcv8K | RxNoWrap |
683 (RX_FIFO_THRESH << RxCfgFIFOShift) |
684 (RX_DMA_BURST << RxCfgDMAShift);
685 #elif RX_BUF_IDX == 1
686 static const unsigned int rtl8139_rx_config =
687 RxCfgRcv16K | RxNoWrap |
688 (RX_FIFO_THRESH << RxCfgFIFOShift) |
689 (RX_DMA_BURST << RxCfgDMAShift);
690 #elif RX_BUF_IDX == 2
691 static const unsigned int rtl8139_rx_config =
692 RxCfgRcv32K | RxNoWrap |
693 (RX_FIFO_THRESH << RxCfgFIFOShift) |
694 (RX_DMA_BURST << RxCfgDMAShift);
695 #elif RX_BUF_IDX == 3
696 static const unsigned int rtl8139_rx_config =
697 RxCfgRcv64K |
698 (RX_FIFO_THRESH << RxCfgFIFOShift) |
699 (RX_DMA_BURST << RxCfgDMAShift);
700 #else
701 #error "Invalid configuration for 8139_RXBUF_IDX"
702 #endif
703
704 static const unsigned int rtl8139_tx_config =
705 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
706
707 static void __rtl8139_cleanup_dev (struct net_device *dev)
708 {
709 struct rtl8139_private *tp = netdev_priv(dev);
710 struct pci_dev *pdev;
711
712 assert (dev != NULL);
713 assert (tp->pci_dev != NULL);
714 pdev = tp->pci_dev;
715
716 if (tp->mmio_addr)
717 pci_iounmap (pdev, tp->mmio_addr);
718
719 /* it's ok to call this even if we have no regions to free */
720 pci_release_regions (pdev);
721
722 free_netdev(dev);
723 pci_set_drvdata (pdev, NULL);
724 }
725
726
727 static void rtl8139_chip_reset (void __iomem *ioaddr)
728 {
729 int i;
730
731 /* Soft reset the chip. */
732 RTL_W8 (ChipCmd, CmdReset);
733
734 /* Check that the chip has finished the reset. */
735 for (i = 1000; i > 0; i--) {
736 barrier();
737 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
738 break;
739 udelay (10);
740 }
741 }
742
743
744 static int __devinit rtl8139_init_board (struct pci_dev *pdev,
745 struct net_device **dev_out)
746 {
747 void __iomem *ioaddr;
748 struct net_device *dev;
749 struct rtl8139_private *tp;
750 u8 tmp8;
751 int rc, disable_dev_on_err = 0;
752 unsigned int i;
753 unsigned long pio_start, pio_end, pio_flags, pio_len;
754 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
755 u32 version;
756
757 assert (pdev != NULL);
758
759 *dev_out = NULL;
760
761 /* dev and priv zeroed in alloc_etherdev */
762 dev = alloc_etherdev (sizeof (*tp));
763 if (dev == NULL) {
764 dev_err(&pdev->dev, "Unable to alloc new net device\n");
765 return -ENOMEM;
766 }
767 SET_NETDEV_DEV(dev, &pdev->dev);
768
769 tp = netdev_priv(dev);
770 tp->pci_dev = pdev;
771
772 /* enable device (incl. PCI PM wakeup and hotplug setup) */
773 rc = pci_enable_device (pdev);
774 if (rc)
775 goto err_out;
776
777 pio_start = pci_resource_start (pdev, 0);
778 pio_end = pci_resource_end (pdev, 0);
779 pio_flags = pci_resource_flags (pdev, 0);
780 pio_len = pci_resource_len (pdev, 0);
781
782 mmio_start = pci_resource_start (pdev, 1);
783 mmio_end = pci_resource_end (pdev, 1);
784 mmio_flags = pci_resource_flags (pdev, 1);
785 mmio_len = pci_resource_len (pdev, 1);
786
787 /* set this immediately, we need to know before
788 * we talk to the chip directly */
789 DPRINTK("PIO region size == 0x%02X\n", pio_len);
790 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
791
792 retry:
793 if (use_io) {
794 /* make sure PCI base addr 0 is PIO */
795 if (!(pio_flags & IORESOURCE_IO)) {
796 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
797 rc = -ENODEV;
798 goto err_out;
799 }
800 /* check for weird/broken PCI region reporting */
801 if (pio_len < RTL_MIN_IO_SIZE) {
802 dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");
803 rc = -ENODEV;
804 goto err_out;
805 }
806 } else {
807 /* make sure PCI base addr 1 is MMIO */
808 if (!(mmio_flags & IORESOURCE_MEM)) {
809 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
810 rc = -ENODEV;
811 goto err_out;
812 }
813 if (mmio_len < RTL_MIN_IO_SIZE) {
814 dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");
815 rc = -ENODEV;
816 goto err_out;
817 }
818 }
819
820 rc = pci_request_regions (pdev, DRV_NAME);
821 if (rc)
822 goto err_out;
823 disable_dev_on_err = 1;
824
825 /* enable PCI bus-mastering */
826 pci_set_master (pdev);
827
828 if (use_io) {
829 ioaddr = pci_iomap(pdev, 0, 0);
830 if (!ioaddr) {
831 dev_err(&pdev->dev, "cannot map PIO, aborting\n");
832 rc = -EIO;
833 goto err_out;
834 }
835 dev->base_addr = pio_start;
836 tp->regs_len = pio_len;
837 } else {
838 /* ioremap MMIO region */
839 ioaddr = pci_iomap(pdev, 1, 0);
840 if (ioaddr == NULL) {
841 dev_err(&pdev->dev, "cannot remap MMIO, trying PIO\n");
842 pci_release_regions(pdev);
843 use_io = 1;
844 goto retry;
845 }
846 dev->base_addr = (long) ioaddr;
847 tp->regs_len = mmio_len;
848 }
849 tp->mmio_addr = ioaddr;
850
851 /* Bring old chips out of low-power mode. */
852 RTL_W8 (HltClk, 'R');
853
854 /* check for missing/broken hardware */
855 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
856 dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
857 rc = -EIO;
858 goto err_out;
859 }
860
861 /* identify chip attached to board */
862 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
863 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
864 if (version == rtl_chip_info[i].version) {
865 tp->chipset = i;
866 goto match;
867 }
868
869 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
870 dev_printk (KERN_DEBUG, &pdev->dev,
871 "unknown chip version, assuming RTL-8139\n");
872 dev_printk (KERN_DEBUG, &pdev->dev,
873 "TxConfig = 0x%lx\n", RTL_R32 (TxConfig));
874 tp->chipset = 0;
875
876 match:
877 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
878 version, i, rtl_chip_info[i].name);
879
880 if (tp->chipset >= CH_8139B) {
881 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
882 DPRINTK("PCI PM wakeup\n");
883 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
884 (tmp8 & LWAKE))
885 new_tmp8 &= ~LWAKE;
886 new_tmp8 |= Cfg1_PM_Enable;
887 if (new_tmp8 != tmp8) {
888 RTL_W8 (Cfg9346, Cfg9346_Unlock);
889 RTL_W8 (Config1, tmp8);
890 RTL_W8 (Cfg9346, Cfg9346_Lock);
891 }
892 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
893 tmp8 = RTL_R8 (Config4);
894 if (tmp8 & LWPTN) {
895 RTL_W8 (Cfg9346, Cfg9346_Unlock);
896 RTL_W8 (Config4, tmp8 & ~LWPTN);
897 RTL_W8 (Cfg9346, Cfg9346_Lock);
898 }
899 }
900 } else {
901 DPRINTK("Old chip wakeup\n");
902 tmp8 = RTL_R8 (Config1);
903 tmp8 &= ~(SLEEP | PWRDN);
904 RTL_W8 (Config1, tmp8);
905 }
906
907 rtl8139_chip_reset (ioaddr);
908
909 *dev_out = dev;
910 return 0;
911
912 err_out:
913 __rtl8139_cleanup_dev (dev);
914 if (disable_dev_on_err)
915 pci_disable_device (pdev);
916 return rc;
917 }
918
919
920 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
921 const struct pci_device_id *ent)
922 {
923 struct net_device *dev = NULL;
924 struct rtl8139_private *tp;
925 int i, addr_len, option;
926 void __iomem *ioaddr;
927 static int board_idx = -1;
928 DECLARE_MAC_BUF(mac);
929
930 assert (pdev != NULL);
931 assert (ent != NULL);
932
933 board_idx++;
934
935 /* when we're built into the kernel, the driver version message
936 * is only printed if at least one 8139 board has been found
937 */
938 #ifndef MODULE
939 {
940 static int printed_version;
941 if (!printed_version++)
942 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
943 }
944 #endif
945
946 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
947 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {
948 dev_info(&pdev->dev,
949 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n",
950 pdev->vendor, pdev->device, pdev->revision);
951 return -ENODEV;
952 }
953
954 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
955 pdev->device == PCI_DEVICE_ID_REALTEK_8139 &&
956 pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS &&
957 pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) {
958 printk(KERN_INFO "8139too: OQO Model 2 detected. Forcing PIO\n");
959 use_io = 1;
960 }
961
962 i = rtl8139_init_board (pdev, &dev);
963 if (i < 0)
964 return i;
965
966 assert (dev != NULL);
967 tp = netdev_priv(dev);
968 tp->dev = dev;
969
970 ioaddr = tp->mmio_addr;
971 assert (ioaddr != NULL);
972
973 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
974 for (i = 0; i < 3; i++)
975 ((__le16 *) (dev->dev_addr))[i] =
976 cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));
977 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
978
979 /* The Rtl8139-specific entries in the device structure. */
980 dev->open = rtl8139_open;
981 dev->hard_start_xmit = rtl8139_start_xmit;
982 netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);
983 dev->stop = rtl8139_close;
984 dev->get_stats = rtl8139_get_stats;
985 dev->set_multicast_list = rtl8139_set_rx_mode;
986 dev->do_ioctl = netdev_ioctl;
987 dev->ethtool_ops = &rtl8139_ethtool_ops;
988 dev->tx_timeout = rtl8139_tx_timeout;
989 dev->watchdog_timeo = TX_TIMEOUT;
990 #ifdef CONFIG_NET_POLL_CONTROLLER
991 dev->poll_controller = rtl8139_poll_controller;
992 #endif
993
994 /* note: the hardware is not capable of sg/csum/highdma, however
995 * through the use of skb_copy_and_csum_dev we enable these
996 * features
997 */
998 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
999
1000 dev->irq = pdev->irq;
1001
1002 /* tp zeroed and aligned in alloc_etherdev */
1003 tp = netdev_priv(dev);
1004
1005 /* note: tp->chipset set in rtl8139_init_board */
1006 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1007 tp->mmio_addr = ioaddr;
1008 tp->msg_enable =
1009 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1010 spin_lock_init (&tp->lock);
1011 spin_lock_init (&tp->rx_lock);
1012 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1013 tp->mii.dev = dev;
1014 tp->mii.mdio_read = mdio_read;
1015 tp->mii.mdio_write = mdio_write;
1016 tp->mii.phy_id_mask = 0x3f;
1017 tp->mii.reg_num_mask = 0x1f;
1018
1019 /* dev is fully set up and ready to use now */
1020 DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
1021 i = register_netdev (dev);
1022 if (i) goto err_out;
1023
1024 pci_set_drvdata (pdev, dev);
1025
1026 printk (KERN_INFO "%s: %s at 0x%lx, "
1027 "%s, IRQ %d\n",
1028 dev->name,
1029 board_info[ent->driver_data].name,
1030 dev->base_addr,
1031 print_mac(mac, dev->dev_addr),
1032 dev->irq);
1033
1034 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
1035 dev->name, rtl_chip_info[tp->chipset].name);
1036
1037 /* Find the connected MII xcvrs.
1038 Doing this in open() would allow detecting external xcvrs later, but
1039 takes too much time. */
1040 #ifdef CONFIG_8139TOO_8129
1041 if (tp->drv_flags & HAS_MII_XCVR) {
1042 int phy, phy_idx = 0;
1043 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1044 int mii_status = mdio_read(dev, phy, 1);
1045 if (mii_status != 0xffff && mii_status != 0x0000) {
1046 u16 advertising = mdio_read(dev, phy, 4);
1047 tp->phys[phy_idx++] = phy;
1048 printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
1049 "advertising %4.4x.\n",
1050 dev->name, phy, mii_status, advertising);
1051 }
1052 }
1053 if (phy_idx == 0) {
1054 printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
1055 "transceiver.\n",
1056 dev->name);
1057 tp->phys[0] = 32;
1058 }
1059 } else
1060 #endif
1061 tp->phys[0] = 32;
1062 tp->mii.phy_id = tp->phys[0];
1063
1064 /* The lower four bits are the media type. */
1065 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1066 if (option > 0) {
1067 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1068 tp->default_port = option & 0xFF;
1069 if (tp->default_port)
1070 tp->mii.force_media = 1;
1071 }
1072 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1073 tp->mii.full_duplex = full_duplex[board_idx];
1074 if (tp->mii.full_duplex) {
1075 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
1076 /* Changing the MII-advertised media because might prevent
1077 re-connection. */
1078 tp->mii.force_media = 1;
1079 }
1080 if (tp->default_port) {
1081 printk(KERN_INFO " Forcing %dMbps %s-duplex operation.\n",
1082 (option & 0x20 ? 100 : 10),
1083 (option & 0x10 ? "full" : "half"));
1084 mdio_write(dev, tp->phys[0], 0,
1085 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1086 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1087 }
1088
1089 /* Put the chip into low-power mode. */
1090 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1091 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1092
1093 return 0;
1094
1095 err_out:
1096 __rtl8139_cleanup_dev (dev);
1097 pci_disable_device (pdev);
1098 return i;
1099 }
1100
1101
1102 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1103 {
1104 struct net_device *dev = pci_get_drvdata (pdev);
1105
1106 assert (dev != NULL);
1107
1108 flush_scheduled_work();
1109
1110 unregister_netdev (dev);
1111
1112 __rtl8139_cleanup_dev (dev);
1113 pci_disable_device (pdev);
1114 }
1115
1116
1117 /* Serial EEPROM section. */
1118
1119 /* EEPROM_Ctrl bits. */
1120 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1121 #define EE_CS 0x08 /* EEPROM chip select. */
1122 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1123 #define EE_WRITE_0 0x00
1124 #define EE_WRITE_1 0x02
1125 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1126 #define EE_ENB (0x80 | EE_CS)
1127
1128 /* Delay between EEPROM clock transitions.
1129 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1130 */
1131
1132 #define eeprom_delay() (void)RTL_R32(Cfg9346)
1133
1134 /* The EEPROM commands include the alway-set leading bit. */
1135 #define EE_WRITE_CMD (5)
1136 #define EE_READ_CMD (6)
1137 #define EE_ERASE_CMD (7)
1138
1139 static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1140 {
1141 int i;
1142 unsigned retval = 0;
1143 int read_cmd = location | (EE_READ_CMD << addr_len);
1144
1145 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1146 RTL_W8 (Cfg9346, EE_ENB);
1147 eeprom_delay ();
1148
1149 /* Shift the read command bits out. */
1150 for (i = 4 + addr_len; i >= 0; i--) {
1151 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1152 RTL_W8 (Cfg9346, EE_ENB | dataval);
1153 eeprom_delay ();
1154 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1155 eeprom_delay ();
1156 }
1157 RTL_W8 (Cfg9346, EE_ENB);
1158 eeprom_delay ();
1159
1160 for (i = 16; i > 0; i--) {
1161 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1162 eeprom_delay ();
1163 retval =
1164 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1165 0);
1166 RTL_W8 (Cfg9346, EE_ENB);
1167 eeprom_delay ();
1168 }
1169
1170 /* Terminate the EEPROM access. */
1171 RTL_W8 (Cfg9346, ~EE_CS);
1172 eeprom_delay ();
1173
1174 return retval;
1175 }
1176
1177 /* MII serial management: mostly bogus for now. */
1178 /* Read and write the MII management registers using software-generated
1179 serial MDIO protocol.
1180 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1181 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1182 "overclocking" issues. */
1183 #define MDIO_DIR 0x80
1184 #define MDIO_DATA_OUT 0x04
1185 #define MDIO_DATA_IN 0x02
1186 #define MDIO_CLK 0x01
1187 #define MDIO_WRITE0 (MDIO_DIR)
1188 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1189
1190 #define mdio_delay() RTL_R8(Config4)
1191
1192
1193 static const char mii_2_8139_map[8] = {
1194 BasicModeCtrl,
1195 BasicModeStatus,
1196 0,
1197 0,
1198 NWayAdvert,
1199 NWayLPAR,
1200 NWayExpansion,
1201 0
1202 };
1203
1204
1205 #ifdef CONFIG_8139TOO_8129
1206 /* Syncronize the MII management interface by shifting 32 one bits out. */
1207 static void mdio_sync (void __iomem *ioaddr)
1208 {
1209 int i;
1210
1211 for (i = 32; i >= 0; i--) {
1212 RTL_W8 (Config4, MDIO_WRITE1);
1213 mdio_delay ();
1214 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1215 mdio_delay ();
1216 }
1217 }
1218 #endif
1219
1220 static int mdio_read (struct net_device *dev, int phy_id, int location)
1221 {
1222 struct rtl8139_private *tp = netdev_priv(dev);
1223 int retval = 0;
1224 #ifdef CONFIG_8139TOO_8129
1225 void __iomem *ioaddr = tp->mmio_addr;
1226 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1227 int i;
1228 #endif
1229
1230 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1231 void __iomem *ioaddr = tp->mmio_addr;
1232 return location < 8 && mii_2_8139_map[location] ?
1233 RTL_R16 (mii_2_8139_map[location]) : 0;
1234 }
1235
1236 #ifdef CONFIG_8139TOO_8129
1237 mdio_sync (ioaddr);
1238 /* Shift the read command bits out. */
1239 for (i = 15; i >= 0; i--) {
1240 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1241
1242 RTL_W8 (Config4, MDIO_DIR | dataval);
1243 mdio_delay ();
1244 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1245 mdio_delay ();
1246 }
1247
1248 /* Read the two transition, 16 data, and wire-idle bits. */
1249 for (i = 19; i > 0; i--) {
1250 RTL_W8 (Config4, 0);
1251 mdio_delay ();
1252 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1253 RTL_W8 (Config4, MDIO_CLK);
1254 mdio_delay ();
1255 }
1256 #endif
1257
1258 return (retval >> 1) & 0xffff;
1259 }
1260
1261
1262 static void mdio_write (struct net_device *dev, int phy_id, int location,
1263 int value)
1264 {
1265 struct rtl8139_private *tp = netdev_priv(dev);
1266 #ifdef CONFIG_8139TOO_8129
1267 void __iomem *ioaddr = tp->mmio_addr;
1268 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1269 int i;
1270 #endif
1271
1272 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1273 void __iomem *ioaddr = tp->mmio_addr;
1274 if (location == 0) {
1275 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1276 RTL_W16 (BasicModeCtrl, value);
1277 RTL_W8 (Cfg9346, Cfg9346_Lock);
1278 } else if (location < 8 && mii_2_8139_map[location])
1279 RTL_W16 (mii_2_8139_map[location], value);
1280 return;
1281 }
1282
1283 #ifdef CONFIG_8139TOO_8129
1284 mdio_sync (ioaddr);
1285
1286 /* Shift the command bits out. */
1287 for (i = 31; i >= 0; i--) {
1288 int dataval =
1289 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1290 RTL_W8 (Config4, dataval);
1291 mdio_delay ();
1292 RTL_W8 (Config4, dataval | MDIO_CLK);
1293 mdio_delay ();
1294 }
1295 /* Clear out extra bits. */
1296 for (i = 2; i > 0; i--) {
1297 RTL_W8 (Config4, 0);
1298 mdio_delay ();
1299 RTL_W8 (Config4, MDIO_CLK);
1300 mdio_delay ();
1301 }
1302 #endif
1303 }
1304
1305
1306 static int rtl8139_open (struct net_device *dev)
1307 {
1308 struct rtl8139_private *tp = netdev_priv(dev);
1309 int retval;
1310 void __iomem *ioaddr = tp->mmio_addr;
1311
1312 retval = request_irq (dev->irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
1313 if (retval)
1314 return retval;
1315
1316 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1317 &tp->tx_bufs_dma, GFP_KERNEL);
1318 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1319 &tp->rx_ring_dma, GFP_KERNEL);
1320 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1321 free_irq(dev->irq, dev);
1322
1323 if (tp->tx_bufs)
1324 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1325 tp->tx_bufs, tp->tx_bufs_dma);
1326 if (tp->rx_ring)
1327 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1328 tp->rx_ring, tp->rx_ring_dma);
1329
1330 return -ENOMEM;
1331
1332 }
1333
1334 napi_enable(&tp->napi);
1335
1336 tp->mii.full_duplex = tp->mii.force_media;
1337 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1338
1339 rtl8139_init_ring (dev);
1340 rtl8139_hw_start (dev);
1341 netif_start_queue (dev);
1342
1343 if (netif_msg_ifup(tp))
1344 printk(KERN_DEBUG "%s: rtl8139_open() ioaddr %#llx IRQ %d"
1345 " GP Pins %2.2x %s-duplex.\n", dev->name,
1346 (unsigned long long)pci_resource_start (tp->pci_dev, 1),
1347 dev->irq, RTL_R8 (MediaStatus),
1348 tp->mii.full_duplex ? "full" : "half");
1349
1350 rtl8139_start_thread(tp);
1351
1352 return 0;
1353 }
1354
1355
1356 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1357 {
1358 struct rtl8139_private *tp = netdev_priv(dev);
1359
1360 if (tp->phys[0] >= 0) {
1361 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1362 }
1363 }
1364
1365 /* Start the hardware at open or resume. */
1366 static void rtl8139_hw_start (struct net_device *dev)
1367 {
1368 struct rtl8139_private *tp = netdev_priv(dev);
1369 void __iomem *ioaddr = tp->mmio_addr;
1370 u32 i;
1371 u8 tmp;
1372
1373 /* Bring old chips out of low-power mode. */
1374 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1375 RTL_W8 (HltClk, 'R');
1376
1377 rtl8139_chip_reset (ioaddr);
1378
1379 /* unlock Config[01234] and BMCR register writes */
1380 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1381 /* Restore our idea of the MAC address. */
1382 RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1383 RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4)));
1384
1385 /* Must enable Tx/Rx before setting transfer thresholds! */
1386 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1387
1388 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1389 RTL_W32 (RxConfig, tp->rx_config);
1390 RTL_W32 (TxConfig, rtl8139_tx_config);
1391
1392 tp->cur_rx = 0;
1393
1394 rtl_check_media (dev, 1);
1395
1396 if (tp->chipset >= CH_8139B) {
1397 /* Disable magic packet scanning, which is enabled
1398 * when PM is enabled in Config1. It can be reenabled
1399 * via ETHTOOL_SWOL if desired. */
1400 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1401 }
1402
1403 DPRINTK("init buffer addresses\n");
1404
1405 /* Lock Config[01234] and BMCR register writes */
1406 RTL_W8 (Cfg9346, Cfg9346_Lock);
1407
1408 /* init Rx ring buffer DMA address */
1409 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1410
1411 /* init Tx buffer DMA addresses */
1412 for (i = 0; i < NUM_TX_DESC; i++)
1413 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1414
1415 RTL_W32 (RxMissed, 0);
1416
1417 rtl8139_set_rx_mode (dev);
1418
1419 /* no early-rx interrupts */
1420 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1421
1422 /* make sure RxTx has started */
1423 tmp = RTL_R8 (ChipCmd);
1424 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1425 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1426
1427 /* Enable all known interrupts by setting the interrupt mask. */
1428 RTL_W16 (IntrMask, rtl8139_intr_mask);
1429 }
1430
1431
1432 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1433 static void rtl8139_init_ring (struct net_device *dev)
1434 {
1435 struct rtl8139_private *tp = netdev_priv(dev);
1436 int i;
1437
1438 tp->cur_rx = 0;
1439 tp->cur_tx = 0;
1440 tp->dirty_tx = 0;
1441
1442 for (i = 0; i < NUM_TX_DESC; i++)
1443 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1444 }
1445
1446
1447 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1448 static int next_tick = 3 * HZ;
1449
1450 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1451 static inline void rtl8139_tune_twister (struct net_device *dev,
1452 struct rtl8139_private *tp) {}
1453 #else
1454 enum TwisterParamVals {
1455 PARA78_default = 0x78fa8388,
1456 PARA7c_default = 0xcb38de43, /* param[0][3] */
1457 PARA7c_xxx = 0xcb38de43,
1458 };
1459
1460 static const unsigned long param[4][4] = {
1461 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1462 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1463 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1464 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1465 };
1466
1467 static void rtl8139_tune_twister (struct net_device *dev,
1468 struct rtl8139_private *tp)
1469 {
1470 int linkcase;
1471 void __iomem *ioaddr = tp->mmio_addr;
1472
1473 /* This is a complicated state machine to configure the "twister" for
1474 impedance/echos based on the cable length.
1475 All of this is magic and undocumented.
1476 */
1477 switch (tp->twistie) {
1478 case 1:
1479 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1480 /* We have link beat, let us tune the twister. */
1481 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1482 tp->twistie = 2; /* Change to state 2. */
1483 next_tick = HZ / 10;
1484 } else {
1485 /* Just put in some reasonable defaults for when beat returns. */
1486 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1487 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1488 RTL_W32 (PARA78, PARA78_default);
1489 RTL_W32 (PARA7c, PARA7c_default);
1490 tp->twistie = 0; /* Bail from future actions. */
1491 }
1492 break;
1493 case 2:
1494 /* Read how long it took to hear the echo. */
1495 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1496 if (linkcase == 0x7000)
1497 tp->twist_row = 3;
1498 else if (linkcase == 0x3000)
1499 tp->twist_row = 2;
1500 else if (linkcase == 0x1000)
1501 tp->twist_row = 1;
1502 else
1503 tp->twist_row = 0;
1504 tp->twist_col = 0;
1505 tp->twistie = 3; /* Change to state 2. */
1506 next_tick = HZ / 10;
1507 break;
1508 case 3:
1509 /* Put out four tuning parameters, one per 100msec. */
1510 if (tp->twist_col == 0)
1511 RTL_W16 (FIFOTMS, 0);
1512 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1513 [(int) tp->twist_col]);
1514 next_tick = HZ / 10;
1515 if (++tp->twist_col >= 4) {
1516 /* For short cables we are done.
1517 For long cables (row == 3) check for mistune. */
1518 tp->twistie =
1519 (tp->twist_row == 3) ? 4 : 0;
1520 }
1521 break;
1522 case 4:
1523 /* Special case for long cables: check for mistune. */
1524 if ((RTL_R16 (CSCR) &
1525 CSCR_LinkStatusBits) == 0x7000) {
1526 tp->twistie = 0;
1527 break;
1528 } else {
1529 RTL_W32 (PARA7c, 0xfb38de03);
1530 tp->twistie = 5;
1531 next_tick = HZ / 10;
1532 }
1533 break;
1534 case 5:
1535 /* Retune for shorter cable (column 2). */
1536 RTL_W32 (FIFOTMS, 0x20);
1537 RTL_W32 (PARA78, PARA78_default);
1538 RTL_W32 (PARA7c, PARA7c_default);
1539 RTL_W32 (FIFOTMS, 0x00);
1540 tp->twist_row = 2;
1541 tp->twist_col = 0;
1542 tp->twistie = 3;
1543 next_tick = HZ / 10;
1544 break;
1545
1546 default:
1547 /* do nothing */
1548 break;
1549 }
1550 }
1551 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1552
1553 static inline void rtl8139_thread_iter (struct net_device *dev,
1554 struct rtl8139_private *tp,
1555 void __iomem *ioaddr)
1556 {
1557 int mii_lpa;
1558
1559 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1560
1561 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1562 int duplex = (mii_lpa & LPA_100FULL)
1563 || (mii_lpa & 0x01C0) == 0x0040;
1564 if (tp->mii.full_duplex != duplex) {
1565 tp->mii.full_duplex = duplex;
1566
1567 if (mii_lpa) {
1568 printk (KERN_INFO
1569 "%s: Setting %s-duplex based on MII #%d link"
1570 " partner ability of %4.4x.\n",
1571 dev->name,
1572 tp->mii.full_duplex ? "full" : "half",
1573 tp->phys[0], mii_lpa);
1574 } else {
1575 printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
1576 dev->name);
1577 }
1578 #if 0
1579 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1580 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1581 RTL_W8 (Cfg9346, Cfg9346_Lock);
1582 #endif
1583 }
1584 }
1585
1586 next_tick = HZ * 60;
1587
1588 rtl8139_tune_twister (dev, tp);
1589
1590 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1591 dev->name, RTL_R16 (NWayLPAR));
1592 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
1593 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
1594 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1595 dev->name, RTL_R8 (Config0),
1596 RTL_R8 (Config1));
1597 }
1598
1599 static void rtl8139_thread (struct work_struct *work)
1600 {
1601 struct rtl8139_private *tp =
1602 container_of(work, struct rtl8139_private, thread.work);
1603 struct net_device *dev = tp->mii.dev;
1604 unsigned long thr_delay = next_tick;
1605
1606 rtnl_lock();
1607
1608 if (!netif_running(dev))
1609 goto out_unlock;
1610
1611 if (tp->watchdog_fired) {
1612 tp->watchdog_fired = 0;
1613 rtl8139_tx_timeout_task(work);
1614 } else
1615 rtl8139_thread_iter(dev, tp, tp->mmio_addr);
1616
1617 if (tp->have_thread)
1618 schedule_delayed_work(&tp->thread, thr_delay);
1619 out_unlock:
1620 rtnl_unlock ();
1621 }
1622
1623 static void rtl8139_start_thread(struct rtl8139_private *tp)
1624 {
1625 tp->twistie = 0;
1626 if (tp->chipset == CH_8139_K)
1627 tp->twistie = 1;
1628 else if (tp->drv_flags & HAS_LNK_CHNG)
1629 return;
1630
1631 tp->have_thread = 1;
1632 tp->watchdog_fired = 0;
1633
1634 schedule_delayed_work(&tp->thread, next_tick);
1635 }
1636
1637 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1638 {
1639 tp->cur_tx = 0;
1640 tp->dirty_tx = 0;
1641
1642 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1643 }
1644
1645 static void rtl8139_tx_timeout_task (struct work_struct *work)
1646 {
1647 struct rtl8139_private *tp =
1648 container_of(work, struct rtl8139_private, thread.work);
1649 struct net_device *dev = tp->mii.dev;
1650 void __iomem *ioaddr = tp->mmio_addr;
1651 int i;
1652 u8 tmp8;
1653
1654 printk (KERN_DEBUG "%s: Transmit timeout, status %2.2x %4.4x %4.4x "
1655 "media %2.2x.\n", dev->name, RTL_R8 (ChipCmd),
1656 RTL_R16(IntrStatus), RTL_R16(IntrMask), RTL_R8(MediaStatus));
1657 /* Emit info to figure out what went wrong. */
1658 printk (KERN_DEBUG "%s: Tx queue start entry %ld dirty entry %ld.\n",
1659 dev->name, tp->cur_tx, tp->dirty_tx);
1660 for (i = 0; i < NUM_TX_DESC; i++)
1661 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1662 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1663 i == tp->dirty_tx % NUM_TX_DESC ?
1664 " (queue head)" : "");
1665
1666 tp->xstats.tx_timeouts++;
1667
1668 /* disable Tx ASAP, if not already */
1669 tmp8 = RTL_R8 (ChipCmd);
1670 if (tmp8 & CmdTxEnb)
1671 RTL_W8 (ChipCmd, CmdRxEnb);
1672
1673 spin_lock_bh(&tp->rx_lock);
1674 /* Disable interrupts by clearing the interrupt mask. */
1675 RTL_W16 (IntrMask, 0x0000);
1676
1677 /* Stop a shared interrupt from scavenging while we are. */
1678 spin_lock_irq(&tp->lock);
1679 rtl8139_tx_clear (tp);
1680 spin_unlock_irq(&tp->lock);
1681
1682 /* ...and finally, reset everything */
1683 if (netif_running(dev)) {
1684 rtl8139_hw_start (dev);
1685 netif_wake_queue (dev);
1686 }
1687 spin_unlock_bh(&tp->rx_lock);
1688 }
1689
1690 static void rtl8139_tx_timeout (struct net_device *dev)
1691 {
1692 struct rtl8139_private *tp = netdev_priv(dev);
1693
1694 tp->watchdog_fired = 1;
1695 if (!tp->have_thread) {
1696 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1697 schedule_delayed_work(&tp->thread, next_tick);
1698 }
1699 }
1700
1701 static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1702 {
1703 struct rtl8139_private *tp = netdev_priv(dev);
1704 void __iomem *ioaddr = tp->mmio_addr;
1705 unsigned int entry;
1706 unsigned int len = skb->len;
1707 unsigned long flags;
1708
1709 /* Calculate the next Tx descriptor entry. */
1710 entry = tp->cur_tx % NUM_TX_DESC;
1711
1712 /* Note: the chip doesn't have auto-pad! */
1713 if (likely(len < TX_BUF_SIZE)) {
1714 if (len < ETH_ZLEN)
1715 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1716 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1717 dev_kfree_skb(skb);
1718 } else {
1719 dev_kfree_skb(skb);
1720 dev->stats.tx_dropped++;
1721 return 0;
1722 }
1723
1724 spin_lock_irqsave(&tp->lock, flags);
1725 /*
1726 * Writing to TxStatus triggers a DMA transfer of the data
1727 * copied to tp->tx_buf[entry] above. Use a memory barrier
1728 * to make sure that the device sees the updated data.
1729 */
1730 wmb();
1731 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1732 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1733
1734 dev->trans_start = jiffies;
1735
1736 tp->cur_tx++;
1737
1738 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1739 netif_stop_queue (dev);
1740 spin_unlock_irqrestore(&tp->lock, flags);
1741
1742 if (netif_msg_tx_queued(tp))
1743 printk (KERN_DEBUG "%s: Queued Tx packet size %u to slot %d.\n",
1744 dev->name, len, entry);
1745
1746 return 0;
1747 }
1748
1749
1750 static void rtl8139_tx_interrupt (struct net_device *dev,
1751 struct rtl8139_private *tp,
1752 void __iomem *ioaddr)
1753 {
1754 unsigned long dirty_tx, tx_left;
1755
1756 assert (dev != NULL);
1757 assert (ioaddr != NULL);
1758
1759 dirty_tx = tp->dirty_tx;
1760 tx_left = tp->cur_tx - dirty_tx;
1761 while (tx_left > 0) {
1762 int entry = dirty_tx % NUM_TX_DESC;
1763 int txstatus;
1764
1765 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1766
1767 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1768 break; /* It still hasn't been Txed */
1769
1770 /* Note: TxCarrierLost is always asserted at 100mbps. */
1771 if (txstatus & (TxOutOfWindow | TxAborted)) {
1772 /* There was an major error, log it. */
1773 if (netif_msg_tx_err(tp))
1774 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1775 dev->name, txstatus);
1776 dev->stats.tx_errors++;
1777 if (txstatus & TxAborted) {
1778 dev->stats.tx_aborted_errors++;
1779 RTL_W32 (TxConfig, TxClearAbt);
1780 RTL_W16 (IntrStatus, TxErr);
1781 wmb();
1782 }
1783 if (txstatus & TxCarrierLost)
1784 dev->stats.tx_carrier_errors++;
1785 if (txstatus & TxOutOfWindow)
1786 dev->stats.tx_window_errors++;
1787 } else {
1788 if (txstatus & TxUnderrun) {
1789 /* Add 64 to the Tx FIFO threshold. */
1790 if (tp->tx_flag < 0x00300000)
1791 tp->tx_flag += 0x00020000;
1792 dev->stats.tx_fifo_errors++;
1793 }
1794 dev->stats.collisions += (txstatus >> 24) & 15;
1795 dev->stats.tx_bytes += txstatus & 0x7ff;
1796 dev->stats.tx_packets++;
1797 }
1798
1799 dirty_tx++;
1800 tx_left--;
1801 }
1802
1803 #ifndef RTL8139_NDEBUG
1804 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1805 printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1806 dev->name, dirty_tx, tp->cur_tx);
1807 dirty_tx += NUM_TX_DESC;
1808 }
1809 #endif /* RTL8139_NDEBUG */
1810
1811 /* only wake the queue if we did work, and the queue is stopped */
1812 if (tp->dirty_tx != dirty_tx) {
1813 tp->dirty_tx = dirty_tx;
1814 mb();
1815 netif_wake_queue (dev);
1816 }
1817 }
1818
1819
1820 /* TODO: clean this up! Rx reset need not be this intensive */
1821 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1822 struct rtl8139_private *tp, void __iomem *ioaddr)
1823 {
1824 u8 tmp8;
1825 #ifdef CONFIG_8139_OLD_RX_RESET
1826 int tmp_work;
1827 #endif
1828
1829 if (netif_msg_rx_err (tp))
1830 printk(KERN_DEBUG "%s: Ethernet frame had errors, status %8.8x.\n",
1831 dev->name, rx_status);
1832 dev->stats.rx_errors++;
1833 if (!(rx_status & RxStatusOK)) {
1834 if (rx_status & RxTooLong) {
1835 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1836 dev->name, rx_status);
1837 /* A.C.: The chip hangs here. */
1838 }
1839 if (rx_status & (RxBadSymbol | RxBadAlign))
1840 dev->stats.rx_frame_errors++;
1841 if (rx_status & (RxRunt | RxTooLong))
1842 dev->stats.rx_length_errors++;
1843 if (rx_status & RxCRCErr)
1844 dev->stats.rx_crc_errors++;
1845 } else {
1846 tp->xstats.rx_lost_in_ring++;
1847 }
1848
1849 #ifndef CONFIG_8139_OLD_RX_RESET
1850 tmp8 = RTL_R8 (ChipCmd);
1851 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1852 RTL_W8 (ChipCmd, tmp8);
1853 RTL_W32 (RxConfig, tp->rx_config);
1854 tp->cur_rx = 0;
1855 #else
1856 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1857
1858 /* disable receive */
1859 RTL_W8_F (ChipCmd, CmdTxEnb);
1860 tmp_work = 200;
1861 while (--tmp_work > 0) {
1862 udelay(1);
1863 tmp8 = RTL_R8 (ChipCmd);
1864 if (!(tmp8 & CmdRxEnb))
1865 break;
1866 }
1867 if (tmp_work <= 0)
1868 printk (KERN_WARNING PFX "rx stop wait too long\n");
1869 /* restart receive */
1870 tmp_work = 200;
1871 while (--tmp_work > 0) {
1872 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1873 udelay(1);
1874 tmp8 = RTL_R8 (ChipCmd);
1875 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1876 break;
1877 }
1878 if (tmp_work <= 0)
1879 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1880
1881 /* and reinitialize all rx related registers */
1882 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1883 /* Must enable Tx/Rx before setting transfer thresholds! */
1884 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1885
1886 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1887 RTL_W32 (RxConfig, tp->rx_config);
1888 tp->cur_rx = 0;
1889
1890 DPRINTK("init buffer addresses\n");
1891
1892 /* Lock Config[01234] and BMCR register writes */
1893 RTL_W8 (Cfg9346, Cfg9346_Lock);
1894
1895 /* init Rx ring buffer DMA address */
1896 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1897
1898 /* A.C.: Reset the multicast list. */
1899 __set_rx_mode (dev);
1900 #endif
1901 }
1902
1903 #if RX_BUF_IDX == 3
1904 static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1905 u32 offset, unsigned int size)
1906 {
1907 u32 left = RX_BUF_LEN - offset;
1908
1909 if (size > left) {
1910 skb_copy_to_linear_data(skb, ring + offset, left);
1911 skb_copy_to_linear_data_offset(skb, left, ring, size - left);
1912 } else
1913 skb_copy_to_linear_data(skb, ring + offset, size);
1914 }
1915 #endif
1916
1917 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1918 {
1919 void __iomem *ioaddr = tp->mmio_addr;
1920 u16 status;
1921
1922 status = RTL_R16 (IntrStatus) & RxAckBits;
1923
1924 /* Clear out errors and receive interrupts */
1925 if (likely(status != 0)) {
1926 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1927 tp->dev->stats.rx_errors++;
1928 if (status & RxFIFOOver)
1929 tp->dev->stats.rx_fifo_errors++;
1930 }
1931 RTL_W16_F (IntrStatus, RxAckBits);
1932 }
1933 }
1934
1935 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1936 int budget)
1937 {
1938 void __iomem *ioaddr = tp->mmio_addr;
1939 int received = 0;
1940 unsigned char *rx_ring = tp->rx_ring;
1941 unsigned int cur_rx = tp->cur_rx;
1942 unsigned int rx_size = 0;
1943
1944 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1945 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx,
1946 RTL_R16 (RxBufAddr),
1947 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1948
1949 while (netif_running(dev) && received < budget
1950 && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1951 u32 ring_offset = cur_rx % RX_BUF_LEN;
1952 u32 rx_status;
1953 unsigned int pkt_size;
1954 struct sk_buff *skb;
1955
1956 rmb();
1957
1958 /* read size+status of next frame from DMA ring buffer */
1959 rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset));
1960 rx_size = rx_status >> 16;
1961 pkt_size = rx_size - 4;
1962
1963 if (netif_msg_rx_status(tp))
1964 printk(KERN_DEBUG "%s: rtl8139_rx() status %4.4x, size %4.4x,"
1965 " cur %4.4x.\n", dev->name, rx_status,
1966 rx_size, cur_rx);
1967 #if RTL8139_DEBUG > 2
1968 {
1969 int i;
1970 DPRINTK ("%s: Frame contents ", dev->name);
1971 for (i = 0; i < 70; i++)
1972 printk (" %2.2x",
1973 rx_ring[ring_offset + i]);
1974 printk (".\n");
1975 }
1976 #endif
1977
1978 /* Packet copy from FIFO still in progress.
1979 * Theoretically, this should never happen
1980 * since EarlyRx is disabled.
1981 */
1982 if (unlikely(rx_size == 0xfff0)) {
1983 if (!tp->fifo_copy_timeout)
1984 tp->fifo_copy_timeout = jiffies + 2;
1985 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1986 DPRINTK ("%s: hung FIFO. Reset.", dev->name);
1987 rx_size = 0;
1988 goto no_early_rx;
1989 }
1990 if (netif_msg_intr(tp)) {
1991 printk(KERN_DEBUG "%s: fifo copy in progress.",
1992 dev->name);
1993 }
1994 tp->xstats.early_rx++;
1995 break;
1996 }
1997
1998 no_early_rx:
1999 tp->fifo_copy_timeout = 0;
2000
2001 /* If Rx err or invalid rx_size/rx_status received
2002 * (which happens if we get lost in the ring),
2003 * Rx process gets reset, so we abort any further
2004 * Rx processing.
2005 */
2006 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
2007 (rx_size < 8) ||
2008 (!(rx_status & RxStatusOK)))) {
2009 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
2010 received = -1;
2011 goto out;
2012 }
2013
2014 /* Malloc up new buffer, compatible with net-2e. */
2015 /* Omit the four octet CRC from the length. */
2016
2017 skb = netdev_alloc_skb(dev, pkt_size + NET_IP_ALIGN);
2018 if (likely(skb)) {
2019 skb_reserve (skb, NET_IP_ALIGN); /* 16 byte align the IP fields. */
2020 #if RX_BUF_IDX == 3
2021 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2022 #else
2023 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size);
2024 #endif
2025 skb_put (skb, pkt_size);
2026
2027 skb->protocol = eth_type_trans (skb, dev);
2028
2029 dev->last_rx = jiffies;
2030 dev->stats.rx_bytes += pkt_size;
2031 dev->stats.rx_packets++;
2032
2033 netif_receive_skb (skb);
2034 } else {
2035 if (net_ratelimit())
2036 printk (KERN_WARNING
2037 "%s: Memory squeeze, dropping packet.\n",
2038 dev->name);
2039 dev->stats.rx_dropped++;
2040 }
2041 received++;
2042
2043 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2044 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2045
2046 rtl8139_isr_ack(tp);
2047 }
2048
2049 if (unlikely(!received || rx_size == 0xfff0))
2050 rtl8139_isr_ack(tp);
2051
2052 #if RTL8139_DEBUG > 1
2053 DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
2054 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
2055 RTL_R16 (RxBufAddr),
2056 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
2057 #endif
2058
2059 tp->cur_rx = cur_rx;
2060
2061 /*
2062 * The receive buffer should be mostly empty.
2063 * Tell NAPI to reenable the Rx irq.
2064 */
2065 if (tp->fifo_copy_timeout)
2066 received = budget;
2067
2068 out:
2069 return received;
2070 }
2071
2072
2073 static void rtl8139_weird_interrupt (struct net_device *dev,
2074 struct rtl8139_private *tp,
2075 void __iomem *ioaddr,
2076 int status, int link_changed)
2077 {
2078 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
2079 dev->name, status);
2080
2081 assert (dev != NULL);
2082 assert (tp != NULL);
2083 assert (ioaddr != NULL);
2084
2085 /* Update the error count. */
2086 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2087 RTL_W32 (RxMissed, 0);
2088
2089 if ((status & RxUnderrun) && link_changed &&
2090 (tp->drv_flags & HAS_LNK_CHNG)) {
2091 rtl_check_media(dev, 0);
2092 status &= ~RxUnderrun;
2093 }
2094
2095 if (status & (RxUnderrun | RxErr))
2096 dev->stats.rx_errors++;
2097
2098 if (status & PCSTimeout)
2099 dev->stats.rx_length_errors++;
2100 if (status & RxUnderrun)
2101 dev->stats.rx_fifo_errors++;
2102 if (status & PCIErr) {
2103 u16 pci_cmd_status;
2104 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2105 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2106
2107 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
2108 dev->name, pci_cmd_status);
2109 }
2110 }
2111
2112 static int rtl8139_poll(struct napi_struct *napi, int budget)
2113 {
2114 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi);
2115 struct net_device *dev = tp->dev;
2116 void __iomem *ioaddr = tp->mmio_addr;
2117 int work_done;
2118
2119 spin_lock(&tp->rx_lock);
2120 work_done = 0;
2121 if (likely(RTL_R16(IntrStatus) & RxAckBits))
2122 work_done += rtl8139_rx(dev, tp, budget);
2123
2124 if (work_done < budget) {
2125 unsigned long flags;
2126 /*
2127 * Order is important since data can get interrupted
2128 * again when we think we are done.
2129 */
2130 spin_lock_irqsave(&tp->lock, flags);
2131 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2132 __netif_rx_complete(dev, napi);
2133 spin_unlock_irqrestore(&tp->lock, flags);
2134 }
2135 spin_unlock(&tp->rx_lock);
2136
2137 return work_done;
2138 }
2139
2140 /* The interrupt handler does all of the Rx thread work and cleans up
2141 after the Tx thread. */
2142 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance)
2143 {
2144 struct net_device *dev = (struct net_device *) dev_instance;
2145 struct rtl8139_private *tp = netdev_priv(dev);
2146 void __iomem *ioaddr = tp->mmio_addr;
2147 u16 status, ackstat;
2148 int link_changed = 0; /* avoid bogus "uninit" warning */
2149 int handled = 0;
2150
2151 spin_lock (&tp->lock);
2152 status = RTL_R16 (IntrStatus);
2153
2154 /* shared irq? */
2155 if (unlikely((status & rtl8139_intr_mask) == 0))
2156 goto out;
2157
2158 handled = 1;
2159
2160 /* h/w no longer present (hotplug?) or major error, bail */
2161 if (unlikely(status == 0xFFFF))
2162 goto out;
2163
2164 /* close possible race's with dev_close */
2165 if (unlikely(!netif_running(dev))) {
2166 RTL_W16 (IntrMask, 0);
2167 goto out;
2168 }
2169
2170 /* Acknowledge all of the current interrupt sources ASAP, but
2171 an first get an additional status bit from CSCR. */
2172 if (unlikely(status & RxUnderrun))
2173 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2174
2175 ackstat = status & ~(RxAckBits | TxErr);
2176 if (ackstat)
2177 RTL_W16 (IntrStatus, ackstat);
2178
2179 /* Receive packets are processed by poll routine.
2180 If not running start it now. */
2181 if (status & RxAckBits){
2182 if (netif_rx_schedule_prep(dev, &tp->napi)) {
2183 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2184 __netif_rx_schedule(dev, &tp->napi);
2185 }
2186 }
2187
2188 /* Check uncommon events with one test. */
2189 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2190 rtl8139_weird_interrupt (dev, tp, ioaddr,
2191 status, link_changed);
2192
2193 if (status & (TxOK | TxErr)) {
2194 rtl8139_tx_interrupt (dev, tp, ioaddr);
2195 if (status & TxErr)
2196 RTL_W16 (IntrStatus, TxErr);
2197 }
2198 out:
2199 spin_unlock (&tp->lock);
2200
2201 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
2202 dev->name, RTL_R16 (IntrStatus));
2203 return IRQ_RETVAL(handled);
2204 }
2205
2206 #ifdef CONFIG_NET_POLL_CONTROLLER
2207 /*
2208 * Polling receive - used by netconsole and other diagnostic tools
2209 * to allow network i/o with interrupts disabled.
2210 */
2211 static void rtl8139_poll_controller(struct net_device *dev)
2212 {
2213 disable_irq(dev->irq);
2214 rtl8139_interrupt(dev->irq, dev);
2215 enable_irq(dev->irq);
2216 }
2217 #endif
2218
2219 static int rtl8139_close (struct net_device *dev)
2220 {
2221 struct rtl8139_private *tp = netdev_priv(dev);
2222 void __iomem *ioaddr = tp->mmio_addr;
2223 unsigned long flags;
2224
2225 netif_stop_queue(dev);
2226 napi_disable(&tp->napi);
2227
2228 if (netif_msg_ifdown(tp))
2229 printk(KERN_DEBUG "%s: Shutting down ethercard, status was 0x%4.4x.\n",
2230 dev->name, RTL_R16 (IntrStatus));
2231
2232 spin_lock_irqsave (&tp->lock, flags);
2233
2234 /* Stop the chip's Tx and Rx DMA processes. */
2235 RTL_W8 (ChipCmd, 0);
2236
2237 /* Disable interrupts by clearing the interrupt mask. */
2238 RTL_W16 (IntrMask, 0);
2239
2240 /* Update the error counts. */
2241 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2242 RTL_W32 (RxMissed, 0);
2243
2244 spin_unlock_irqrestore (&tp->lock, flags);
2245
2246 free_irq (dev->irq, dev);
2247
2248 rtl8139_tx_clear (tp);
2249
2250 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
2251 tp->rx_ring, tp->rx_ring_dma);
2252 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
2253 tp->tx_bufs, tp->tx_bufs_dma);
2254 tp->rx_ring = NULL;
2255 tp->tx_bufs = NULL;
2256
2257 /* Green! Put the chip in low-power mode. */
2258 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2259
2260 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2261 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2262
2263 return 0;
2264 }
2265
2266
2267 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2268 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2269 other threads or interrupts aren't messing with the 8139. */
2270 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2271 {
2272 struct rtl8139_private *np = netdev_priv(dev);
2273 void __iomem *ioaddr = np->mmio_addr;
2274
2275 spin_lock_irq(&np->lock);
2276 if (rtl_chip_info[np->chipset].flags & HasLWake) {
2277 u8 cfg3 = RTL_R8 (Config3);
2278 u8 cfg5 = RTL_R8 (Config5);
2279
2280 wol->supported = WAKE_PHY | WAKE_MAGIC
2281 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2282
2283 wol->wolopts = 0;
2284 if (cfg3 & Cfg3_LinkUp)
2285 wol->wolopts |= WAKE_PHY;
2286 if (cfg3 & Cfg3_Magic)
2287 wol->wolopts |= WAKE_MAGIC;
2288 /* (KON)FIXME: See how netdev_set_wol() handles the
2289 following constants. */
2290 if (cfg5 & Cfg5_UWF)
2291 wol->wolopts |= WAKE_UCAST;
2292 if (cfg5 & Cfg5_MWF)
2293 wol->wolopts |= WAKE_MCAST;
2294 if (cfg5 & Cfg5_BWF)
2295 wol->wolopts |= WAKE_BCAST;
2296 }
2297 spin_unlock_irq(&np->lock);
2298 }
2299
2300
2301 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2302 that wol points to kernel memory and other threads or interrupts
2303 aren't messing with the 8139. */
2304 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2305 {
2306 struct rtl8139_private *np = netdev_priv(dev);
2307 void __iomem *ioaddr = np->mmio_addr;
2308 u32 support;
2309 u8 cfg3, cfg5;
2310
2311 support = ((rtl_chip_info[np->chipset].flags & HasLWake)
2312 ? (WAKE_PHY | WAKE_MAGIC
2313 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2314 : 0);
2315 if (wol->wolopts & ~support)
2316 return -EINVAL;
2317
2318 spin_lock_irq(&np->lock);
2319 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2320 if (wol->wolopts & WAKE_PHY)
2321 cfg3 |= Cfg3_LinkUp;
2322 if (wol->wolopts & WAKE_MAGIC)
2323 cfg3 |= Cfg3_Magic;
2324 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2325 RTL_W8 (Config3, cfg3);
2326 RTL_W8 (Cfg9346, Cfg9346_Lock);
2327
2328 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2329 /* (KON)FIXME: These are untested. We may have to set the
2330 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2331 documentation. */
2332 if (wol->wolopts & WAKE_UCAST)
2333 cfg5 |= Cfg5_UWF;
2334 if (wol->wolopts & WAKE_MCAST)
2335 cfg5 |= Cfg5_MWF;
2336 if (wol->wolopts & WAKE_BCAST)
2337 cfg5 |= Cfg5_BWF;
2338 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2339 spin_unlock_irq(&np->lock);
2340
2341 return 0;
2342 }
2343
2344 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2345 {
2346 struct rtl8139_private *np = netdev_priv(dev);
2347 strcpy(info->driver, DRV_NAME);
2348 strcpy(info->version, DRV_VERSION);
2349 strcpy(info->bus_info, pci_name(np->pci_dev));
2350 info->regdump_len = np->regs_len;
2351 }
2352
2353 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2354 {
2355 struct rtl8139_private *np = netdev_priv(dev);
2356 spin_lock_irq(&np->lock);
2357 mii_ethtool_gset(&np->mii, cmd);
2358 spin_unlock_irq(&np->lock);
2359 return 0;
2360 }
2361
2362 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2363 {
2364 struct rtl8139_private *np = netdev_priv(dev);
2365 int rc;
2366 spin_lock_irq(&np->lock);
2367 rc = mii_ethtool_sset(&np->mii, cmd);
2368 spin_unlock_irq(&np->lock);
2369 return rc;
2370 }
2371
2372 static int rtl8139_nway_reset(struct net_device *dev)
2373 {
2374 struct rtl8139_private *np = netdev_priv(dev);
2375 return mii_nway_restart(&np->mii);
2376 }
2377
2378 static u32 rtl8139_get_link(struct net_device *dev)
2379 {
2380 struct rtl8139_private *np = netdev_priv(dev);
2381 return mii_link_ok(&np->mii);
2382 }
2383
2384 static u32 rtl8139_get_msglevel(struct net_device *dev)
2385 {
2386 struct rtl8139_private *np = netdev_priv(dev);
2387 return np->msg_enable;
2388 }
2389
2390 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2391 {
2392 struct rtl8139_private *np = netdev_priv(dev);
2393 np->msg_enable = datum;
2394 }
2395
2396 static int rtl8139_get_regs_len(struct net_device *dev)
2397 {
2398 struct rtl8139_private *np;
2399 /* TODO: we are too slack to do reg dumping for pio, for now */
2400 if (use_io)
2401 return 0;
2402 np = netdev_priv(dev);
2403 return np->regs_len;
2404 }
2405
2406 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2407 {
2408 struct rtl8139_private *np;
2409
2410 /* TODO: we are too slack to do reg dumping for pio, for now */
2411 if (use_io)
2412 return;
2413 np = netdev_priv(dev);
2414
2415 regs->version = RTL_REGS_VER;
2416
2417 spin_lock_irq(&np->lock);
2418 memcpy_fromio(regbuf, np->mmio_addr, regs->len);
2419 spin_unlock_irq(&np->lock);
2420 }
2421
2422 static int rtl8139_get_sset_count(struct net_device *dev, int sset)
2423 {
2424 switch (sset) {
2425 case ETH_SS_STATS:
2426 return RTL_NUM_STATS;
2427 default:
2428 return -EOPNOTSUPP;
2429 }
2430 }
2431
2432 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2433 {
2434 struct rtl8139_private *np = netdev_priv(dev);
2435
2436 data[0] = np->xstats.early_rx;
2437 data[1] = np->xstats.tx_buf_mapped;
2438 data[2] = np->xstats.tx_timeouts;
2439 data[3] = np->xstats.rx_lost_in_ring;
2440 }
2441
2442 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2443 {
2444 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2445 }
2446
2447 static const struct ethtool_ops rtl8139_ethtool_ops = {
2448 .get_drvinfo = rtl8139_get_drvinfo,
2449 .get_settings = rtl8139_get_settings,
2450 .set_settings = rtl8139_set_settings,
2451 .get_regs_len = rtl8139_get_regs_len,
2452 .get_regs = rtl8139_get_regs,
2453 .nway_reset = rtl8139_nway_reset,
2454 .get_link = rtl8139_get_link,
2455 .get_msglevel = rtl8139_get_msglevel,
2456 .set_msglevel = rtl8139_set_msglevel,
2457 .get_wol = rtl8139_get_wol,
2458 .set_wol = rtl8139_set_wol,
2459 .get_strings = rtl8139_get_strings,
2460 .get_sset_count = rtl8139_get_sset_count,
2461 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2462 };
2463
2464 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2465 {
2466 struct rtl8139_private *np = netdev_priv(dev);
2467 int rc;
2468
2469 if (!netif_running(dev))
2470 return -EINVAL;
2471
2472 spin_lock_irq(&np->lock);
2473 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
2474 spin_unlock_irq(&np->lock);
2475
2476 return rc;
2477 }
2478
2479
2480 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2481 {
2482 struct rtl8139_private *tp = netdev_priv(dev);
2483 void __iomem *ioaddr = tp->mmio_addr;
2484 unsigned long flags;
2485
2486 if (netif_running(dev)) {
2487 spin_lock_irqsave (&tp->lock, flags);
2488 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2489 RTL_W32 (RxMissed, 0);
2490 spin_unlock_irqrestore (&tp->lock, flags);
2491 }
2492
2493 return &dev->stats;
2494 }
2495
2496 /* Set or clear the multicast filter for this adaptor.
2497 This routine is not state sensitive and need not be SMP locked. */
2498
2499 static void __set_rx_mode (struct net_device *dev)
2500 {
2501 struct rtl8139_private *tp = netdev_priv(dev);
2502 void __iomem *ioaddr = tp->mmio_addr;
2503 u32 mc_filter[2]; /* Multicast hash filter */
2504 int i, rx_mode;
2505 u32 tmp;
2506
2507 DPRINTK ("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2508 dev->name, dev->flags, RTL_R32 (RxConfig));
2509
2510 /* Note: do not reorder, GCC is clever about common statements. */
2511 if (dev->flags & IFF_PROMISC) {
2512 rx_mode =
2513 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2514 AcceptAllPhys;
2515 mc_filter[1] = mc_filter[0] = 0xffffffff;
2516 } else if ((dev->mc_count > multicast_filter_limit)
2517 || (dev->flags & IFF_ALLMULTI)) {
2518 /* Too many to filter perfectly -- accept all multicasts. */
2519 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2520 mc_filter[1] = mc_filter[0] = 0xffffffff;
2521 } else {
2522 struct dev_mc_list *mclist;
2523 rx_mode = AcceptBroadcast | AcceptMyPhys;
2524 mc_filter[1] = mc_filter[0] = 0;
2525 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2526 i++, mclist = mclist->next) {
2527 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2528
2529 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2530 rx_mode |= AcceptMulticast;
2531 }
2532 }
2533
2534 /* We can safely update without stopping the chip. */
2535 tmp = rtl8139_rx_config | rx_mode;
2536 if (tp->rx_config != tmp) {
2537 RTL_W32_F (RxConfig, tmp);
2538 tp->rx_config = tmp;
2539 }
2540 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2541 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2542 }
2543
2544 static void rtl8139_set_rx_mode (struct net_device *dev)
2545 {
2546 unsigned long flags;
2547 struct rtl8139_private *tp = netdev_priv(dev);
2548
2549 spin_lock_irqsave (&tp->lock, flags);
2550 __set_rx_mode(dev);
2551 spin_unlock_irqrestore (&tp->lock, flags);
2552 }
2553
2554 #ifdef CONFIG_PM
2555
2556 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2557 {
2558 struct net_device *dev = pci_get_drvdata (pdev);
2559 struct rtl8139_private *tp = netdev_priv(dev);
2560 void __iomem *ioaddr = tp->mmio_addr;
2561 unsigned long flags;
2562
2563 pci_save_state (pdev);
2564
2565 if (!netif_running (dev))
2566 return 0;
2567
2568 netif_device_detach (dev);
2569
2570 spin_lock_irqsave (&tp->lock, flags);
2571
2572 /* Disable interrupts, stop Tx and Rx. */
2573 RTL_W16 (IntrMask, 0);
2574 RTL_W8 (ChipCmd, 0);
2575
2576 /* Update the error counts. */
2577 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2578 RTL_W32 (RxMissed, 0);
2579
2580 spin_unlock_irqrestore (&tp->lock, flags);
2581
2582 pci_set_power_state (pdev, PCI_D3hot);
2583
2584 return 0;
2585 }
2586
2587
2588 static int rtl8139_resume (struct pci_dev *pdev)
2589 {
2590 struct net_device *dev = pci_get_drvdata (pdev);
2591
2592 pci_restore_state (pdev);
2593 if (!netif_running (dev))
2594 return 0;
2595 pci_set_power_state (pdev, PCI_D0);
2596 rtl8139_init_ring (dev);
2597 rtl8139_hw_start (dev);
2598 netif_device_attach (dev);
2599 return 0;
2600 }
2601
2602 #endif /* CONFIG_PM */
2603
2604
2605 static struct pci_driver rtl8139_pci_driver = {
2606 .name = DRV_NAME,
2607 .id_table = rtl8139_pci_tbl,
2608 .probe = rtl8139_init_one,
2609 .remove = __devexit_p(rtl8139_remove_one),
2610 #ifdef CONFIG_PM
2611 .suspend = rtl8139_suspend,
2612 .resume = rtl8139_resume,
2613 #endif /* CONFIG_PM */
2614 };
2615
2616
2617 static int __init rtl8139_init_module (void)
2618 {
2619 /* when we're a module, we always print a version message,
2620 * even if no 8139 board is found.
2621 */
2622 #ifdef MODULE
2623 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2624 #endif
2625
2626 return pci_register_driver(&rtl8139_pci_driver);
2627 }
2628
2629
2630 static void __exit rtl8139_cleanup_module (void)
2631 {
2632 pci_unregister_driver (&rtl8139_pci_driver);
2633 }
2634
2635
2636 module_init(rtl8139_init_module);
2637 module_exit(rtl8139_cleanup_module);
Stable & featurefull patchset based on Linus's git branch