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powerpc/pmac: Fix issues with sleep on some powerbooks
[linux-2.6/verdex.git] / sound / soc / codecs / tlv320aic3x.c
blobcb0d1bf34b5723b9933ffc023430100b0594511d
1 /*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33.
16 *
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 is as follows:
19 * aic32 | aic31
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
33 */
34
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/pm.h>
40 #include <linux/i2c.h>
41 #include <linux/platform_device.h>
42 #include <sound/core.h>
43 #include <sound/pcm.h>
44 #include <sound/pcm_params.h>
45 #include <sound/soc.h>
46 #include <sound/soc-dapm.h>
47 #include <sound/initval.h>
48 #include <sound/tlv.h>
49
50 #include "tlv320aic3x.h"
51
52 #define AIC3X_VERSION "0.2"
53
54 /* codec private data */
55 struct aic3x_priv {
56 unsigned int sysclk;
57 int master;
58 };
59
60 /*
61 * AIC3X register cache
62 * We can't read the AIC3X register space when we are
63 * using 2 wire for device control, so we cache them instead.
64 * There is no point in caching the reset register
65 */
66 static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
67 0x00, 0x00, 0x00, 0x10, /* 0 */
68 0x04, 0x00, 0x00, 0x00, /* 4 */
69 0x00, 0x00, 0x00, 0x01, /* 8 */
70 0x00, 0x00, 0x00, 0x80, /* 12 */
71 0x80, 0xff, 0xff, 0x78, /* 16 */
72 0x78, 0x78, 0x78, 0x78, /* 20 */
73 0x78, 0x00, 0x00, 0xfe, /* 24 */
74 0x00, 0x00, 0xfe, 0x00, /* 28 */
75 0x18, 0x18, 0x00, 0x00, /* 32 */
76 0x00, 0x00, 0x00, 0x00, /* 36 */
77 0x00, 0x00, 0x00, 0x80, /* 40 */
78 0x80, 0x00, 0x00, 0x00, /* 44 */
79 0x00, 0x00, 0x00, 0x04, /* 48 */
80 0x00, 0x00, 0x00, 0x00, /* 52 */
81 0x00, 0x00, 0x04, 0x00, /* 56 */
82 0x00, 0x00, 0x00, 0x00, /* 60 */
83 0x00, 0x04, 0x00, 0x00, /* 64 */
84 0x00, 0x00, 0x00, 0x00, /* 68 */
85 0x04, 0x00, 0x00, 0x00, /* 72 */
86 0x00, 0x00, 0x00, 0x00, /* 76 */
87 0x00, 0x00, 0x00, 0x00, /* 80 */
88 0x00, 0x00, 0x00, 0x00, /* 84 */
89 0x00, 0x00, 0x00, 0x00, /* 88 */
90 0x00, 0x00, 0x00, 0x00, /* 92 */
91 0x00, 0x00, 0x00, 0x00, /* 96 */
92 0x00, 0x00, 0x02, /* 100 */
93 };
94
95 /*
96 * read aic3x register cache
97 */
98 static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec,
99 unsigned int reg)
100 {
101 u8 *cache = codec->reg_cache;
102 if (reg >= AIC3X_CACHEREGNUM)
103 return -1;
104 return cache[reg];
105 }
106
107 /*
108 * write aic3x register cache
109 */
110 static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec,
111 u8 reg, u8 value)
112 {
113 u8 *cache = codec->reg_cache;
114 if (reg >= AIC3X_CACHEREGNUM)
115 return;
116 cache[reg] = value;
117 }
118
119 /*
120 * write to the aic3x register space
121 */
122 static int aic3x_write(struct snd_soc_codec *codec, unsigned int reg,
123 unsigned int value)
124 {
125 u8 data[2];
126
127 /* data is
128 * D15..D8 aic3x register offset
129 * D7...D0 register data
130 */
131 data[0] = reg & 0xff;
132 data[1] = value & 0xff;
133
134 aic3x_write_reg_cache(codec, data[0], data[1]);
135 if (codec->hw_write(codec->control_data, data, 2) == 2)
136 return 0;
137 else
138 return -EIO;
139 }
140
141 /*
142 * read from the aic3x register space
143 */
144 static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
145 u8 *value)
146 {
147 *value = reg & 0xff;
148 if (codec->hw_read(codec->control_data, value, 1) != 1)
149 return -EIO;
150
151 aic3x_write_reg_cache(codec, reg, *value);
152 return 0;
153 }
154
155 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
156 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
157 .info = snd_soc_info_volsw, \
158 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
159 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
160
161 /*
162 * All input lines are connected when !0xf and disconnected with 0xf bit field,
163 * so we have to use specific dapm_put call for input mixer
164 */
165 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
166 struct snd_ctl_elem_value *ucontrol)
167 {
168 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
169 struct soc_mixer_control *mc =
170 (struct soc_mixer_control *)kcontrol->private_value;
171 unsigned int reg = mc->reg;
172 unsigned int shift = mc->shift;
173 int max = mc->max;
174 unsigned int mask = (1 << fls(max)) - 1;
175 unsigned int invert = mc->invert;
176 unsigned short val, val_mask;
177 int ret;
178 struct snd_soc_dapm_path *path;
179 int found = 0;
180
181 val = (ucontrol->value.integer.value[0] & mask);
182
183 mask = 0xf;
184 if (val)
185 val = mask;
186
187 if (invert)
188 val = mask - val;
189 val_mask = mask << shift;
190 val = val << shift;
191
192 mutex_lock(&widget->codec->mutex);
193
194 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
195 /* find dapm widget path assoc with kcontrol */
196 list_for_each_entry(path, &widget->codec->dapm_paths, list) {
197 if (path->kcontrol != kcontrol)
198 continue;
199
200 /* found, now check type */
201 found = 1;
202 if (val)
203 /* new connection */
204 path->connect = invert ? 0 : 1;
205 else
206 /* old connection must be powered down */
207 path->connect = invert ? 1 : 0;
208 break;
209 }
210
211 if (found)
212 snd_soc_dapm_sync(widget->codec);
213 }
214
215 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
216
217 mutex_unlock(&widget->codec->mutex);
218 return ret;
219 }
220
221 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
222 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
223 static const char *aic3x_left_hpcom_mux[] =
224 { "differential of HPLOUT", "constant VCM", "single-ended" };
225 static const char *aic3x_right_hpcom_mux[] =
226 { "differential of HPROUT", "constant VCM", "single-ended",
227 "differential of HPLCOM", "external feedback" };
228 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
229 static const char *aic3x_adc_hpf[] =
230 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
231
232 #define LDAC_ENUM 0
233 #define RDAC_ENUM 1
234 #define LHPCOM_ENUM 2
235 #define RHPCOM_ENUM 3
236 #define LINE1L_ENUM 4
237 #define LINE1R_ENUM 5
238 #define LINE2L_ENUM 6
239 #define LINE2R_ENUM 7
240 #define ADC_HPF_ENUM 8
241
242 static const struct soc_enum aic3x_enum[] = {
243 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
244 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
245 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
246 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
247 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
248 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
249 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
250 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
251 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
252 };
253
254 /*
255 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
256 */
257 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
258 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
259 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
260 /*
261 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
262 * Step size is approximately 0.5 dB over most of the scale but increasing
263 * near the very low levels.
264 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
265 * but having increasing dB difference below that (and where it doesn't count
266 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
267 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
268 */
269 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
270
271 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
272 /* Output */
273 SOC_DOUBLE_R_TLV("PCM Playback Volume",
274 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
275
276 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
277 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
278 0, 118, 1, output_stage_tlv),
279 SOC_SINGLE("LineL Playback Switch", LLOPM_CTRL, 3, 0x01, 0),
280 SOC_SINGLE("LineR Playback Switch", RLOPM_CTRL, 3, 0x01, 0),
281 SOC_DOUBLE_R_TLV("LineL DAC Playback Volume",
282 DACL1_2_LLOPM_VOL, DACR1_2_LLOPM_VOL,
283 0, 118, 1, output_stage_tlv),
284 SOC_SINGLE_TLV("LineL Left PGA Bypass Playback Volume",
285 PGAL_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
286 SOC_SINGLE_TLV("LineR Right PGA Bypass Playback Volume",
287 PGAR_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
288 SOC_DOUBLE_R_TLV("LineL Line2 Bypass Playback Volume",
289 LINE2L_2_LLOPM_VOL, LINE2R_2_LLOPM_VOL,
290 0, 118, 1, output_stage_tlv),
291 SOC_DOUBLE_R_TLV("LineR Line2 Bypass Playback Volume",
292 LINE2L_2_RLOPM_VOL, LINE2R_2_RLOPM_VOL,
293 0, 118, 1, output_stage_tlv),
294
295 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
296 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
297 0, 118, 1, output_stage_tlv),
298 SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
299 SOC_DOUBLE_R_TLV("Mono PGA Bypass Playback Volume",
300 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
301 0, 118, 1, output_stage_tlv),
302 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Playback Volume",
303 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
304 0, 118, 1, output_stage_tlv),
305
306 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
307 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
308 0, 118, 1, output_stage_tlv),
309 SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
310 0x01, 0),
311 SOC_DOUBLE_R_TLV("HP Right PGA Bypass Playback Volume",
312 PGAR_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
313 0, 118, 1, output_stage_tlv),
314 SOC_SINGLE_TLV("HPL PGA Bypass Playback Volume",
315 PGAL_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
316 SOC_SINGLE_TLV("HPR PGA Bypass Playback Volume",
317 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
318 SOC_DOUBLE_R_TLV("HP Line2 Bypass Playback Volume",
319 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
320 0, 118, 1, output_stage_tlv),
321
322 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
323 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
324 0, 118, 1, output_stage_tlv),
325 SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
326 0x01, 0),
327 SOC_SINGLE_TLV("HPLCOM PGA Bypass Playback Volume",
328 PGAL_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
329 SOC_SINGLE_TLV("HPRCOM PGA Bypass Playback Volume",
330 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
331 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Playback Volume",
332 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
333 0, 118, 1, output_stage_tlv),
334
335 /*
336 * Note: enable Automatic input Gain Controller with care. It can
337 * adjust PGA to max value when ADC is on and will never go back.
338 */
339 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
340
341 /* Input */
342 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
343 0, 119, 0, adc_tlv),
344 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
345
346 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
347 };
348
349 /* Left DAC Mux */
350 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
351 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
352
353 /* Right DAC Mux */
354 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
355 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
356
357 /* Left HPCOM Mux */
358 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
359 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
360
361 /* Right HPCOM Mux */
362 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
363 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
364
365 /* Left DAC_L1 Mixer */
366 static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = {
367 SOC_DAPM_SINGLE("LineL Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
368 SOC_DAPM_SINGLE("LineR Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
369 SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
370 SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
371 SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
372 };
373
374 /* Right DAC_R1 Mixer */
375 static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = {
376 SOC_DAPM_SINGLE("LineL Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
377 SOC_DAPM_SINGLE("LineR Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
378 SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
379 SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
380 SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
381 };
382
383 /* Left PGA Mixer */
384 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
385 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
386 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
387 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
388 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
389 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
390 };
391
392 /* Right PGA Mixer */
393 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
394 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
395 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
396 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
397 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
398 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
399 };
400
401 /* Left Line1 Mux */
402 static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
403 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
404
405 /* Right Line1 Mux */
406 static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
407 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
408
409 /* Left Line2 Mux */
410 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
411 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
412
413 /* Right Line2 Mux */
414 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
415 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
416
417 /* Left PGA Bypass Mixer */
418 static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = {
419 SOC_DAPM_SINGLE("LineL Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
420 SOC_DAPM_SINGLE("LineR Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
421 SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
422 SOC_DAPM_SINGLE("HPL Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
423 SOC_DAPM_SINGLE("HPR Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
424 SOC_DAPM_SINGLE("HPLCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
425 SOC_DAPM_SINGLE("HPRCOM Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
426 };
427
428 /* Right PGA Bypass Mixer */
429 static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = {
430 SOC_DAPM_SINGLE("LineL Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
431 SOC_DAPM_SINGLE("LineR Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
432 SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
433 SOC_DAPM_SINGLE("HPL Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
434 SOC_DAPM_SINGLE("HPR Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
435 SOC_DAPM_SINGLE("HPLCOM Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
436 SOC_DAPM_SINGLE("HPRCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
437 };
438
439 /* Left Line2 Bypass Mixer */
440 static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = {
441 SOC_DAPM_SINGLE("LineL Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
442 SOC_DAPM_SINGLE("LineR Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
443 SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
444 SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
445 SOC_DAPM_SINGLE("HPLCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
446 };
447
448 /* Right Line2 Bypass Mixer */
449 static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = {
450 SOC_DAPM_SINGLE("LineL Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
451 SOC_DAPM_SINGLE("LineR Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
452 SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
453 SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
454 SOC_DAPM_SINGLE("HPRCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
455 };
456
457 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
458 /* Left DAC to Left Outputs */
459 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
460 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
461 &aic3x_left_dac_mux_controls),
462 SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0,
463 &aic3x_left_dac_mixer_controls[0],
464 ARRAY_SIZE(aic3x_left_dac_mixer_controls)),
465 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
466 &aic3x_left_hpcom_mux_controls),
467 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
468 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
469 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
470
471 /* Right DAC to Right Outputs */
472 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
473 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
474 &aic3x_right_dac_mux_controls),
475 SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0,
476 &aic3x_right_dac_mixer_controls[0],
477 ARRAY_SIZE(aic3x_right_dac_mixer_controls)),
478 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
479 &aic3x_right_hpcom_mux_controls),
480 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
481 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
482 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
483
484 /* Mono Output */
485 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
486
487 /* Inputs to Left ADC */
488 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
489 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
490 &aic3x_left_pga_mixer_controls[0],
491 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
492 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
493 &aic3x_left_line1_mux_controls),
494 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
495 &aic3x_left_line1_mux_controls),
496 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
497 &aic3x_left_line2_mux_controls),
498
499 /* Inputs to Right ADC */
500 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
501 LINE1R_2_RADC_CTRL, 2, 0),
502 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
503 &aic3x_right_pga_mixer_controls[0],
504 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
505 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
506 &aic3x_right_line1_mux_controls),
507 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
508 &aic3x_right_line1_mux_controls),
509 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
510 &aic3x_right_line2_mux_controls),
511
512 /*
513 * Not a real mic bias widget but similar function. This is for dynamic
514 * control of GPIO1 digital mic modulator clock output function when
515 * using digital mic.
516 */
517 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
518 AIC3X_GPIO1_REG, 4, 0xf,
519 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
520 AIC3X_GPIO1_FUNC_DISABLED),
521
522 /*
523 * Also similar function like mic bias. Selects digital mic with
524 * configurable oversampling rate instead of ADC converter.
525 */
526 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
527 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
528 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
529 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
530 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
531 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
532
533 /* Mic Bias */
534 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
535 MICBIAS_CTRL, 6, 3, 1, 0),
536 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
537 MICBIAS_CTRL, 6, 3, 2, 0),
538 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
539 MICBIAS_CTRL, 6, 3, 3, 0),
540
541 /* Left PGA to Left Output bypass */
542 SND_SOC_DAPM_MIXER("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
543 &aic3x_left_pga_bp_mixer_controls[0],
544 ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls)),
545
546 /* Right PGA to Right Output bypass */
547 SND_SOC_DAPM_MIXER("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
548 &aic3x_right_pga_bp_mixer_controls[0],
549 ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls)),
550
551 /* Left Line2 to Left Output bypass */
552 SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
553 &aic3x_left_line2_bp_mixer_controls[0],
554 ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)),
555
556 /* Right Line2 to Right Output bypass */
557 SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
558 &aic3x_right_line2_bp_mixer_controls[0],
559 ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)),
560
561 SND_SOC_DAPM_OUTPUT("LLOUT"),
562 SND_SOC_DAPM_OUTPUT("RLOUT"),
563 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
564 SND_SOC_DAPM_OUTPUT("HPLOUT"),
565 SND_SOC_DAPM_OUTPUT("HPROUT"),
566 SND_SOC_DAPM_OUTPUT("HPLCOM"),
567 SND_SOC_DAPM_OUTPUT("HPRCOM"),
568
569 SND_SOC_DAPM_INPUT("MIC3L"),
570 SND_SOC_DAPM_INPUT("MIC3R"),
571 SND_SOC_DAPM_INPUT("LINE1L"),
572 SND_SOC_DAPM_INPUT("LINE1R"),
573 SND_SOC_DAPM_INPUT("LINE2L"),
574 SND_SOC_DAPM_INPUT("LINE2R"),
575 };
576
577 static const struct snd_soc_dapm_route intercon[] = {
578 /* Left Output */
579 {"Left DAC Mux", "DAC_L1", "Left DAC"},
580 {"Left DAC Mux", "DAC_L2", "Left DAC"},
581 {"Left DAC Mux", "DAC_L3", "Left DAC"},
582
583 {"Left DAC_L1 Mixer", "LineL Switch", "Left DAC Mux"},
584 {"Left DAC_L1 Mixer", "LineR Switch", "Left DAC Mux"},
585 {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"},
586 {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"},
587 {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"},
588 {"Left Line Out", NULL, "Left DAC Mux"},
589 {"Left HP Out", NULL, "Left DAC Mux"},
590
591 {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"},
592 {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"},
593 {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"},
594
595 {"Left Line Out", NULL, "Left DAC_L1 Mixer"},
596 {"Mono Out", NULL, "Left DAC_L1 Mixer"},
597 {"Left HP Out", NULL, "Left DAC_L1 Mixer"},
598 {"Left HP Com", NULL, "Left HPCOM Mux"},
599
600 {"LLOUT", NULL, "Left Line Out"},
601 {"LLOUT", NULL, "Left Line Out"},
602 {"HPLOUT", NULL, "Left HP Out"},
603 {"HPLCOM", NULL, "Left HP Com"},
604
605 /* Right Output */
606 {"Right DAC Mux", "DAC_R1", "Right DAC"},
607 {"Right DAC Mux", "DAC_R2", "Right DAC"},
608 {"Right DAC Mux", "DAC_R3", "Right DAC"},
609
610 {"Right DAC_R1 Mixer", "LineL Switch", "Right DAC Mux"},
611 {"Right DAC_R1 Mixer", "LineR Switch", "Right DAC Mux"},
612 {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"},
613 {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"},
614 {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"},
615 {"Right Line Out", NULL, "Right DAC Mux"},
616 {"Right HP Out", NULL, "Right DAC Mux"},
617
618 {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"},
619 {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"},
620 {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"},
621 {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"},
622 {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"},
623
624 {"Right Line Out", NULL, "Right DAC_R1 Mixer"},
625 {"Mono Out", NULL, "Right DAC_R1 Mixer"},
626 {"Right HP Out", NULL, "Right DAC_R1 Mixer"},
627 {"Right HP Com", NULL, "Right HPCOM Mux"},
628
629 {"RLOUT", NULL, "Right Line Out"},
630 {"RLOUT", NULL, "Right Line Out"},
631 {"HPROUT", NULL, "Right HP Out"},
632 {"HPRCOM", NULL, "Right HP Com"},
633
634 /* Mono Output */
635 {"MONO_LOUT", NULL, "Mono Out"},
636 {"MONO_LOUT", NULL, "Mono Out"},
637
638 /* Left Input */
639 {"Left Line1L Mux", "single-ended", "LINE1L"},
640 {"Left Line1L Mux", "differential", "LINE1L"},
641
642 {"Left Line2L Mux", "single-ended", "LINE2L"},
643 {"Left Line2L Mux", "differential", "LINE2L"},
644
645 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
646 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
647 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
648 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
649 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
650
651 {"Left ADC", NULL, "Left PGA Mixer"},
652 {"Left ADC", NULL, "GPIO1 dmic modclk"},
653
654 /* Right Input */
655 {"Right Line1R Mux", "single-ended", "LINE1R"},
656 {"Right Line1R Mux", "differential", "LINE1R"},
657
658 {"Right Line2R Mux", "single-ended", "LINE2R"},
659 {"Right Line2R Mux", "differential", "LINE2R"},
660
661 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
662 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
663 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
664 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
665 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
666
667 {"Right ADC", NULL, "Right PGA Mixer"},
668 {"Right ADC", NULL, "GPIO1 dmic modclk"},
669
670 /* Left PGA Bypass */
671 {"Left PGA Bypass Mixer", "LineL Switch", "Left PGA Mixer"},
672 {"Left PGA Bypass Mixer", "LineR Switch", "Left PGA Mixer"},
673 {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"},
674 {"Left PGA Bypass Mixer", "HPL Switch", "Left PGA Mixer"},
675 {"Left PGA Bypass Mixer", "HPR Switch", "Left PGA Mixer"},
676 {"Left PGA Bypass Mixer", "HPLCOM Switch", "Left PGA Mixer"},
677 {"Left PGA Bypass Mixer", "HPRCOM Switch", "Left PGA Mixer"},
678
679 {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"},
680 {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"},
681 {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"},
682
683 {"Left Line Out", NULL, "Left PGA Bypass Mixer"},
684 {"Mono Out", NULL, "Left PGA Bypass Mixer"},
685 {"Left HP Out", NULL, "Left PGA Bypass Mixer"},
686
687 /* Right PGA Bypass */
688 {"Right PGA Bypass Mixer", "LineL Switch", "Right PGA Mixer"},
689 {"Right PGA Bypass Mixer", "LineR Switch", "Right PGA Mixer"},
690 {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"},
691 {"Right PGA Bypass Mixer", "HPL Switch", "Right PGA Mixer"},
692 {"Right PGA Bypass Mixer", "HPR Switch", "Right PGA Mixer"},
693 {"Right PGA Bypass Mixer", "HPLCOM Switch", "Right PGA Mixer"},
694 {"Right PGA Bypass Mixer", "HPRCOM Switch", "Right PGA Mixer"},
695
696 {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"},
697 {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"},
698 {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"},
699 {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"},
700 {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"},
701
702 {"Right Line Out", NULL, "Right PGA Bypass Mixer"},
703 {"Mono Out", NULL, "Right PGA Bypass Mixer"},
704 {"Right HP Out", NULL, "Right PGA Bypass Mixer"},
705
706 /* Left Line2 Bypass */
707 {"Left Line2 Bypass Mixer", "LineL Switch", "Left Line2L Mux"},
708 {"Left Line2 Bypass Mixer", "LineR Switch", "Left Line2L Mux"},
709 {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"},
710 {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"},
711 {"Left Line2 Bypass Mixer", "HPLCOM Switch", "Left Line2L Mux"},
712
713 {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"},
714 {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"},
715 {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"},
716
717 {"Left Line Out", NULL, "Left Line2 Bypass Mixer"},
718 {"Mono Out", NULL, "Left Line2 Bypass Mixer"},
719 {"Left HP Out", NULL, "Left Line2 Bypass Mixer"},
720
721 /* Right Line2 Bypass */
722 {"Right Line2 Bypass Mixer", "LineL Switch", "Right Line2R Mux"},
723 {"Right Line2 Bypass Mixer", "LineR Switch", "Right Line2R Mux"},
724 {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"},
725 {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"},
726 {"Right Line2 Bypass Mixer", "HPRCOM Switch", "Right Line2R Mux"},
727
728 {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"},
729 {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"},
730 {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"},
731 {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"},
732 {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"},
733
734 {"Right Line Out", NULL, "Right Line2 Bypass Mixer"},
735 {"Mono Out", NULL, "Right Line2 Bypass Mixer"},
736 {"Right HP Out", NULL, "Right Line2 Bypass Mixer"},
737
738 /*
739 * Logical path between digital mic enable and GPIO1 modulator clock
740 * output function
741 */
742 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
743 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
744 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
745 };
746
747 static int aic3x_add_widgets(struct snd_soc_codec *codec)
748 {
749 snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets,
750 ARRAY_SIZE(aic3x_dapm_widgets));
751
752 /* set up audio path interconnects */
753 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
754
755 snd_soc_dapm_new_widgets(codec);
756 return 0;
757 }
758
759 static int aic3x_hw_params(struct snd_pcm_substream *substream,
760 struct snd_pcm_hw_params *params,
761 struct snd_soc_dai *dai)
762 {
763 struct snd_soc_pcm_runtime *rtd = substream->private_data;
764 struct snd_soc_device *socdev = rtd->socdev;
765 struct snd_soc_codec *codec = socdev->card->codec;
766 struct aic3x_priv *aic3x = codec->private_data;
767 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
768 u8 data, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
769 u16 pll_d = 1;
770 u8 reg;
771
772 /* select data word length */
773 data =
774 aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
775 switch (params_format(params)) {
776 case SNDRV_PCM_FORMAT_S16_LE:
777 break;
778 case SNDRV_PCM_FORMAT_S20_3LE:
779 data |= (0x01 << 4);
780 break;
781 case SNDRV_PCM_FORMAT_S24_LE:
782 data |= (0x02 << 4);
783 break;
784 case SNDRV_PCM_FORMAT_S32_LE:
785 data |= (0x03 << 4);
786 break;
787 }
788 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data);
789
790 /* Fsref can be 44100 or 48000 */
791 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
792
793 /* Try to find a value for Q which allows us to bypass the PLL and
794 * generate CODEC_CLK directly. */
795 for (pll_q = 2; pll_q < 18; pll_q++)
796 if (aic3x->sysclk / (128 * pll_q) == fsref) {
797 bypass_pll = 1;
798 break;
799 }
800
801 if (bypass_pll) {
802 pll_q &= 0xf;
803 aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
804 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
805 /* disable PLL if it is bypassed */
806 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
807 aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE);
808
809 } else {
810 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
811 /* enable PLL when it is used */
812 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
813 aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE);
814 }
815
816 /* Route Left DAC to left channel input and
817 * right DAC to right channel input */
818 data = (LDAC2LCH | RDAC2RCH);
819 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
820 if (params_rate(params) >= 64000)
821 data |= DUAL_RATE_MODE;
822 aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
823
824 /* codec sample rate select */
825 data = (fsref * 20) / params_rate(params);
826 if (params_rate(params) < 64000)
827 data /= 2;
828 data /= 5;
829 data -= 2;
830 data |= (data << 4);
831 aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
832
833 if (bypass_pll)
834 return 0;
835
836 /* Use PLL
837 * find an apropriate setup for j, d, r and p by iterating over
838 * p and r - j and d are calculated for each fraction.
839 * Up to 128 values are probed, the closest one wins the game.
840 * The sysclk is divided by 1000 to prevent integer overflows.
841 */
842 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
843
844 for (r = 1; r <= 16; r++)
845 for (p = 1; p <= 8; p++) {
846 int clk, tmp = (codec_clk * pll_r * 10) / pll_p;
847 u8 j = tmp / 10000;
848 u16 d = tmp % 10000;
849
850 if (j > 63)
851 continue;
852
853 if (d != 0 && aic3x->sysclk < 10000000)
854 continue;
855
856 /* This is actually 1000 * ((j + (d/10000)) * r) / p
857 * The term had to be converted to get rid of the
858 * division by 10000 */
859 clk = ((10000 * j * r) + (d * r)) / (10 * p);
860
861 /* check whether this values get closer than the best
862 * ones we had before */
863 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
864 pll_j = j; pll_d = d; pll_r = r; pll_p = p;
865 last_clk = clk;
866 }
867
868 /* Early exit for exact matches */
869 if (clk == codec_clk)
870 break;
871 }
872
873 if (last_clk == 0) {
874 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
875 return -EINVAL;
876 }
877
878 data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
879 aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT));
880 aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT);
881 aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
882 aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT);
883 aic3x_write(codec, AIC3X_PLL_PROGD_REG,
884 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
885
886 return 0;
887 }
888
889 static int aic3x_mute(struct snd_soc_dai *dai, int mute)
890 {
891 struct snd_soc_codec *codec = dai->codec;
892 u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON;
893 u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON;
894
895 if (mute) {
896 aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
897 aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
898 } else {
899 aic3x_write(codec, LDAC_VOL, ldac_reg);
900 aic3x_write(codec, RDAC_VOL, rdac_reg);
901 }
902
903 return 0;
904 }
905
906 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
907 int clk_id, unsigned int freq, int dir)
908 {
909 struct snd_soc_codec *codec = codec_dai->codec;
910 struct aic3x_priv *aic3x = codec->private_data;
911
912 aic3x->sysclk = freq;
913 return 0;
914 }
915
916 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
917 unsigned int fmt)
918 {
919 struct snd_soc_codec *codec = codec_dai->codec;
920 struct aic3x_priv *aic3x = codec->private_data;
921 u8 iface_areg, iface_breg;
922 int delay = 0;
923
924 iface_areg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
925 iface_breg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
926
927 /* set master/slave audio interface */
928 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
929 case SND_SOC_DAIFMT_CBM_CFM:
930 aic3x->master = 1;
931 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
932 break;
933 case SND_SOC_DAIFMT_CBS_CFS:
934 aic3x->master = 0;
935 break;
936 default:
937 return -EINVAL;
938 }
939
940 /*
941 * match both interface format and signal polarities since they
942 * are fixed
943 */
944 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
945 SND_SOC_DAIFMT_INV_MASK)) {
946 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
947 break;
948 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
949 delay = 1;
950 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
951 iface_breg |= (0x01 << 6);
952 break;
953 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
954 iface_breg |= (0x02 << 6);
955 break;
956 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
957 iface_breg |= (0x03 << 6);
958 break;
959 default:
960 return -EINVAL;
961 }
962
963 /* set iface */
964 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
965 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
966 aic3x_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
967
968 return 0;
969 }
970
971 static int aic3x_set_bias_level(struct snd_soc_codec *codec,
972 enum snd_soc_bias_level level)
973 {
974 struct aic3x_priv *aic3x = codec->private_data;
975 u8 reg;
976
977 switch (level) {
978 case SND_SOC_BIAS_ON:
979 /* all power is driven by DAPM system */
980 if (aic3x->master) {
981 /* enable pll */
982 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
983 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
984 reg | PLL_ENABLE);
985 }
986 break;
987 case SND_SOC_BIAS_PREPARE:
988 break;
989 case SND_SOC_BIAS_STANDBY:
990 /*
991 * all power is driven by DAPM system,
992 * so output power is safe if bypass was set
993 */
994 if (aic3x->master) {
995 /* disable pll */
996 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
997 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
998 reg & ~PLL_ENABLE);
999 }
1000 break;
1001 case SND_SOC_BIAS_OFF:
1002 /* force all power off */
1003 reg = aic3x_read_reg_cache(codec, LINE1L_2_LADC_CTRL);
1004 aic3x_write(codec, LINE1L_2_LADC_CTRL, reg & ~LADC_PWR_ON);
1005 reg = aic3x_read_reg_cache(codec, LINE1R_2_RADC_CTRL);
1006 aic3x_write(codec, LINE1R_2_RADC_CTRL, reg & ~RADC_PWR_ON);
1007
1008 reg = aic3x_read_reg_cache(codec, DAC_PWR);
1009 aic3x_write(codec, DAC_PWR, reg & ~(LDAC_PWR_ON | RDAC_PWR_ON));
1010
1011 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1012 aic3x_write(codec, HPLOUT_CTRL, reg & ~HPLOUT_PWR_ON);
1013 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1014 aic3x_write(codec, HPROUT_CTRL, reg & ~HPROUT_PWR_ON);
1015
1016 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1017 aic3x_write(codec, HPLCOM_CTRL, reg & ~HPLCOM_PWR_ON);
1018 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1019 aic3x_write(codec, HPRCOM_CTRL, reg & ~HPRCOM_PWR_ON);
1020
1021 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1022 aic3x_write(codec, MONOLOPM_CTRL, reg & ~MONOLOPM_PWR_ON);
1023
1024 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1025 aic3x_write(codec, LLOPM_CTRL, reg & ~LLOPM_PWR_ON);
1026 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1027 aic3x_write(codec, RLOPM_CTRL, reg & ~RLOPM_PWR_ON);
1028
1029 if (aic3x->master) {
1030 /* disable pll */
1031 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1032 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1033 reg & ~PLL_ENABLE);
1034 }
1035 break;
1036 }
1037 codec->bias_level = level;
1038
1039 return 0;
1040 }
1041
1042 void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
1043 {
1044 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1045 u8 bit = gpio ? 3: 0;
1046 u8 val = aic3x_read_reg_cache(codec, reg) & ~(1 << bit);
1047 aic3x_write(codec, reg, val | (!!state << bit));
1048 }
1049 EXPORT_SYMBOL_GPL(aic3x_set_gpio);
1050
1051 int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
1052 {
1053 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1054 u8 val, bit = gpio ? 2: 1;
1055
1056 aic3x_read(codec, reg, &val);
1057 return (val >> bit) & 1;
1058 }
1059 EXPORT_SYMBOL_GPL(aic3x_get_gpio);
1060
1061 void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
1062 int headset_debounce, int button_debounce)
1063 {
1064 u8 val;
1065
1066 val = ((detect & AIC3X_HEADSET_DETECT_MASK)
1067 << AIC3X_HEADSET_DETECT_SHIFT) |
1068 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK)
1069 << AIC3X_HEADSET_DEBOUNCE_SHIFT) |
1070 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK)
1071 << AIC3X_BUTTON_DEBOUNCE_SHIFT);
1072
1073 if (detect & AIC3X_HEADSET_DETECT_MASK)
1074 val |= AIC3X_HEADSET_DETECT_ENABLED;
1075
1076 aic3x_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val);
1077 }
1078 EXPORT_SYMBOL_GPL(aic3x_set_headset_detection);
1079
1080 int aic3x_headset_detected(struct snd_soc_codec *codec)
1081 {
1082 u8 val;
1083 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1084 return (val >> 4) & 1;
1085 }
1086 EXPORT_SYMBOL_GPL(aic3x_headset_detected);
1087
1088 int aic3x_button_pressed(struct snd_soc_codec *codec)
1089 {
1090 u8 val;
1091 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1092 return (val >> 5) & 1;
1093 }
1094 EXPORT_SYMBOL_GPL(aic3x_button_pressed);
1095
1096 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1097 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1098 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1099
1100 static struct snd_soc_dai_ops aic3x_dai_ops = {
1101 .hw_params = aic3x_hw_params,
1102 .digital_mute = aic3x_mute,
1103 .set_sysclk = aic3x_set_dai_sysclk,
1104 .set_fmt = aic3x_set_dai_fmt,
1105 };
1106
1107 struct snd_soc_dai aic3x_dai = {
1108 .name = "tlv320aic3x",
1109 .playback = {
1110 .stream_name = "Playback",
1111 .channels_min = 1,
1112 .channels_max = 2,
1113 .rates = AIC3X_RATES,
1114 .formats = AIC3X_FORMATS,},
1115 .capture = {
1116 .stream_name = "Capture",
1117 .channels_min = 1,
1118 .channels_max = 2,
1119 .rates = AIC3X_RATES,
1120 .formats = AIC3X_FORMATS,},
1121 .ops = &aic3x_dai_ops,
1122 };
1123 EXPORT_SYMBOL_GPL(aic3x_dai);
1124
1125 static int aic3x_suspend(struct platform_device *pdev, pm_message_t state)
1126 {
1127 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1128 struct snd_soc_codec *codec = socdev->card->codec;
1129
1130 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1131
1132 return 0;
1133 }
1134
1135 static int aic3x_resume(struct platform_device *pdev)
1136 {
1137 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1138 struct snd_soc_codec *codec = socdev->card->codec;
1139 int i;
1140 u8 data[2];
1141 u8 *cache = codec->reg_cache;
1142
1143 /* Sync reg_cache with the hardware */
1144 for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) {
1145 data[0] = i;
1146 data[1] = cache[i];
1147 codec->hw_write(codec->control_data, data, 2);
1148 }
1149
1150 aic3x_set_bias_level(codec, codec->suspend_bias_level);
1151
1152 return 0;
1153 }
1154
1155 /*
1156 * initialise the AIC3X driver
1157 * register the mixer and dsp interfaces with the kernel
1158 */
1159 static int aic3x_init(struct snd_soc_device *socdev)
1160 {
1161 struct snd_soc_codec *codec = socdev->card->codec;
1162 struct aic3x_setup_data *setup = socdev->codec_data;
1163 int reg, ret = 0;
1164
1165 codec->name = "tlv320aic3x";
1166 codec->owner = THIS_MODULE;
1167 codec->read = aic3x_read_reg_cache;
1168 codec->write = aic3x_write;
1169 codec->set_bias_level = aic3x_set_bias_level;
1170 codec->dai = &aic3x_dai;
1171 codec->num_dai = 1;
1172 codec->reg_cache_size = ARRAY_SIZE(aic3x_reg);
1173 codec->reg_cache = kmemdup(aic3x_reg, sizeof(aic3x_reg), GFP_KERNEL);
1174 if (codec->reg_cache == NULL)
1175 return -ENOMEM;
1176
1177 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1178 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
1179
1180 /* register pcms */
1181 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1182 if (ret < 0) {
1183 printk(KERN_ERR "aic3x: failed to create pcms\n");
1184 goto pcm_err;
1185 }
1186
1187 /* DAC default volume and mute */
1188 aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1189 aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1190
1191 /* DAC to HP default volume and route to Output mixer */
1192 aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1193 aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1194 aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1195 aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1196 /* DAC to Line Out default volume and route to Output mixer */
1197 aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1198 aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1199 /* DAC to Mono Line Out default volume and route to Output mixer */
1200 aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1201 aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1202
1203 /* unmute all outputs */
1204 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1205 aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE);
1206 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1207 aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE);
1208 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1209 aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1210 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1211 aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1212 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1213 aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE);
1214 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1215 aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1216 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1217 aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE);
1218
1219 /* ADC default volume and unmute */
1220 aic3x_write(codec, LADC_VOL, DEFAULT_GAIN);
1221 aic3x_write(codec, RADC_VOL, DEFAULT_GAIN);
1222 /* By default route Line1 to ADC PGA mixer */
1223 aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1224 aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1225
1226 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1227 aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1228 aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1229 aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1230 aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1231 /* PGA to Line Out default volume, disconnect from Output Mixer */
1232 aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1233 aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1234 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1235 aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1236 aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1237
1238 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1239 aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1240 aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1241 aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1242 aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1243 /* Line2 Line Out default volume, disconnect from Output Mixer */
1244 aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1245 aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1246 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1247 aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1248 aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1249
1250 /* off, with power on */
1251 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1252
1253 /* setup GPIO functions */
1254 aic3x_write(codec, AIC3X_GPIO1_REG, (setup->gpio_func[0] & 0xf) << 4);
1255 aic3x_write(codec, AIC3X_GPIO2_REG, (setup->gpio_func[1] & 0xf) << 4);
1256
1257 snd_soc_add_controls(codec, aic3x_snd_controls,
1258 ARRAY_SIZE(aic3x_snd_controls));
1259 aic3x_add_widgets(codec);
1260 ret = snd_soc_init_card(socdev);
1261 if (ret < 0) {
1262 printk(KERN_ERR "aic3x: failed to register card\n");
1263 goto card_err;
1264 }
1265
1266 return ret;
1267
1268 card_err:
1269 snd_soc_free_pcms(socdev);
1270 snd_soc_dapm_free(socdev);
1271 pcm_err:
1272 kfree(codec->reg_cache);
1273 return ret;
1274 }
1275
1276 static struct snd_soc_device *aic3x_socdev;
1277
1278 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1279 /*
1280 * AIC3X 2 wire address can be up to 4 devices with device addresses
1281 * 0x18, 0x19, 0x1A, 0x1B
1282 */
1283
1284 /*
1285 * If the i2c layer weren't so broken, we could pass this kind of data
1286 * around
1287 */
1288 static int aic3x_i2c_probe(struct i2c_client *i2c,
1289 const struct i2c_device_id *id)
1290 {
1291 struct snd_soc_device *socdev = aic3x_socdev;
1292 struct snd_soc_codec *codec = socdev->card->codec;
1293 int ret;
1294
1295 i2c_set_clientdata(i2c, codec);
1296 codec->control_data = i2c;
1297
1298 ret = aic3x_init(socdev);
1299 if (ret < 0)
1300 printk(KERN_ERR "aic3x: failed to initialise AIC3X\n");
1301 return ret;
1302 }
1303
1304 static int aic3x_i2c_remove(struct i2c_client *client)
1305 {
1306 struct snd_soc_codec *codec = i2c_get_clientdata(client);
1307 kfree(codec->reg_cache);
1308 return 0;
1309 }
1310
1311 static const struct i2c_device_id aic3x_i2c_id[] = {
1312 { "tlv320aic3x", 0 },
1313 { }
1314 };
1315 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1316
1317 /* machine i2c codec control layer */
1318 static struct i2c_driver aic3x_i2c_driver = {
1319 .driver = {
1320 .name = "aic3x I2C Codec",
1321 .owner = THIS_MODULE,
1322 },
1323 .probe = aic3x_i2c_probe,
1324 .remove = aic3x_i2c_remove,
1325 .id_table = aic3x_i2c_id,
1326 };
1327
1328 static int aic3x_i2c_read(struct i2c_client *client, u8 *value, int len)
1329 {
1330 value[0] = i2c_smbus_read_byte_data(client, value[0]);
1331 return (len == 1);
1332 }
1333
1334 static int aic3x_add_i2c_device(struct platform_device *pdev,
1335 const struct aic3x_setup_data *setup)
1336 {
1337 struct i2c_board_info info;
1338 struct i2c_adapter *adapter;
1339 struct i2c_client *client;
1340 int ret;
1341
1342 ret = i2c_add_driver(&aic3x_i2c_driver);
1343 if (ret != 0) {
1344 dev_err(&pdev->dev, "can't add i2c driver\n");
1345 return ret;
1346 }
1347
1348 memset(&info, 0, sizeof(struct i2c_board_info));
1349 info.addr = setup->i2c_address;
1350 strlcpy(info.type, "tlv320aic3x", I2C_NAME_SIZE);
1351
1352 adapter = i2c_get_adapter(setup->i2c_bus);
1353 if (!adapter) {
1354 dev_err(&pdev->dev, "can't get i2c adapter %d\n",
1355 setup->i2c_bus);
1356 goto err_driver;
1357 }
1358
1359 client = i2c_new_device(adapter, &info);
1360 i2c_put_adapter(adapter);
1361 if (!client) {
1362 dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
1363 (unsigned int)info.addr);
1364 goto err_driver;
1365 }
1366
1367 return 0;
1368
1369 err_driver:
1370 i2c_del_driver(&aic3x_i2c_driver);
1371 return -ENODEV;
1372 }
1373 #endif
1374
1375 static int aic3x_probe(struct platform_device *pdev)
1376 {
1377 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1378 struct aic3x_setup_data *setup;
1379 struct snd_soc_codec *codec;
1380 struct aic3x_priv *aic3x;
1381 int ret = 0;
1382
1383 printk(KERN_INFO "AIC3X Audio Codec %s\n", AIC3X_VERSION);
1384
1385 setup = socdev->codec_data;
1386 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1387 if (codec == NULL)
1388 return -ENOMEM;
1389
1390 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1391 if (aic3x == NULL) {
1392 kfree(codec);
1393 return -ENOMEM;
1394 }
1395
1396 codec->private_data = aic3x;
1397 socdev->card->codec = codec;
1398 mutex_init(&codec->mutex);
1399 INIT_LIST_HEAD(&codec->dapm_widgets);
1400 INIT_LIST_HEAD(&codec->dapm_paths);
1401
1402 aic3x_socdev = socdev;
1403 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1404 if (setup->i2c_address) {
1405 codec->hw_write = (hw_write_t) i2c_master_send;
1406 codec->hw_read = (hw_read_t) aic3x_i2c_read;
1407 ret = aic3x_add_i2c_device(pdev, setup);
1408 }
1409 #else
1410 /* Add other interfaces here */
1411 #endif
1412
1413 if (ret != 0) {
1414 kfree(codec->private_data);
1415 kfree(codec);
1416 }
1417 return ret;
1418 }
1419
1420 static int aic3x_remove(struct platform_device *pdev)
1421 {
1422 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1423 struct snd_soc_codec *codec = socdev->card->codec;
1424
1425 /* power down chip */
1426 if (codec->control_data)
1427 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1428
1429 snd_soc_free_pcms(socdev);
1430 snd_soc_dapm_free(socdev);
1431 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1432 i2c_unregister_device(codec->control_data);
1433 i2c_del_driver(&aic3x_i2c_driver);
1434 #endif
1435 kfree(codec->private_data);
1436 kfree(codec);
1437
1438 return 0;
1439 }
1440
1441 struct snd_soc_codec_device soc_codec_dev_aic3x = {
1442 .probe = aic3x_probe,
1443 .remove = aic3x_remove,
1444 .suspend = aic3x_suspend,
1445 .resume = aic3x_resume,
1446 };
1447 EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x);
1448
1449 static int __init aic3x_modinit(void)
1450 {
1451 return snd_soc_register_dai(&aic3x_dai);
1452 }
1453 module_init(aic3x_modinit);
1454
1455 static void __exit aic3x_exit(void)
1456 {
1457 snd_soc_unregister_dai(&aic3x_dai);
1458 }
1459 module_exit(aic3x_exit);
1460
1461 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1462 MODULE_AUTHOR("Vladimir Barinov");
1463 MODULE_LICENSE("GPL");
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