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dpt_i2o: Fix up copy*user
[linux-2.6/verdex.git] / drivers / serial / imx.c
blob5d7b58f1fe42a38596072ba9355d619ffcfd54a2
1 /*
2 * linux/drivers/serial/imx.c
3 *
4 * Driver for Motorola IMX serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Author: Sascha Hauer <sascha@saschahauer.de>
9 * Copyright (C) 2004 Pengutronix
10 *
11 * Copyright (C) 2009 emlix GmbH
12 * Author: Fabian Godehardt (added IrDA support for iMX)
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 * [29-Mar-2005] Mike Lee
29 * Added hardware handshake
30 */
31
32 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
33 #define SUPPORT_SYSRQ
34 #endif
35
36 #include <linux/module.h>
37 #include <linux/ioport.h>
38 #include <linux/init.h>
39 #include <linux/console.h>
40 #include <linux/sysrq.h>
41 #include <linux/platform_device.h>
42 #include <linux/tty.h>
43 #include <linux/tty_flip.h>
44 #include <linux/serial_core.h>
45 #include <linux/serial.h>
46 #include <linux/clk.h>
47 #include <linux/delay.h>
48 #include <linux/rational.h>
49
50 #include <asm/io.h>
51 #include <asm/irq.h>
52 #include <mach/hardware.h>
53 #include <mach/imx-uart.h>
54
55 /* Register definitions */
56 #define URXD0 0x0 /* Receiver Register */
57 #define URTX0 0x40 /* Transmitter Register */
58 #define UCR1 0x80 /* Control Register 1 */
59 #define UCR2 0x84 /* Control Register 2 */
60 #define UCR3 0x88 /* Control Register 3 */
61 #define UCR4 0x8c /* Control Register 4 */
62 #define UFCR 0x90 /* FIFO Control Register */
63 #define USR1 0x94 /* Status Register 1 */
64 #define USR2 0x98 /* Status Register 2 */
65 #define UESC 0x9c /* Escape Character Register */
66 #define UTIM 0xa0 /* Escape Timer Register */
67 #define UBIR 0xa4 /* BRM Incremental Register */
68 #define UBMR 0xa8 /* BRM Modulator Register */
69 #define UBRC 0xac /* Baud Rate Count Register */
70 #if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
71 #define ONEMS 0xb0 /* One Millisecond register */
72 #define UTS 0xb4 /* UART Test Register */
73 #endif
74 #ifdef CONFIG_ARCH_MX1
75 #define BIPR1 0xb0 /* Incremental Preset Register 1 */
76 #define BIPR2 0xb4 /* Incremental Preset Register 2 */
77 #define BIPR3 0xb8 /* Incremental Preset Register 3 */
78 #define BIPR4 0xbc /* Incremental Preset Register 4 */
79 #define BMPR1 0xc0 /* BRM Modulator Register 1 */
80 #define BMPR2 0xc4 /* BRM Modulator Register 2 */
81 #define BMPR3 0xc8 /* BRM Modulator Register 3 */
82 #define BMPR4 0xcc /* BRM Modulator Register 4 */
83 #define UTS 0xd0 /* UART Test Register */
84 #endif
85
86 /* UART Control Register Bit Fields.*/
87 #define URXD_CHARRDY (1<<15)
88 #define URXD_ERR (1<<14)
89 #define URXD_OVRRUN (1<<13)
90 #define URXD_FRMERR (1<<12)
91 #define URXD_BRK (1<<11)
92 #define URXD_PRERR (1<<10)
93 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
94 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
95 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
96 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
97 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
98 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
99 #define UCR1_IREN (1<<7) /* Infrared interface enable */
100 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
101 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
102 #define UCR1_SNDBRK (1<<4) /* Send break */
103 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
104 #ifdef CONFIG_ARCH_MX1
105 #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
106 #endif
107 #if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
108 #define UCR1_UARTCLKEN (0) /* not present on mx2/mx3 */
109 #endif
110 #define UCR1_DOZE (1<<1) /* Doze */
111 #define UCR1_UARTEN (1<<0) /* UART enabled */
112 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
113 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
114 #define UCR2_CTSC (1<<13) /* CTS pin control */
115 #define UCR2_CTS (1<<12) /* Clear to send */
116 #define UCR2_ESCEN (1<<11) /* Escape enable */
117 #define UCR2_PREN (1<<8) /* Parity enable */
118 #define UCR2_PROE (1<<7) /* Parity odd/even */
119 #define UCR2_STPB (1<<6) /* Stop */
120 #define UCR2_WS (1<<5) /* Word size */
121 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
122 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
123 #define UCR2_RXEN (1<<1) /* Receiver enabled */
124 #define UCR2_SRST (1<<0) /* SW reset */
125 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
126 #define UCR3_PARERREN (1<<12) /* Parity enable */
127 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
128 #define UCR3_DSR (1<<10) /* Data set ready */
129 #define UCR3_DCD (1<<9) /* Data carrier detect */
130 #define UCR3_RI (1<<8) /* Ring indicator */
131 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
132 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
133 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
134 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
135 #ifdef CONFIG_ARCH_MX1
136 #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz, only on mx1 */
137 #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz, only on mx1 */
138 #endif
139 #if defined CONFIG_ARCH_MX2 || defined CONFIG_ARCH_MX3
140 #define UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select, on mx2/mx3 */
141 #endif
142 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
143 #define UCR3_BPEN (1<<0) /* Preset registers enable */
144 #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
145 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
146 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
147 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
148 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
149 #define UCR4_IRSC (1<<5) /* IR special case */
150 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
151 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
152 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
153 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
154 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
155 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
156 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
157 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
158 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
159 #define USR1_RTSS (1<<14) /* RTS pin status */
160 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
161 #define USR1_RTSD (1<<12) /* RTS delta */
162 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
163 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
164 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
165 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
166 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
167 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
168 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
169 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
170 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
171 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
172 #define USR2_IDLE (1<<12) /* Idle condition */
173 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
174 #define USR2_WAKE (1<<7) /* Wake */
175 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
176 #define USR2_TXDC (1<<3) /* Transmitter complete */
177 #define USR2_BRCD (1<<2) /* Break condition */
178 #define USR2_ORE (1<<1) /* Overrun error */
179 #define USR2_RDR (1<<0) /* Recv data ready */
180 #define UTS_FRCPERR (1<<13) /* Force parity error */
181 #define UTS_LOOP (1<<12) /* Loop tx and rx */
182 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
183 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
184 #define UTS_TXFULL (1<<4) /* TxFIFO full */
185 #define UTS_RXFULL (1<<3) /* RxFIFO full */
186 #define UTS_SOFTRST (1<<0) /* Software reset */
187
188 /* We've been assigned a range on the "Low-density serial ports" major */
189 #ifdef CONFIG_ARCH_MXC
190 #define SERIAL_IMX_MAJOR 207
191 #define MINOR_START 16
192 #define DEV_NAME "ttymxc"
193 #define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS
194 #endif
195
196 /*
197 * This determines how often we check the modem status signals
198 * for any change. They generally aren't connected to an IRQ
199 * so we have to poll them. We also check immediately before
200 * filling the TX fifo incase CTS has been dropped.
201 */
202 #define MCTRL_TIMEOUT (250*HZ/1000)
203
204 #define DRIVER_NAME "IMX-uart"
205
206 #define UART_NR 8
207
208 struct imx_port {
209 struct uart_port port;
210 struct timer_list timer;
211 unsigned int old_status;
212 int txirq,rxirq,rtsirq;
213 unsigned int have_rtscts:1;
214 unsigned int use_irda:1;
215 unsigned int irda_inv_rx:1;
216 unsigned int irda_inv_tx:1;
217 unsigned short trcv_delay; /* transceiver delay */
218 struct clk *clk;
219 };
220
221 #ifdef CONFIG_IRDA
222 #define USE_IRDA(sport) ((sport)->use_irda)
223 #else
224 #define USE_IRDA(sport) (0)
225 #endif
226
227 /*
228 * Handle any change of modem status signal since we were last called.
229 */
230 static void imx_mctrl_check(struct imx_port *sport)
231 {
232 unsigned int status, changed;
233
234 status = sport->port.ops->get_mctrl(&sport->port);
235 changed = status ^ sport->old_status;
236
237 if (changed == 0)
238 return;
239
240 sport->old_status = status;
241
242 if (changed & TIOCM_RI)
243 sport->port.icount.rng++;
244 if (changed & TIOCM_DSR)
245 sport->port.icount.dsr++;
246 if (changed & TIOCM_CAR)
247 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
248 if (changed & TIOCM_CTS)
249 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
250
251 wake_up_interruptible(&sport->port.info->delta_msr_wait);
252 }
253
254 /*
255 * This is our per-port timeout handler, for checking the
256 * modem status signals.
257 */
258 static void imx_timeout(unsigned long data)
259 {
260 struct imx_port *sport = (struct imx_port *)data;
261 unsigned long flags;
262
263 if (sport->port.info) {
264 spin_lock_irqsave(&sport->port.lock, flags);
265 imx_mctrl_check(sport);
266 spin_unlock_irqrestore(&sport->port.lock, flags);
267
268 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
269 }
270 }
271
272 /*
273 * interrupts disabled on entry
274 */
275 static void imx_stop_tx(struct uart_port *port)
276 {
277 struct imx_port *sport = (struct imx_port *)port;
278 unsigned long temp;
279
280 if (USE_IRDA(sport)) {
281 /* half duplex - wait for end of transmission */
282 int n = 256;
283 while ((--n > 0) &&
284 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
285 udelay(5);
286 barrier();
287 }
288 /*
289 * irda transceiver - wait a bit more to avoid
290 * cutoff, hardware dependent
291 */
292 udelay(sport->trcv_delay);
293
294 /*
295 * half duplex - reactivate receive mode,
296 * flush receive pipe echo crap
297 */
298 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
299 temp = readl(sport->port.membase + UCR1);
300 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
301 writel(temp, sport->port.membase + UCR1);
302
303 temp = readl(sport->port.membase + UCR4);
304 temp &= ~(UCR4_TCEN);
305 writel(temp, sport->port.membase + UCR4);
306
307 while (readl(sport->port.membase + URXD0) &
308 URXD_CHARRDY)
309 barrier();
310
311 temp = readl(sport->port.membase + UCR1);
312 temp |= UCR1_RRDYEN;
313 writel(temp, sport->port.membase + UCR1);
314
315 temp = readl(sport->port.membase + UCR4);
316 temp |= UCR4_DREN;
317 writel(temp, sport->port.membase + UCR4);
318 }
319 return;
320 }
321
322 temp = readl(sport->port.membase + UCR1);
323 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
324 }
325
326 /*
327 * interrupts disabled on entry
328 */
329 static void imx_stop_rx(struct uart_port *port)
330 {
331 struct imx_port *sport = (struct imx_port *)port;
332 unsigned long temp;
333
334 temp = readl(sport->port.membase + UCR2);
335 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
336 }
337
338 /*
339 * Set the modem control timer to fire immediately.
340 */
341 static void imx_enable_ms(struct uart_port *port)
342 {
343 struct imx_port *sport = (struct imx_port *)port;
344
345 mod_timer(&sport->timer, jiffies);
346 }
347
348 static inline void imx_transmit_buffer(struct imx_port *sport)
349 {
350 struct circ_buf *xmit = &sport->port.info->xmit;
351
352 while (!(readl(sport->port.membase + UTS) & UTS_TXFULL)) {
353 /* send xmit->buf[xmit->tail]
354 * out the port here */
355 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
356 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
357 sport->port.icount.tx++;
358 if (uart_circ_empty(xmit))
359 break;
360 }
361
362 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
363 uart_write_wakeup(&sport->port);
364
365 if (uart_circ_empty(xmit))
366 imx_stop_tx(&sport->port);
367 }
368
369 /*
370 * interrupts disabled on entry
371 */
372 static void imx_start_tx(struct uart_port *port)
373 {
374 struct imx_port *sport = (struct imx_port *)port;
375 unsigned long temp;
376
377 if (USE_IRDA(sport)) {
378 /* half duplex in IrDA mode; have to disable receive mode */
379 temp = readl(sport->port.membase + UCR4);
380 temp &= ~(UCR4_DREN);
381 writel(temp, sport->port.membase + UCR4);
382
383 temp = readl(sport->port.membase + UCR1);
384 temp &= ~(UCR1_RRDYEN);
385 writel(temp, sport->port.membase + UCR1);
386 }
387
388 temp = readl(sport->port.membase + UCR1);
389 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
390
391 if (USE_IRDA(sport)) {
392 temp = readl(sport->port.membase + UCR1);
393 temp |= UCR1_TRDYEN;
394 writel(temp, sport->port.membase + UCR1);
395
396 temp = readl(sport->port.membase + UCR4);
397 temp |= UCR4_TCEN;
398 writel(temp, sport->port.membase + UCR4);
399 }
400
401 if (readl(sport->port.membase + UTS) & UTS_TXEMPTY)
402 imx_transmit_buffer(sport);
403 }
404
405 static irqreturn_t imx_rtsint(int irq, void *dev_id)
406 {
407 struct imx_port *sport = dev_id;
408 unsigned int val = readl(sport->port.membase + USR1) & USR1_RTSS;
409 unsigned long flags;
410
411 spin_lock_irqsave(&sport->port.lock, flags);
412
413 writel(USR1_RTSD, sport->port.membase + USR1);
414 uart_handle_cts_change(&sport->port, !!val);
415 wake_up_interruptible(&sport->port.info->delta_msr_wait);
416
417 spin_unlock_irqrestore(&sport->port.lock, flags);
418 return IRQ_HANDLED;
419 }
420
421 static irqreturn_t imx_txint(int irq, void *dev_id)
422 {
423 struct imx_port *sport = dev_id;
424 struct circ_buf *xmit = &sport->port.info->xmit;
425 unsigned long flags;
426
427 spin_lock_irqsave(&sport->port.lock,flags);
428 if (sport->port.x_char)
429 {
430 /* Send next char */
431 writel(sport->port.x_char, sport->port.membase + URTX0);
432 goto out;
433 }
434
435 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
436 imx_stop_tx(&sport->port);
437 goto out;
438 }
439
440 imx_transmit_buffer(sport);
441
442 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
443 uart_write_wakeup(&sport->port);
444
445 out:
446 spin_unlock_irqrestore(&sport->port.lock,flags);
447 return IRQ_HANDLED;
448 }
449
450 static irqreturn_t imx_rxint(int irq, void *dev_id)
451 {
452 struct imx_port *sport = dev_id;
453 unsigned int rx,flg,ignored = 0;
454 struct tty_struct *tty = sport->port.info->port.tty;
455 unsigned long flags, temp;
456
457 spin_lock_irqsave(&sport->port.lock,flags);
458
459 while (readl(sport->port.membase + USR2) & USR2_RDR) {
460 flg = TTY_NORMAL;
461 sport->port.icount.rx++;
462
463 rx = readl(sport->port.membase + URXD0);
464
465 temp = readl(sport->port.membase + USR2);
466 if (temp & USR2_BRCD) {
467 writel(temp | USR2_BRCD, sport->port.membase + USR2);
468 if (uart_handle_break(&sport->port))
469 continue;
470 }
471
472 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
473 continue;
474
475 if (rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) {
476 if (rx & URXD_PRERR)
477 sport->port.icount.parity++;
478 else if (rx & URXD_FRMERR)
479 sport->port.icount.frame++;
480 if (rx & URXD_OVRRUN)
481 sport->port.icount.overrun++;
482
483 if (rx & sport->port.ignore_status_mask) {
484 if (++ignored > 100)
485 goto out;
486 continue;
487 }
488
489 rx &= sport->port.read_status_mask;
490
491 if (rx & URXD_PRERR)
492 flg = TTY_PARITY;
493 else if (rx & URXD_FRMERR)
494 flg = TTY_FRAME;
495 if (rx & URXD_OVRRUN)
496 flg = TTY_OVERRUN;
497
498 #ifdef SUPPORT_SYSRQ
499 sport->port.sysrq = 0;
500 #endif
501 }
502
503 tty_insert_flip_char(tty, rx, flg);
504 }
505
506 out:
507 spin_unlock_irqrestore(&sport->port.lock,flags);
508 tty_flip_buffer_push(tty);
509 return IRQ_HANDLED;
510 }
511
512 static irqreturn_t imx_int(int irq, void *dev_id)
513 {
514 struct imx_port *sport = dev_id;
515 unsigned int sts;
516
517 sts = readl(sport->port.membase + USR1);
518
519 if (sts & USR1_RRDY)
520 imx_rxint(irq, dev_id);
521
522 if (sts & USR1_TRDY &&
523 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
524 imx_txint(irq, dev_id);
525
526 if (sts & USR1_RTSD)
527 imx_rtsint(irq, dev_id);
528
529 return IRQ_HANDLED;
530 }
531
532 /*
533 * Return TIOCSER_TEMT when transmitter is not busy.
534 */
535 static unsigned int imx_tx_empty(struct uart_port *port)
536 {
537 struct imx_port *sport = (struct imx_port *)port;
538
539 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
540 }
541
542 /*
543 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
544 */
545 static unsigned int imx_get_mctrl(struct uart_port *port)
546 {
547 struct imx_port *sport = (struct imx_port *)port;
548 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
549
550 if (readl(sport->port.membase + USR1) & USR1_RTSS)
551 tmp |= TIOCM_CTS;
552
553 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
554 tmp |= TIOCM_RTS;
555
556 return tmp;
557 }
558
559 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
560 {
561 struct imx_port *sport = (struct imx_port *)port;
562 unsigned long temp;
563
564 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
565
566 if (mctrl & TIOCM_RTS)
567 temp |= UCR2_CTS;
568
569 writel(temp, sport->port.membase + UCR2);
570 }
571
572 /*
573 * Interrupts always disabled.
574 */
575 static void imx_break_ctl(struct uart_port *port, int break_state)
576 {
577 struct imx_port *sport = (struct imx_port *)port;
578 unsigned long flags, temp;
579
580 spin_lock_irqsave(&sport->port.lock, flags);
581
582 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
583
584 if ( break_state != 0 )
585 temp |= UCR1_SNDBRK;
586
587 writel(temp, sport->port.membase + UCR1);
588
589 spin_unlock_irqrestore(&sport->port.lock, flags);
590 }
591
592 #define TXTL 2 /* reset default */
593 #define RXTL 1 /* reset default */
594
595 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
596 {
597 unsigned int val;
598 unsigned int ufcr_rfdiv;
599
600 /* set receiver / transmitter trigger level.
601 * RFDIV is set such way to satisfy requested uartclk value
602 */
603 val = TXTL << 10 | RXTL;
604 ufcr_rfdiv = (clk_get_rate(sport->clk) + sport->port.uartclk / 2)
605 / sport->port.uartclk;
606
607 if(!ufcr_rfdiv)
608 ufcr_rfdiv = 1;
609
610 val |= UFCR_RFDIV_REG(ufcr_rfdiv);
611
612 writel(val, sport->port.membase + UFCR);
613
614 return 0;
615 }
616
617 static int imx_startup(struct uart_port *port)
618 {
619 struct imx_port *sport = (struct imx_port *)port;
620 int retval;
621 unsigned long flags, temp;
622
623 imx_setup_ufcr(sport, 0);
624
625 /* disable the DREN bit (Data Ready interrupt enable) before
626 * requesting IRQs
627 */
628 temp = readl(sport->port.membase + UCR4);
629
630 if (USE_IRDA(sport))
631 temp |= UCR4_IRSC;
632
633 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
634
635 if (USE_IRDA(sport)) {
636 /* reset fifo's and state machines */
637 int i = 100;
638 temp = readl(sport->port.membase + UCR2);
639 temp &= ~UCR2_SRST;
640 writel(temp, sport->port.membase + UCR2);
641 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) &&
642 (--i > 0)) {
643 udelay(1);
644 }
645 }
646
647 /*
648 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
649 * chips only have one interrupt.
650 */
651 if (sport->txirq > 0) {
652 retval = request_irq(sport->rxirq, imx_rxint, 0,
653 DRIVER_NAME, sport);
654 if (retval)
655 goto error_out1;
656
657 retval = request_irq(sport->txirq, imx_txint, 0,
658 DRIVER_NAME, sport);
659 if (retval)
660 goto error_out2;
661
662 /* do not use RTS IRQ on IrDA */
663 if (!USE_IRDA(sport)) {
664 retval = request_irq(sport->rtsirq, imx_rtsint,
665 (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 :
666 IRQF_TRIGGER_FALLING |
667 IRQF_TRIGGER_RISING,
668 DRIVER_NAME, sport);
669 if (retval)
670 goto error_out3;
671 }
672 } else {
673 retval = request_irq(sport->port.irq, imx_int, 0,
674 DRIVER_NAME, sport);
675 if (retval) {
676 free_irq(sport->port.irq, sport);
677 goto error_out1;
678 }
679 }
680
681 /*
682 * Finally, clear and enable interrupts
683 */
684 writel(USR1_RTSD, sport->port.membase + USR1);
685
686 temp = readl(sport->port.membase + UCR1);
687 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
688
689 if (USE_IRDA(sport)) {
690 temp |= UCR1_IREN;
691 temp &= ~(UCR1_RTSDEN);
692 }
693
694 writel(temp, sport->port.membase + UCR1);
695
696 temp = readl(sport->port.membase + UCR2);
697 temp |= (UCR2_RXEN | UCR2_TXEN);
698 writel(temp, sport->port.membase + UCR2);
699
700 if (USE_IRDA(sport)) {
701 /* clear RX-FIFO */
702 int i = 64;
703 while ((--i > 0) &&
704 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) {
705 barrier();
706 }
707 }
708
709 #if defined CONFIG_ARCH_MX2 || defined CONFIG_ARCH_MX3
710 temp = readl(sport->port.membase + UCR3);
711 temp |= UCR3_RXDMUXSEL;
712 writel(temp, sport->port.membase + UCR3);
713 #endif
714
715 if (USE_IRDA(sport)) {
716 temp = readl(sport->port.membase + UCR4);
717 if (sport->irda_inv_rx)
718 temp |= UCR4_INVR;
719 else
720 temp &= ~(UCR4_INVR);
721 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
722
723 temp = readl(sport->port.membase + UCR3);
724 if (sport->irda_inv_tx)
725 temp |= UCR3_INVT;
726 else
727 temp &= ~(UCR3_INVT);
728 writel(temp, sport->port.membase + UCR3);
729 }
730
731 /*
732 * Enable modem status interrupts
733 */
734 spin_lock_irqsave(&sport->port.lock,flags);
735 imx_enable_ms(&sport->port);
736 spin_unlock_irqrestore(&sport->port.lock,flags);
737
738 if (USE_IRDA(sport)) {
739 struct imxuart_platform_data *pdata;
740 pdata = sport->port.dev->platform_data;
741 sport->irda_inv_rx = pdata->irda_inv_rx;
742 sport->irda_inv_tx = pdata->irda_inv_tx;
743 sport->trcv_delay = pdata->transceiver_delay;
744 if (pdata->irda_enable)
745 pdata->irda_enable(1);
746 }
747
748 return 0;
749
750 error_out3:
751 if (sport->txirq)
752 free_irq(sport->txirq, sport);
753 error_out2:
754 if (sport->rxirq)
755 free_irq(sport->rxirq, sport);
756 error_out1:
757 return retval;
758 }
759
760 static void imx_shutdown(struct uart_port *port)
761 {
762 struct imx_port *sport = (struct imx_port *)port;
763 unsigned long temp;
764
765 temp = readl(sport->port.membase + UCR2);
766 temp &= ~(UCR2_TXEN);
767 writel(temp, sport->port.membase + UCR2);
768
769 if (USE_IRDA(sport)) {
770 struct imxuart_platform_data *pdata;
771 pdata = sport->port.dev->platform_data;
772 if (pdata->irda_enable)
773 pdata->irda_enable(0);
774 }
775
776 /*
777 * Stop our timer.
778 */
779 del_timer_sync(&sport->timer);
780
781 /*
782 * Free the interrupts
783 */
784 if (sport->txirq > 0) {
785 if (!USE_IRDA(sport))
786 free_irq(sport->rtsirq, sport);
787 free_irq(sport->txirq, sport);
788 free_irq(sport->rxirq, sport);
789 } else
790 free_irq(sport->port.irq, sport);
791
792 /*
793 * Disable all interrupts, port and break condition.
794 */
795
796 temp = readl(sport->port.membase + UCR1);
797 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
798 if (USE_IRDA(sport))
799 temp &= ~(UCR1_IREN);
800
801 writel(temp, sport->port.membase + UCR1);
802 }
803
804 static void
805 imx_set_termios(struct uart_port *port, struct ktermios *termios,
806 struct ktermios *old)
807 {
808 struct imx_port *sport = (struct imx_port *)port;
809 unsigned long flags;
810 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
811 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
812 unsigned int div, ufcr;
813 unsigned long num, denom;
814 uint64_t tdiv64;
815
816 /*
817 * If we don't support modem control lines, don't allow
818 * these to be set.
819 */
820 if (0) {
821 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
822 termios->c_cflag |= CLOCAL;
823 }
824
825 /*
826 * We only support CS7 and CS8.
827 */
828 while ((termios->c_cflag & CSIZE) != CS7 &&
829 (termios->c_cflag & CSIZE) != CS8) {
830 termios->c_cflag &= ~CSIZE;
831 termios->c_cflag |= old_csize;
832 old_csize = CS8;
833 }
834
835 if ((termios->c_cflag & CSIZE) == CS8)
836 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
837 else
838 ucr2 = UCR2_SRST | UCR2_IRTS;
839
840 if (termios->c_cflag & CRTSCTS) {
841 if( sport->have_rtscts ) {
842 ucr2 &= ~UCR2_IRTS;
843 ucr2 |= UCR2_CTSC;
844 } else {
845 termios->c_cflag &= ~CRTSCTS;
846 }
847 }
848
849 if (termios->c_cflag & CSTOPB)
850 ucr2 |= UCR2_STPB;
851 if (termios->c_cflag & PARENB) {
852 ucr2 |= UCR2_PREN;
853 if (termios->c_cflag & PARODD)
854 ucr2 |= UCR2_PROE;
855 }
856
857 /*
858 * Ask the core to calculate the divisor for us.
859 */
860 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
861 quot = uart_get_divisor(port, baud);
862
863 spin_lock_irqsave(&sport->port.lock, flags);
864
865 sport->port.read_status_mask = 0;
866 if (termios->c_iflag & INPCK)
867 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
868 if (termios->c_iflag & (BRKINT | PARMRK))
869 sport->port.read_status_mask |= URXD_BRK;
870
871 /*
872 * Characters to ignore
873 */
874 sport->port.ignore_status_mask = 0;
875 if (termios->c_iflag & IGNPAR)
876 sport->port.ignore_status_mask |= URXD_PRERR;
877 if (termios->c_iflag & IGNBRK) {
878 sport->port.ignore_status_mask |= URXD_BRK;
879 /*
880 * If we're ignoring parity and break indicators,
881 * ignore overruns too (for real raw support).
882 */
883 if (termios->c_iflag & IGNPAR)
884 sport->port.ignore_status_mask |= URXD_OVRRUN;
885 }
886
887 del_timer_sync(&sport->timer);
888
889 /*
890 * Update the per-port timeout.
891 */
892 uart_update_timeout(port, termios->c_cflag, baud);
893
894 /*
895 * disable interrupts and drain transmitter
896 */
897 old_ucr1 = readl(sport->port.membase + UCR1);
898 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
899 sport->port.membase + UCR1);
900
901 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
902 barrier();
903
904 /* then, disable everything */
905 old_txrxen = readl(sport->port.membase + UCR2);
906 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
907 sport->port.membase + UCR2);
908 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
909
910 if (USE_IRDA(sport)) {
911 /*
912 * use maximum available submodule frequency to
913 * avoid missing short pulses due to low sampling rate
914 */
915 div = 1;
916 } else {
917 div = sport->port.uartclk / (baud * 16);
918 if (div > 7)
919 div = 7;
920 if (!div)
921 div = 1;
922 }
923
924 rational_best_approximation(16 * div * baud, sport->port.uartclk,
925 1 << 16, 1 << 16, &num, &denom);
926
927 if (port->info && port->info->port.tty) {
928 tdiv64 = sport->port.uartclk;
929 tdiv64 *= num;
930 do_div(tdiv64, denom * 16 * div);
931 tty_encode_baud_rate(sport->port.info->port.tty,
932 (speed_t)tdiv64, (speed_t)tdiv64);
933 }
934
935 num -= 1;
936 denom -= 1;
937
938 ufcr = readl(sport->port.membase + UFCR);
939 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
940 writel(ufcr, sport->port.membase + UFCR);
941
942 writel(num, sport->port.membase + UBIR);
943 writel(denom, sport->port.membase + UBMR);
944
945 #ifdef ONEMS
946 writel(sport->port.uartclk / div / 1000, sport->port.membase + ONEMS);
947 #endif
948
949 writel(old_ucr1, sport->port.membase + UCR1);
950
951 /* set the parity, stop bits and data size */
952 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
953
954 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
955 imx_enable_ms(&sport->port);
956
957 spin_unlock_irqrestore(&sport->port.lock, flags);
958 }
959
960 static const char *imx_type(struct uart_port *port)
961 {
962 struct imx_port *sport = (struct imx_port *)port;
963
964 return sport->port.type == PORT_IMX ? "IMX" : NULL;
965 }
966
967 /*
968 * Release the memory region(s) being used by 'port'.
969 */
970 static void imx_release_port(struct uart_port *port)
971 {
972 struct platform_device *pdev = to_platform_device(port->dev);
973 struct resource *mmres;
974
975 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
976 release_mem_region(mmres->start, mmres->end - mmres->start + 1);
977 }
978
979 /*
980 * Request the memory region(s) being used by 'port'.
981 */
982 static int imx_request_port(struct uart_port *port)
983 {
984 struct platform_device *pdev = to_platform_device(port->dev);
985 struct resource *mmres;
986 void *ret;
987
988 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
989 if (!mmres)
990 return -ENODEV;
991
992 ret = request_mem_region(mmres->start, mmres->end - mmres->start + 1,
993 "imx-uart");
994
995 return ret ? 0 : -EBUSY;
996 }
997
998 /*
999 * Configure/autoconfigure the port.
1000 */
1001 static void imx_config_port(struct uart_port *port, int flags)
1002 {
1003 struct imx_port *sport = (struct imx_port *)port;
1004
1005 if (flags & UART_CONFIG_TYPE &&
1006 imx_request_port(&sport->port) == 0)
1007 sport->port.type = PORT_IMX;
1008 }
1009
1010 /*
1011 * Verify the new serial_struct (for TIOCSSERIAL).
1012 * The only change we allow are to the flags and type, and
1013 * even then only between PORT_IMX and PORT_UNKNOWN
1014 */
1015 static int
1016 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1017 {
1018 struct imx_port *sport = (struct imx_port *)port;
1019 int ret = 0;
1020
1021 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1022 ret = -EINVAL;
1023 if (sport->port.irq != ser->irq)
1024 ret = -EINVAL;
1025 if (ser->io_type != UPIO_MEM)
1026 ret = -EINVAL;
1027 if (sport->port.uartclk / 16 != ser->baud_base)
1028 ret = -EINVAL;
1029 if ((void *)sport->port.mapbase != ser->iomem_base)
1030 ret = -EINVAL;
1031 if (sport->port.iobase != ser->port)
1032 ret = -EINVAL;
1033 if (ser->hub6 != 0)
1034 ret = -EINVAL;
1035 return ret;
1036 }
1037
1038 static struct uart_ops imx_pops = {
1039 .tx_empty = imx_tx_empty,
1040 .set_mctrl = imx_set_mctrl,
1041 .get_mctrl = imx_get_mctrl,
1042 .stop_tx = imx_stop_tx,
1043 .start_tx = imx_start_tx,
1044 .stop_rx = imx_stop_rx,
1045 .enable_ms = imx_enable_ms,
1046 .break_ctl = imx_break_ctl,
1047 .startup = imx_startup,
1048 .shutdown = imx_shutdown,
1049 .set_termios = imx_set_termios,
1050 .type = imx_type,
1051 .release_port = imx_release_port,
1052 .request_port = imx_request_port,
1053 .config_port = imx_config_port,
1054 .verify_port = imx_verify_port,
1055 };
1056
1057 static struct imx_port *imx_ports[UART_NR];
1058
1059 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1060 static void imx_console_putchar(struct uart_port *port, int ch)
1061 {
1062 struct imx_port *sport = (struct imx_port *)port;
1063
1064 while (readl(sport->port.membase + UTS) & UTS_TXFULL)
1065 barrier();
1066
1067 writel(ch, sport->port.membase + URTX0);
1068 }
1069
1070 /*
1071 * Interrupts are disabled on entering
1072 */
1073 static void
1074 imx_console_write(struct console *co, const char *s, unsigned int count)
1075 {
1076 struct imx_port *sport = imx_ports[co->index];
1077 unsigned int old_ucr1, old_ucr2;
1078
1079 /*
1080 * First, save UCR1/2 and then disable interrupts
1081 */
1082 old_ucr1 = readl(sport->port.membase + UCR1);
1083 old_ucr2 = readl(sport->port.membase + UCR2);
1084
1085 writel((old_ucr1 | UCR1_UARTCLKEN | UCR1_UARTEN) &
1086 ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1087 sport->port.membase + UCR1);
1088
1089 writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1090
1091 uart_console_write(&sport->port, s, count, imx_console_putchar);
1092
1093 /*
1094 * Finally, wait for transmitter to become empty
1095 * and restore UCR1/2
1096 */
1097 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1098
1099 writel(old_ucr1, sport->port.membase + UCR1);
1100 writel(old_ucr2, sport->port.membase + UCR2);
1101 }
1102
1103 /*
1104 * If the port was already initialised (eg, by a boot loader),
1105 * try to determine the current setup.
1106 */
1107 static void __init
1108 imx_console_get_options(struct imx_port *sport, int *baud,
1109 int *parity, int *bits)
1110 {
1111
1112 if ( readl(sport->port.membase + UCR1) | UCR1_UARTEN ) {
1113 /* ok, the port was enabled */
1114 unsigned int ucr2, ubir,ubmr, uartclk;
1115 unsigned int baud_raw;
1116 unsigned int ucfr_rfdiv;
1117
1118 ucr2 = readl(sport->port.membase + UCR2);
1119
1120 *parity = 'n';
1121 if (ucr2 & UCR2_PREN) {
1122 if (ucr2 & UCR2_PROE)
1123 *parity = 'o';
1124 else
1125 *parity = 'e';
1126 }
1127
1128 if (ucr2 & UCR2_WS)
1129 *bits = 8;
1130 else
1131 *bits = 7;
1132
1133 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1134 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1135
1136 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1137 if (ucfr_rfdiv == 6)
1138 ucfr_rfdiv = 7;
1139 else
1140 ucfr_rfdiv = 6 - ucfr_rfdiv;
1141
1142 uartclk = clk_get_rate(sport->clk);
1143 uartclk /= ucfr_rfdiv;
1144
1145 { /*
1146 * The next code provides exact computation of
1147 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1148 * without need of float support or long long division,
1149 * which would be required to prevent 32bit arithmetic overflow
1150 */
1151 unsigned int mul = ubir + 1;
1152 unsigned int div = 16 * (ubmr + 1);
1153 unsigned int rem = uartclk % div;
1154
1155 baud_raw = (uartclk / div) * mul;
1156 baud_raw += (rem * mul + div / 2) / div;
1157 *baud = (baud_raw + 50) / 100 * 100;
1158 }
1159
1160 if(*baud != baud_raw)
1161 printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n",
1162 baud_raw, *baud);
1163 }
1164 }
1165
1166 static int __init
1167 imx_console_setup(struct console *co, char *options)
1168 {
1169 struct imx_port *sport;
1170 int baud = 9600;
1171 int bits = 8;
1172 int parity = 'n';
1173 int flow = 'n';
1174
1175 /*
1176 * Check whether an invalid uart number has been specified, and
1177 * if so, search for the first available port that does have
1178 * console support.
1179 */
1180 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1181 co->index = 0;
1182 sport = imx_ports[co->index];
1183 if(sport == NULL)
1184 return -ENODEV;
1185
1186 if (options)
1187 uart_parse_options(options, &baud, &parity, &bits, &flow);
1188 else
1189 imx_console_get_options(sport, &baud, &parity, &bits);
1190
1191 imx_setup_ufcr(sport, 0);
1192
1193 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1194 }
1195
1196 static struct uart_driver imx_reg;
1197 static struct console imx_console = {
1198 .name = DEV_NAME,
1199 .write = imx_console_write,
1200 .device = uart_console_device,
1201 .setup = imx_console_setup,
1202 .flags = CON_PRINTBUFFER,
1203 .index = -1,
1204 .data = &imx_reg,
1205 };
1206
1207 #define IMX_CONSOLE &imx_console
1208 #else
1209 #define IMX_CONSOLE NULL
1210 #endif
1211
1212 static struct uart_driver imx_reg = {
1213 .owner = THIS_MODULE,
1214 .driver_name = DRIVER_NAME,
1215 .dev_name = DEV_NAME,
1216 .major = SERIAL_IMX_MAJOR,
1217 .minor = MINOR_START,
1218 .nr = ARRAY_SIZE(imx_ports),
1219 .cons = IMX_CONSOLE,
1220 };
1221
1222 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1223 {
1224 struct imx_port *sport = platform_get_drvdata(dev);
1225
1226 if (sport)
1227 uart_suspend_port(&imx_reg, &sport->port);
1228
1229 return 0;
1230 }
1231
1232 static int serial_imx_resume(struct platform_device *dev)
1233 {
1234 struct imx_port *sport = platform_get_drvdata(dev);
1235
1236 if (sport)
1237 uart_resume_port(&imx_reg, &sport->port);
1238
1239 return 0;
1240 }
1241
1242 static int serial_imx_probe(struct platform_device *pdev)
1243 {
1244 struct imx_port *sport;
1245 struct imxuart_platform_data *pdata;
1246 void __iomem *base;
1247 int ret = 0;
1248 struct resource *res;
1249
1250 sport = kzalloc(sizeof(*sport), GFP_KERNEL);
1251 if (!sport)
1252 return -ENOMEM;
1253
1254 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1255 if (!res) {
1256 ret = -ENODEV;
1257 goto free;
1258 }
1259
1260 base = ioremap(res->start, PAGE_SIZE);
1261 if (!base) {
1262 ret = -ENOMEM;
1263 goto free;
1264 }
1265
1266 sport->port.dev = &pdev->dev;
1267 sport->port.mapbase = res->start;
1268 sport->port.membase = base;
1269 sport->port.type = PORT_IMX,
1270 sport->port.iotype = UPIO_MEM;
1271 sport->port.irq = platform_get_irq(pdev, 0);
1272 sport->rxirq = platform_get_irq(pdev, 0);
1273 sport->txirq = platform_get_irq(pdev, 1);
1274 sport->rtsirq = platform_get_irq(pdev, 2);
1275 sport->port.fifosize = 32;
1276 sport->port.ops = &imx_pops;
1277 sport->port.flags = UPF_BOOT_AUTOCONF;
1278 sport->port.line = pdev->id;
1279 init_timer(&sport->timer);
1280 sport->timer.function = imx_timeout;
1281 sport->timer.data = (unsigned long)sport;
1282
1283 sport->clk = clk_get(&pdev->dev, "uart");
1284 if (IS_ERR(sport->clk)) {
1285 ret = PTR_ERR(sport->clk);
1286 goto unmap;
1287 }
1288 clk_enable(sport->clk);
1289
1290 sport->port.uartclk = clk_get_rate(sport->clk);
1291
1292 imx_ports[pdev->id] = sport;
1293
1294 pdata = pdev->dev.platform_data;
1295 if (pdata && (pdata->flags & IMXUART_HAVE_RTSCTS))
1296 sport->have_rtscts = 1;
1297
1298 #ifdef CONFIG_IRDA
1299 if (pdata && (pdata->flags & IMXUART_IRDA))
1300 sport->use_irda = 1;
1301 #endif
1302
1303 if (pdata->init) {
1304 ret = pdata->init(pdev);
1305 if (ret)
1306 goto clkput;
1307 }
1308
1309 ret = uart_add_one_port(&imx_reg, &sport->port);
1310 if (ret)
1311 goto deinit;
1312 platform_set_drvdata(pdev, &sport->port);
1313
1314 return 0;
1315 deinit:
1316 if (pdata->exit)
1317 pdata->exit(pdev);
1318 clkput:
1319 clk_put(sport->clk);
1320 clk_disable(sport->clk);
1321 unmap:
1322 iounmap(sport->port.membase);
1323 free:
1324 kfree(sport);
1325
1326 return ret;
1327 }
1328
1329 static int serial_imx_remove(struct platform_device *pdev)
1330 {
1331 struct imxuart_platform_data *pdata;
1332 struct imx_port *sport = platform_get_drvdata(pdev);
1333
1334 pdata = pdev->dev.platform_data;
1335
1336 platform_set_drvdata(pdev, NULL);
1337
1338 if (sport) {
1339 uart_remove_one_port(&imx_reg, &sport->port);
1340 clk_put(sport->clk);
1341 }
1342
1343 clk_disable(sport->clk);
1344
1345 if (pdata->exit)
1346 pdata->exit(pdev);
1347
1348 iounmap(sport->port.membase);
1349 kfree(sport);
1350
1351 return 0;
1352 }
1353
1354 static struct platform_driver serial_imx_driver = {
1355 .probe = serial_imx_probe,
1356 .remove = serial_imx_remove,
1357
1358 .suspend = serial_imx_suspend,
1359 .resume = serial_imx_resume,
1360 .driver = {
1361 .name = "imx-uart",
1362 .owner = THIS_MODULE,
1363 },
1364 };
1365
1366 static int __init imx_serial_init(void)
1367 {
1368 int ret;
1369
1370 printk(KERN_INFO "Serial: IMX driver\n");
1371
1372 ret = uart_register_driver(&imx_reg);
1373 if (ret)
1374 return ret;
1375
1376 ret = platform_driver_register(&serial_imx_driver);
1377 if (ret != 0)
1378 uart_unregister_driver(&imx_reg);
1379
1380 return 0;
1381 }
1382
1383 static void __exit imx_serial_exit(void)
1384 {
1385 platform_driver_unregister(&serial_imx_driver);
1386 uart_unregister_driver(&imx_reg);
1387 }
1388
1389 module_init(imx_serial_init);
1390 module_exit(imx_serial_exit);
1391
1392 MODULE_AUTHOR("Sascha Hauer");
1393 MODULE_DESCRIPTION("IMX generic serial port driver");
1394 MODULE_LICENSE("GPL");
1395 MODULE_ALIAS("platform:imx-uart");
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