| blob | 65fe3332364aa8cb414793ec0f0a057e40038252 |
1 /*
2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
21 /*
22 Module: rt61pci
23 Abstract: Data structures and registers for the rt61pci module.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
27 #ifndef RT61PCI_H
28 #define RT61PCI_H
30 /*
31 * RF chip defines.
32 */
33 #define RF5225 0x0001
34 #define RF5325 0x0002
35 #define RF2527 0x0003
36 #define RF2529 0x0004
38 /*
39 * Signal information.
40 * Defaul offset is required for RSSI <-> dBm conversion.
41 */
42 #define DEFAULT_RSSI_OFFSET 120
44 /*
45 * Register layout information.
46 */
47 #define CSR_REG_BASE 0x3000
48 #define CSR_REG_SIZE 0x04b0
49 #define EEPROM_BASE 0x0000
50 #define EEPROM_SIZE 0x0100
51 #define BBP_BASE 0x0000
52 #define BBP_SIZE 0x0080
53 #define RF_BASE 0x0000
54 #define RF_SIZE 0x0014
56 /*
57 * Number of TX queues.
58 */
59 #define NUM_TX_QUEUES 4
61 /*
62 * PCI registers.
63 */
65 /*
66 * PCI Configuration Header
67 */
68 #define PCI_CONFIG_HEADER_VENDOR 0x0000
69 #define PCI_CONFIG_HEADER_DEVICE 0x0002
71 /*
72 * HOST_CMD_CSR: For HOST to interrupt embedded processor
73 */
74 #define HOST_CMD_CSR 0x0008
75 #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x0000007f)
76 #define HOST_CMD_CSR_INTERRUPT_MCU FIELD32(0x00000080)
78 /*
79 * MCU_CNTL_CSR
80 * SELECT_BANK: Select 8051 program bank.
81 * RESET: Enable 8051 reset state.
82 * READY: Ready state for 8051.
83 */
84 #define MCU_CNTL_CSR 0x000c
85 #define MCU_CNTL_CSR_SELECT_BANK FIELD32(0x00000001)
86 #define MCU_CNTL_CSR_RESET FIELD32(0x00000002)
87 #define MCU_CNTL_CSR_READY FIELD32(0x00000004)
89 /*
90 * SOFT_RESET_CSR
91 */
92 #define SOFT_RESET_CSR 0x0010
94 /*
95 * MCU_INT_SOURCE_CSR: MCU interrupt source/mask register.
96 */
97 #define MCU_INT_SOURCE_CSR 0x0014
98 #define MCU_INT_SOURCE_CSR_0 FIELD32(0x00000001)
99 #define MCU_INT_SOURCE_CSR_1 FIELD32(0x00000002)
100 #define MCU_INT_SOURCE_CSR_2 FIELD32(0x00000004)
101 #define MCU_INT_SOURCE_CSR_3 FIELD32(0x00000008)
102 #define MCU_INT_SOURCE_CSR_4 FIELD32(0x00000010)
103 #define MCU_INT_SOURCE_CSR_5 FIELD32(0x00000020)
104 #define MCU_INT_SOURCE_CSR_6 FIELD32(0x00000040)
105 #define MCU_INT_SOURCE_CSR_7 FIELD32(0x00000080)
106 #define MCU_INT_SOURCE_CSR_TWAKEUP FIELD32(0x00000100)
107 #define MCU_INT_SOURCE_CSR_TBTT_EXPIRE FIELD32(0x00000200)
109 /*
110 * MCU_INT_MASK_CSR: MCU interrupt source/mask register.
111 */
112 #define MCU_INT_MASK_CSR 0x0018
113 #define MCU_INT_MASK_CSR_0 FIELD32(0x00000001)
114 #define MCU_INT_MASK_CSR_1 FIELD32(0x00000002)
115 #define MCU_INT_MASK_CSR_2 FIELD32(0x00000004)
116 #define MCU_INT_MASK_CSR_3 FIELD32(0x00000008)
117 #define MCU_INT_MASK_CSR_4 FIELD32(0x00000010)
118 #define MCU_INT_MASK_CSR_5 FIELD32(0x00000020)
119 #define MCU_INT_MASK_CSR_6 FIELD32(0x00000040)
120 #define MCU_INT_MASK_CSR_7 FIELD32(0x00000080)
121 #define MCU_INT_MASK_CSR_TWAKEUP FIELD32(0x00000100)
122 #define MCU_INT_MASK_CSR_TBTT_EXPIRE FIELD32(0x00000200)
124 /*
125 * PCI_USEC_CSR
126 */
127 #define PCI_USEC_CSR 0x001c
129 /*
130 * Security key table memory.
131 * 16 entries 32-byte for shared key table
132 * 64 entries 32-byte for pairwise key table
133 * 64 entries 8-byte for pairwise ta key table
134 */
135 #define SHARED_KEY_TABLE_BASE 0x1000
136 #define PAIRWISE_KEY_TABLE_BASE 0x1200
137 #define PAIRWISE_TA_TABLE_BASE 0x1a00
139 #define SHARED_KEY_ENTRY(__idx) \
140 ( SHARED_KEY_TABLE_BASE + \
141 ((__idx) * sizeof(struct hw_key_entry)) )
142 #define PAIRWISE_KEY_ENTRY(__idx) \
143 ( PAIRWISE_KEY_TABLE_BASE + \
144 ((__idx) * sizeof(struct hw_key_entry)) )
145 #define PAIRWISE_TA_ENTRY(__idx) \
146 ( PAIRWISE_TA_TABLE_BASE + \
147 ((__idx) * sizeof(struct hw_pairwise_ta_entry)) )
157 u8 cipher;
158 u8 reserved;
161 /*
162 * Other on-chip shared memory space.
163 */
164 #define HW_CIS_BASE 0x2000
165 #define HW_NULL_BASE 0x2b00
167 /*
168 * Since NULL frame won't be that long (256 byte),
169 * We steal 16 tail bytes to save debugging settings.
170 */
171 #define HW_DEBUG_SETTING_BASE 0x2bf0
173 /*
174 * On-chip BEACON frame space.
175 */
176 #define HW_BEACON_BASE0 0x2c00
177 #define HW_BEACON_BASE1 0x2d00
178 #define HW_BEACON_BASE2 0x2e00
179 #define HW_BEACON_BASE3 0x2f00
181 #define HW_BEACON_OFFSET(__index) \
182 ( HW_BEACON_BASE0 + (__index * 0x0100) )
184 /*
185 * HOST-MCU shared memory.
186 */
188 /*
189 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
190 */
191 #define H2M_MAILBOX_CSR 0x2100
192 #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
193 #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
194 #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
195 #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
197 /*
198 * MCU_LEDCS: LED control for MCU Mailbox.
199 */
200 #define MCU_LEDCS_LED_MODE FIELD16(0x001f)
201 #define MCU_LEDCS_RADIO_STATUS FIELD16(0x0020)
202 #define MCU_LEDCS_LINK_BG_STATUS FIELD16(0x0040)
203 #define MCU_LEDCS_LINK_A_STATUS FIELD16(0x0080)
204 #define MCU_LEDCS_POLARITY_GPIO_0 FIELD16(0x0100)
205 #define MCU_LEDCS_POLARITY_GPIO_1 FIELD16(0x0200)
206 #define MCU_LEDCS_POLARITY_GPIO_2 FIELD16(0x0400)
207 #define MCU_LEDCS_POLARITY_GPIO_3 FIELD16(0x0800)
208 #define MCU_LEDCS_POLARITY_GPIO_4 FIELD16(0x1000)
209 #define MCU_LEDCS_POLARITY_ACT FIELD16(0x2000)
210 #define MCU_LEDCS_POLARITY_READY_BG FIELD16(0x4000)
211 #define MCU_LEDCS_POLARITY_READY_A FIELD16(0x8000)
213 /*
214 * M2H_CMD_DONE_CSR.
215 */
216 #define M2H_CMD_DONE_CSR 0x2104
218 /*
219 * MCU_TXOP_ARRAY_BASE.
220 */
221 #define MCU_TXOP_ARRAY_BASE 0x2110
223 /*
224 * MAC Control/Status Registers(CSR).
225 * Some values are set in TU, whereas 1 TU == 1024 us.
226 */
228 /*
229 * MAC_CSR0: ASIC revision number.
230 */
231 #define MAC_CSR0 0x3000
233 /*
234 * MAC_CSR1: System control register.
235 * SOFT_RESET: Software reset bit, 1: reset, 0: normal.
236 * BBP_RESET: Hardware reset BBP.
237 * HOST_READY: Host is ready after initialization, 1: ready.
238 */
239 #define MAC_CSR1 0x3004
240 #define MAC_CSR1_SOFT_RESET FIELD32(0x00000001)
241 #define MAC_CSR1_BBP_RESET FIELD32(0x00000002)
242 #define MAC_CSR1_HOST_READY FIELD32(0x00000004)
244 /*
245 * MAC_CSR2: STA MAC register 0.
246 */
247 #define MAC_CSR2 0x3008
248 #define MAC_CSR2_BYTE0 FIELD32(0x000000ff)
249 #define MAC_CSR2_BYTE1 FIELD32(0x0000ff00)
250 #define MAC_CSR2_BYTE2 FIELD32(0x00ff0000)
251 #define MAC_CSR2_BYTE3 FIELD32(0xff000000)
253 /*
254 * MAC_CSR3: STA MAC register 1.
255 * UNICAST_TO_ME_MASK:
256 * Used to mask off bits from byte 5 of the MAC address
257 * to determine the UNICAST_TO_ME bit for RX frames.
258 * The full mask is complemented by BSS_ID_MASK:
259 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
260 */
261 #define MAC_CSR3 0x300c
262 #define MAC_CSR3_BYTE4 FIELD32(0x000000ff)
263 #define MAC_CSR3_BYTE5 FIELD32(0x0000ff00)
264 #define MAC_CSR3_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
266 /*
267 * MAC_CSR4: BSSID register 0.
268 */
269 #define MAC_CSR4 0x3010
270 #define MAC_CSR4_BYTE0 FIELD32(0x000000ff)
271 #define MAC_CSR4_BYTE1 FIELD32(0x0000ff00)
272 #define MAC_CSR4_BYTE2 FIELD32(0x00ff0000)
273 #define MAC_CSR4_BYTE3 FIELD32(0xff000000)
275 /*
276 * MAC_CSR5: BSSID register 1.
277 * BSS_ID_MASK:
278 * This mask is used to mask off bits 0 and 1 of byte 5 of the
279 * BSSID. This will make sure that those bits will be ignored
280 * when determining the MY_BSS of RX frames.
281 * 0: 1-BSSID mode (BSS index = 0)
282 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
283 * 2: 2-BSSID mode (BSS index: byte5, bit 1)
284 * 3: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
285 */
286 #define MAC_CSR5 0x3014
287 #define MAC_CSR5_BYTE4 FIELD32(0x000000ff)
288 #define MAC_CSR5_BYTE5 FIELD32(0x0000ff00)
289 #define MAC_CSR5_BSS_ID_MASK FIELD32(0x00ff0000)
291 /*
292 * MAC_CSR6: Maximum frame length register.
293 */
294 #define MAC_CSR6 0x3018
295 #define MAC_CSR6_MAX_FRAME_UNIT FIELD32(0x00000fff)
297 /*
298 * MAC_CSR7: Reserved
299 */
300 #define MAC_CSR7 0x301c
302 /*
303 * MAC_CSR8: SIFS/EIFS register.
304 * All units are in US.
305 */
306 #define MAC_CSR8 0x3020
307 #define MAC_CSR8_SIFS FIELD32(0x000000ff)
308 #define MAC_CSR8_SIFS_AFTER_RX_OFDM FIELD32(0x0000ff00)
309 #define MAC_CSR8_EIFS FIELD32(0xffff0000)
311 /*
312 * MAC_CSR9: Back-Off control register.
313 * SLOT_TIME: Slot time, default is 20us for 802.11BG.
314 * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
315 * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
316 * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
317 */
318 #define MAC_CSR9 0x3024
319 #define MAC_CSR9_SLOT_TIME FIELD32(0x000000ff)
320 #define MAC_CSR9_CWMIN FIELD32(0x00000f00)
321 #define MAC_CSR9_CWMAX FIELD32(0x0000f000)
322 #define MAC_CSR9_CW_SELECT FIELD32(0x00010000)
324 /*
325 * MAC_CSR10: Power state configuration.
326 */
327 #define MAC_CSR10 0x3028
329 /*
330 * MAC_CSR11: Power saving transition time register.
331 * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.
332 * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
333 * WAKEUP_LATENCY: In unit of TU.
334 */
335 #define MAC_CSR11 0x302c
336 #define MAC_CSR11_DELAY_AFTER_TBCN FIELD32(0x000000ff)
337 #define MAC_CSR11_TBCN_BEFORE_WAKEUP FIELD32(0x00007f00)
338 #define MAC_CSR11_AUTOWAKE FIELD32(0x00008000)
339 #define MAC_CSR11_WAKEUP_LATENCY FIELD32(0x000f0000)
341 /*
342 * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).
343 * CURRENT_STATE: 0:sleep, 1:awake.
344 * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.
345 * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
346 */
347 #define MAC_CSR12 0x3030
348 #define MAC_CSR12_CURRENT_STATE FIELD32(0x00000001)
349 #define MAC_CSR12_PUT_TO_SLEEP FIELD32(0x00000002)
350 #define MAC_CSR12_FORCE_WAKEUP FIELD32(0x00000004)
351 #define MAC_CSR12_BBP_CURRENT_STATE FIELD32(0x00000008)
353 /*
354 * MAC_CSR13: GPIO.
355 */
356 #define MAC_CSR13 0x3034
357 #define MAC_CSR13_BIT0 FIELD32(0x00000001)
358 #define MAC_CSR13_BIT1 FIELD32(0x00000002)
359 #define MAC_CSR13_BIT2 FIELD32(0x00000004)
360 #define MAC_CSR13_BIT3 FIELD32(0x00000008)
361 #define MAC_CSR13_BIT4 FIELD32(0x00000010)
362 #define MAC_CSR13_BIT5 FIELD32(0x00000020)
363 #define MAC_CSR13_BIT6 FIELD32(0x00000040)
364 #define MAC_CSR13_BIT7 FIELD32(0x00000080)
365 #define MAC_CSR13_BIT8 FIELD32(0x00000100)
366 #define MAC_CSR13_BIT9 FIELD32(0x00000200)
367 #define MAC_CSR13_BIT10 FIELD32(0x00000400)
368 #define MAC_CSR13_BIT11 FIELD32(0x00000800)
369 #define MAC_CSR13_BIT12 FIELD32(0x00001000)
371 /*
372 * MAC_CSR14: LED control register.
373 * ON_PERIOD: On period, default 70ms.
374 * OFF_PERIOD: Off period, default 30ms.
375 * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
376 * SW_LED: s/w LED, 1: ON, 0: OFF.
377 * HW_LED_POLARITY: 0: active low, 1: active high.
378 */
379 #define MAC_CSR14 0x3038
380 #define MAC_CSR14_ON_PERIOD FIELD32(0x000000ff)
381 #define MAC_CSR14_OFF_PERIOD FIELD32(0x0000ff00)
382 #define MAC_CSR14_HW_LED FIELD32(0x00010000)
383 #define MAC_CSR14_SW_LED FIELD32(0x00020000)
384 #define MAC_CSR14_HW_LED_POLARITY FIELD32(0x00040000)
385 #define MAC_CSR14_SW_LED2 FIELD32(0x00080000)
387 /*
388 * MAC_CSR15: NAV control.
389 */
390 #define MAC_CSR15 0x303c
392 /*
393 * TXRX control registers.
394 * Some values are set in TU, whereas 1 TU == 1024 us.
395 */
397 /*
398 * TXRX_CSR0: TX/RX configuration register.
399 * TSF_OFFSET: Default is 24.
400 * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.
401 * DISABLE_RX: Disable Rx engine.
402 * DROP_CRC: Drop CRC error.
403 * DROP_PHYSICAL: Drop physical error.
404 * DROP_CONTROL: Drop control frame.
405 * DROP_NOT_TO_ME: Drop not to me unicast frame.
406 * DROP_TO_DS: Drop fram ToDs bit is true.
407 * DROP_VERSION_ERROR: Drop version error frame.
408 * DROP_MULTICAST: Drop multicast frames.
409 * DROP_BORADCAST: Drop broadcast frames.
410 * ROP_ACK_CTS: Drop received ACK and CTS.
411 */
412 #define TXRX_CSR0 0x3040
413 #define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff)
414 #define TXRX_CSR0_TSF_OFFSET FIELD32(0x00007e00)
415 #define TXRX_CSR0_AUTO_TX_SEQ FIELD32(0x00008000)
416 #define TXRX_CSR0_DISABLE_RX FIELD32(0x00010000)
417 #define TXRX_CSR0_DROP_CRC FIELD32(0x00020000)
418 #define TXRX_CSR0_DROP_PHYSICAL FIELD32(0x00040000)
419 #define TXRX_CSR0_DROP_CONTROL FIELD32(0x00080000)
420 #define TXRX_CSR0_DROP_NOT_TO_ME FIELD32(0x00100000)
421 #define TXRX_CSR0_DROP_TO_DS FIELD32(0x00200000)
422 #define TXRX_CSR0_DROP_VERSION_ERROR FIELD32(0x00400000)
423 #define TXRX_CSR0_DROP_MULTICAST FIELD32(0x00800000)
424 #define TXRX_CSR0_DROP_BROADCAST FIELD32(0x01000000)
425 #define TXRX_CSR0_DROP_ACK_CTS FIELD32(0x02000000)
426 #define TXRX_CSR0_TX_WITHOUT_WAITING FIELD32(0x04000000)
428 /*
429 * TXRX_CSR1
430 */
431 #define TXRX_CSR1 0x3044
432 #define TXRX_CSR1_BBP_ID0 FIELD32(0x0000007f)
433 #define TXRX_CSR1_BBP_ID0_VALID FIELD32(0x00000080)
434 #define TXRX_CSR1_BBP_ID1 FIELD32(0x00007f00)
435 #define TXRX_CSR1_BBP_ID1_VALID FIELD32(0x00008000)
436 #define TXRX_CSR1_BBP_ID2 FIELD32(0x007f0000)
437 #define TXRX_CSR1_BBP_ID2_VALID FIELD32(0x00800000)
438 #define TXRX_CSR1_BBP_ID3 FIELD32(0x7f000000)
439 #define TXRX_CSR1_BBP_ID3_VALID FIELD32(0x80000000)
441 /*
442 * TXRX_CSR2
443 */
444 #define TXRX_CSR2 0x3048
445 #define TXRX_CSR2_BBP_ID0 FIELD32(0x0000007f)
446 #define TXRX_CSR2_BBP_ID0_VALID FIELD32(0x00000080)
447 #define TXRX_CSR2_BBP_ID1 FIELD32(0x00007f00)
448 #define TXRX_CSR2_BBP_ID1_VALID FIELD32(0x00008000)
449 #define TXRX_CSR2_BBP_ID2 FIELD32(0x007f0000)
450 #define TXRX_CSR2_BBP_ID2_VALID FIELD32(0x00800000)
451 #define TXRX_CSR2_BBP_ID3 FIELD32(0x7f000000)
452 #define TXRX_CSR2_BBP_ID3_VALID FIELD32(0x80000000)
454 /*
455 * TXRX_CSR3
456 */
457 #define TXRX_CSR3 0x304c
458 #define TXRX_CSR3_BBP_ID0 FIELD32(0x0000007f)
459 #define TXRX_CSR3_BBP_ID0_VALID FIELD32(0x00000080)
460 #define TXRX_CSR3_BBP_ID1 FIELD32(0x00007f00)
461 #define TXRX_CSR3_BBP_ID1_VALID FIELD32(0x00008000)
462 #define TXRX_CSR3_BBP_ID2 FIELD32(0x007f0000)
463 #define TXRX_CSR3_BBP_ID2_VALID FIELD32(0x00800000)
464 #define TXRX_CSR3_BBP_ID3 FIELD32(0x7f000000)
465 #define TXRX_CSR3_BBP_ID3_VALID FIELD32(0x80000000)
467 /*
468 * TXRX_CSR4: Auto-Responder/Tx-retry register.
469 * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.
470 * OFDM_TX_RATE_DOWN: 1:enable.
471 * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.
472 * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.
473 */
474 #define TXRX_CSR4 0x3050
475 #define TXRX_CSR4_TX_ACK_TIMEOUT FIELD32(0x000000ff)
476 #define TXRX_CSR4_CNTL_ACK_POLICY FIELD32(0x00000700)
477 #define TXRX_CSR4_ACK_CTS_PSM FIELD32(0x00010000)
478 #define TXRX_CSR4_AUTORESPOND_ENABLE FIELD32(0x00020000)
479 #define TXRX_CSR4_AUTORESPOND_PREAMBLE FIELD32(0x00040000)
480 #define TXRX_CSR4_OFDM_TX_RATE_DOWN FIELD32(0x00080000)
481 #define TXRX_CSR4_OFDM_TX_RATE_STEP FIELD32(0x00300000)
482 #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK FIELD32(0x00400000)
483 #define TXRX_CSR4_LONG_RETRY_LIMIT FIELD32(0x0f000000)
484 #define TXRX_CSR4_SHORT_RETRY_LIMIT FIELD32(0xf0000000)
486 /*
487 * TXRX_CSR5
488 */
489 #define TXRX_CSR5 0x3054
491 /*
492 * TXRX_CSR6: ACK/CTS payload consumed time
493 */
494 #define TXRX_CSR6 0x3058
496 /*
497 * TXRX_CSR7: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
498 */
499 #define TXRX_CSR7 0x305c
500 #define TXRX_CSR7_ACK_CTS_6MBS FIELD32(0x000000ff)
501 #define TXRX_CSR7_ACK_CTS_9MBS FIELD32(0x0000ff00)
502 #define TXRX_CSR7_ACK_CTS_12MBS FIELD32(0x00ff0000)
503 #define TXRX_CSR7_ACK_CTS_18MBS FIELD32(0xff000000)
505 /*
506 * TXRX_CSR8: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
507 */
508 #define TXRX_CSR8 0x3060
509 #define TXRX_CSR8_ACK_CTS_24MBS FIELD32(0x000000ff)
510 #define TXRX_CSR8_ACK_CTS_36MBS FIELD32(0x0000ff00)
511 #define TXRX_CSR8_ACK_CTS_48MBS FIELD32(0x00ff0000)
512 #define TXRX_CSR8_ACK_CTS_54MBS FIELD32(0xff000000)
514 /*
515 * TXRX_CSR9: Synchronization control register.
516 * BEACON_INTERVAL: In unit of 1/16 TU.
517 * TSF_TICKING: Enable TSF auto counting.
518 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
519 * BEACON_GEN: Enable beacon generator.
520 */
521 #define TXRX_CSR9 0x3064
522 #define TXRX_CSR9_BEACON_INTERVAL FIELD32(0x0000ffff)
523 #define TXRX_CSR9_TSF_TICKING FIELD32(0x00010000)
524 #define TXRX_CSR9_TSF_SYNC FIELD32(0x00060000)
525 #define TXRX_CSR9_TBTT_ENABLE FIELD32(0x00080000)
526 #define TXRX_CSR9_BEACON_GEN FIELD32(0x00100000)
527 #define TXRX_CSR9_TIMESTAMP_COMPENSATE FIELD32(0xff000000)
529 /*
530 * TXRX_CSR10: BEACON alignment.
531 */
532 #define TXRX_CSR10 0x3068
534 /*
535 * TXRX_CSR11: AES mask.
536 */
537 #define TXRX_CSR11 0x306c
539 /*
540 * TXRX_CSR12: TSF low 32.
541 */
542 #define TXRX_CSR12 0x3070
543 #define TXRX_CSR12_LOW_TSFTIMER FIELD32(0xffffffff)
545 /*
546 * TXRX_CSR13: TSF high 32.
547 */
548 #define TXRX_CSR13 0x3074
549 #define TXRX_CSR13_HIGH_TSFTIMER FIELD32(0xffffffff)
551 /*
552 * TXRX_CSR14: TBTT timer.
553 */
554 #define TXRX_CSR14 0x3078
556 /*
557 * TXRX_CSR15: TKIP MIC priority byte "AND" mask.
558 */
559 #define TXRX_CSR15 0x307c
561 /*
562 * PHY control registers.
563 * Some values are set in TU, whereas 1 TU == 1024 us.
564 */
566 /*
567 * PHY_CSR0: RF/PS control.
568 */
569 #define PHY_CSR0 0x3080
570 #define PHY_CSR0_PA_PE_BG FIELD32(0x00010000)
571 #define PHY_CSR0_PA_PE_A FIELD32(0x00020000)
573 /*
574 * PHY_CSR1
575 */
576 #define PHY_CSR1 0x3084
578 /*
579 * PHY_CSR2: Pre-TX BBP control.
580 */
581 #define PHY_CSR2 0x3088
583 /*
584 * PHY_CSR3: BBP serial control register.
585 * VALUE: Register value to program into BBP.
586 * REG_NUM: Selected BBP register.
587 * READ_CONTROL: 0: Write BBP, 1: Read BBP.
588 * BUSY: 1: ASIC is busy execute BBP programming.
589 */
590 #define PHY_CSR3 0x308c
591 #define PHY_CSR3_VALUE FIELD32(0x000000ff)
592 #define PHY_CSR3_REGNUM FIELD32(0x00007f00)
593 #define PHY_CSR3_READ_CONTROL FIELD32(0x00008000)
594 #define PHY_CSR3_BUSY FIELD32(0x00010000)
596 /*
597 * PHY_CSR4: RF serial control register
598 * VALUE: Register value (include register id) serial out to RF/IF chip.
599 * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22).
600 * IF_SELECT: 1: select IF to program, 0: select RF to program.
601 * PLL_LD: RF PLL_LD status.
602 * BUSY: 1: ASIC is busy execute RF programming.
603 */
604 #define PHY_CSR4 0x3090
605 #define PHY_CSR4_VALUE FIELD32(0x00ffffff)
606 #define PHY_CSR4_NUMBER_OF_BITS FIELD32(0x1f000000)
607 #define PHY_CSR4_IF_SELECT FIELD32(0x20000000)
608 #define PHY_CSR4_PLL_LD FIELD32(0x40000000)
609 #define PHY_CSR4_BUSY FIELD32(0x80000000)
611 /*
612 * PHY_CSR5: RX to TX signal switch timing control.
613 */
614 #define PHY_CSR5 0x3094
615 #define PHY_CSR5_IQ_FLIP FIELD32(0x00000004)
617 /*
618 * PHY_CSR6: TX to RX signal timing control.
619 */
620 #define PHY_CSR6 0x3098
621 #define PHY_CSR6_IQ_FLIP FIELD32(0x00000004)
623 /*
624 * PHY_CSR7: TX DAC switching timing control.
625 */
626 #define PHY_CSR7 0x309c
628 /*
629 * Security control register.
630 */
632 /*
633 * SEC_CSR0: Shared key table control.
634 */
635 #define SEC_CSR0 0x30a0
636 #define SEC_CSR0_BSS0_KEY0_VALID FIELD32(0x00000001)
637 #define SEC_CSR0_BSS0_KEY1_VALID FIELD32(0x00000002)
638 #define SEC_CSR0_BSS0_KEY2_VALID FIELD32(0x00000004)
639 #define SEC_CSR0_BSS0_KEY3_VALID FIELD32(0x00000008)
640 #define SEC_CSR0_BSS1_KEY0_VALID FIELD32(0x00000010)
641 #define SEC_CSR0_BSS1_KEY1_VALID FIELD32(0x00000020)
642 #define SEC_CSR0_BSS1_KEY2_VALID FIELD32(0x00000040)
643 #define SEC_CSR0_BSS1_KEY3_VALID FIELD32(0x00000080)
644 #define SEC_CSR0_BSS2_KEY0_VALID FIELD32(0x00000100)
645 #define SEC_CSR0_BSS2_KEY1_VALID FIELD32(0x00000200)
646 #define SEC_CSR0_BSS2_KEY2_VALID FIELD32(0x00000400)
647 #define SEC_CSR0_BSS2_KEY3_VALID FIELD32(0x00000800)
648 #define SEC_CSR0_BSS3_KEY0_VALID FIELD32(0x00001000)
649 #define SEC_CSR0_BSS3_KEY1_VALID FIELD32(0x00002000)
650 #define SEC_CSR0_BSS3_KEY2_VALID FIELD32(0x00004000)
651 #define SEC_CSR0_BSS3_KEY3_VALID FIELD32(0x00008000)
653 /*
654 * SEC_CSR1: Shared key table security mode register.
655 */
656 #define SEC_CSR1 0x30a4
657 #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG FIELD32(0x00000007)
658 #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG FIELD32(0x00000070)
659 #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG FIELD32(0x00000700)
660 #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG FIELD32(0x00007000)
661 #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG FIELD32(0x00070000)
662 #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG FIELD32(0x00700000)
663 #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG FIELD32(0x07000000)
664 #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG FIELD32(0x70000000)
666 /*
667 * Pairwise key table valid bitmap registers.
668 * SEC_CSR2: pairwise key table valid bitmap 0.
669 * SEC_CSR3: pairwise key table valid bitmap 1.
670 */
671 #define SEC_CSR2 0x30a8
672 #define SEC_CSR3 0x30ac
674 /*
675 * SEC_CSR4: Pairwise key table lookup control.
676 */
677 #define SEC_CSR4 0x30b0
678 #define SEC_CSR4_ENABLE_BSS0 FIELD32(0x00000001)
679 #define SEC_CSR4_ENABLE_BSS1 FIELD32(0x00000002)
680 #define SEC_CSR4_ENABLE_BSS2 FIELD32(0x00000004)
681 #define SEC_CSR4_ENABLE_BSS3 FIELD32(0x00000008)
683 /*
684 * SEC_CSR5: shared key table security mode register.
685 */
686 #define SEC_CSR5 0x30b4
687 #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG FIELD32(0x00000007)
688 #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG FIELD32(0x00000070)
689 #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG FIELD32(0x00000700)
690 #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG FIELD32(0x00007000)
691 #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG FIELD32(0x00070000)
692 #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG FIELD32(0x00700000)
693 #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG FIELD32(0x07000000)
694 #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG FIELD32(0x70000000)
696 /*
697 * STA control registers.
698 */
700 /*
701 * STA_CSR0: RX PLCP error count & RX FCS error count.
702 */
703 #define STA_CSR0 0x30c0
704 #define STA_CSR0_FCS_ERROR FIELD32(0x0000ffff)
705 #define STA_CSR0_PLCP_ERROR FIELD32(0xffff0000)
707 /*
708 * STA_CSR1: RX False CCA count & RX LONG frame count.
709 */
710 #define STA_CSR1 0x30c4
711 #define STA_CSR1_PHYSICAL_ERROR FIELD32(0x0000ffff)
712 #define STA_CSR1_FALSE_CCA_ERROR FIELD32(0xffff0000)
714 /*
715 * STA_CSR2: TX Beacon count and RX FIFO overflow count.
716 */
717 #define STA_CSR2 0x30c8
718 #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
719 #define STA_CSR2_RX_OVERFLOW_COUNT FIELD32(0xffff0000)
721 /*
722 * STA_CSR3: TX Beacon count.
723 */
724 #define STA_CSR3 0x30cc
725 #define STA_CSR3_TX_BEACON_COUNT FIELD32(0x0000ffff)
727 /*
728 * STA_CSR4: TX Result status register.
729 * VALID: 1:This register contains a valid TX result.
730 */
731 #define STA_CSR4 0x30d0
732 #define STA_CSR4_VALID FIELD32(0x00000001)
733 #define STA_CSR4_TX_RESULT FIELD32(0x0000000e)
734 #define STA_CSR4_RETRY_COUNT FIELD32(0x000000f0)
735 #define STA_CSR4_PID_SUBTYPE FIELD32(0x00001f00)
736 #define STA_CSR4_PID_TYPE FIELD32(0x0000e000)
737 #define STA_CSR4_TXRATE FIELD32(0x000f0000)
739 /*
740 * QOS control registers.
741 */
743 /*
744 * QOS_CSR0: TXOP holder MAC address register.
745 */
746 #define QOS_CSR0 0x30e0
747 #define QOS_CSR0_BYTE0 FIELD32(0x000000ff)
748 #define QOS_CSR0_BYTE1 FIELD32(0x0000ff00)
749 #define QOS_CSR0_BYTE2 FIELD32(0x00ff0000)
750 #define QOS_CSR0_BYTE3 FIELD32(0xff000000)
752 /*
753 * QOS_CSR1: TXOP holder MAC address register.
754 */
755 #define QOS_CSR1 0x30e4
756 #define QOS_CSR1_BYTE4 FIELD32(0x000000ff)
757 #define QOS_CSR1_BYTE5 FIELD32(0x0000ff00)
759 /*
760 * QOS_CSR2: TXOP holder timeout register.
761 */
762 #define QOS_CSR2 0x30e8
764 /*
765 * RX QOS-CFPOLL MAC address register.
766 * QOS_CSR3: RX QOS-CFPOLL MAC address 0.
767 * QOS_CSR4: RX QOS-CFPOLL MAC address 1.
768 */
769 #define QOS_CSR3 0x30ec
770 #define QOS_CSR4 0x30f0
772 /*
773 * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL.
774 */
775 #define QOS_CSR5 0x30f4
777 /*
778 * Host DMA registers.
779 */
781 /*
782 * AC0_BASE_CSR: AC_BK base address.
783 */
784 #define AC0_BASE_CSR 0x3400
785 #define AC0_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
787 /*
788 * AC1_BASE_CSR: AC_BE base address.
789 */
790 #define AC1_BASE_CSR 0x3404
791 #define AC1_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
793 /*
794 * AC2_BASE_CSR: AC_VI base address.
795 */
796 #define AC2_BASE_CSR 0x3408
797 #define AC2_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
799 /*
800 * AC3_BASE_CSR: AC_VO base address.
801 */
802 #define AC3_BASE_CSR 0x340c
803 #define AC3_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
805 /*
806 * MGMT_BASE_CSR: MGMT ring base address.
807 */
808 #define MGMT_BASE_CSR 0x3410
809 #define MGMT_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
811 /*
812 * TX_RING_CSR0: TX Ring size for AC_BK, AC_BE, AC_VI, AC_VO.
813 */
814 #define TX_RING_CSR0 0x3418
815 #define TX_RING_CSR0_AC0_RING_SIZE FIELD32(0x000000ff)
816 #define TX_RING_CSR0_AC1_RING_SIZE FIELD32(0x0000ff00)
817 #define TX_RING_CSR0_AC2_RING_SIZE FIELD32(0x00ff0000)
818 #define TX_RING_CSR0_AC3_RING_SIZE FIELD32(0xff000000)
820 /*
821 * TX_RING_CSR1: TX Ring size for MGMT Ring, HCCA Ring
822 * TXD_SIZE: In unit of 32-bit.
823 */
824 #define TX_RING_CSR1 0x341c
825 #define TX_RING_CSR1_MGMT_RING_SIZE FIELD32(0x000000ff)
826 #define TX_RING_CSR1_HCCA_RING_SIZE FIELD32(0x0000ff00)
827 #define TX_RING_CSR1_TXD_SIZE FIELD32(0x003f0000)
829 /*
830 * AIFSN_CSR: AIFSN for each EDCA AC.
831 * AIFSN0: For AC_BK.
832 * AIFSN1: For AC_BE.
833 * AIFSN2: For AC_VI.
834 * AIFSN3: For AC_VO.
835 */
836 #define AIFSN_CSR 0x3420
837 #define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f)
838 #define AIFSN_CSR_AIFSN1 FIELD32(0x000000f0)
839 #define AIFSN_CSR_AIFSN2 FIELD32(0x00000f00)
840 #define AIFSN_CSR_AIFSN3 FIELD32(0x0000f000)
842 /*
843 * CWMIN_CSR: CWmin for each EDCA AC.
844 * CWMIN0: For AC_BK.
845 * CWMIN1: For AC_BE.
846 * CWMIN2: For AC_VI.
847 * CWMIN3: For AC_VO.
848 */
849 #define CWMIN_CSR 0x3424
850 #define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f)
851 #define CWMIN_CSR_CWMIN1 FIELD32(0x000000f0)
852 #define CWMIN_CSR_CWMIN2 FIELD32(0x00000f00)
853 #define CWMIN_CSR_CWMIN3 FIELD32(0x0000f000)
855 /*
856 * CWMAX_CSR: CWmax for each EDCA AC.
857 * CWMAX0: For AC_BK.
858 * CWMAX1: For AC_BE.
859 * CWMAX2: For AC_VI.
860 * CWMAX3: For AC_VO.
861 */
862 #define CWMAX_CSR 0x3428
863 #define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f)
864 #define CWMAX_CSR_CWMAX1 FIELD32(0x000000f0)
865 #define CWMAX_CSR_CWMAX2 FIELD32(0x00000f00)
866 #define CWMAX_CSR_CWMAX3 FIELD32(0x0000f000)
868 /*
869 * TX_DMA_DST_CSR: TX DMA destination
870 * 0: TX ring0, 1: TX ring1, 2: TX ring2 3: invalid
871 */
872 #define TX_DMA_DST_CSR 0x342c
873 #define TX_DMA_DST_CSR_DEST_AC0 FIELD32(0x00000003)
874 #define TX_DMA_DST_CSR_DEST_AC1 FIELD32(0x0000000c)
875 #define TX_DMA_DST_CSR_DEST_AC2 FIELD32(0x00000030)
876 #define TX_DMA_DST_CSR_DEST_AC3 FIELD32(0x000000c0)
877 #define TX_DMA_DST_CSR_DEST_MGMT FIELD32(0x00000300)
879 /*
880 * TX_CNTL_CSR: KICK/Abort TX.
881 * KICK_TX_AC0: For AC_BK.
882 * KICK_TX_AC1: For AC_BE.
883 * KICK_TX_AC2: For AC_VI.
884 * KICK_TX_AC3: For AC_VO.
885 * ABORT_TX_AC0: For AC_BK.
886 * ABORT_TX_AC1: For AC_BE.
887 * ABORT_TX_AC2: For AC_VI.
888 * ABORT_TX_AC3: For AC_VO.
889 */
890 #define TX_CNTL_CSR 0x3430
891 #define TX_CNTL_CSR_KICK_TX_AC0 FIELD32(0x00000001)
892 #define TX_CNTL_CSR_KICK_TX_AC1 FIELD32(0x00000002)
893 #define TX_CNTL_CSR_KICK_TX_AC2 FIELD32(0x00000004)
894 #define TX_CNTL_CSR_KICK_TX_AC3 FIELD32(0x00000008)
895 #define TX_CNTL_CSR_KICK_TX_MGMT FIELD32(0x00000010)
896 #define TX_CNTL_CSR_ABORT_TX_AC0 FIELD32(0x00010000)
897 #define TX_CNTL_CSR_ABORT_TX_AC1 FIELD32(0x00020000)
898 #define TX_CNTL_CSR_ABORT_TX_AC2 FIELD32(0x00040000)
899 #define TX_CNTL_CSR_ABORT_TX_AC3 FIELD32(0x00080000)
900 #define TX_CNTL_CSR_ABORT_TX_MGMT FIELD32(0x00100000)
902 /*
903 * LOAD_TX_RING_CSR: Load RX desriptor
904 */
905 #define LOAD_TX_RING_CSR 0x3434
906 #define LOAD_TX_RING_CSR_LOAD_TXD_AC0 FIELD32(0x00000001)
907 #define LOAD_TX_RING_CSR_LOAD_TXD_AC1 FIELD32(0x00000002)
908 #define LOAD_TX_RING_CSR_LOAD_TXD_AC2 FIELD32(0x00000004)
909 #define LOAD_TX_RING_CSR_LOAD_TXD_AC3 FIELD32(0x00000008)
910 #define LOAD_TX_RING_CSR_LOAD_TXD_MGMT FIELD32(0x00000010)
912 /*
913 * Several read-only registers, for debugging.
914 */
915 #define AC0_TXPTR_CSR 0x3438
916 #define AC1_TXPTR_CSR 0x343c
917 #define AC2_TXPTR_CSR 0x3440
918 #define AC3_TXPTR_CSR 0x3444
919 #define MGMT_TXPTR_CSR 0x3448
921 /*
922 * RX_BASE_CSR
923 */
924 #define RX_BASE_CSR 0x3450
925 #define RX_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
927 /*
928 * RX_RING_CSR.
929 * RXD_SIZE: In unit of 32-bit.
930 */
931 #define RX_RING_CSR 0x3454
932 #define RX_RING_CSR_RING_SIZE FIELD32(0x000000ff)
933 #define RX_RING_CSR_RXD_SIZE FIELD32(0x00003f00)
934 #define RX_RING_CSR_RXD_WRITEBACK_SIZE FIELD32(0x00070000)
936 /*
937 * RX_CNTL_CSR
938 */
939 #define RX_CNTL_CSR 0x3458
940 #define RX_CNTL_CSR_ENABLE_RX_DMA FIELD32(0x00000001)
941 #define RX_CNTL_CSR_LOAD_RXD FIELD32(0x00000002)
943 /*
944 * RXPTR_CSR: Read-only, for debugging.
945 */
946 #define RXPTR_CSR 0x345c
948 /*
949 * PCI_CFG_CSR
950 */
951 #define PCI_CFG_CSR 0x3460
953 /*
954 * BUF_FORMAT_CSR
955 */
956 #define BUF_FORMAT_CSR 0x3464
958 /*
959 * INT_SOURCE_CSR: Interrupt source register.
960 * Write one to clear corresponding bit.
961 */
962 #define INT_SOURCE_CSR 0x3468
963 #define INT_SOURCE_CSR_TXDONE FIELD32(0x00000001)
964 #define INT_SOURCE_CSR_RXDONE FIELD32(0x00000002)
965 #define INT_SOURCE_CSR_BEACON_DONE FIELD32(0x00000004)
966 #define INT_SOURCE_CSR_TX_ABORT_DONE FIELD32(0x00000010)
967 #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00010000)
968 #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00020000)
969 #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00040000)
970 #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00080000)
971 #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00100000)
972 #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00200000)
974 /*
975 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
976 * MITIGATION_PERIOD: Interrupt mitigation in unit of 32 PCI clock.
977 */
978 #define INT_MASK_CSR 0x346c
979 #define INT_MASK_CSR_TXDONE FIELD32(0x00000001)
980 #define INT_MASK_CSR_RXDONE FIELD32(0x00000002)
981 #define INT_MASK_CSR_BEACON_DONE FIELD32(0x00000004)
982 #define INT_MASK_CSR_TX_ABORT_DONE FIELD32(0x00000010)
983 #define INT_MASK_CSR_ENABLE_MITIGATION FIELD32(0x00000080)
984 #define INT_MASK_CSR_MITIGATION_PERIOD FIELD32(0x0000ff00)
985 #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00010000)
986 #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00020000)
987 #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00040000)
988 #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00080000)
989 #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00100000)
990 #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00200000)
992 /*
993 * E2PROM_CSR: EEPROM control register.
994 * RELOAD: Write 1 to reload eeprom content.
995 * TYPE_93C46: 1: 93c46, 0:93c66.
996 * LOAD_STATUS: 1:loading, 0:done.
997 */
998 #define E2PROM_CSR 0x3470
999 #define E2PROM_CSR_RELOAD FIELD32(0x00000001)
1000 #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000002)
1001 #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000004)
1002 #define E2PROM_CSR_DATA_IN FIELD32(0x00000008)
1003 #define E2PROM_CSR_DATA_OUT FIELD32(0x00000010)
1004 #define E2PROM_CSR_TYPE_93C46 FIELD32(0x00000020)
1005 #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
1007 /*
1008 * AC_TXOP_CSR0: AC_BK/AC_BE TXOP register.
1009 * AC0_TX_OP: For AC_BK, in unit of 32us.
1010 * AC1_TX_OP: For AC_BE, in unit of 32us.
1011 */
1012 #define AC_TXOP_CSR0 0x3474
1013 #define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff)
1014 #define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000)
1016 /*
1017 * AC_TXOP_CSR1: AC_VO/AC_VI TXOP register.
1018 * AC2_TX_OP: For AC_VI, in unit of 32us.
1019 * AC3_TX_OP: For AC_VO, in unit of 32us.
1020 */
1021 #define AC_TXOP_CSR1 0x3478
1022 #define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff)
1023 #define AC_TXOP_CSR1_AC3_TX_OP FIELD32(0xffff0000)
1025 /*
1026 * DMA_STATUS_CSR
1027 */
1028 #define DMA_STATUS_CSR 0x3480
1030 /*
1031 * TEST_MODE_CSR
1032 */
1033 #define TEST_MODE_CSR 0x3484
1035 /*
1036 * UART0_TX_CSR
1037 */
1038 #define UART0_TX_CSR 0x3488
1040 /*
1041 * UART0_RX_CSR
1042 */
1043 #define UART0_RX_CSR 0x348c
1045 /*
1046 * UART0_FRAME_CSR
1047 */
1048 #define UART0_FRAME_CSR 0x3490
1050 /*
1051 * UART0_BUFFER_CSR
1052 */
1053 #define UART0_BUFFER_CSR 0x3494
1055 /*
1056 * IO_CNTL_CSR
1057 */
1058 #define IO_CNTL_CSR 0x3498
1060 /*
1061 * UART_INT_SOURCE_CSR
1062 */
1063 #define UART_INT_SOURCE_CSR 0x34a8
1065 /*
1066 * UART_INT_MASK_CSR
1067 */
1068 #define UART_INT_MASK_CSR 0x34ac
1070 /*
1071 * PBF_QUEUE_CSR
1072 */
1073 #define PBF_QUEUE_CSR 0x34b0
1075 /*
1076 * Firmware DMA registers.
1077 * Firmware DMA registers are dedicated for MCU usage
1078 * and should not be touched by host driver.
1079 * Therefore we skip the definition of these registers.
1080 */
1081 #define FW_TX_BASE_CSR 0x34c0
1082 #define FW_TX_START_CSR 0x34c4
1083 #define FW_TX_LAST_CSR 0x34c8
1084 #define FW_MODE_CNTL_CSR 0x34cc
1085 #define FW_TXPTR_CSR 0x34d0
1087 /*
1088 * 8051 firmware image.
1089 */
1093 #define FIRMWARE_IMAGE_BASE 0x4000
1095 /*
1096 * BBP registers.
1097 * The wordsize of the BBP is 8 bits.
1098 */
1100 /*
1101 * R2
1102 */
1103 #define BBP_R2_BG_MODE FIELD8(0x20)
1105 /*
1106 * R3
1107 */
1108 #define BBP_R3_SMART_MODE FIELD8(0x01)
1110 /*
1111 * R4: RX antenna control
1112 * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)
1113 */
1115 /*
1116 * ANTENNA_CONTROL semantics (guessed):
1117 * 0x1: Software controlled antenna switching (fixed or SW diversity)
1118 * 0x2: Hardware diversity.
1119 */
1120 #define BBP_R4_RX_ANTENNA_CONTROL FIELD8(0x03)
1121 #define BBP_R4_RX_FRAME_END FIELD8(0x20)
1123 /*
1124 * R77
1125 */
1126 #define BBP_R77_RX_ANTENNA FIELD8(0x03)
1128 /*
1129 * RF registers
1130 */
1132 /*
1133 * RF 3
1134 */
1135 #define RF3_TXPOWER FIELD32(0x00003e00)
1137 /*
1138 * RF 4
1139 */
1140 #define RF4_FREQ_OFFSET FIELD32(0x0003f000)
1142 /*
1143 * EEPROM content.
1144 * The wordsize of the EEPROM is 16 bits.
1145 */
1147 /*
1148 * HW MAC address.
1149 */
1150 #define EEPROM_MAC_ADDR_0 0x0002
1151 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1152 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1153 #define EEPROM_MAC_ADDR1 0x0003
1154 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1155 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1156 #define EEPROM_MAC_ADDR_2 0x0004
1157 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1158 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1160 /*
1161 * EEPROM antenna.
1162 * ANTENNA_NUM: Number of antenna's.
1163 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1164 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1165 * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.
1166 * DYN_TXAGC: Dynamic TX AGC control.
1167 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
1168 * RF_TYPE: Rf_type of this adapter.
1169 */
1170 #define EEPROM_ANTENNA 0x0010
1171 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
1172 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
1173 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
1174 #define EEPROM_ANTENNA_FRAME_TYPE FIELD16(0x0040)
1175 #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
1176 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
1177 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
1179 /*
1180 * EEPROM NIC config.
1181 * ENABLE_DIVERSITY: 1:enable, 0:disable.
1182 * EXTERNAL_LNA_BG: External LNA enable for 2.4G.
1183 * CARDBUS_ACCEL: 0:enable, 1:disable.
1184 * EXTERNAL_LNA_A: External LNA enable for 5G.
1185 */
1186 #define EEPROM_NIC 0x0011
1187 #define EEPROM_NIC_ENABLE_DIVERSITY FIELD16(0x0001)
1188 #define EEPROM_NIC_TX_DIVERSITY FIELD16(0x0002)
1189 #define EEPROM_NIC_TX_RX_FIXED FIELD16(0x000c)
1190 #define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0010)
1191 #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0020)
1192 #define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0040)
1194 /*
1195 * EEPROM geography.
1196 * GEO_A: Default geographical setting for 5GHz band
1197 * GEO: Default geographical setting.
1198 */
1199 #define EEPROM_GEOGRAPHY 0x0012
1200 #define EEPROM_GEOGRAPHY_GEO_A FIELD16(0x00ff)
1201 #define EEPROM_GEOGRAPHY_GEO FIELD16(0xff00)
1203 /*
1204 * EEPROM BBP.
1205 */
1206 #define EEPROM_BBP_START 0x0013
1207 #define EEPROM_BBP_SIZE 16
1208 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
1209 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
1211 /*
1212 * EEPROM TXPOWER 802.11G
1213 */
1214 #define EEPROM_TXPOWER_G_START 0x0023
1215 #define EEPROM_TXPOWER_G_SIZE 7
1216 #define EEPROM_TXPOWER_G_1 FIELD16(0x00ff)
1217 #define EEPROM_TXPOWER_G_2 FIELD16(0xff00)
1219 /*
1220 * EEPROM Frequency
1221 */
1222 #define EEPROM_FREQ 0x002f
1223 #define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
1224 #define EEPROM_FREQ_SEQ_MASK FIELD16(0xff00)
1225 #define EEPROM_FREQ_SEQ FIELD16(0x0300)
1227 /*
1228 * EEPROM LED.
1229 * POLARITY_RDY_G: Polarity RDY_G setting.
1230 * POLARITY_RDY_A: Polarity RDY_A setting.
1231 * POLARITY_ACT: Polarity ACT setting.
1232 * POLARITY_GPIO_0: Polarity GPIO0 setting.
1233 * POLARITY_GPIO_1: Polarity GPIO1 setting.
1234 * POLARITY_GPIO_2: Polarity GPIO2 setting.
1235 * POLARITY_GPIO_3: Polarity GPIO3 setting.
1236 * POLARITY_GPIO_4: Polarity GPIO4 setting.
1237 * LED_MODE: Led mode.
1238 */
1239 #define EEPROM_LED 0x0030
1240 #define EEPROM_LED_POLARITY_RDY_G FIELD16(0x0001)
1241 #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
1242 #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
1243 #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
1244 #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
1245 #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
1246 #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
1247 #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
1248 #define EEPROM_LED_LED_MODE FIELD16(0x1f00)
1250 /*
1251 * EEPROM TXPOWER 802.11A
1252 */
1253 #define EEPROM_TXPOWER_A_START 0x0031
1254 #define EEPROM_TXPOWER_A_SIZE 12
1255 #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
1256 #define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
1258 /*
1259 * EEPROM RSSI offset 802.11BG
1260 */
1261 #define EEPROM_RSSI_OFFSET_BG 0x004d
1262 #define EEPROM_RSSI_OFFSET_BG_1 FIELD16(0x00ff)
1263 #define EEPROM_RSSI_OFFSET_BG_2 FIELD16(0xff00)
1265 /*
1266 * EEPROM RSSI offset 802.11A
1267 */
1268 #define EEPROM_RSSI_OFFSET_A 0x004e
1269 #define EEPROM_RSSI_OFFSET_A_1 FIELD16(0x00ff)
1270 #define EEPROM_RSSI_OFFSET_A_2 FIELD16(0xff00)
1272 /*
1273 * MCU mailbox commands.
1274 */
1275 #define MCU_SLEEP 0x30
1276 #define MCU_WAKEUP 0x31
1277 #define MCU_LED 0x50
1278 #define MCU_LED_STRENGTH 0x52
1280 /*
1281 * DMA descriptor defines.
1282 */
1283 #define TXD_DESC_SIZE ( 16 * sizeof(__le32) )
1284 #define TXINFO_SIZE ( 6 * sizeof(__le32) )
1285 #define RXD_DESC_SIZE ( 16 * sizeof(__le32) )
1287 /*
1288 * TX descriptor format for TX, PRIO and Beacon Ring.
1289 */
1291 /*
1292 * Word0
1293 * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used.
1294 * KEY_TABLE: Use per-client pairwise KEY table.
1295 * KEY_INDEX:
1296 * Key index (0~31) to the pairwise KEY table.
1297 * 0~3 to shared KEY table 0 (BSS0).
1298 * 4~7 to shared KEY table 1 (BSS1).
1299 * 8~11 to shared KEY table 2 (BSS2).
1300 * 12~15 to shared KEY table 3 (BSS3).
1301 * BURST: Next frame belongs to same "burst" event.
1302 */
1303 #define TXD_W0_OWNER_NIC FIELD32(0x00000001)
1304 #define TXD_W0_VALID FIELD32(0x00000002)
1305 #define TXD_W0_MORE_FRAG FIELD32(0x00000004)
1306 #define TXD_W0_ACK FIELD32(0x00000008)
1307 #define TXD_W0_TIMESTAMP FIELD32(0x00000010)
1308 #define TXD_W0_OFDM FIELD32(0x00000020)
1309 #define TXD_W0_IFS FIELD32(0x00000040)
1310 #define TXD_W0_RETRY_MODE FIELD32(0x00000080)
1311 #define TXD_W0_TKIP_MIC FIELD32(0x00000100)
1312 #define TXD_W0_KEY_TABLE FIELD32(0x00000200)
1313 #define TXD_W0_KEY_INDEX FIELD32(0x0000fc00)
1314 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1315 #define TXD_W0_BURST FIELD32(0x10000000)
1316 #define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1318 /*
1319 * Word1
1320 * HOST_Q_ID: EDCA/HCCA queue ID.
1321 * HW_SEQUENCE: MAC overwrites the frame sequence number.
1322 * BUFFER_COUNT: Number of buffers in this TXD.
1323 */
1324 #define TXD_W1_HOST_Q_ID FIELD32(0x0000000f)
1325 #define TXD_W1_AIFSN FIELD32(0x000000f0)
1326 #define TXD_W1_CWMIN FIELD32(0x00000f00)
1327 #define TXD_W1_CWMAX FIELD32(0x0000f000)
1328 #define TXD_W1_IV_OFFSET FIELD32(0x003f0000)
1329 #define TXD_W1_PIGGY_BACK FIELD32(0x01000000)
1330 #define TXD_W1_HW_SEQUENCE FIELD32(0x10000000)
1331 #define TXD_W1_BUFFER_COUNT FIELD32(0xe0000000)
1333 /*
1334 * Word2: PLCP information
1335 */
1336 #define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
1337 #define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
1338 #define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
1339 #define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
1341 /*
1342 * Word3
1343 */
1344 #define TXD_W3_IV FIELD32(0xffffffff)
1346 /*
1347 * Word4
1348 */
1349 #define TXD_W4_EIV FIELD32(0xffffffff)
1351 /*
1352 * Word5
1353 * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field).
1354 * TXD_W5_PID_SUBTYPE: Driver assigned packet ID index for txdone handler.
1355 * TXD_W5_PID_TYPE: Driver assigned packet ID type for txdone handler.
1356 * WAITING_DMA_DONE_INT: TXD been filled with data
1357 * and waiting for TxDoneISR housekeeping.
1358 */
1359 #define TXD_W5_FRAME_OFFSET FIELD32(0x000000ff)
1360 #define TXD_W5_PID_SUBTYPE FIELD32(0x00001f00)
1361 #define TXD_W5_PID_TYPE FIELD32(0x0000e000)
1362 #define TXD_W5_TX_POWER FIELD32(0x00ff0000)
1363 #define TXD_W5_WAITING_DMA_DONE_INT FIELD32(0x01000000)
1365 /*
1366 * the above 24-byte is called TXINFO and will be DMAed to MAC block
1367 * through TXFIFO. MAC block use this TXINFO to control the transmission
1368 * behavior of this frame.
1369 * The following fields are not used by MAC block.
1370 * They are used by DMA block and HOST driver only.
1371 * Once a frame has been DMA to ASIC, all the following fields are useless
1372 * to ASIC.
1373 */
1375 /*
1376 * Word6-10: Buffer physical address
1377 */
1378 #define TXD_W6_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1379 #define TXD_W7_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1380 #define TXD_W8_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1381 #define TXD_W9_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1382 #define TXD_W10_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1384 /*
1385 * Word11-13: Buffer length
1386 */
1387 #define TXD_W11_BUFFER_LENGTH0 FIELD32(0x00000fff)
1388 #define TXD_W11_BUFFER_LENGTH1 FIELD32(0x0fff0000)
1389 #define TXD_W12_BUFFER_LENGTH2 FIELD32(0x00000fff)
1390 #define TXD_W12_BUFFER_LENGTH3 FIELD32(0x0fff0000)
1391 #define TXD_W13_BUFFER_LENGTH4 FIELD32(0x00000fff)
1393 /*
1394 * Word14
1395 */
1396 #define TXD_W14_SK_BUFFER FIELD32(0xffffffff)
1398 /*
1399 * Word15
1400 */
1401 #define TXD_W15_NEXT_SK_BUFFER FIELD32(0xffffffff)
1403 /*
1404 * RX descriptor format for RX Ring.
1405 */
1407 /*
1408 * Word0
1409 * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key.
1410 * KEY_INDEX: Decryption key actually used.
1411 */
1412 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
1413 #define RXD_W0_DROP FIELD32(0x00000002)
1414 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000004)
1415 #define RXD_W0_MULTICAST FIELD32(0x00000008)
1416 #define RXD_W0_BROADCAST FIELD32(0x00000010)
1417 #define RXD_W0_MY_BSS FIELD32(0x00000020)
1418 #define RXD_W0_CRC_ERROR FIELD32(0x00000040)
1419 #define RXD_W0_OFDM FIELD32(0x00000080)
1420 #define RXD_W0_CIPHER_ERROR FIELD32(0x00000300)
1421 #define RXD_W0_KEY_INDEX FIELD32(0x0000fc00)
1422 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1423 #define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1425 /*
1426 * Word1
1427 * SIGNAL: RX raw data rate reported by BBP.
1428 */
1429 #define RXD_W1_SIGNAL FIELD32(0x000000ff)
1430 #define RXD_W1_RSSI_AGC FIELD32(0x00001f00)
1431 #define RXD_W1_RSSI_LNA FIELD32(0x00006000)
1432 #define RXD_W1_FRAME_OFFSET FIELD32(0x7f000000)
1434 /*
1435 * Word2
1436 * IV: Received IV of originally encrypted.
1437 */
1438 #define RXD_W2_IV FIELD32(0xffffffff)
1440 /*
1441 * Word3
1442 * EIV: Received EIV of originally encrypted.
1443 */
1444 #define RXD_W3_EIV FIELD32(0xffffffff)
1446 /*
1447 * Word4
1448 * ICV: Received ICV of originally encrypted.
1449 * NOTE: This is a guess, the official definition is "reserved"
1450 */
1451 #define RXD_W4_ICV FIELD32(0xffffffff)
1453 /*
1454 * the above 20-byte is called RXINFO and will be DMAed to MAC RX block
1455 * and passed to the HOST driver.
1456 * The following fields are for DMA block and HOST usage only.
1457 * Can't be touched by ASIC MAC block.
1458 */
1460 /*
1461 * Word5
1462 */
1463 #define RXD_W5_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1465 /*
1466 * Word6-15: Reserved
1467 */
1468 #define RXD_W6_RESERVED FIELD32(0xffffffff)
1469 #define RXD_W7_RESERVED FIELD32(0xffffffff)
1470 #define RXD_W8_RESERVED FIELD32(0xffffffff)
1471 #define RXD_W9_RESERVED FIELD32(0xffffffff)
1472 #define RXD_W10_RESERVED FIELD32(0xffffffff)
1473 #define RXD_W11_RESERVED FIELD32(0xffffffff)
1474 #define RXD_W12_RESERVED FIELD32(0xffffffff)
1475 #define RXD_W13_RESERVED FIELD32(0xffffffff)
1476 #define RXD_W14_RESERVED FIELD32(0xffffffff)
1477 #define RXD_W15_RESERVED FIELD32(0xffffffff)
1479 /*
1480 * Macro's for converting txpower from EEPROM to mac80211 value
1481 * and from mac80211 value to register value.
1482 */
1483 #define MIN_TXPOWER 0
1484 #define MAX_TXPOWER 31
1485 #define DEFAULT_TXPOWER 24
1487 #define TXPOWER_FROM_DEV(__txpower) \
1488 (((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1490 #define TXPOWER_TO_DEV(__txpower) \
1491 clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)