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MERGE-master-patchset-edits
[linux-2.6/openmoko-kernel.git] / drivers / net / wireless / rt2x00 / rt2500pci.c
blobd3bc218ec85cc2debcd5dfd52e8c00fcdf4124bf
1 /*
2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt2500pci
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
25 */
26
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
34
35 #include "rt2x00.h"
36 #include "rt2x00pci.h"
37 #include "rt2500pci.h"
38
39 /*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 */
52 #define WAIT_FOR_BBP(__dev, __reg) \
53 rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
54 #define WAIT_FOR_RF(__dev, __reg) \
55 rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
56
57 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
58 const unsigned int word, const u8 value)
59 {
60 u32 reg;
61
62 mutex_lock(&rt2x00dev->csr_mutex);
63
64 /*
65 * Wait until the BBP becomes available, afterwards we
66 * can safely write the new data into the register.
67 */
68 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
69 reg = 0;
70 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
71 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
72 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
73 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
74
75 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
76 }
77
78 mutex_unlock(&rt2x00dev->csr_mutex);
79 }
80
81 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
82 const unsigned int word, u8 *value)
83 {
84 u32 reg;
85
86 mutex_lock(&rt2x00dev->csr_mutex);
87
88 /*
89 * Wait until the BBP becomes available, afterwards we
90 * can safely write the read request into the register.
91 * After the data has been written, we wait until hardware
92 * returns the correct value, if at any time the register
93 * doesn't become available in time, reg will be 0xffffffff
94 * which means we return 0xff to the caller.
95 */
96 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
97 reg = 0;
98 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
99 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
100 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
101
102 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
103
104 WAIT_FOR_BBP(rt2x00dev, &reg);
105 }
106
107 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110 }
111
112 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, const u32 value)
114 {
115 u32 reg;
116
117 if (!word)
118 return;
119
120 mutex_lock(&rt2x00dev->csr_mutex);
121
122 /*
123 * Wait until the RF becomes available, afterwards we
124 * can safely write the new data into the register.
125 */
126 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
127 reg = 0;
128 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
129 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
130 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
131 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
132
133 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
134 rt2x00_rf_write(rt2x00dev, word, value);
135 }
136
137 mutex_unlock(&rt2x00dev->csr_mutex);
138 }
139
140 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
141 {
142 struct rt2x00_dev *rt2x00dev = eeprom->data;
143 u32 reg;
144
145 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
146
147 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
148 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
149 eeprom->reg_data_clock =
150 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
151 eeprom->reg_chip_select =
152 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
153 }
154
155 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
156 {
157 struct rt2x00_dev *rt2x00dev = eeprom->data;
158 u32 reg = 0;
159
160 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
161 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
162 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
163 !!eeprom->reg_data_clock);
164 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
165 !!eeprom->reg_chip_select);
166
167 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
168 }
169
170 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
171 static const struct rt2x00debug rt2500pci_rt2x00debug = {
172 .owner = THIS_MODULE,
173 .csr = {
174 .read = rt2x00pci_register_read,
175 .write = rt2x00pci_register_write,
176 .flags = RT2X00DEBUGFS_OFFSET,
177 .word_base = CSR_REG_BASE,
178 .word_size = sizeof(u32),
179 .word_count = CSR_REG_SIZE / sizeof(u32),
180 },
181 .eeprom = {
182 .read = rt2x00_eeprom_read,
183 .write = rt2x00_eeprom_write,
184 .word_base = EEPROM_BASE,
185 .word_size = sizeof(u16),
186 .word_count = EEPROM_SIZE / sizeof(u16),
187 },
188 .bbp = {
189 .read = rt2500pci_bbp_read,
190 .write = rt2500pci_bbp_write,
191 .word_base = BBP_BASE,
192 .word_size = sizeof(u8),
193 .word_count = BBP_SIZE / sizeof(u8),
194 },
195 .rf = {
196 .read = rt2x00_rf_read,
197 .write = rt2500pci_rf_write,
198 .word_base = RF_BASE,
199 .word_size = sizeof(u32),
200 .word_count = RF_SIZE / sizeof(u32),
201 },
202 };
203 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
204
205 #ifdef CONFIG_RT2X00_LIB_RFKILL
206 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
207 {
208 u32 reg;
209
210 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
211 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
212 }
213 #else
214 #define rt2500pci_rfkill_poll NULL
215 #endif /* CONFIG_RT2X00_LIB_RFKILL */
216
217 #ifdef CONFIG_RT2X00_LIB_LEDS
218 static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
219 enum led_brightness brightness)
220 {
221 struct rt2x00_led *led =
222 container_of(led_cdev, struct rt2x00_led, led_dev);
223 unsigned int enabled = brightness != LED_OFF;
224 u32 reg;
225
226 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
227
228 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
229 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
230 else if (led->type == LED_TYPE_ACTIVITY)
231 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
232
233 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
234 }
235
236 static int rt2500pci_blink_set(struct led_classdev *led_cdev,
237 unsigned long *delay_on,
238 unsigned long *delay_off)
239 {
240 struct rt2x00_led *led =
241 container_of(led_cdev, struct rt2x00_led, led_dev);
242 u32 reg;
243
244 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
245 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
246 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
247 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
248
249 return 0;
250 }
251
252 static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
253 struct rt2x00_led *led,
254 enum led_type type)
255 {
256 led->rt2x00dev = rt2x00dev;
257 led->type = type;
258 led->led_dev.brightness_set = rt2500pci_brightness_set;
259 led->led_dev.blink_set = rt2500pci_blink_set;
260 led->flags = LED_INITIALIZED;
261 }
262 #endif /* CONFIG_RT2X00_LIB_LEDS */
263
264 /*
265 * Configuration handlers.
266 */
267 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
268 const unsigned int filter_flags)
269 {
270 u32 reg;
271
272 /*
273 * Start configuration steps.
274 * Note that the version error will always be dropped
275 * and broadcast frames will always be accepted since
276 * there is no filter for it at this time.
277 */
278 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
279 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
280 !(filter_flags & FIF_FCSFAIL));
281 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
282 !(filter_flags & FIF_PLCPFAIL));
283 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
284 !(filter_flags & FIF_CONTROL));
285 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
286 !(filter_flags & FIF_PROMISC_IN_BSS));
287 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
288 !(filter_flags & FIF_PROMISC_IN_BSS) &&
289 !rt2x00dev->intf_ap_count);
290 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
291 rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
292 !(filter_flags & FIF_ALLMULTI));
293 rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
294 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
295 }
296
297 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
298 struct rt2x00_intf *intf,
299 struct rt2x00intf_conf *conf,
300 const unsigned int flags)
301 {
302 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON);
303 unsigned int bcn_preload;
304 u32 reg;
305
306 if (flags & CONFIG_UPDATE_TYPE) {
307 /*
308 * Enable beacon config
309 */
310 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
311 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
312 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
313 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
314 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
315
316 /*
317 * Enable synchronisation.
318 */
319 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
320 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
321 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
322 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
323 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
324 }
325
326 if (flags & CONFIG_UPDATE_MAC)
327 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
328 conf->mac, sizeof(conf->mac));
329
330 if (flags & CONFIG_UPDATE_BSSID)
331 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
332 conf->bssid, sizeof(conf->bssid));
333 }
334
335 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
336 struct rt2x00lib_erp *erp)
337 {
338 int preamble_mask;
339 u32 reg;
340
341 /*
342 * When short preamble is enabled, we should set bit 0x08
343 */
344 preamble_mask = erp->short_preamble << 3;
345
346 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
347 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
348 erp->ack_timeout);
349 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
350 erp->ack_consume_time);
351 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
352
353 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
354 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
355 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
356 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
357 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
358
359 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
360 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
361 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
362 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
363 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
364
365 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
366 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
367 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
368 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
369 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
370
371 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
372 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
373 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
374 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
375 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
376
377 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
378
379 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
380 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
381 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
382
383 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
384 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
385 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
386 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
387
388 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
389 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
390 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
391 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
392 }
393
394 static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
395 struct antenna_setup *ant)
396 {
397 u32 reg;
398 u8 r14;
399 u8 r2;
400
401 /*
402 * We should never come here because rt2x00lib is supposed
403 * to catch this and send us the correct antenna explicitely.
404 */
405 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
406 ant->tx == ANTENNA_SW_DIVERSITY);
407
408 rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
409 rt2500pci_bbp_read(rt2x00dev, 14, &r14);
410 rt2500pci_bbp_read(rt2x00dev, 2, &r2);
411
412 /*
413 * Configure the TX antenna.
414 */
415 switch (ant->tx) {
416 case ANTENNA_A:
417 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
418 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
419 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
420 break;
421 case ANTENNA_B:
422 default:
423 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
424 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
425 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
426 break;
427 }
428
429 /*
430 * Configure the RX antenna.
431 */
432 switch (ant->rx) {
433 case ANTENNA_A:
434 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
435 break;
436 case ANTENNA_B:
437 default:
438 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
439 break;
440 }
441
442 /*
443 * RT2525E and RT5222 need to flip TX I/Q
444 */
445 if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
446 rt2x00_rf(&rt2x00dev->chip, RF5222)) {
447 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
448 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
449 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
450
451 /*
452 * RT2525E does not need RX I/Q Flip.
453 */
454 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
455 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
456 } else {
457 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
458 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
459 }
460
461 rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
462 rt2500pci_bbp_write(rt2x00dev, 14, r14);
463 rt2500pci_bbp_write(rt2x00dev, 2, r2);
464 }
465
466 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
467 struct rf_channel *rf, const int txpower)
468 {
469 u8 r70;
470
471 /*
472 * Set TXpower.
473 */
474 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
475
476 /*
477 * Switch on tuning bits.
478 * For RT2523 devices we do not need to update the R1 register.
479 */
480 if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
481 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
482 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
483
484 /*
485 * For RT2525 we should first set the channel to half band higher.
486 */
487 if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
488 static const u32 vals[] = {
489 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
490 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
491 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
492 0x00080d2e, 0x00080d3a
493 };
494
495 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
496 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
497 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
498 if (rf->rf4)
499 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
500 }
501
502 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
503 rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
504 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
505 if (rf->rf4)
506 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
507
508 /*
509 * Channel 14 requires the Japan filter bit to be set.
510 */
511 r70 = 0x46;
512 rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
513 rt2500pci_bbp_write(rt2x00dev, 70, r70);
514
515 msleep(1);
516
517 /*
518 * Switch off tuning bits.
519 * For RT2523 devices we do not need to update the R1 register.
520 */
521 if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
522 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
523 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
524 }
525
526 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
527 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
528
529 /*
530 * Clear false CRC during channel switch.
531 */
532 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
533 }
534
535 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
536 const int txpower)
537 {
538 u32 rf3;
539
540 rt2x00_rf_read(rt2x00dev, 3, &rf3);
541 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
542 rt2500pci_rf_write(rt2x00dev, 3, rf3);
543 }
544
545 static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
546 struct rt2x00lib_conf *libconf)
547 {
548 u32 reg;
549
550 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
551 rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
552 libconf->conf->long_frame_max_tx_count);
553 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
554 libconf->conf->short_frame_max_tx_count);
555 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
556 }
557
558 static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
559 struct rt2x00lib_conf *libconf)
560 {
561 u32 reg;
562
563 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
564 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
565 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
566 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
567
568 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
569 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
570 libconf->conf->beacon_int * 16);
571 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
572 libconf->conf->beacon_int * 16);
573 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
574 }
575
576 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
577 struct rt2x00lib_conf *libconf,
578 const unsigned int flags)
579 {
580 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
581 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
582 libconf->conf->power_level);
583 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
584 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
585 rt2500pci_config_txpower(rt2x00dev,
586 libconf->conf->power_level);
587 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
588 rt2500pci_config_retry_limit(rt2x00dev, libconf);
589 if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
590 rt2500pci_config_duration(rt2x00dev, libconf);
591 }
592
593 /*
594 * Link tuning
595 */
596 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
597 struct link_qual *qual)
598 {
599 u32 reg;
600
601 /*
602 * Update FCS error count from register.
603 */
604 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
605 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
606
607 /*
608 * Update False CCA count from register.
609 */
610 rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
611 qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
612 }
613
614 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
615 {
616 rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
617 rt2x00dev->link.vgc_level = 0x48;
618 }
619
620 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
621 {
622 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
623 u8 r17;
624
625 /*
626 * To prevent collisions with MAC ASIC on chipsets
627 * up to version C the link tuning should halt after 20
628 * seconds while being associated.
629 */
630 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
631 rt2x00dev->intf_associated &&
632 rt2x00dev->link.count > 20)
633 return;
634
635 rt2500pci_bbp_read(rt2x00dev, 17, &r17);
636
637 /*
638 * Chipset versions C and lower should directly continue
639 * to the dynamic CCA tuning. Chipset version D and higher
640 * should go straight to dynamic CCA tuning when they
641 * are not associated.
642 */
643 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D ||
644 !rt2x00dev->intf_associated)
645 goto dynamic_cca_tune;
646
647 /*
648 * A too low RSSI will cause too much false CCA which will
649 * then corrupt the R17 tuning. To remidy this the tuning should
650 * be stopped (While making sure the R17 value will not exceed limits)
651 */
652 if (rssi < -80 && rt2x00dev->link.count > 20) {
653 if (r17 >= 0x41) {
654 r17 = rt2x00dev->link.vgc_level;
655 rt2500pci_bbp_write(rt2x00dev, 17, r17);
656 }
657 return;
658 }
659
660 /*
661 * Special big-R17 for short distance
662 */
663 if (rssi >= -58) {
664 if (r17 != 0x50)
665 rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
666 return;
667 }
668
669 /*
670 * Special mid-R17 for middle distance
671 */
672 if (rssi >= -74) {
673 if (r17 != 0x41)
674 rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
675 return;
676 }
677
678 /*
679 * Leave short or middle distance condition, restore r17
680 * to the dynamic tuning range.
681 */
682 if (r17 >= 0x41) {
683 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
684 return;
685 }
686
687 dynamic_cca_tune:
688
689 /*
690 * R17 is inside the dynamic tuning range,
691 * start tuning the link based on the false cca counter.
692 */
693 if (rt2x00dev->link.qual.false_cca > 512 && r17 < 0x40) {
694 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
695 rt2x00dev->link.vgc_level = r17;
696 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > 0x32) {
697 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
698 rt2x00dev->link.vgc_level = r17;
699 }
700 }
701
702 /*
703 * Initialization functions.
704 */
705 static bool rt2500pci_get_entry_state(struct queue_entry *entry)
706 {
707 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
708 u32 word;
709
710 if (entry->queue->qid == QID_RX) {
711 rt2x00_desc_read(entry_priv->desc, 0, &word);
712
713 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
714 } else {
715 rt2x00_desc_read(entry_priv->desc, 0, &word);
716
717 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
718 rt2x00_get_field32(word, TXD_W0_VALID));
719 }
720 }
721
722 static void rt2500pci_clear_entry(struct queue_entry *entry)
723 {
724 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
725 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
726 u32 word;
727
728 if (entry->queue->qid == QID_RX) {
729 rt2x00_desc_read(entry_priv->desc, 1, &word);
730 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
731 rt2x00_desc_write(entry_priv->desc, 1, word);
732
733 rt2x00_desc_read(entry_priv->desc, 0, &word);
734 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
735 rt2x00_desc_write(entry_priv->desc, 0, word);
736 } else {
737 rt2x00_desc_read(entry_priv->desc, 0, &word);
738 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
739 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
740 rt2x00_desc_write(entry_priv->desc, 0, word);
741 }
742 }
743
744 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
745 {
746 struct queue_entry_priv_pci *entry_priv;
747 u32 reg;
748
749 /*
750 * Initialize registers.
751 */
752 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
753 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
754 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
755 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
756 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
757 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
758
759 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
760 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
761 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
762 entry_priv->desc_dma);
763 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
764
765 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
766 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
767 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
768 entry_priv->desc_dma);
769 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
770
771 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
772 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
773 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
774 entry_priv->desc_dma);
775 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
776
777 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
778 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
779 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
780 entry_priv->desc_dma);
781 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
782
783 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
784 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
785 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
786 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
787
788 entry_priv = rt2x00dev->rx->entries[0].priv_data;
789 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
790 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
791 entry_priv->desc_dma);
792 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
793
794 return 0;
795 }
796
797 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
798 {
799 u32 reg;
800
801 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
802 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
803 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
804 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
805
806 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
807 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
808 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
809 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
810 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
811
812 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
813 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
814 rt2x00dev->rx->data_size / 128);
815 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
816
817 /*
818 * Always use CWmin and CWmax set in descriptor.
819 */
820 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
821 rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
822 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
823
824 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
825 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
826 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
827 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
828 rt2x00_set_field32(&reg, CSR14_TCFP, 0);
829 rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
830 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
831 rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
832 rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
833 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
834
835 rt2x00pci_register_write(rt2x00dev, CNT3, 0);
836
837 rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
838 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
839 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
840 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
841 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
842 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
843 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
844 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
845 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
846 rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
847
848 rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
849 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
850 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
851 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
852 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
853 rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
854
855 rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
856 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
857 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
858 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
859 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
860 rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
861
862 rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
863 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
864 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
865 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
866 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
867 rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
868
869 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
870 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
871 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
872 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
873 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
874 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
875 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
876 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
877 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
878 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
879
880 rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
881 rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
882 rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
883 rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
884 rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
885 rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
886 rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
887 rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
888 rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
889
890 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
891
892 rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
893 rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
894
895 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
896 return -EBUSY;
897
898 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
899 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
900
901 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
902 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
903 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
904
905 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
906 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
907 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
908 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
909 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
910 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
911 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
912 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
913
914 rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
915
916 rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
917
918 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
919 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
920 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
921 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
922 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
923
924 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
925 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
926 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
927 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
928
929 /*
930 * We must clear the FCS and FIFO error count.
931 * These registers are cleared on read,
932 * so we may pass a useless variable to store the value.
933 */
934 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
935 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
936
937 return 0;
938 }
939
940 static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
941 {
942 unsigned int i;
943 u8 value;
944
945 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
946 rt2500pci_bbp_read(rt2x00dev, 0, &value);
947 if ((value != 0xff) && (value != 0x00))
948 return 0;
949 udelay(REGISTER_BUSY_DELAY);
950 }
951
952 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
953 return -EACCES;
954 }
955
956 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
957 {
958 unsigned int i;
959 u16 eeprom;
960 u8 reg_id;
961 u8 value;
962
963 if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
964 return -EACCES;
965
966 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
967 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
968 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
969 rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
970 rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
971 rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
972 rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
973 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
974 rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
975 rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
976 rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
977 rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
978 rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
979 rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
980 rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
981 rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
982 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
983 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
984 rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
985 rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
986 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
987 rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
988 rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
989 rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
990 rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
991 rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
992 rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
993 rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
994 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
995 rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
996
997 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
998 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
999
1000 if (eeprom != 0xffff && eeprom != 0x0000) {
1001 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1002 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1003 rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1004 }
1005 }
1006
1007 return 0;
1008 }
1009
1010 /*
1011 * Device state switch handlers.
1012 */
1013 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1014 enum dev_state state)
1015 {
1016 u32 reg;
1017
1018 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1019 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1020 (state == STATE_RADIO_RX_OFF) ||
1021 (state == STATE_RADIO_RX_OFF_LINK));
1022 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1023 }
1024
1025 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1026 enum dev_state state)
1027 {
1028 int mask = (state == STATE_RADIO_IRQ_OFF);
1029 u32 reg;
1030
1031 /*
1032 * When interrupts are being enabled, the interrupt registers
1033 * should clear the register to assure a clean state.
1034 */
1035 if (state == STATE_RADIO_IRQ_ON) {
1036 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1037 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1038 }
1039
1040 /*
1041 * Only toggle the interrupts bits we are going to use.
1042 * Non-checked interrupt bits are disabled by default.
1043 */
1044 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1045 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1046 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1047 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1048 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1049 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1050 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1051 }
1052
1053 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1054 {
1055 /*
1056 * Initialize all registers.
1057 */
1058 if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1059 rt2500pci_init_registers(rt2x00dev) ||
1060 rt2500pci_init_bbp(rt2x00dev)))
1061 return -EIO;
1062
1063 return 0;
1064 }
1065
1066 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1067 {
1068 u32 reg;
1069
1070 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1071
1072 /*
1073 * Disable synchronisation.
1074 */
1075 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1076
1077 /*
1078 * Cancel RX and TX.
1079 */
1080 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1081 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1082 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1083 }
1084
1085 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1086 enum dev_state state)
1087 {
1088 u32 reg;
1089 unsigned int i;
1090 char put_to_sleep;
1091 char bbp_state;
1092 char rf_state;
1093
1094 put_to_sleep = (state != STATE_AWAKE);
1095
1096 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1097 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1098 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1099 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1100 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1101 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1102
1103 /*
1104 * Device is not guaranteed to be in the requested state yet.
1105 * We must wait until the register indicates that the
1106 * device has entered the correct state.
1107 */
1108 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1109 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1110 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1111 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1112 if (bbp_state == state && rf_state == state)
1113 return 0;
1114 msleep(10);
1115 }
1116
1117 return -EBUSY;
1118 }
1119
1120 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1121 enum dev_state state)
1122 {
1123 int retval = 0;
1124
1125 switch (state) {
1126 case STATE_RADIO_ON:
1127 retval = rt2500pci_enable_radio(rt2x00dev);
1128 break;
1129 case STATE_RADIO_OFF:
1130 rt2500pci_disable_radio(rt2x00dev);
1131 break;
1132 case STATE_RADIO_RX_ON:
1133 case STATE_RADIO_RX_ON_LINK:
1134 case STATE_RADIO_RX_OFF:
1135 case STATE_RADIO_RX_OFF_LINK:
1136 rt2500pci_toggle_rx(rt2x00dev, state);
1137 break;
1138 case STATE_RADIO_IRQ_ON:
1139 case STATE_RADIO_IRQ_OFF:
1140 rt2500pci_toggle_irq(rt2x00dev, state);
1141 break;
1142 case STATE_DEEP_SLEEP:
1143 case STATE_SLEEP:
1144 case STATE_STANDBY:
1145 case STATE_AWAKE:
1146 retval = rt2500pci_set_state(rt2x00dev, state);
1147 break;
1148 default:
1149 retval = -ENOTSUPP;
1150 break;
1151 }
1152
1153 if (unlikely(retval))
1154 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1155 state, retval);
1156
1157 return retval;
1158 }
1159
1160 /*
1161 * TX descriptor initialization
1162 */
1163 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1164 struct sk_buff *skb,
1165 struct txentry_desc *txdesc)
1166 {
1167 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1168 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1169 __le32 *txd = skbdesc->desc;
1170 u32 word;
1171
1172 /*
1173 * Start writing the descriptor words.
1174 */
1175 rt2x00_desc_read(entry_priv->desc, 1, &word);
1176 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1177 rt2x00_desc_write(entry_priv->desc, 1, word);
1178
1179 rt2x00_desc_read(txd, 2, &word);
1180 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1181 rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1182 rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1183 rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
1184 rt2x00_desc_write(txd, 2, word);
1185
1186 rt2x00_desc_read(txd, 3, &word);
1187 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1188 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1189 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1190 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
1191 rt2x00_desc_write(txd, 3, word);
1192
1193 rt2x00_desc_read(txd, 10, &word);
1194 rt2x00_set_field32(&word, TXD_W10_RTS,
1195 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1196 rt2x00_desc_write(txd, 10, word);
1197
1198 rt2x00_desc_read(txd, 0, &word);
1199 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1200 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1201 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1202 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1203 rt2x00_set_field32(&word, TXD_W0_ACK,
1204 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1205 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1206 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1207 rt2x00_set_field32(&word, TXD_W0_OFDM,
1208 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1209 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1210 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1211 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1212 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1213 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1214 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1215 rt2x00_desc_write(txd, 0, word);
1216 }
1217
1218 /*
1219 * TX data initialization
1220 */
1221 static void rt2500pci_write_beacon(struct queue_entry *entry)
1222 {
1223 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1224 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1225 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1226 u32 word;
1227 u32 reg;
1228
1229 /*
1230 * Disable beaconing while we are reloading the beacon data,
1231 * otherwise we might be sending out invalid data.
1232 */
1233 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1234 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1235 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1236 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1237 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1238
1239 /*
1240 * Replace rt2x00lib allocated descriptor with the
1241 * pointer to the _real_ hardware descriptor.
1242 * After that, map the beacon to DMA and update the
1243 * descriptor.
1244 */
1245 memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1246 skbdesc->desc = entry_priv->desc;
1247
1248 rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1249
1250 rt2x00_desc_read(entry_priv->desc, 1, &word);
1251 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1252 rt2x00_desc_write(entry_priv->desc, 1, word);
1253 }
1254
1255 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1256 const enum data_queue_qid queue)
1257 {
1258 u32 reg;
1259
1260 if (queue == QID_BEACON) {
1261 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1262 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1263 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1264 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1265 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1266 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1267 }
1268 return;
1269 }
1270
1271 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1272 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1273 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1274 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1275 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1276 }
1277
1278 /*
1279 * RX control handlers
1280 */
1281 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1282 struct rxdone_entry_desc *rxdesc)
1283 {
1284 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1285 u32 word0;
1286 u32 word2;
1287
1288 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1289 rt2x00_desc_read(entry_priv->desc, 2, &word2);
1290
1291 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1292 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1293 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1294 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1295
1296 /*
1297 * Obtain the status about this packet.
1298 * When frame was received with an OFDM bitrate,
1299 * the signal is the PLCP value. If it was received with
1300 * a CCK bitrate the signal is the rate in 100kbit/s.
1301 */
1302 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1303 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1304 entry->queue->rt2x00dev->rssi_offset;
1305 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1306
1307 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1308 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1309 else
1310 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1311 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1312 rxdesc->dev_flags |= RXDONE_MY_BSS;
1313 }
1314
1315 /*
1316 * Interrupt functions.
1317 */
1318 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1319 const enum data_queue_qid queue_idx)
1320 {
1321 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1322 struct queue_entry_priv_pci *entry_priv;
1323 struct queue_entry *entry;
1324 struct txdone_entry_desc txdesc;
1325 u32 word;
1326
1327 while (!rt2x00queue_empty(queue)) {
1328 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1329 entry_priv = entry->priv_data;
1330 rt2x00_desc_read(entry_priv->desc, 0, &word);
1331
1332 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1333 !rt2x00_get_field32(word, TXD_W0_VALID))
1334 break;
1335
1336 /*
1337 * Obtain the status about this packet.
1338 */
1339 txdesc.flags = 0;
1340 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1341 case 0: /* Success */
1342 case 1: /* Success with retry */
1343 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1344 break;
1345 case 2: /* Failure, excessive retries */
1346 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1347 /* Don't break, this is a failed frame! */
1348 default: /* Failure */
1349 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1350 }
1351 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1352
1353 rt2x00lib_txdone(entry, &txdesc);
1354 }
1355 }
1356
1357 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1358 {
1359 struct rt2x00_dev *rt2x00dev = dev_instance;
1360 u32 reg;
1361
1362 /*
1363 * Get the interrupt sources & saved to local variable.
1364 * Write register value back to clear pending interrupts.
1365 */
1366 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1367 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1368
1369 if (!reg)
1370 return IRQ_NONE;
1371
1372 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1373 return IRQ_HANDLED;
1374
1375 /*
1376 * Handle interrupts, walk through all bits
1377 * and run the tasks, the bits are checked in order of
1378 * priority.
1379 */
1380
1381 /*
1382 * 1 - Beacon timer expired interrupt.
1383 */
1384 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1385 rt2x00lib_beacondone(rt2x00dev);
1386
1387 /*
1388 * 2 - Rx ring done interrupt.
1389 */
1390 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1391 rt2x00pci_rxdone(rt2x00dev);
1392
1393 /*
1394 * 3 - Atim ring transmit done interrupt.
1395 */
1396 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1397 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1398
1399 /*
1400 * 4 - Priority ring transmit done interrupt.
1401 */
1402 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1403 rt2500pci_txdone(rt2x00dev, QID_AC_BE);
1404
1405 /*
1406 * 5 - Tx ring transmit done interrupt.
1407 */
1408 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1409 rt2500pci_txdone(rt2x00dev, QID_AC_BK);
1410
1411 return IRQ_HANDLED;
1412 }
1413
1414 /*
1415 * Device probe functions.
1416 */
1417 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1418 {
1419 struct eeprom_93cx6 eeprom;
1420 u32 reg;
1421 u16 word;
1422 u8 *mac;
1423
1424 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1425
1426 eeprom.data = rt2x00dev;
1427 eeprom.register_read = rt2500pci_eepromregister_read;
1428 eeprom.register_write = rt2500pci_eepromregister_write;
1429 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1430 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1431 eeprom.reg_data_in = 0;
1432 eeprom.reg_data_out = 0;
1433 eeprom.reg_data_clock = 0;
1434 eeprom.reg_chip_select = 0;
1435
1436 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1437 EEPROM_SIZE / sizeof(u16));
1438
1439 /*
1440 * Start validation of the data that has been read.
1441 */
1442 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1443 if (!is_valid_ether_addr(mac)) {
1444 random_ether_addr(mac);
1445 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1446 }
1447
1448 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1449 if (word == 0xffff) {
1450 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1451 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1452 ANTENNA_SW_DIVERSITY);
1453 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1454 ANTENNA_SW_DIVERSITY);
1455 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1456 LED_MODE_DEFAULT);
1457 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1458 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1459 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1460 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1461 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1462 }
1463
1464 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1465 if (word == 0xffff) {
1466 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1467 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1468 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1469 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1470 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1471 }
1472
1473 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1474 if (word == 0xffff) {
1475 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1476 DEFAULT_RSSI_OFFSET);
1477 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1478 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1479 }
1480
1481 return 0;
1482 }
1483
1484 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1485 {
1486 u32 reg;
1487 u16 value;
1488 u16 eeprom;
1489
1490 /*
1491 * Read EEPROM word for configuration.
1492 */
1493 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1494
1495 /*
1496 * Identify RF chipset.
1497 */
1498 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1499 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1500 rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1501
1502 if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1503 !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1504 !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1505 !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1506 !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1507 !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1508 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1509 return -ENODEV;
1510 }
1511
1512 /*
1513 * Identify default antenna configuration.
1514 */
1515 rt2x00dev->default_ant.tx =
1516 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1517 rt2x00dev->default_ant.rx =
1518 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1519
1520 /*
1521 * Store led mode, for correct led behaviour.
1522 */
1523 #ifdef CONFIG_RT2X00_LIB_LEDS
1524 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1525
1526 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1527 if (value == LED_MODE_TXRX_ACTIVITY)
1528 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1529 LED_TYPE_ACTIVITY);
1530 #endif /* CONFIG_RT2X00_LIB_LEDS */
1531
1532 /*
1533 * Detect if this device has an hardware controlled radio.
1534 */
1535 #ifdef CONFIG_RT2X00_LIB_RFKILL
1536 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1537 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1538 #endif /* CONFIG_RT2X00_LIB_RFKILL */
1539
1540 /*
1541 * Check if the BBP tuning should be enabled.
1542 */
1543 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1544
1545 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1546 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1547
1548 /*
1549 * Read the RSSI <-> dBm offset information.
1550 */
1551 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1552 rt2x00dev->rssi_offset =
1553 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1554
1555 return 0;
1556 }
1557
1558 /*
1559 * RF value list for RF2522
1560 * Supports: 2.4 GHz
1561 */
1562 static const struct rf_channel rf_vals_bg_2522[] = {
1563 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1564 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1565 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1566 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1567 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1568 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1569 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1570 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1571 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1572 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1573 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1574 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1575 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1576 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1577 };
1578
1579 /*
1580 * RF value list for RF2523
1581 * Supports: 2.4 GHz
1582 */
1583 static const struct rf_channel rf_vals_bg_2523[] = {
1584 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1585 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1586 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1587 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1588 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1589 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1590 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1591 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1592 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1593 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1594 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1595 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1596 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1597 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1598 };
1599
1600 /*
1601 * RF value list for RF2524
1602 * Supports: 2.4 GHz
1603 */
1604 static const struct rf_channel rf_vals_bg_2524[] = {
1605 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1606 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1607 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1608 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1609 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1610 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1611 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1612 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1613 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1614 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1615 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1616 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1617 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1618 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1619 };
1620
1621 /*
1622 * RF value list for RF2525
1623 * Supports: 2.4 GHz
1624 */
1625 static const struct rf_channel rf_vals_bg_2525[] = {
1626 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1627 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1628 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1629 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1630 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1631 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1632 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1633 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1634 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1635 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1636 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1637 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1638 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1639 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1640 };
1641
1642 /*
1643 * RF value list for RF2525e
1644 * Supports: 2.4 GHz
1645 */
1646 static const struct rf_channel rf_vals_bg_2525e[] = {
1647 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1648 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1649 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1650 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1651 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1652 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1653 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1654 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1655 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1656 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1657 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1658 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1659 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1660 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1661 };
1662
1663 /*
1664 * RF value list for RF5222
1665 * Supports: 2.4 GHz & 5.2 GHz
1666 */
1667 static const struct rf_channel rf_vals_5222[] = {
1668 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1669 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1670 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1671 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1672 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1673 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1674 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1675 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1676 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1677 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1678 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1679 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1680 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1681 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1682
1683 /* 802.11 UNI / HyperLan 2 */
1684 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1685 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1686 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1687 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1688 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1689 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1690 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1691 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1692
1693 /* 802.11 HyperLan 2 */
1694 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1695 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1696 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1697 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1698 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1699 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1700 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1701 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1702 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1703 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1704
1705 /* 802.11 UNII */
1706 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1707 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1708 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1709 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1710 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1711 };
1712
1713 static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1714 {
1715 struct hw_mode_spec *spec = &rt2x00dev->spec;
1716 struct channel_info *info;
1717 char *tx_power;
1718 unsigned int i;
1719
1720 /*
1721 * Initialize all hw fields.
1722 */
1723 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1724 IEEE80211_HW_SIGNAL_DBM;
1725
1726 rt2x00dev->hw->extra_tx_headroom = 0;
1727
1728 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1729 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1730 rt2x00_eeprom_addr(rt2x00dev,
1731 EEPROM_MAC_ADDR_0));
1732
1733 /*
1734 * Initialize hw_mode information.
1735 */
1736 spec->supported_bands = SUPPORT_BAND_2GHZ;
1737 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1738
1739 if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1740 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1741 spec->channels = rf_vals_bg_2522;
1742 } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1743 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1744 spec->channels = rf_vals_bg_2523;
1745 } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1746 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1747 spec->channels = rf_vals_bg_2524;
1748 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1749 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1750 spec->channels = rf_vals_bg_2525;
1751 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1752 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1753 spec->channels = rf_vals_bg_2525e;
1754 } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1755 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1756 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1757 spec->channels = rf_vals_5222;
1758 }
1759
1760 /*
1761 * Create channel information array
1762 */
1763 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1764 if (!info)
1765 return -ENOMEM;
1766
1767 spec->channels_info = info;
1768
1769 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1770 for (i = 0; i < 14; i++)
1771 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1772
1773 if (spec->num_channels > 14) {
1774 for (i = 14; i < spec->num_channels; i++)
1775 info[i].tx_power1 = DEFAULT_TXPOWER;
1776 }
1777
1778 return 0;
1779 }
1780
1781 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1782 {
1783 int retval;
1784
1785 /*
1786 * Allocate eeprom data.
1787 */
1788 retval = rt2500pci_validate_eeprom(rt2x00dev);
1789 if (retval)
1790 return retval;
1791
1792 retval = rt2500pci_init_eeprom(rt2x00dev);
1793 if (retval)
1794 return retval;
1795
1796 /*
1797 * Initialize hw specifications.
1798 */
1799 retval = rt2500pci_probe_hw_mode(rt2x00dev);
1800 if (retval)
1801 return retval;
1802
1803 /*
1804 * This device requires the atim queue and DMA-mapped skbs.
1805 */
1806 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1807 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1808
1809 /*
1810 * Set the rssi offset.
1811 */
1812 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1813
1814 return 0;
1815 }
1816
1817 /*
1818 * IEEE80211 stack callback functions.
1819 */
1820 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1821 {
1822 struct rt2x00_dev *rt2x00dev = hw->priv;
1823 u64 tsf;
1824 u32 reg;
1825
1826 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1827 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1828 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1829 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1830
1831 return tsf;
1832 }
1833
1834 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1835 {
1836 struct rt2x00_dev *rt2x00dev = hw->priv;
1837 u32 reg;
1838
1839 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1840 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1841 }
1842
1843 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1844 .tx = rt2x00mac_tx,
1845 .start = rt2x00mac_start,
1846 .stop = rt2x00mac_stop,
1847 .add_interface = rt2x00mac_add_interface,
1848 .remove_interface = rt2x00mac_remove_interface,
1849 .config = rt2x00mac_config,
1850 .config_interface = rt2x00mac_config_interface,
1851 .configure_filter = rt2x00mac_configure_filter,
1852 .get_stats = rt2x00mac_get_stats,
1853 .bss_info_changed = rt2x00mac_bss_info_changed,
1854 .conf_tx = rt2x00mac_conf_tx,
1855 .get_tx_stats = rt2x00mac_get_tx_stats,
1856 .get_tsf = rt2500pci_get_tsf,
1857 .tx_last_beacon = rt2500pci_tx_last_beacon,
1858 };
1859
1860 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1861 .irq_handler = rt2500pci_interrupt,
1862 .probe_hw = rt2500pci_probe_hw,
1863 .initialize = rt2x00pci_initialize,
1864 .uninitialize = rt2x00pci_uninitialize,
1865 .get_entry_state = rt2500pci_get_entry_state,
1866 .clear_entry = rt2500pci_clear_entry,
1867 .set_device_state = rt2500pci_set_device_state,
1868 .rfkill_poll = rt2500pci_rfkill_poll,
1869 .link_stats = rt2500pci_link_stats,
1870 .reset_tuner = rt2500pci_reset_tuner,
1871 .link_tuner = rt2500pci_link_tuner,
1872 .write_tx_desc = rt2500pci_write_tx_desc,
1873 .write_tx_data = rt2x00pci_write_tx_data,
1874 .write_beacon = rt2500pci_write_beacon,
1875 .kick_tx_queue = rt2500pci_kick_tx_queue,
1876 .fill_rxdone = rt2500pci_fill_rxdone,
1877 .config_filter = rt2500pci_config_filter,
1878 .config_intf = rt2500pci_config_intf,
1879 .config_erp = rt2500pci_config_erp,
1880 .config_ant = rt2500pci_config_ant,
1881 .config = rt2500pci_config,
1882 };
1883
1884 static const struct data_queue_desc rt2500pci_queue_rx = {
1885 .entry_num = RX_ENTRIES,
1886 .data_size = DATA_FRAME_SIZE,
1887 .desc_size = RXD_DESC_SIZE,
1888 .priv_size = sizeof(struct queue_entry_priv_pci),
1889 };
1890
1891 static const struct data_queue_desc rt2500pci_queue_tx = {
1892 .entry_num = TX_ENTRIES,
1893 .data_size = DATA_FRAME_SIZE,
1894 .desc_size = TXD_DESC_SIZE,
1895 .priv_size = sizeof(struct queue_entry_priv_pci),
1896 };
1897
1898 static const struct data_queue_desc rt2500pci_queue_bcn = {
1899 .entry_num = BEACON_ENTRIES,
1900 .data_size = MGMT_FRAME_SIZE,
1901 .desc_size = TXD_DESC_SIZE,
1902 .priv_size = sizeof(struct queue_entry_priv_pci),
1903 };
1904
1905 static const struct data_queue_desc rt2500pci_queue_atim = {
1906 .entry_num = ATIM_ENTRIES,
1907 .data_size = DATA_FRAME_SIZE,
1908 .desc_size = TXD_DESC_SIZE,
1909 .priv_size = sizeof(struct queue_entry_priv_pci),
1910 };
1911
1912 static const struct rt2x00_ops rt2500pci_ops = {
1913 .name = KBUILD_MODNAME,
1914 .max_sta_intf = 1,
1915 .max_ap_intf = 1,
1916 .eeprom_size = EEPROM_SIZE,
1917 .rf_size = RF_SIZE,
1918 .tx_queues = NUM_TX_QUEUES,
1919 .rx = &rt2500pci_queue_rx,
1920 .tx = &rt2500pci_queue_tx,
1921 .bcn = &rt2500pci_queue_bcn,
1922 .atim = &rt2500pci_queue_atim,
1923 .lib = &rt2500pci_rt2x00_ops,
1924 .hw = &rt2500pci_mac80211_ops,
1925 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1926 .debugfs = &rt2500pci_rt2x00debug,
1927 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1928 };
1929
1930 /*
1931 * RT2500pci module information.
1932 */
1933 static struct pci_device_id rt2500pci_device_table[] = {
1934 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1935 { 0, }
1936 };
1937
1938 MODULE_AUTHOR(DRV_PROJECT);
1939 MODULE_VERSION(DRV_VERSION);
1940 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1941 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1942 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1943 MODULE_LICENSE("GPL");
1944
1945 static struct pci_driver rt2500pci_driver = {
1946 .name = KBUILD_MODNAME,
1947 .id_table = rt2500pci_device_table,
1948 .probe = rt2x00pci_probe,
1949 .remove = __devexit_p(rt2x00pci_remove),
1950 .suspend = rt2x00pci_suspend,
1951 .resume = rt2x00pci_resume,
1952 };
1953
1954 static int __init rt2500pci_init(void)
1955 {
1956 return pci_register_driver(&rt2500pci_driver);
1957 }
1958
1959 static void __exit rt2500pci_exit(void)
1960 {
1961 pci_unregister_driver(&rt2500pci_driver);
1962 }
1963
1964 module_init(rt2500pci_init);
1965 module_exit(rt2500pci_exit);
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