| blob | 9aefda4ab3c263c4163543fff32a7853b8139ec8 |
1 /*
2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
21 /*
22 Module: rt2400pci
23 Abstract: Data structures and registers for the rt2400pci module.
24 Supported chipsets: RT2460.
25 */
27 #ifndef RT2400PCI_H
28 #define RT2400PCI_H
30 /*
31 * RF chip defines.
32 */
33 #define RF2420 0x0000
34 #define RF2421 0x0001
36 /*
37 * Signal information.
38 * Defaul offset is required for RSSI <-> dBm conversion.
39 */
40 #define DEFAULT_RSSI_OFFSET 100
42 /*
43 * Register layout information.
44 */
45 #define CSR_REG_BASE 0x0000
46 #define CSR_REG_SIZE 0x014c
47 #define EEPROM_BASE 0x0000
48 #define EEPROM_SIZE 0x0100
49 #define BBP_BASE 0x0000
50 #define BBP_SIZE 0x0020
51 #define RF_BASE 0x0000
52 #define RF_SIZE 0x0010
54 /*
55 * Number of TX queues.
56 */
57 #define NUM_TX_QUEUES 2
59 /*
60 * Control/Status Registers(CSR).
61 * Some values are set in TU, whereas 1 TU == 1024 us.
62 */
64 /*
65 * CSR0: ASIC revision number.
66 */
67 #define CSR0 0x0000
69 /*
70 * CSR1: System control register.
71 * SOFT_RESET: Software reset, 1: reset, 0: normal.
72 * BBP_RESET: Hardware reset, 1: reset, 0, release.
73 * HOST_READY: Host ready after initialization.
74 */
75 #define CSR1 0x0004
76 #define CSR1_SOFT_RESET FIELD32(0x00000001)
77 #define CSR1_BBP_RESET FIELD32(0x00000002)
78 #define CSR1_HOST_READY FIELD32(0x00000004)
80 /*
81 * CSR2: System admin status register (invalid).
82 */
83 #define CSR2 0x0008
85 /*
86 * CSR3: STA MAC address register 0.
87 */
88 #define CSR3 0x000c
89 #define CSR3_BYTE0 FIELD32(0x000000ff)
90 #define CSR3_BYTE1 FIELD32(0x0000ff00)
91 #define CSR3_BYTE2 FIELD32(0x00ff0000)
92 #define CSR3_BYTE3 FIELD32(0xff000000)
94 /*
95 * CSR4: STA MAC address register 1.
96 */
97 #define CSR4 0x0010
98 #define CSR4_BYTE4 FIELD32(0x000000ff)
99 #define CSR4_BYTE5 FIELD32(0x0000ff00)
101 /*
102 * CSR5: BSSID register 0.
103 */
104 #define CSR5 0x0014
105 #define CSR5_BYTE0 FIELD32(0x000000ff)
106 #define CSR5_BYTE1 FIELD32(0x0000ff00)
107 #define CSR5_BYTE2 FIELD32(0x00ff0000)
108 #define CSR5_BYTE3 FIELD32(0xff000000)
110 /*
111 * CSR6: BSSID register 1.
112 */
113 #define CSR6 0x0018
114 #define CSR6_BYTE4 FIELD32(0x000000ff)
115 #define CSR6_BYTE5 FIELD32(0x0000ff00)
117 /*
118 * CSR7: Interrupt source register.
119 * Write 1 to clear interrupt.
120 * TBCN_EXPIRE: Beacon timer expired interrupt.
121 * TWAKE_EXPIRE: Wakeup timer expired interrupt.
122 * TATIMW_EXPIRE: Timer of atim window expired interrupt.
123 * TXDONE_TXRING: Tx ring transmit done interrupt.
124 * TXDONE_ATIMRING: Atim ring transmit done interrupt.
125 * TXDONE_PRIORING: Priority ring transmit done interrupt.
126 * RXDONE: Receive done interrupt.
127 */
128 #define CSR7 0x001c
129 #define CSR7_TBCN_EXPIRE FIELD32(0x00000001)
130 #define CSR7_TWAKE_EXPIRE FIELD32(0x00000002)
131 #define CSR7_TATIMW_EXPIRE FIELD32(0x00000004)
132 #define CSR7_TXDONE_TXRING FIELD32(0x00000008)
133 #define CSR7_TXDONE_ATIMRING FIELD32(0x00000010)
134 #define CSR7_TXDONE_PRIORING FIELD32(0x00000020)
135 #define CSR7_RXDONE FIELD32(0x00000040)
137 /*
138 * CSR8: Interrupt mask register.
139 * Write 1 to mask interrupt.
140 * TBCN_EXPIRE: Beacon timer expired interrupt.
141 * TWAKE_EXPIRE: Wakeup timer expired interrupt.
142 * TATIMW_EXPIRE: Timer of atim window expired interrupt.
143 * TXDONE_TXRING: Tx ring transmit done interrupt.
144 * TXDONE_ATIMRING: Atim ring transmit done interrupt.
145 * TXDONE_PRIORING: Priority ring transmit done interrupt.
146 * RXDONE: Receive done interrupt.
147 */
148 #define CSR8 0x0020
149 #define CSR8_TBCN_EXPIRE FIELD32(0x00000001)
150 #define CSR8_TWAKE_EXPIRE FIELD32(0x00000002)
151 #define CSR8_TATIMW_EXPIRE FIELD32(0x00000004)
152 #define CSR8_TXDONE_TXRING FIELD32(0x00000008)
153 #define CSR8_TXDONE_ATIMRING FIELD32(0x00000010)
154 #define CSR8_TXDONE_PRIORING FIELD32(0x00000020)
155 #define CSR8_RXDONE FIELD32(0x00000040)
157 /*
158 * CSR9: Maximum frame length register.
159 * MAX_FRAME_UNIT: Maximum frame length in 128b unit, default: 12.
160 */
161 #define CSR9 0x0024
162 #define CSR9_MAX_FRAME_UNIT FIELD32(0x00000f80)
164 /*
165 * CSR11: Back-off control register.
166 * CWMIN: CWmin. Default cwmin is 31 (2^5 - 1).
167 * CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1).
168 * SLOT_TIME: Slot time, default is 20us for 802.11b.
169 * LONG_RETRY: Long retry count.
170 * SHORT_RETRY: Short retry count.
171 */
172 #define CSR11 0x002c
173 #define CSR11_CWMIN FIELD32(0x0000000f)
174 #define CSR11_CWMAX FIELD32(0x000000f0)
175 #define CSR11_SLOT_TIME FIELD32(0x00001f00)
176 #define CSR11_LONG_RETRY FIELD32(0x00ff0000)
177 #define CSR11_SHORT_RETRY FIELD32(0xff000000)
179 /*
180 * CSR12: Synchronization configuration register 0.
181 * All units in 1/16 TU.
182 * BEACON_INTERVAL: Beacon interval, default is 100 TU.
183 * CFPMAX_DURATION: Cfp maximum duration, default is 100 TU.
184 */
185 #define CSR12 0x0030
186 #define CSR12_BEACON_INTERVAL FIELD32(0x0000ffff)
187 #define CSR12_CFP_MAX_DURATION FIELD32(0xffff0000)
189 /*
190 * CSR13: Synchronization configuration register 1.
191 * All units in 1/16 TU.
192 * ATIMW_DURATION: Atim window duration.
193 * CFP_PERIOD: Cfp period, default is 0 TU.
194 */
195 #define CSR13 0x0034
196 #define CSR13_ATIMW_DURATION FIELD32(0x0000ffff)
197 #define CSR13_CFP_PERIOD FIELD32(0x00ff0000)
199 /*
200 * CSR14: Synchronization control register.
201 * TSF_COUNT: Enable tsf auto counting.
202 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
203 * TBCN: Enable tbcn with reload value.
204 * TCFP: Enable tcfp & cfp / cp switching.
205 * TATIMW: Enable tatimw & atim window switching.
206 * BEACON_GEN: Enable beacon generator.
207 * CFP_COUNT_PRELOAD: Cfp count preload value.
208 * TBCM_PRELOAD: Tbcn preload value in units of 64us.
209 */
210 #define CSR14 0x0038
211 #define CSR14_TSF_COUNT FIELD32(0x00000001)
212 #define CSR14_TSF_SYNC FIELD32(0x00000006)
213 #define CSR14_TBCN FIELD32(0x00000008)
214 #define CSR14_TCFP FIELD32(0x00000010)
215 #define CSR14_TATIMW FIELD32(0x00000020)
216 #define CSR14_BEACON_GEN FIELD32(0x00000040)
217 #define CSR14_CFP_COUNT_PRELOAD FIELD32(0x0000ff00)
218 #define CSR14_TBCM_PRELOAD FIELD32(0xffff0000)
220 /*
221 * CSR15: Synchronization status register.
222 * CFP: ASIC is in contention-free period.
223 * ATIMW: ASIC is in ATIM window.
224 * BEACON_SENT: Beacon is send.
225 */
226 #define CSR15 0x003c
227 #define CSR15_CFP FIELD32(0x00000001)
228 #define CSR15_ATIMW FIELD32(0x00000002)
229 #define CSR15_BEACON_SENT FIELD32(0x00000004)
231 /*
232 * CSR16: TSF timer register 0.
233 */
234 #define CSR16 0x0040
235 #define CSR16_LOW_TSFTIMER FIELD32(0xffffffff)
237 /*
238 * CSR17: TSF timer register 1.
239 */
240 #define CSR17 0x0044
241 #define CSR17_HIGH_TSFTIMER FIELD32(0xffffffff)
243 /*
244 * CSR18: IFS timer register 0.
245 * SIFS: Sifs, default is 10 us.
246 * PIFS: Pifs, default is 30 us.
247 */
248 #define CSR18 0x0048
249 #define CSR18_SIFS FIELD32(0x0000ffff)
250 #define CSR18_PIFS FIELD32(0xffff0000)
252 /*
253 * CSR19: IFS timer register 1.
254 * DIFS: Difs, default is 50 us.
255 * EIFS: Eifs, default is 364 us.
256 */
257 #define CSR19 0x004c
258 #define CSR19_DIFS FIELD32(0x0000ffff)
259 #define CSR19_EIFS FIELD32(0xffff0000)
261 /*
262 * CSR20: Wakeup timer register.
263 * DELAY_AFTER_TBCN: Delay after tbcn expired in units of 1/16 TU.
264 * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
265 * AUTOWAKE: Enable auto wakeup / sleep mechanism.
266 */
267 #define CSR20 0x0050
268 #define CSR20_DELAY_AFTER_TBCN FIELD32(0x0000ffff)
269 #define CSR20_TBCN_BEFORE_WAKEUP FIELD32(0x00ff0000)
270 #define CSR20_AUTOWAKE FIELD32(0x01000000)
272 /*
273 * CSR21: EEPROM control register.
274 * RELOAD: Write 1 to reload eeprom content.
275 * TYPE_93C46: 1: 93c46, 0:93c66.
276 */
277 #define CSR21 0x0054
278 #define CSR21_RELOAD FIELD32(0x00000001)
279 #define CSR21_EEPROM_DATA_CLOCK FIELD32(0x00000002)
280 #define CSR21_EEPROM_CHIP_SELECT FIELD32(0x00000004)
281 #define CSR21_EEPROM_DATA_IN FIELD32(0x00000008)
282 #define CSR21_EEPROM_DATA_OUT FIELD32(0x00000010)
283 #define CSR21_TYPE_93C46 FIELD32(0x00000020)
285 /*
286 * CSR22: CFP control register.
287 * CFP_DURATION_REMAIN: Cfp duration remain, in units of TU.
288 * RELOAD_CFP_DURATION: Write 1 to reload cfp duration remain.
289 */
290 #define CSR22 0x0058
291 #define CSR22_CFP_DURATION_REMAIN FIELD32(0x0000ffff)
292 #define CSR22_RELOAD_CFP_DURATION FIELD32(0x00010000)
294 /*
295 * Transmit related CSRs.
296 * Some values are set in TU, whereas 1 TU == 1024 us.
297 */
299 /*
300 * TXCSR0: TX Control Register.
301 * KICK_TX: Kick tx ring.
302 * KICK_ATIM: Kick atim ring.
303 * KICK_PRIO: Kick priority ring.
304 * ABORT: Abort all transmit related ring operation.
305 */
306 #define TXCSR0 0x0060
307 #define TXCSR0_KICK_TX FIELD32(0x00000001)
308 #define TXCSR0_KICK_ATIM FIELD32(0x00000002)
309 #define TXCSR0_KICK_PRIO FIELD32(0x00000004)
310 #define TXCSR0_ABORT FIELD32(0x00000008)
312 /*
313 * TXCSR1: TX Configuration Register.
314 * ACK_TIMEOUT: Ack timeout, default = sifs + 2*slottime + acktime @ 1mbps.
315 * ACK_CONSUME_TIME: Ack consume time, default = sifs + acktime @ 1mbps.
316 * TSF_OFFSET: Insert tsf offset.
317 * AUTORESPONDER: Enable auto responder which include ack & cts.
318 */
319 #define TXCSR1 0x0064
320 #define TXCSR1_ACK_TIMEOUT FIELD32(0x000001ff)
321 #define TXCSR1_ACK_CONSUME_TIME FIELD32(0x0003fe00)
322 #define TXCSR1_TSF_OFFSET FIELD32(0x00fc0000)
323 #define TXCSR1_AUTORESPONDER FIELD32(0x01000000)
325 /*
326 * TXCSR2: Tx descriptor configuration register.
327 * TXD_SIZE: Tx descriptor size, default is 48.
328 * NUM_TXD: Number of tx entries in ring.
329 * NUM_ATIM: Number of atim entries in ring.
330 * NUM_PRIO: Number of priority entries in ring.
331 */
332 #define TXCSR2 0x0068
333 #define TXCSR2_TXD_SIZE FIELD32(0x000000ff)
334 #define TXCSR2_NUM_TXD FIELD32(0x0000ff00)
335 #define TXCSR2_NUM_ATIM FIELD32(0x00ff0000)
336 #define TXCSR2_NUM_PRIO FIELD32(0xff000000)
338 /*
339 * TXCSR3: TX Ring Base address register.
340 */
341 #define TXCSR3 0x006c
342 #define TXCSR3_TX_RING_REGISTER FIELD32(0xffffffff)
344 /*
345 * TXCSR4: TX Atim Ring Base address register.
346 */
347 #define TXCSR4 0x0070
348 #define TXCSR4_ATIM_RING_REGISTER FIELD32(0xffffffff)
350 /*
351 * TXCSR5: TX Prio Ring Base address register.
352 */
353 #define TXCSR5 0x0074
354 #define TXCSR5_PRIO_RING_REGISTER FIELD32(0xffffffff)
356 /*
357 * TXCSR6: Beacon Base address register.
358 */
359 #define TXCSR6 0x0078
360 #define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff)
362 /*
363 * TXCSR7: Auto responder control register.
364 * AR_POWERMANAGEMENT: Auto responder power management bit.
365 */
366 #define TXCSR7 0x007c
367 #define TXCSR7_AR_POWERMANAGEMENT FIELD32(0x00000001)
369 /*
370 * Receive related CSRs.
371 * Some values are set in TU, whereas 1 TU == 1024 us.
372 */
374 /*
375 * RXCSR0: RX Control Register.
376 * DISABLE_RX: Disable rx engine.
377 * DROP_CRC: Drop crc error.
378 * DROP_PHYSICAL: Drop physical error.
379 * DROP_CONTROL: Drop control frame.
380 * DROP_NOT_TO_ME: Drop not to me unicast frame.
381 * DROP_TODS: Drop frame tods bit is true.
382 * DROP_VERSION_ERROR: Drop version error frame.
383 * PASS_CRC: Pass all packets with crc attached.
384 */
385 #define RXCSR0 0x0080
386 #define RXCSR0_DISABLE_RX FIELD32(0x00000001)
387 #define RXCSR0_DROP_CRC FIELD32(0x00000002)
388 #define RXCSR0_DROP_PHYSICAL FIELD32(0x00000004)
389 #define RXCSR0_DROP_CONTROL FIELD32(0x00000008)
390 #define RXCSR0_DROP_NOT_TO_ME FIELD32(0x00000010)
391 #define RXCSR0_DROP_TODS FIELD32(0x00000020)
392 #define RXCSR0_DROP_VERSION_ERROR FIELD32(0x00000040)
393 #define RXCSR0_PASS_CRC FIELD32(0x00000080)
395 /*
396 * RXCSR1: RX descriptor configuration register.
397 * RXD_SIZE: Rx descriptor size, default is 32b.
398 * NUM_RXD: Number of rx entries in ring.
399 */
400 #define RXCSR1 0x0084
401 #define RXCSR1_RXD_SIZE FIELD32(0x000000ff)
402 #define RXCSR1_NUM_RXD FIELD32(0x0000ff00)
404 /*
405 * RXCSR2: RX Ring base address register.
406 */
407 #define RXCSR2 0x0088
408 #define RXCSR2_RX_RING_REGISTER FIELD32(0xffffffff)
410 /*
411 * RXCSR3: BBP ID register for Rx operation.
412 * BBP_ID#: BBP register # id.
413 * BBP_ID#_VALID: BBP register # id is valid or not.
414 */
415 #define RXCSR3 0x0090
416 #define RXCSR3_BBP_ID0 FIELD32(0x0000007f)
417 #define RXCSR3_BBP_ID0_VALID FIELD32(0x00000080)
418 #define RXCSR3_BBP_ID1 FIELD32(0x00007f00)
419 #define RXCSR3_BBP_ID1_VALID FIELD32(0x00008000)
420 #define RXCSR3_BBP_ID2 FIELD32(0x007f0000)
421 #define RXCSR3_BBP_ID2_VALID FIELD32(0x00800000)
422 #define RXCSR3_BBP_ID3 FIELD32(0x7f000000)
423 #define RXCSR3_BBP_ID3_VALID FIELD32(0x80000000)
425 /*
426 * RXCSR4: BBP ID register for Rx operation.
427 * BBP_ID#: BBP register # id.
428 * BBP_ID#_VALID: BBP register # id is valid or not.
429 */
430 #define RXCSR4 0x0094
431 #define RXCSR4_BBP_ID4 FIELD32(0x0000007f)
432 #define RXCSR4_BBP_ID4_VALID FIELD32(0x00000080)
433 #define RXCSR4_BBP_ID5 FIELD32(0x00007f00)
434 #define RXCSR4_BBP_ID5_VALID FIELD32(0x00008000)
436 /*
437 * ARCSR0: Auto Responder PLCP config register 0.
438 * ARCSR0_AR_BBP_DATA#: Auto responder BBP register # data.
439 * ARCSR0_AR_BBP_ID#: Auto responder BBP register # Id.
440 */
441 #define ARCSR0 0x0098
442 #define ARCSR0_AR_BBP_DATA0 FIELD32(0x000000ff)
443 #define ARCSR0_AR_BBP_ID0 FIELD32(0x0000ff00)
444 #define ARCSR0_AR_BBP_DATA1 FIELD32(0x00ff0000)
445 #define ARCSR0_AR_BBP_ID1 FIELD32(0xff000000)
447 /*
448 * ARCSR1: Auto Responder PLCP config register 1.
449 * ARCSR0_AR_BBP_DATA#: Auto responder BBP register # data.
450 * ARCSR0_AR_BBP_ID#: Auto responder BBP register # Id.
451 */
452 #define ARCSR1 0x009c
453 #define ARCSR1_AR_BBP_DATA2 FIELD32(0x000000ff)
454 #define ARCSR1_AR_BBP_ID2 FIELD32(0x0000ff00)
455 #define ARCSR1_AR_BBP_DATA3 FIELD32(0x00ff0000)
456 #define ARCSR1_AR_BBP_ID3 FIELD32(0xff000000)
458 /*
459 * Miscellaneous Registers.
460 * Some values are set in TU, whereas 1 TU == 1024 us.
461 */
463 /*
464 * PCICSR: PCI control register.
465 * BIG_ENDIAN: 1: big endian, 0: little endian.
466 * RX_TRESHOLD: Rx threshold in dw to start pci access
467 * 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw.
468 * TX_TRESHOLD: Tx threshold in dw to start pci access
469 * 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward.
470 * BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw.
471 * ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational.
472 */
473 #define PCICSR 0x008c
474 #define PCICSR_BIG_ENDIAN FIELD32(0x00000001)
475 #define PCICSR_RX_TRESHOLD FIELD32(0x00000006)
476 #define PCICSR_TX_TRESHOLD FIELD32(0x00000018)
477 #define PCICSR_BURST_LENTH FIELD32(0x00000060)
478 #define PCICSR_ENABLE_CLK FIELD32(0x00000080)
480 /*
481 * CNT0: FCS error count.
482 * FCS_ERROR: FCS error count, cleared when read.
483 */
484 #define CNT0 0x00a0
485 #define CNT0_FCS_ERROR FIELD32(0x0000ffff)
487 /*
488 * Statistic Register.
489 * CNT1: PLCP error count.
490 * CNT2: Long error count.
491 * CNT3: CCA false alarm count.
492 * CNT4: Rx FIFO overflow count.
493 * CNT5: Tx FIFO underrun count.
494 */
495 #define TIMECSR2 0x00a8
496 #define CNT1 0x00ac
497 #define CNT2 0x00b0
498 #define TIMECSR3 0x00b4
499 #define CNT3 0x00b8
500 #define CNT4 0x00bc
501 #define CNT5 0x00c0
503 /*
504 * Baseband Control Register.
505 */
507 /*
508 * PWRCSR0: Power mode configuration register.
509 */
510 #define PWRCSR0 0x00c4
512 /*
513 * Power state transition time registers.
514 */
515 #define PSCSR0 0x00c8
516 #define PSCSR1 0x00cc
517 #define PSCSR2 0x00d0
518 #define PSCSR3 0x00d4
520 /*
521 * PWRCSR1: Manual power control / status register.
522 * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
523 * SET_STATE: Set state. Write 1 to trigger, self cleared.
524 * BBP_DESIRE_STATE: BBP desired state.
525 * RF_DESIRE_STATE: RF desired state.
526 * BBP_CURR_STATE: BBP current state.
527 * RF_CURR_STATE: RF current state.
528 * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
529 */
530 #define PWRCSR1 0x00d8
531 #define PWRCSR1_SET_STATE FIELD32(0x00000001)
532 #define PWRCSR1_BBP_DESIRE_STATE FIELD32(0x00000006)
533 #define PWRCSR1_RF_DESIRE_STATE FIELD32(0x00000018)
534 #define PWRCSR1_BBP_CURR_STATE FIELD32(0x00000060)
535 #define PWRCSR1_RF_CURR_STATE FIELD32(0x00000180)
536 #define PWRCSR1_PUT_TO_SLEEP FIELD32(0x00000200)
538 /*
539 * TIMECSR: Timer control register.
540 * US_COUNT: 1 us timer count in units of clock cycles.
541 * US_64_COUNT: 64 us timer count in units of 1 us timer.
542 * BEACON_EXPECT: Beacon expect window.
543 */
544 #define TIMECSR 0x00dc
545 #define TIMECSR_US_COUNT FIELD32(0x000000ff)
546 #define TIMECSR_US_64_COUNT FIELD32(0x0000ff00)
547 #define TIMECSR_BEACON_EXPECT FIELD32(0x00070000)
549 /*
550 * MACCSR0: MAC configuration register 0.
551 */
552 #define MACCSR0 0x00e0
554 /*
555 * MACCSR1: MAC configuration register 1.
556 * KICK_RX: Kick one-shot rx in one-shot rx mode.
557 * ONESHOT_RXMODE: Enable one-shot rx mode for debugging.
558 * BBPRX_RESET_MODE: Ralink bbp rx reset mode.
559 * AUTO_TXBBP: Auto tx logic access bbp control register.
560 * AUTO_RXBBP: Auto rx logic access bbp control register.
561 * LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd.
562 * INTERSIL_IF: Intersil if calibration pin.
563 */
564 #define MACCSR1 0x00e4
565 #define MACCSR1_KICK_RX FIELD32(0x00000001)
566 #define MACCSR1_ONESHOT_RXMODE FIELD32(0x00000002)
567 #define MACCSR1_BBPRX_RESET_MODE FIELD32(0x00000004)
568 #define MACCSR1_AUTO_TXBBP FIELD32(0x00000008)
569 #define MACCSR1_AUTO_RXBBP FIELD32(0x00000010)
570 #define MACCSR1_LOOPBACK FIELD32(0x00000060)
571 #define MACCSR1_INTERSIL_IF FIELD32(0x00000080)
573 /*
574 * RALINKCSR: Ralink Rx auto-reset BBCR.
575 * AR_BBP_DATA#: Auto reset BBP register # data.
576 * AR_BBP_ID#: Auto reset BBP register # id.
577 */
578 #define RALINKCSR 0x00e8
579 #define RALINKCSR_AR_BBP_DATA0 FIELD32(0x000000ff)
580 #define RALINKCSR_AR_BBP_ID0 FIELD32(0x0000ff00)
581 #define RALINKCSR_AR_BBP_DATA1 FIELD32(0x00ff0000)
582 #define RALINKCSR_AR_BBP_ID1 FIELD32(0xff000000)
584 /*
585 * BCNCSR: Beacon interval control register.
586 * CHANGE: Write one to change beacon interval.
587 * DELTATIME: The delta time value.
588 * NUM_BEACON: Number of beacon according to mode.
589 * MODE: Please refer to asic specs.
590 * PLUS: Plus or minus delta time value.
591 */
592 #define BCNCSR 0x00ec
593 #define BCNCSR_CHANGE FIELD32(0x00000001)
594 #define BCNCSR_DELTATIME FIELD32(0x0000001e)
595 #define BCNCSR_NUM_BEACON FIELD32(0x00001fe0)
596 #define BCNCSR_MODE FIELD32(0x00006000)
597 #define BCNCSR_PLUS FIELD32(0x00008000)
599 /*
600 * BBP / RF / IF Control Register.
601 */
603 /*
604 * BBPCSR: BBP serial control register.
605 * VALUE: Register value to program into BBP.
606 * REGNUM: Selected BBP register.
607 * BUSY: 1: asic is busy execute BBP programming.
608 * WRITE_CONTROL: 1: write BBP, 0: read BBP.
609 */
610 #define BBPCSR 0x00f0
611 #define BBPCSR_VALUE FIELD32(0x000000ff)
612 #define BBPCSR_REGNUM FIELD32(0x00007f00)
613 #define BBPCSR_BUSY FIELD32(0x00008000)
614 #define BBPCSR_WRITE_CONTROL FIELD32(0x00010000)
616 /*
617 * RFCSR: RF serial control register.
618 * VALUE: Register value + id to program into rf/if.
619 * NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
620 * IF_SELECT: Chip to program: 0: rf, 1: if.
621 * PLL_LD: Rf pll_ld status.
622 * BUSY: 1: asic is busy execute rf programming.
623 */
624 #define RFCSR 0x00f4
625 #define RFCSR_VALUE FIELD32(0x00ffffff)
626 #define RFCSR_NUMBER_OF_BITS FIELD32(0x1f000000)
627 #define RFCSR_IF_SELECT FIELD32(0x20000000)
628 #define RFCSR_PLL_LD FIELD32(0x40000000)
629 #define RFCSR_BUSY FIELD32(0x80000000)
631 /*
632 * LEDCSR: LED control register.
633 * ON_PERIOD: On period, default 70ms.
634 * OFF_PERIOD: Off period, default 30ms.
635 * LINK: 0: linkoff, 1: linkup.
636 * ACTIVITY: 0: idle, 1: active.
637 */
638 #define LEDCSR 0x00f8
639 #define LEDCSR_ON_PERIOD FIELD32(0x000000ff)
640 #define LEDCSR_OFF_PERIOD FIELD32(0x0000ff00)
641 #define LEDCSR_LINK FIELD32(0x00010000)
642 #define LEDCSR_ACTIVITY FIELD32(0x00020000)
644 /*
645 * ASIC pointer information.
646 * RXPTR: Current RX ring address.
647 * TXPTR: Current Tx ring address.
648 * PRIPTR: Current Priority ring address.
649 * ATIMPTR: Current ATIM ring address.
650 */
651 #define RXPTR 0x0100
652 #define TXPTR 0x0104
653 #define PRIPTR 0x0108
654 #define ATIMPTR 0x010c
656 /*
657 * GPIO and others.
658 */
660 /*
661 * GPIOCSR: GPIO control register.
662 */
663 #define GPIOCSR 0x0120
664 #define GPIOCSR_BIT0 FIELD32(0x00000001)
665 #define GPIOCSR_BIT1 FIELD32(0x00000002)
666 #define GPIOCSR_BIT2 FIELD32(0x00000004)
667 #define GPIOCSR_BIT3 FIELD32(0x00000008)
668 #define GPIOCSR_BIT4 FIELD32(0x00000010)
669 #define GPIOCSR_BIT5 FIELD32(0x00000020)
670 #define GPIOCSR_BIT6 FIELD32(0x00000040)
671 #define GPIOCSR_BIT7 FIELD32(0x00000080)
673 /*
674 * BBPPCSR: BBP Pin control register.
675 */
676 #define BBPPCSR 0x0124
678 /*
679 * BCNCSR1: Tx BEACON offset time control register.
680 * PRELOAD: Beacon timer offset in units of usec.
681 */
682 #define BCNCSR1 0x0130
683 #define BCNCSR1_PRELOAD FIELD32(0x0000ffff)
685 /*
686 * MACCSR2: TX_PE to RX_PE turn-around time control register
687 * DELAY: RX_PE low width, in units of pci clock cycle.
688 */
689 #define MACCSR2 0x0134
690 #define MACCSR2_DELAY FIELD32(0x000000ff)
692 /*
693 * ARCSR2: 1 Mbps ACK/CTS PLCP.
694 */
695 #define ARCSR2 0x013c
696 #define ARCSR2_SIGNAL FIELD32(0x000000ff)
697 #define ARCSR2_SERVICE FIELD32(0x0000ff00)
698 #define ARCSR2_LENGTH_LOW FIELD32(0x00ff0000)
699 #define ARCSR2_LENGTH FIELD32(0xffff0000)
701 /*
702 * ARCSR3: 2 Mbps ACK/CTS PLCP.
703 */
704 #define ARCSR3 0x0140
705 #define ARCSR3_SIGNAL FIELD32(0x000000ff)
706 #define ARCSR3_SERVICE FIELD32(0x0000ff00)
707 #define ARCSR3_LENGTH FIELD32(0xffff0000)
709 /*
710 * ARCSR4: 5.5 Mbps ACK/CTS PLCP.
711 */
712 #define ARCSR4 0x0144
713 #define ARCSR4_SIGNAL FIELD32(0x000000ff)
714 #define ARCSR4_SERVICE FIELD32(0x0000ff00)
715 #define ARCSR4_LENGTH FIELD32(0xffff0000)
717 /*
718 * ARCSR5: 11 Mbps ACK/CTS PLCP.
719 */
720 #define ARCSR5 0x0148
721 #define ARCSR5_SIGNAL FIELD32(0x000000ff)
722 #define ARCSR5_SERVICE FIELD32(0x0000ff00)
723 #define ARCSR5_LENGTH FIELD32(0xffff0000)
725 /*
726 * BBP registers.
727 * The wordsize of the BBP is 8 bits.
728 */
730 /*
731 * R1: TX antenna control
732 */
733 #define BBP_R1_TX_ANTENNA FIELD8(0x03)
735 /*
736 * R4: RX antenna control
737 */
738 #define BBP_R4_RX_ANTENNA FIELD8(0x06)
740 /*
741 * RF registers
742 */
744 /*
745 * RF 1
746 */
747 #define RF1_TUNER FIELD32(0x00020000)
749 /*
750 * RF 3
751 */
752 #define RF3_TUNER FIELD32(0x00000100)
753 #define RF3_TXPOWER FIELD32(0x00003e00)
755 /*
756 * EEPROM content.
757 * The wordsize of the EEPROM is 16 bits.
758 */
760 /*
761 * HW MAC address.
762 */
763 #define EEPROM_MAC_ADDR_0 0x0002
764 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
765 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
766 #define EEPROM_MAC_ADDR1 0x0003
767 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
768 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
769 #define EEPROM_MAC_ADDR_2 0x0004
770 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
771 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
773 /*
774 * EEPROM antenna.
775 * ANTENNA_NUM: Number of antenna's.
776 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
777 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
778 * RF_TYPE: Rf_type of this adapter.
779 * LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd.
780 * RX_AGCVGC: 0: disable, 1:enable BBP R13 tuning.
781 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
782 */
783 #define EEPROM_ANTENNA 0x0b
784 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
785 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
786 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
787 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0040)
788 #define EEPROM_ANTENNA_LED_MODE FIELD16(0x0180)
789 #define EEPROM_ANTENNA_RX_AGCVGC_TUNING FIELD16(0x0200)
790 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
792 /*
793 * EEPROM BBP.
794 */
795 #define EEPROM_BBP_START 0x0c
796 #define EEPROM_BBP_SIZE 7
797 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
798 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
800 /*
801 * EEPROM TXPOWER
802 */
803 #define EEPROM_TXPOWER_START 0x13
804 #define EEPROM_TXPOWER_SIZE 7
805 #define EEPROM_TXPOWER_1 FIELD16(0x00ff)
806 #define EEPROM_TXPOWER_2 FIELD16(0xff00)
808 /*
809 * DMA descriptor defines.
810 */
811 #define TXD_DESC_SIZE ( 8 * sizeof(__le32) )
812 #define RXD_DESC_SIZE ( 8 * sizeof(__le32) )
814 /*
815 * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
816 */
818 /*
819 * Word0
820 */
821 #define TXD_W0_OWNER_NIC FIELD32(0x00000001)
822 #define TXD_W0_VALID FIELD32(0x00000002)
823 #define TXD_W0_RESULT FIELD32(0x0000001c)
824 #define TXD_W0_RETRY_COUNT FIELD32(0x000000e0)
825 #define TXD_W0_MORE_FRAG FIELD32(0x00000100)
826 #define TXD_W0_ACK FIELD32(0x00000200)
827 #define TXD_W0_TIMESTAMP FIELD32(0x00000400)
828 #define TXD_W0_RTS FIELD32(0x00000800)
829 #define TXD_W0_IFS FIELD32(0x00006000)
830 #define TXD_W0_RETRY_MODE FIELD32(0x00008000)
831 #define TXD_W0_AGC FIELD32(0x00ff0000)
832 #define TXD_W0_R2 FIELD32(0xff000000)
834 /*
835 * Word1
836 */
837 #define TXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
839 /*
840 * Word2
841 */
842 #define TXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff)
843 #define TXD_W2_DATABYTE_COUNT FIELD32(0xffff0000)
845 /*
846 * Word3 & 4: PLCP information
847 * The PLCP values should be treated as if they were BBP values.
848 */
849 #define TXD_W3_PLCP_SIGNAL FIELD32(0x000000ff)
850 #define TXD_W3_PLCP_SIGNAL_REGNUM FIELD32(0x00007f00)
851 #define TXD_W3_PLCP_SIGNAL_BUSY FIELD32(0x00008000)
852 #define TXD_W3_PLCP_SERVICE FIELD32(0x00ff0000)
853 #define TXD_W3_PLCP_SERVICE_REGNUM FIELD32(0x7f000000)
854 #define TXD_W3_PLCP_SERVICE_BUSY FIELD32(0x80000000)
856 #define TXD_W4_PLCP_LENGTH_LOW FIELD32(0x000000ff)
857 #define TXD_W3_PLCP_LENGTH_LOW_REGNUM FIELD32(0x00007f00)
858 #define TXD_W3_PLCP_LENGTH_LOW_BUSY FIELD32(0x00008000)
859 #define TXD_W4_PLCP_LENGTH_HIGH FIELD32(0x00ff0000)
860 #define TXD_W3_PLCP_LENGTH_HIGH_REGNUM FIELD32(0x7f000000)
861 #define TXD_W3_PLCP_LENGTH_HIGH_BUSY FIELD32(0x80000000)
863 /*
864 * Word5
865 */
866 #define TXD_W5_BBCR4 FIELD32(0x0000ffff)
867 #define TXD_W5_AGC_REG FIELD32(0x007f0000)
868 #define TXD_W5_AGC_REG_VALID FIELD32(0x00800000)
869 #define TXD_W5_XXX_REG FIELD32(0x7f000000)
870 #define TXD_W5_XXX_REG_VALID FIELD32(0x80000000)
872 /*
873 * Word6
874 */
875 #define TXD_W6_SK_BUFF FIELD32(0xffffffff)
877 /*
878 * Word7
879 */
880 #define TXD_W7_RESERVED FIELD32(0xffffffff)
882 /*
883 * RX descriptor format for RX Ring.
884 */
886 /*
887 * Word0
888 */
889 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
890 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
891 #define RXD_W0_MULTICAST FIELD32(0x00000004)
892 #define RXD_W0_BROADCAST FIELD32(0x00000008)
893 #define RXD_W0_MY_BSS FIELD32(0x00000010)
894 #define RXD_W0_CRC_ERROR FIELD32(0x00000020)
895 #define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
896 #define RXD_W0_DATABYTE_COUNT FIELD32(0xffff0000)
898 /*
899 * Word1
900 */
901 #define RXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
903 /*
904 * Word2
905 */
906 #define RXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff)
907 #define RXD_W2_BBR0 FIELD32(0x00ff0000)
908 #define RXD_W2_SIGNAL FIELD32(0xff000000)
910 /*
911 * Word3
912 */
913 #define RXD_W3_RSSI FIELD32(0x000000ff)
914 #define RXD_W3_BBR3 FIELD32(0x0000ff00)
915 #define RXD_W3_BBR4 FIELD32(0x00ff0000)
916 #define RXD_W3_BBR5 FIELD32(0xff000000)
918 /*
919 * Word4
920 */
921 #define RXD_W4_RX_END_TIME FIELD32(0xffffffff)
923 /*
924 * Word5 & 6 & 7: Reserved
925 */
926 #define RXD_W5_RESERVED FIELD32(0xffffffff)
927 #define RXD_W6_RESERVED FIELD32(0xffffffff)
928 #define RXD_W7_RESERVED FIELD32(0xffffffff)
930 /*
931 * Macro's for converting txpower from EEPROM to mac80211 value
932 * and from mac80211 value to register value.
933 * NOTE: Logics in rt2400pci for txpower are reversed
934 * compared to the other rt2x00 drivers. A higher txpower
935 * value means that the txpower must be lowered. This is
936 * important when converting the value coming from the
937 * mac80211 stack to the rt2400 acceptable value.
938 */
939 #define MIN_TXPOWER 31
940 #define MAX_TXPOWER 62
941 #define DEFAULT_TXPOWER 39
943 #define __CLAMP_TX(__txpower) \
944 clamp_t(char, (__txpower), MIN_TXPOWER, MAX_TXPOWER)
946 #define TXPOWER_FROM_DEV(__txpower) \
947 ((__CLAMP_TX(__txpower) - MAX_TXPOWER) + MIN_TXPOWER)
949 #define TXPOWER_TO_DEV(__txpower) \
950 MAX_TXPOWER - (__CLAMP_TX(__txpower) - MIN_TXPOWER)