arch/mips/kernel/cevt-smtc.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2007 MIPS Technologies, Inc.
   7  * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
   8  * Copyright (C) 2008 Kevin D. Kissell, Paralogos sarl
   9  */
  10 #include <linux/clockchips.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/percpu.h>
  13
  14 #include <asm/smtc_ipi.h>
  15 #include <asm/time.h>
  16 #include <asm/cevt-r4k.h>
  17
  18 /*
  19  * Variant clock event timer support for SMTC on MIPS 34K, 1004K
  20  * or other MIPS MT cores.
  21  *
  22  * Notes on SMTC Support:
  23  *
  24  * SMTC has multiple microthread TCs pretending to be Linux CPUs.
  25  * But there's only one Count/Compare pair per VPE, and Compare
  26  * interrupts are taken opportunisitically by available TCs
  27  * bound to the VPE with the Count register.  The new timer
  28  * framework provides for global broadcasts, but we really
  29  * want VPE-level multicasts for best behavior. So instead
  30  * of invoking the high-level clock-event broadcast code,
  31  * this version of SMTC support uses the historical SMTC
  32  * multicast mechanisms "under the hood", appearing to the
  33  * generic clock layer as if the interrupts are per-CPU.
  34  *
  35  * The approach taken here is to maintain a set of NR_CPUS
  36  * virtual timers, and track which "CPU" needs to be alerted
  37  * at each event.
  38  *
  39  * It's unlikely that we'll see a MIPS MT core with more than
  40  * 2 VPEs, but we *know* that we won't need to handle more
  41  * VPEs than we have "CPUs".  So NCPUs arrays of NCPUs elements
  42  * is always going to be overkill, but always going to be enough.
  43  */
  44
  45 unsigned long smtc_nexttime[NR_CPUS][NR_CPUS];
  46 static int smtc_nextinvpe[NR_CPUS];
  47
  48 /*
  49  * Timestamps stored are absolute values to be programmed
  50  * into Count register.  Valid timestamps will never be zero.
  51  * If a Zero Count value is actually calculated, it is converted
  52  * to be a 1, which will introduce 1 or two CPU cycles of error
  53  * roughly once every four billion events, which at 1000 HZ means
  54  * about once every 50 days.  If that's actually a problem, one
  55  * could alternate squashing 0 to 1 and to -1.
  56  */
  57
  58 #define MAKEVALID(x) (((x) == 0L) ? 1L : (x))
  59 #define ISVALID(x) ((x) != 0L)
  60
  61 /*
  62  * Time comparison is subtle, as it's really truncated
  63  * modular arithmetic.
  64  */
  65
  66 #define IS_SOONER(a, b, reference) \
  67     (((a) - (unsigned long)(reference)) < ((b) - (unsigned long)(reference)))
  68
  69 /*
  70  * CATCHUP_INCREMENT, used when the function falls behind the counter.
  71  * Could be an increasing function instead of a constant;
  72  */
  73
  74 #define CATCHUP_INCREMENT 64
  75
  76 static int mips_next_event(unsigned long delta,
  77                                 struct clock_event_device *evt)
  78 {
  79         unsigned long flags;
  80         unsigned int mtflags;
  81         unsigned long timestamp, reference, previous;
  82         unsigned long nextcomp = 0L;
  83         int vpe = current_cpu_data.vpe_id;
  84         int cpu = smp_processor_id();
  85         local_irq_save(flags);
  86         mtflags = dmt();
  87
  88         /*
  89          * Maintain the per-TC virtual timer
  90          * and program the per-VPE shared Count register
  91          * as appropriate here...
  92          */
  93         reference = (unsigned long)read_c0_count();
  94         timestamp = MAKEVALID(reference + delta);
  95         /*
  96          * To really model the clock, we have to catch the case
  97          * where the current next-in-VPE timestamp is the old
  98          * timestamp for the calling CPE, but the new value is
  99          * in fact later.  In that case, we have to do a full
 100          * scan and discover the new next-in-VPE CPU id and
 101          * timestamp.
 102          */
 103         previous = smtc_nexttime[vpe][cpu];
 104         if (cpu == smtc_nextinvpe[vpe] && ISVALID(previous)
 105             && IS_SOONER(previous, timestamp, reference)) {
 106                 int i;
 107                 int soonest = cpu;
 108
 109                 /*
 110                  * Update timestamp array here, so that new
 111                  * value gets considered along with those of
 112                  * other virtual CPUs on the VPE.
 113                  */
 114                 smtc_nexttime[vpe][cpu] = timestamp;
 115                 for_each_online_cpu(i) {
 116                         if (ISVALID(smtc_nexttime[vpe][i])
 117                             && IS_SOONER(smtc_nexttime[vpe][i],
 118                                 smtc_nexttime[vpe][soonest], reference)) {
 119                                     soonest = i;
 120                         }
 121                 }
 122                 smtc_nextinvpe[vpe] = soonest;
 123                 nextcomp = smtc_nexttime[vpe][soonest];
 124         /*
 125          * Otherwise, we don't have to process the whole array rank,
 126          * we just have to see if the event horizon has gotten closer.
 127          */
 128         } else {
 129                 if (!ISVALID(smtc_nexttime[vpe][smtc_nextinvpe[vpe]]) ||
 130                     IS_SOONER(timestamp,
 131                         smtc_nexttime[vpe][smtc_nextinvpe[vpe]], reference)) {
 132                             smtc_nextinvpe[vpe] = cpu;
 133                             nextcomp = timestamp;
 134                 }
 135                 /*
 136                  * Since next-in-VPE may me the same as the executing
 137                  * virtual CPU, we update the array *after* checking
 138                  * its value.
 139                  */
 140                 smtc_nexttime[vpe][cpu] = timestamp;
 141         }
 142
 143         /*
 144          * It may be that, in fact, we don't need to update Compare,
 145          * but if we do, we want to make sure we didn't fall into
 146          * a crack just behind Count.
 147          */
 148         if (ISVALID(nextcomp)) {
 149                 write_c0_compare(nextcomp);
 150                 ehb();
 151                 /*
 152                  * We never return an error, we just make sure
 153                  * that we trigger the handlers as quickly as
 154                  * we can if we fell behind.
 155                  */
 156                 while ((nextcomp - (unsigned long)read_c0_count())
 157                         > (unsigned long)LONG_MAX) {
 158                         nextcomp += CATCHUP_INCREMENT;
 159                         write_c0_compare(nextcomp);
 160                         ehb();
 161                 }
 162         }
 163         emt(mtflags);
 164         local_irq_restore(flags);
 165         return 0;
 166 }
 167
 168
 169 void smtc_distribute_timer(int vpe)
 170 {
 171         unsigned long flags;
 172         unsigned int mtflags;
 173         int cpu;
 174         struct clock_event_device *cd;
 175         unsigned long nextstamp = 0L;
 176         unsigned long reference;
 177
 178
 179 repeat:
 180         for_each_online_cpu(cpu) {
 181             /*
 182              * Find virtual CPUs within the current VPE who have
 183              * unserviced timer requests whose time is now past.
 184              */
 185             local_irq_save(flags);
 186             mtflags = dmt();
 187             if (cpu_data[cpu].vpe_id == vpe &&
 188                 ISVALID(smtc_nexttime[vpe][cpu])) {
 189                 reference = (unsigned long)read_c0_count();
 190                 if ((smtc_nexttime[vpe][cpu] - reference)
 191                          > (unsigned long)LONG_MAX) {
 192                             smtc_nexttime[vpe][cpu] = 0L;
 193                             emt(mtflags);
 194                             local_irq_restore(flags);
 195                             /*
 196                              * We don't send IPIs to ourself.
 197                              */
 198                             if (cpu != smp_processor_id()) {
 199                                 smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0);
 200                             } else {
 201                                 cd = &per_cpu(mips_clockevent_device, cpu);
 202                                 cd->event_handler(cd);
 203                             }
 204                 } else {
 205                         /* Local to VPE but Valid Time not yet reached. */
 206                         if (!ISVALID(nextstamp) ||
 207                             IS_SOONER(smtc_nexttime[vpe][cpu], nextstamp,
 208                             reference)) {
 209                                 smtc_nextinvpe[vpe] = cpu;
 210                                 nextstamp = smtc_nexttime[vpe][cpu];
 211                         }
 212                         emt(mtflags);
 213                         local_irq_restore(flags);
 214                 }
 215             } else {
 216                 emt(mtflags);
 217                 local_irq_restore(flags);
 218
 219             }
 220         }
 221         /* Reprogram for interrupt at next soonest timestamp for VPE */
 222         if (ISVALID(nextstamp)) {
 223                 write_c0_compare(nextstamp);
 224                 ehb();
 225                 if ((nextstamp - (unsigned long)read_c0_count())
 226                         > (unsigned long)LONG_MAX)
 227                                 goto repeat;
 228         }
 229 }
 230
 231
 232 irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
 233 {
 234         int cpu = smp_processor_id();
 235
 236         /* If we're running SMTC, we've got MIPS MT and therefore MIPS32R2 */
 237         handle_perf_irq(1);
 238
 239         if (read_c0_cause() & (1 << 30)) {
 240                 /* Clear Count/Compare Interrupt */
 241                 write_c0_compare(read_c0_compare());
 242                 smtc_distribute_timer(cpu_data[cpu].vpe_id);
 243         }
 244         return IRQ_HANDLED;
 245 }
 246
 247
 248 int __cpuinit mips_clockevent_init(void)
 249 {
 250         uint64_t mips_freq = mips_hpt_frequency;
 251         unsigned int cpu = smp_processor_id();
 252         struct clock_event_device *cd;
 253         unsigned int irq;
 254         int i;
 255         int j;
 256
 257         if (!cpu_has_counter || !mips_hpt_frequency)
 258                 return -ENXIO;
 259         if (cpu == 0) {
 260                 for (i = 0; i < num_possible_cpus(); i++) {
 261                         smtc_nextinvpe[i] = 0;
 262                         for (j = 0; j < num_possible_cpus(); j++)
 263                                 smtc_nexttime[i][j] = 0L;
 264                 }
 265                 /*
 266                  * SMTC also can't have the usablility test
 267                  * run by secondary TCs once Compare is in use.
 268                  */
 269                 if (!c0_compare_int_usable())
 270                         return -ENXIO;
 271         }
 272
 273         /*
 274          * With vectored interrupts things are getting platform specific.
 275          * get_c0_compare_int is a hook to allow a platform to return the
 276          * interrupt number of it's liking.
 277          */
 278         irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
 279         if (get_c0_compare_int)
 280                 irq = get_c0_compare_int();
 281
 282         cd = &per_cpu(mips_clockevent_device, cpu);
 283
 284         cd->name                = "MIPS";
 285         cd->features            = CLOCK_EVT_FEAT_ONESHOT;
 286
 287         /* Calculate the min / max delta */
 288         cd->mult        = div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
 289         cd->shift               = 32;
 290         cd->max_delta_ns        = clockevent_delta2ns(0x7fffffff, cd);
 291         cd->min_delta_ns        = clockevent_delta2ns(0x300, cd);
 292
 293         cd->rating              = 300;
 294         cd->irq                 = irq;
 295         cd->cpumask             = cpumask_of(cpu);
 296         cd->set_next_event      = mips_next_event;
 297         cd->set_mode            = mips_set_clock_mode;
 298         cd->event_handler       = mips_event_handler;
 299
 300         clockevents_register_device(cd);
 301
 302         /*
 303          * On SMTC we only want to do the data structure
 304          * initialization and IRQ setup once.
 305          */
 306         if (cpu)
 307                 return 0;
 308         /*
 309          * And we need the hwmask associated with the c0_compare
 310          * vector to be initialized.
 311          */
 312         irq_hwmask[irq] = (0x100 << cp0_compare_irq);
 313         if (cp0_timer_irq_installed)
 314                 return 0;
 315
 316         cp0_timer_irq_installed = 1;
 317
 318         setup_irq(irq, &c0_compare_irqaction);
 319
 320         return 0;
 321 }