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MERGE-master-patchset-edits
[linux-2.6/openmoko-kernel.git] / drivers / mmc / host / s3cmci.c
blob2019773114c2cc6d686840c6f21a25078692376e
1 /*
2 * linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
3 *
4 * Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
5 *
6 * Current driver maintained by Ben Dooks and Simtec Electronics
7 * Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/clk.h>
17 #include <linux/mmc/host.h>
18 #include <linux/platform_device.h>
19 #include <linux/cpufreq.h>
20 #include <linux/irq.h>
21 #include <linux/io.h>
22
23 #include <mach/dma.h>
24
25 #include <mach/regs-sdi.h>
26 #include <mach/regs-gpio.h>
27
28 #include <plat/mci.h>
29
30 #include "s3cmci.h"
31
32 #define DRIVER_NAME "s3c-mci"
33
34 enum dbg_channels {
35 dbg_err = (1 << 0),
36 dbg_debug = (1 << 1),
37 dbg_info = (1 << 2),
38 dbg_irq = (1 << 3),
39 dbg_sg = (1 << 4),
40 dbg_dma = (1 << 5),
41 dbg_pio = (1 << 6),
42 dbg_fail = (1 << 7),
43 dbg_conf = (1 << 8),
44 };
45
46 static const int dbgmap_err = dbg_fail;
47 static const int dbgmap_info = dbg_info | dbg_conf;
48 static const int dbgmap_debug = dbg_err | dbg_debug;
49
50 #define dbg(host, channels, args...) \
51 do { \
52 if (dbgmap_err & channels) \
53 dev_err(&host->pdev->dev, args); \
54 else if (dbgmap_info & channels) \
55 dev_info(&host->pdev->dev, args); \
56 else if (dbgmap_debug & channels) \
57 dev_dbg(&host->pdev->dev, args); \
58 } while (0)
59
60 #define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1)
61
62 static struct s3c2410_dma_client s3cmci_dma_client = {
63 .name = "s3c-mci",
64 };
65
66 static void finalize_request(struct s3cmci_host *host);
67 static void s3cmci_send_request(struct mmc_host *mmc);
68 static void s3cmci_reset(struct s3cmci_host *host);
69
70 #ifdef CONFIG_MMC_DEBUG
71
72 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix)
73 {
74 u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer, bsize;
75 u32 datcon, datcnt, datsta, fsta, imask;
76
77 con = readl(host->base + S3C2410_SDICON);
78 pre = readl(host->base + S3C2410_SDIPRE);
79 cmdarg = readl(host->base + S3C2410_SDICMDARG);
80 cmdcon = readl(host->base + S3C2410_SDICMDCON);
81 cmdsta = readl(host->base + S3C2410_SDICMDSTAT);
82 r0 = readl(host->base + S3C2410_SDIRSP0);
83 r1 = readl(host->base + S3C2410_SDIRSP1);
84 r2 = readl(host->base + S3C2410_SDIRSP2);
85 r3 = readl(host->base + S3C2410_SDIRSP3);
86 timer = readl(host->base + S3C2410_SDITIMER);
87 bsize = readl(host->base + S3C2410_SDIBSIZE);
88 datcon = readl(host->base + S3C2410_SDIDCON);
89 datcnt = readl(host->base + S3C2410_SDIDCNT);
90 datsta = readl(host->base + S3C2410_SDIDSTA);
91 fsta = readl(host->base + S3C2410_SDIFSTA);
92 imask = readl(host->base + host->sdiimsk);
93
94 dbg(host, dbg_debug, "%s CON:[%08x] PRE:[%08x] TMR:[%08x]\n",
95 prefix, con, pre, timer);
96
97 dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n",
98 prefix, cmdcon, cmdarg, cmdsta);
99
100 dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]"
101 " DSTA:[%08x] DCNT:[%08x]\n",
102 prefix, datcon, fsta, datsta, datcnt);
103
104 dbg(host, dbg_debug, "%s R0:[%08x] R1:[%08x]"
105 " R2:[%08x] R3:[%08x]\n",
106 prefix, r0, r1, r2, r3);
107 }
108
109 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
110 int stop)
111 {
112 snprintf(host->dbgmsg_cmd, 300,
113 "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u",
114 host->ccnt, (stop ? " (STOP)" : ""),
115 cmd->opcode, cmd->arg, cmd->flags, cmd->retries);
116
117 if (cmd->data) {
118 snprintf(host->dbgmsg_dat, 300,
119 "#%u bsize:%u blocks:%u bytes:%u",
120 host->dcnt, cmd->data->blksz,
121 cmd->data->blocks,
122 cmd->data->blocks * cmd->data->blksz);
123 } else {
124 host->dbgmsg_dat[0] = '\0';
125 }
126 }
127
128 static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd,
129 int fail)
130 {
131 unsigned int dbglvl = fail ? dbg_fail : dbg_debug;
132
133 if (!cmd)
134 return;
135
136 if (cmd->error == 0) {
137 dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n",
138 host->dbgmsg_cmd, cmd->resp[0]);
139 } else {
140 dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n",
141 cmd->error, host->dbgmsg_cmd, host->status);
142 }
143
144 if (!cmd->data)
145 return;
146
147 if (cmd->data->error == 0) {
148 dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat);
149 } else {
150 dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n",
151 cmd->data->error, host->dbgmsg_dat,
152 readl(host->base + S3C2410_SDIDCNT));
153 }
154 }
155 #else
156 static void dbg_dumpcmd(struct s3cmci_host *host,
157 struct mmc_command *cmd, int fail) { }
158
159 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
160 int stop) { }
161
162 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { }
163
164 #endif /* CONFIG_MMC_DEBUG */
165
166 static inline u32 enable_imask(struct s3cmci_host *host, u32 imask)
167 {
168 u32 newmask;
169
170 newmask = readl(host->base + host->sdiimsk);
171 newmask |= imask;
172
173 writel(newmask, host->base + host->sdiimsk);
174
175 return newmask;
176 }
177
178 static inline u32 disable_imask(struct s3cmci_host *host, u32 imask)
179 {
180 u32 newmask;
181
182 newmask = readl(host->base + host->sdiimsk);
183 newmask &= ~imask;
184
185 writel(newmask, host->base + host->sdiimsk);
186
187 return newmask;
188 }
189
190 static inline void clear_imask(struct s3cmci_host *host)
191 {
192 writel(0, host->base + host->sdiimsk);
193 }
194
195 static inline int get_data_buffer(struct s3cmci_host *host,
196 u32 *bytes, u32 **pointer)
197 {
198 struct scatterlist *sg;
199
200 if (host->pio_active == XFER_NONE)
201 return -EINVAL;
202
203 if ((!host->mrq) || (!host->mrq->data))
204 return -EINVAL;
205
206 if (host->pio_sgptr >= host->mrq->data->sg_len) {
207 dbg(host, dbg_debug, "no more buffers (%i/%i)\n",
208 host->pio_sgptr, host->mrq->data->sg_len);
209 return -EBUSY;
210 }
211 sg = &host->mrq->data->sg[host->pio_sgptr];
212
213 *bytes = sg->length;
214 *pointer = sg_virt(sg);
215
216 host->pio_sgptr++;
217
218 dbg(host, dbg_sg, "new buffer (%i/%i)\n",
219 host->pio_sgptr, host->mrq->data->sg_len);
220
221 return 0;
222 }
223
224 static inline u32 fifo_count(struct s3cmci_host *host)
225 {
226 u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
227
228 fifostat &= S3C2410_SDIFSTA_COUNTMASK;
229 return fifostat;
230 }
231
232 static inline u32 fifo_free(struct s3cmci_host *host)
233 {
234 u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
235
236 fifostat &= S3C2410_SDIFSTA_COUNTMASK;
237 return 63 - fifostat;
238 }
239
240 static void do_pio_read(struct s3cmci_host *host)
241 {
242 int res;
243 u32 fifo;
244 u32 *ptr;
245 u32 fifo_words;
246 void __iomem *from_ptr;
247
248 /* write real prescaler to host, it might be set slow to fix */
249 writel(host->prescaler, host->base + S3C2410_SDIPRE);
250
251 from_ptr = host->base + host->sdidata;
252
253 while ((fifo = fifo_count(host))) {
254 if (!host->pio_bytes) {
255 res = get_data_buffer(host, &host->pio_bytes,
256 &host->pio_ptr);
257 if (res) {
258 host->pio_active = XFER_NONE;
259 host->complete_what = COMPLETION_FINALIZE;
260
261 dbg(host, dbg_pio, "pio_read(): "
262 "complete (no more data).\n");
263 return;
264 }
265
266 dbg(host, dbg_pio,
267 "pio_read(): new target: [%i]@[%p]\n",
268 host->pio_bytes, host->pio_ptr);
269 }
270
271 dbg(host, dbg_pio,
272 "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n",
273 fifo, host->pio_bytes,
274 readl(host->base + S3C2410_SDIDCNT));
275
276 /* If we have reached the end of the block, we can
277 * read a word and get 1 to 3 bytes. If we in the
278 * middle of the block, we have to read full words,
279 * otherwise we will write garbage, so round down to
280 * an even multiple of 4. */
281 if (fifo >= host->pio_bytes)
282 fifo = host->pio_bytes;
283 else
284 fifo -= fifo & 3;
285
286 host->pio_bytes -= fifo;
287 host->pio_count += fifo;
288
289 fifo_words = fifo >> 2;
290 ptr = host->pio_ptr;
291 while (fifo_words--)
292 *ptr++ = readl(from_ptr);
293 host->pio_ptr = ptr;
294
295 if (fifo & 3) {
296 u32 n = fifo & 3;
297 u32 data = readl(from_ptr);
298 u8 *p = (u8 *)host->pio_ptr;
299
300 while (n--) {
301 *p++ = data;
302 data >>= 8;
303 }
304 }
305 }
306
307 if (!host->pio_bytes) {
308 res = get_data_buffer(host, &host->pio_bytes, &host->pio_ptr);
309 if (res) {
310 dbg(host, dbg_pio,
311 "pio_read(): complete (no more buffers).\n");
312 host->pio_active = XFER_NONE;
313 host->complete_what = COMPLETION_FINALIZE;
314
315 return;
316 }
317 }
318
319 enable_imask(host,
320 S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST);
321 }
322
323 static void do_pio_write(struct s3cmci_host *host)
324 {
325 void __iomem *to_ptr;
326 int res;
327 u32 fifo;
328 u32 *ptr;
329
330 to_ptr = host->base + host->sdidata;
331
332 while ((fifo = fifo_free(host))) {
333 if (!host->pio_bytes) {
334 res = get_data_buffer(host, &host->pio_bytes,
335 &host->pio_ptr);
336 if (res) {
337 dbg(host, dbg_pio,
338 "pio_write(): complete (no more data).\n");
339 host->pio_active = XFER_NONE;
340
341 return;
342 }
343
344 dbg(host, dbg_pio,
345 "pio_write(): new source: [%i]@[%p]\n",
346 host->pio_bytes, host->pio_ptr);
347
348 }
349
350 /* If we have reached the end of the block, we have to
351 * write exactly the remaining number of bytes. If we
352 * in the middle of the block, we have to write full
353 * words, so round down to an even multiple of 4. */
354 if (fifo >= host->pio_bytes)
355 fifo = host->pio_bytes;
356 else
357 fifo -= fifo & 3;
358
359 host->pio_bytes -= fifo;
360 host->pio_count += fifo;
361
362 fifo = (fifo + 3) >> 2;
363 ptr = host->pio_ptr;
364 while (fifo--)
365 writel(*ptr++, to_ptr);
366 host->pio_ptr = ptr;
367 }
368
369 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
370 }
371
372 static void pio_tasklet(unsigned long data)
373 {
374 struct s3cmci_host *host = (struct s3cmci_host *) data;
375
376
377 disable_irq(host->irq);
378
379 if (host->pio_active == XFER_WRITE)
380 do_pio_write(host);
381
382 if (host->pio_active == XFER_READ)
383 do_pio_read(host);
384
385 if (host->complete_what == COMPLETION_FINALIZE) {
386 clear_imask(host);
387 if (host->pio_active != XFER_NONE) {
388 dbg(host, dbg_err, "unfinished %s "
389 "- pio_count:[%u] pio_bytes:[%u]\n",
390 (host->pio_active == XFER_READ) ? "read" : "write",
391 host->pio_count, host->pio_bytes);
392
393 if (host->mrq->data)
394 host->mrq->data->error = -EINVAL;
395 }
396
397 finalize_request(host);
398 } else
399 enable_irq(host->irq);
400 }
401
402 /*
403 * ISR for SDI Interface IRQ
404 * Communication between driver and ISR works as follows:
405 * host->mrq points to current request
406 * host->complete_what Indicates when the request is considered done
407 * COMPLETION_CMDSENT when the command was sent
408 * COMPLETION_RSPFIN when a response was received
409 * COMPLETION_XFERFINISH when the data transfer is finished
410 * COMPLETION_XFERFINISH_RSPFIN both of the above.
411 * host->complete_request is the completion-object the driver waits for
412 *
413 * 1) Driver sets up host->mrq and host->complete_what
414 * 2) Driver prepares the transfer
415 * 3) Driver enables interrupts
416 * 4) Driver starts transfer
417 * 5) Driver waits for host->complete_rquest
418 * 6) ISR checks for request status (errors and success)
419 * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
420 * 7) ISR completes host->complete_request
421 * 8) ISR disables interrupts
422 * 9) Driver wakes up and takes care of the request
423 *
424 * Note: "->error"-fields are expected to be set to 0 before the request
425 * was issued by mmc.c - therefore they are only set, when an error
426 * contition comes up
427 */
428
429 static irqreturn_t s3cmci_irq(int irq, void *dev_id)
430 {
431 struct s3cmci_host *host = dev_id;
432 struct mmc_command *cmd;
433 u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk;
434 u32 mci_cclear, mci_dclear;
435 unsigned long iflags;
436
437 spin_lock_irqsave(&host->complete_lock, iflags);
438
439 mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
440 mci_dsta = readl(host->base + S3C2410_SDIDSTA);
441 mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
442 mci_fsta = readl(host->base + S3C2410_SDIFSTA);
443 mci_imsk = readl(host->base + host->sdiimsk);
444 mci_cclear = 0;
445 mci_dclear = 0;
446
447 if ((host->complete_what == COMPLETION_NONE) ||
448 (host->complete_what == COMPLETION_FINALIZE)) {
449 host->status = "nothing to complete";
450 clear_imask(host);
451 goto irq_out;
452 }
453
454 if (!host->mrq) {
455 host->status = "no active mrq";
456 clear_imask(host);
457 goto irq_out;
458 }
459
460 cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd;
461
462 if (!cmd) {
463 host->status = "no active cmd";
464 clear_imask(host);
465 goto irq_out;
466 }
467
468 if (!host->dodma) {
469 if ((host->pio_active == XFER_WRITE) &&
470 (mci_fsta & S3C2410_SDIFSTA_TFDET)) {
471
472 disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
473 tasklet_schedule(&host->pio_tasklet);
474 host->status = "pio tx";
475 }
476
477 if ((host->pio_active == XFER_READ) &&
478 (mci_fsta & S3C2410_SDIFSTA_RFDET)) {
479
480 disable_imask(host,
481 S3C2410_SDIIMSK_RXFIFOHALF |
482 S3C2410_SDIIMSK_RXFIFOLAST);
483
484 tasklet_schedule(&host->pio_tasklet);
485 host->status = "pio rx";
486 }
487 }
488
489 if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) {
490 dbg(host, dbg_err, "CMDSTAT: error CMDTIMEOUT\n");
491 cmd->error = -ETIMEDOUT;
492 host->status = "error: command timeout";
493 goto fail_transfer;
494 }
495
496 if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) {
497 if (host->complete_what == COMPLETION_CMDSENT) {
498 host->status = "ok: command sent";
499 goto close_transfer;
500 }
501
502 mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT;
503 }
504
505 if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) {
506 if (cmd->flags & MMC_RSP_CRC) {
507 if (host->mrq->cmd->flags & MMC_RSP_136) {
508 dbg(host, dbg_irq,
509 "fixup: ignore CRC fail with long rsp\n");
510 } else {
511 /* note, we used to fail the transfer
512 * here, but it seems that this is just
513 * the hardware getting it wrong.
514 *
515 * cmd->error = -EILSEQ;
516 * host->status = "error: bad command crc";
517 * goto fail_transfer;
518 */
519 }
520 }
521
522 mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL;
523 }
524
525 if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) {
526 if (host->complete_what == COMPLETION_RSPFIN) {
527 host->status = "ok: command response received";
528 goto close_transfer;
529 }
530
531 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
532 host->complete_what = COMPLETION_XFERFINISH;
533
534 mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN;
535 }
536
537 /* errors handled after this point are only relevant
538 when a data transfer is in progress */
539
540 if (!cmd->data)
541 goto clear_status_bits;
542
543 /* Check for FIFO failure */
544 if (host->is2440) {
545 if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) {
546 dbg(host, dbg_err, "FIFO failure\n");
547 host->mrq->data->error = -EILSEQ;
548 host->status = "error: 2440 fifo failure";
549 goto fail_transfer;
550 }
551 } else {
552 if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) {
553 dbg(host, dbg_err, "FIFO failure\n");
554 cmd->data->error = -EILSEQ;
555 host->status = "error: fifo failure";
556 goto fail_transfer;
557 }
558 }
559
560 if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) {
561 dbg(host, dbg_err, "bad data crc (outgoing)\n");
562 cmd->data->error = -EILSEQ;
563 host->status = "error: bad data crc (outgoing)";
564 goto fail_transfer;
565 }
566
567 if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) {
568 dbg(host, dbg_err, "bad data crc (incoming)\n");
569 cmd->data->error = -EILSEQ;
570 host->status = "error: bad data crc (incoming)";
571 goto fail_transfer;
572 }
573
574 if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) {
575 dbg(host, dbg_err, "data timeout\n");
576 cmd->data->error = -ETIMEDOUT;
577 host->status = "error: data timeout";
578 goto fail_transfer;
579 }
580
581 if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) {
582 if (host->complete_what == COMPLETION_XFERFINISH) {
583 host->status = "ok: data transfer completed";
584 goto close_transfer;
585 }
586
587 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
588 host->complete_what = COMPLETION_RSPFIN;
589
590 mci_dclear |= S3C2410_SDIDSTA_XFERFINISH;
591 }
592
593 clear_status_bits:
594 writel(mci_cclear, host->base + S3C2410_SDICMDSTAT);
595 writel(mci_dclear, host->base + S3C2410_SDIDSTA);
596
597 goto irq_out;
598
599 fail_transfer:
600 host->pio_active = XFER_NONE;
601
602 close_transfer:
603 host->complete_what = COMPLETION_FINALIZE;
604
605 clear_imask(host);
606 tasklet_schedule(&host->pio_tasklet);
607
608 goto irq_out;
609
610 irq_out:
611 dbg(host, dbg_irq,
612 "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n",
613 mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status);
614
615 spin_unlock_irqrestore(&host->complete_lock, iflags);
616 return IRQ_HANDLED;
617
618 }
619
620 /*
621 * ISR for the CardDetect Pin
622 */
623
624 static irqreturn_t s3cmci_irq_cd(int irq, void *dev_id)
625 {
626 struct s3cmci_host *host = (struct s3cmci_host *)dev_id;
627
628 dbg(host, dbg_irq, "card detect\n");
629
630 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
631
632 return IRQ_HANDLED;
633 }
634
635 static void s3cmci_dma_done_callback(struct s3c2410_dma_chan *dma_ch,
636 void *buf_id, int size,
637 enum s3c2410_dma_buffresult result)
638 {
639 struct s3cmci_host *host = buf_id;
640 unsigned long iflags;
641 u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt;
642
643 mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
644 mci_dsta = readl(host->base + S3C2410_SDIDSTA);
645 mci_fsta = readl(host->base + S3C2410_SDIFSTA);
646 mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
647
648 BUG_ON(!host->mrq);
649 BUG_ON(!host->mrq->data);
650 BUG_ON(!host->dmatogo);
651
652 spin_lock_irqsave(&host->complete_lock, iflags);
653
654 if (result != S3C2410_RES_OK) {
655 dbg(host, dbg_fail, "DMA FAILED: csta=0x%08x dsta=0x%08x "
656 "fsta=0x%08x dcnt:0x%08x result:0x%08x toGo:%u\n",
657 mci_csta, mci_dsta, mci_fsta,
658 mci_dcnt, result, host->dmatogo);
659
660 goto fail_request;
661 }
662
663 host->dmatogo--;
664 if (host->dmatogo) {
665 dbg(host, dbg_dma, "DMA DONE Size:%i DSTA:[%08x] "
666 "DCNT:[%08x] toGo:%u\n",
667 size, mci_dsta, mci_dcnt, host->dmatogo);
668
669 goto out;
670 }
671
672 dbg(host, dbg_dma, "DMA FINISHED Size:%i DSTA:%08x DCNT:%08x\n",
673 size, mci_dsta, mci_dcnt);
674
675 host->complete_what = COMPLETION_FINALIZE;
676
677 out:
678 tasklet_schedule(&host->pio_tasklet);
679 spin_unlock_irqrestore(&host->complete_lock, iflags);
680 return;
681
682 fail_request:
683 host->mrq->data->error = -EINVAL;
684 host->complete_what = COMPLETION_FINALIZE;
685 writel(0, host->base + host->sdiimsk);
686 goto out;
687
688 }
689
690 static void finalize_request(struct s3cmci_host *host)
691 {
692 struct mmc_request *mrq = host->mrq;
693 struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
694 int debug_as_failure = 0;
695
696 if (host->complete_what != COMPLETION_FINALIZE)
697 return;
698
699 if (!mrq)
700 return;
701
702 if (cmd->data && (cmd->error == 0) &&
703 (cmd->data->error == 0)) {
704 if (host->dodma && (!host->dma_complete)) {
705 dbg(host, dbg_dma, "DMA Missing!\n");
706 return;
707 }
708 }
709
710 /* Read response from controller. */
711 cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0);
712 cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1);
713 cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2);
714 cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3);
715
716 writel(host->prescaler, host->base + S3C2410_SDIPRE);
717
718 if (cmd->error)
719 debug_as_failure = 1;
720
721 if (cmd->data && cmd->data->error)
722 debug_as_failure = 1;
723
724 dbg_dumpcmd(host, cmd, debug_as_failure);
725
726 /* Cleanup controller */
727 writel(0, host->base + S3C2410_SDICMDARG);
728 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
729 writel(0, host->base + S3C2410_SDICMDCON);
730 writel(0, host->base + host->sdiimsk);
731
732 if (cmd->data && cmd->error)
733 cmd->data->error = cmd->error;
734
735 if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) {
736 host->cmd_is_stop = 1;
737 s3cmci_send_request(host->mmc);
738 return;
739 }
740
741 /* If we have no data transfer we are finished here */
742 if (!mrq->data)
743 goto request_done;
744
745 /* Calulate the amout of bytes transfer if there was no error */
746 if (mrq->data->error == 0) {
747 mrq->data->bytes_xfered =
748 (mrq->data->blocks * mrq->data->blksz);
749 } else {
750 mrq->data->bytes_xfered = 0;
751 }
752
753 /* If we had an error while transfering data we flush the
754 * DMA channel and the fifo to clear out any garbage. */
755 if (mrq->data->error != 0) {
756 if (host->dodma)
757 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
758
759 if (host->is2440) {
760 /* Clear failure register and reset fifo. */
761 writel(S3C2440_SDIFSTA_FIFORESET |
762 S3C2440_SDIFSTA_FIFOFAIL,
763 host->base + S3C2410_SDIFSTA);
764 } else {
765 u32 mci_con;
766
767 /* reset fifo */
768 mci_con = readl(host->base + S3C2410_SDICON);
769 mci_con |= S3C2410_SDICON_FIFORESET;
770
771 writel(mci_con, host->base + S3C2410_SDICON);
772 }
773 }
774
775 request_done:
776 host->complete_what = COMPLETION_NONE;
777 host->mrq = NULL;
778 mmc_request_done(host->mmc, mrq);
779 }
780
781 static void s3cmci_dma_setup(struct s3cmci_host *host,
782 enum s3c2410_dmasrc source)
783 {
784 static enum s3c2410_dmasrc last_source = -1;
785 static int setup_ok;
786
787 if (last_source == source)
788 return;
789
790 last_source = source;
791
792 s3c2410_dma_devconfig(host->dma, source,
793 host->mem->start + host->sdidata);
794
795 if (!setup_ok) {
796 s3c2410_dma_config(host->dma, 4, 0);
797 s3c2410_dma_set_buffdone_fn(host->dma,
798 s3cmci_dma_done_callback);
799 s3c2410_dma_setflags(host->dma, S3C2410_DMAF_AUTOSTART);
800 setup_ok = 1;
801 }
802 }
803
804 static void s3cmci_send_command(struct s3cmci_host *host,
805 struct mmc_command *cmd)
806 {
807 u32 ccon, imsk;
808
809 imsk = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT |
810 S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT |
811 S3C2410_SDIIMSK_RESPONSECRC;
812
813 enable_imask(host, imsk);
814
815 if (cmd->data)
816 host->complete_what = COMPLETION_XFERFINISH_RSPFIN;
817 else if (cmd->flags & MMC_RSP_PRESENT)
818 host->complete_what = COMPLETION_RSPFIN;
819 else
820 host->complete_what = COMPLETION_CMDSENT;
821
822 writel(cmd->arg, host->base + S3C2410_SDICMDARG);
823
824 ccon = cmd->opcode & S3C2410_SDICMDCON_INDEX;
825 ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART;
826
827 if (cmd->flags & MMC_RSP_PRESENT)
828 ccon |= S3C2410_SDICMDCON_WAITRSP;
829
830 if (cmd->flags & MMC_RSP_136)
831 ccon |= S3C2410_SDICMDCON_LONGRSP;
832
833 writel(ccon, host->base + S3C2410_SDICMDCON);
834 }
835
836 static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
837 {
838 u32 dcon, imsk, stoptries = 3;
839
840 /* write DCON register */
841
842 if (!data) {
843 writel(0, host->base + S3C2410_SDIDCON);
844 return 0;
845 }
846
847 if ((data->blksz & 3) != 0) {
848 /* We cannot deal with unaligned blocks with more than
849 * one block being transfered. */
850
851 if (data->blocks > 1) {
852 pr_warning("%s: can't do non-word sized block transfers (blksz %d)\n", __func__, data->blksz);
853 return -EINVAL;
854 }
855 }
856
857 while (readl(host->base + S3C2410_SDIDSTA) &
858 (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) {
859
860 dbg(host, dbg_err,
861 "mci_setup_data() transfer stillin progress.\n");
862
863 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
864 s3cmci_reset(host);
865
866 if ((stoptries--) == 0) {
867 dbg_dumpregs(host, "DRF");
868 return -EINVAL;
869 }
870 }
871
872 dcon = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK;
873
874 if (host->dodma)
875 dcon |= S3C2410_SDIDCON_DMAEN;
876
877 if (host->bus_width == MMC_BUS_WIDTH_4)
878 dcon |= S3C2410_SDIDCON_WIDEBUS;
879
880 if (!(data->flags & MMC_DATA_STREAM))
881 dcon |= S3C2410_SDIDCON_BLOCKMODE;
882
883 if (data->flags & MMC_DATA_WRITE) {
884 dcon |= S3C2410_SDIDCON_TXAFTERRESP;
885 dcon |= S3C2410_SDIDCON_XFER_TXSTART;
886 }
887
888 if (data->flags & MMC_DATA_READ) {
889 dcon |= S3C2410_SDIDCON_RXAFTERCMD;
890 dcon |= S3C2410_SDIDCON_XFER_RXSTART;
891 }
892
893 if (host->is2440) {
894 dcon |= S3C2440_SDIDCON_DS_WORD;
895 dcon |= S3C2440_SDIDCON_DATSTART;
896 }
897
898 writel(dcon, host->base + S3C2410_SDIDCON);
899
900 /* write BSIZE register */
901
902 writel(data->blksz, host->base + S3C2410_SDIBSIZE);
903
904 /* add to IMASK register */
905 imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC |
906 S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH;
907
908 enable_imask(host, imsk);
909
910 /* write TIMER register */
911
912 if (host->is2440) {
913 writel(0x007FFFFF, host->base + S3C2410_SDITIMER);
914 } else {
915 writel(0x0000FFFF, host->base + S3C2410_SDITIMER);
916
917 /* FIX: set slow clock to prevent timeouts on read */
918 if (data->flags & MMC_DATA_READ)
919 writel(0xFF, host->base + S3C2410_SDIPRE);
920 }
921
922 return 0;
923 }
924
925 #define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
926
927 static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data)
928 {
929 int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
930
931 BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
932
933 host->pio_sgptr = 0;
934 host->pio_bytes = 0;
935 host->pio_count = 0;
936 host->pio_active = rw ? XFER_WRITE : XFER_READ;
937
938 if (rw) {
939 do_pio_write(host);
940 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
941 } else {
942 enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF
943 | S3C2410_SDIIMSK_RXFIFOLAST);
944 }
945
946 return 0;
947 }
948
949 static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
950 {
951 int dma_len, i;
952 int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
953
954 BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
955
956 s3cmci_dma_setup(host, rw ? S3C2410_DMASRC_MEM : S3C2410_DMASRC_HW);
957 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
958
959 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
960 (rw) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
961
962 if (dma_len == 0)
963 return -ENOMEM;
964
965 host->dma_complete = 0;
966 host->dmatogo = dma_len;
967
968 for (i = 0; i < dma_len; i++) {
969 int res;
970
971 dbg(host, dbg_dma, "enqueue %i:%u@%u\n", i,
972 sg_dma_address(&data->sg[i]),
973 sg_dma_len(&data->sg[i]));
974
975 res = s3c2410_dma_enqueue(host->dma, (void *) host,
976 sg_dma_address(&data->sg[i]),
977 sg_dma_len(&data->sg[i]));
978
979 if (res) {
980 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
981 return -EBUSY;
982 }
983 }
984
985 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_START);
986
987 return 0;
988 }
989
990 static void s3cmci_send_request(struct mmc_host *mmc)
991 {
992 struct s3cmci_host *host = mmc_priv(mmc);
993 struct mmc_request *mrq = host->mrq;
994 struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
995
996 host->ccnt++;
997 prepare_dbgmsg(host, cmd, host->cmd_is_stop);
998
999 /* Clear command, data and fifo status registers
1000 Fifo clear only necessary on 2440, but doesn't hurt on 2410
1001 */
1002 writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT);
1003 writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA);
1004 writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA);
1005
1006 if (cmd->data) {
1007 int res = s3cmci_setup_data(host, cmd->data);
1008
1009 host->dcnt++;
1010
1011 if (res) {
1012 dbg(host, dbg_err, "setup data error %d\n", res);
1013 cmd->error = res;
1014 cmd->data->error = res;
1015
1016 mmc_request_done(mmc, mrq);
1017 return;
1018 }
1019
1020 if (host->dodma)
1021 res = s3cmci_prepare_dma(host, cmd->data);
1022 else
1023 res = s3cmci_prepare_pio(host, cmd->data);
1024
1025 if (res) {
1026 dbg(host, dbg_err, "data prepare error %d\n", res);
1027 cmd->error = res;
1028 cmd->data->error = res;
1029
1030 mmc_request_done(mmc, mrq);
1031 return;
1032 }
1033 }
1034
1035 /* Send command */
1036 s3cmci_send_command(host, cmd);
1037
1038 /* Enable Interrupt */
1039 enable_irq(host->irq);
1040 }
1041
1042 static int s3cmci_card_present(struct mmc_host *mmc)
1043 {
1044 struct s3cmci_host *host = mmc_priv(mmc);
1045 struct s3c24xx_mci_pdata *pdata = host->pdata;
1046 int ret;
1047
1048 if (pdata->gpio_detect == 0)
1049 return -ENOSYS;
1050
1051 ret = s3c2410_gpio_getpin(pdata->gpio_detect) ? 0 : 1;
1052 return ret ^ pdata->detect_invert;
1053 }
1054
1055 static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1056 {
1057 struct s3cmci_host *host = mmc_priv(mmc);
1058
1059 host->status = "mmc request";
1060 host->cmd_is_stop = 0;
1061 host->mrq = mrq;
1062
1063 if (s3cmci_card_present(mmc) == 0) {
1064 dbg(host, dbg_err, "%s: no medium present\n", __func__);
1065 host->mrq->cmd->error = -ENOMEDIUM;
1066 mmc_request_done(mmc, mrq);
1067 } else
1068 s3cmci_send_request(mmc);
1069 }
1070
1071 static void s3cmci_set_clk(struct s3cmci_host *host, struct mmc_ios *ios)
1072 {
1073 u32 mci_psc;
1074
1075 /* Set clock */
1076 for (mci_psc = 0; mci_psc < 255; mci_psc++) {
1077 host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1));
1078
1079 if (host->real_rate <= ios->clock)
1080 break;
1081 }
1082
1083 if (mci_psc > 255)
1084 mci_psc = 255;
1085
1086 host->prescaler = mci_psc;
1087 writel(host->prescaler, host->base + S3C2410_SDIPRE);
1088
1089 /* If requested clock is 0, real_rate will be 0, too */
1090 if (ios->clock == 0)
1091 host->real_rate = 0;
1092 }
1093
1094 static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1095 {
1096 struct s3cmci_host *host = mmc_priv(mmc);
1097 u32 mci_con;
1098
1099 /* Set the power state */
1100
1101 mci_con = readl(host->base + S3C2410_SDICON);
1102
1103 switch (ios->power_mode) {
1104 case MMC_POWER_ON:
1105 case MMC_POWER_UP:
1106 s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2410_GPE5_SDCLK);
1107 s3c2410_gpio_cfgpin(S3C2410_GPE6, S3C2410_GPE6_SDCMD);
1108 s3c2410_gpio_cfgpin(S3C2410_GPE7, S3C2410_GPE7_SDDAT0);
1109 s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1);
1110 s3c2410_gpio_cfgpin(S3C2410_GPE9, S3C2410_GPE9_SDDAT2);
1111 s3c2410_gpio_cfgpin(S3C2410_GPE10, S3C2410_GPE10_SDDAT3);
1112
1113 if (host->pdata->set_power)
1114 host->pdata->set_power(ios->power_mode, ios->vdd);
1115
1116 if (!host->is2440)
1117 mci_con |= S3C2410_SDICON_FIFORESET;
1118
1119 break;
1120
1121 case MMC_POWER_OFF:
1122 default:
1123 s3c2410_gpio_setpin(S3C2410_GPE5, 0);
1124 s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2410_GPE5_OUTP);
1125
1126 if (host->is2440)
1127 mci_con |= S3C2440_SDICON_SDRESET;
1128
1129 if (host->pdata->set_power)
1130 host->pdata->set_power(ios->power_mode, ios->vdd);
1131
1132 break;
1133 }
1134
1135 s3cmci_set_clk(host, ios);
1136
1137 /* Set CLOCK_ENABLE */
1138 if (ios->clock)
1139 mci_con |= S3C2410_SDICON_CLOCKTYPE;
1140 else
1141 mci_con &= ~S3C2410_SDICON_CLOCKTYPE;
1142
1143 writel(mci_con, host->base + S3C2410_SDICON);
1144
1145 if ((ios->power_mode == MMC_POWER_ON) ||
1146 (ios->power_mode == MMC_POWER_UP)) {
1147 dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n",
1148 host->real_rate/1000, ios->clock/1000);
1149 } else {
1150 dbg(host, dbg_conf, "powered down.\n");
1151 }
1152
1153 host->bus_width = ios->bus_width;
1154 }
1155
1156 static void s3cmci_reset(struct s3cmci_host *host)
1157 {
1158 u32 con = readl(host->base + S3C2410_SDICON);
1159
1160 con |= S3C2440_SDICON_SDRESET;
1161 writel(con, host->base + S3C2410_SDICON);
1162 }
1163
1164 static int s3cmci_get_ro(struct mmc_host *mmc)
1165 {
1166 struct s3cmci_host *host = mmc_priv(mmc);
1167 struct s3c24xx_mci_pdata *pdata = host->pdata;
1168 int ret;
1169
1170 if (pdata->gpio_wprotect == 0)
1171 return 0;
1172
1173 ret = s3c2410_gpio_getpin(pdata->gpio_wprotect);
1174
1175 if (pdata->wprotect_invert)
1176 ret = !ret;
1177
1178 return ret;
1179 }
1180
1181 static struct mmc_host_ops s3cmci_ops = {
1182 .request = s3cmci_request,
1183 .set_ios = s3cmci_set_ios,
1184 .get_ro = s3cmci_get_ro,
1185 .get_cd = s3cmci_card_present,
1186 };
1187
1188 static struct s3c24xx_mci_pdata s3cmci_def_pdata = {
1189 /* This is currently here to avoid a number of if (host->pdata)
1190 * checks. Any zero fields to ensure reaonable defaults are picked. */
1191 };
1192
1193 #ifdef CONFIG_CPU_FREQ
1194
1195 static int s3cmci_cpufreq_transition(struct notifier_block *nb,
1196 unsigned long val, void *data)
1197 {
1198 struct s3cmci_host *host;
1199 struct mmc_host *mmc;
1200 unsigned long newclk;
1201 unsigned long flags;
1202
1203 host = container_of(nb, struct s3cmci_host, freq_transition);
1204 newclk = clk_get_rate(host->clk);
1205 mmc = host->mmc;
1206
1207 if ((val == CPUFREQ_PRECHANGE && newclk > host->clk_rate) ||
1208 (val == CPUFREQ_POSTCHANGE && newclk < host->clk_rate)) {
1209 spin_lock_irqsave(&mmc->lock, flags);
1210
1211 host->clk_rate = newclk;
1212
1213 if (mmc->ios.power_mode != MMC_POWER_OFF &&
1214 mmc->ios.clock != 0)
1215 s3cmci_set_clk(host, &mmc->ios);
1216
1217 spin_unlock_irqrestore(&mmc->lock, flags);
1218 }
1219
1220 return 0;
1221 }
1222
1223 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1224 {
1225 host->freq_transition.notifier_call = s3cmci_cpufreq_transition;
1226
1227 return cpufreq_register_notifier(&host->freq_transition,
1228 CPUFREQ_TRANSITION_NOTIFIER);
1229 }
1230
1231 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1232 {
1233 cpufreq_unregister_notifier(&host->freq_transition,
1234 CPUFREQ_TRANSITION_NOTIFIER);
1235 }
1236
1237 #else
1238 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1239 {
1240 return 0;
1241 }
1242
1243 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1244 {
1245 }
1246 #endif
1247
1248 static int __devinit s3cmci_probe(struct platform_device *pdev, int is2440)
1249 {
1250 struct s3cmci_host *host;
1251 struct mmc_host *mmc;
1252 int ret;
1253
1254 mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev);
1255 if (!mmc) {
1256 ret = -ENOMEM;
1257 goto probe_out;
1258 }
1259
1260 host = mmc_priv(mmc);
1261 host->mmc = mmc;
1262 host->pdev = pdev;
1263 host->is2440 = is2440;
1264
1265 host->pdata = pdev->dev.platform_data;
1266 if (!host->pdata) {
1267 pdev->dev.platform_data = &s3cmci_def_pdata;
1268 host->pdata = &s3cmci_def_pdata;
1269 }
1270
1271 spin_lock_init(&host->complete_lock);
1272 tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
1273
1274 if (is2440) {
1275 host->sdiimsk = S3C2440_SDIIMSK;
1276 host->sdidata = S3C2440_SDIDATA;
1277 host->clk_div = 1;
1278 } else {
1279 host->sdiimsk = S3C2410_SDIIMSK;
1280 host->sdidata = S3C2410_SDIDATA;
1281 host->clk_div = 2;
1282 }
1283
1284 host->dodma = 0;
1285 host->complete_what = COMPLETION_NONE;
1286 host->pio_active = XFER_NONE;
1287
1288 host->dma = S3CMCI_DMA;
1289
1290 host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1291 if (!host->mem) {
1292 dev_err(&pdev->dev,
1293 "failed to get io memory region resouce.\n");
1294
1295 ret = -ENOENT;
1296 goto probe_free_host;
1297 }
1298
1299 host->mem = request_mem_region(host->mem->start,
1300 RESSIZE(host->mem), pdev->name);
1301
1302 if (!host->mem) {
1303 dev_err(&pdev->dev, "failed to request io memory region.\n");
1304 ret = -ENOENT;
1305 goto probe_free_host;
1306 }
1307
1308 host->base = ioremap(host->mem->start, RESSIZE(host->mem));
1309 if (!host->base) {
1310 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
1311 ret = -EINVAL;
1312 goto probe_free_mem_region;
1313 }
1314
1315 host->irq = platform_get_irq(pdev, 0);
1316 if (host->irq == 0) {
1317 dev_err(&pdev->dev, "failed to get interrupt resouce.\n");
1318 ret = -EINVAL;
1319 goto probe_iounmap;
1320 }
1321
1322 if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) {
1323 dev_err(&pdev->dev, "failed to request mci interrupt.\n");
1324 ret = -ENOENT;
1325 goto probe_iounmap;
1326 }
1327
1328 /* We get spurious interrupts even when we have set the IMSK
1329 * register to ignore everything, so use disable_irq() to make
1330 * ensure we don't lock the system with un-serviceable requests. */
1331
1332 disable_irq(host->irq);
1333
1334 host->irq_cd = s3c2410_gpio_getirq(host->pdata->gpio_detect);
1335
1336 if (host->irq_cd >= 0) {
1337 if (request_irq(host->irq_cd, s3cmci_irq_cd,
1338 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
1339 DRIVER_NAME, host)) {
1340 dev_err(&pdev->dev, "can't get card detect irq.\n");
1341 ret = -ENOENT;
1342 goto probe_free_irq;
1343 }
1344 } else {
1345 dev_warn(&pdev->dev, "host detect has no irq available\n");
1346 s3c2410_gpio_cfgpin(host->pdata->gpio_detect,
1347 S3C2410_GPIO_INPUT);
1348 }
1349
1350 if (host->pdata->gpio_wprotect)
1351 s3c2410_gpio_cfgpin(host->pdata->gpio_wprotect,
1352 S3C2410_GPIO_INPUT);
1353
1354 if (s3c2410_dma_request(S3CMCI_DMA, &s3cmci_dma_client, NULL) < 0) {
1355 dev_err(&pdev->dev, "unable to get DMA channel.\n");
1356 ret = -EBUSY;
1357 goto probe_free_irq_cd;
1358 }
1359
1360 host->clk = clk_get(&pdev->dev, "sdi");
1361 if (IS_ERR(host->clk)) {
1362 dev_err(&pdev->dev, "failed to find clock source.\n");
1363 ret = PTR_ERR(host->clk);
1364 host->clk = NULL;
1365 goto probe_free_host;
1366 }
1367
1368 ret = clk_enable(host->clk);
1369 if (ret) {
1370 dev_err(&pdev->dev, "failed to enable clock source.\n");
1371 goto clk_free;
1372 }
1373
1374 host->clk_rate = clk_get_rate(host->clk);
1375
1376 mmc->ops = &s3cmci_ops;
1377 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1378 mmc->caps = MMC_CAP_4_BIT_DATA;
1379 mmc->f_min = host->clk_rate / (host->clk_div * 256);
1380 mmc->f_max = host->clk_rate / host->clk_div;
1381
1382 if (host->pdata->ocr_avail)
1383 mmc->ocr_avail = host->pdata->ocr_avail;
1384
1385 mmc->max_blk_count = 4095;
1386 mmc->max_blk_size = 4095;
1387 mmc->max_req_size = 4095 * 512;
1388 mmc->max_seg_size = mmc->max_req_size;
1389
1390 mmc->max_phys_segs = 128;
1391 mmc->max_hw_segs = 128;
1392
1393 dbg(host, dbg_debug,
1394 "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%u.\n",
1395 (host->is2440?"2440":""),
1396 host->base, host->irq, host->irq_cd, host->dma);
1397
1398 ret = s3cmci_cpufreq_register(host);
1399 if (ret) {
1400 dev_err(&pdev->dev, "failed to register cpufreq\n");
1401 goto free_dmabuf;
1402 }
1403
1404 ret = mmc_add_host(mmc);
1405 if (ret) {
1406 dev_err(&pdev->dev, "failed to add mmc host.\n");
1407 goto free_cpufreq;
1408 }
1409
1410 platform_set_drvdata(pdev, mmc);
1411 dev_info(&pdev->dev, "initialisation done.\n");
1412
1413 return 0;
1414
1415 free_cpufreq:
1416 s3cmci_cpufreq_deregister(host);
1417
1418 free_dmabuf:
1419 clk_disable(host->clk);
1420
1421 clk_free:
1422 clk_put(host->clk);
1423
1424 probe_free_irq_cd:
1425 if (host->irq_cd >= 0)
1426 free_irq(host->irq_cd, host);
1427
1428 probe_free_irq:
1429 free_irq(host->irq, host);
1430
1431 probe_iounmap:
1432 iounmap(host->base);
1433
1434 probe_free_mem_region:
1435 release_mem_region(host->mem->start, RESSIZE(host->mem));
1436
1437 probe_free_host:
1438 mmc_free_host(mmc);
1439 probe_out:
1440 return ret;
1441 }
1442
1443 static void s3cmci_shutdown(struct platform_device *pdev)
1444 {
1445 struct mmc_host *mmc = platform_get_drvdata(pdev);
1446 struct s3cmci_host *host = mmc_priv(mmc);
1447
1448 if (host->irq_cd >= 0)
1449 free_irq(host->irq_cd, host);
1450
1451 s3cmci_cpufreq_deregister(host);
1452 mmc_remove_host(mmc);
1453 clk_disable(host->clk);
1454 }
1455
1456 static int __devexit s3cmci_remove(struct platform_device *pdev)
1457 {
1458 struct mmc_host *mmc = platform_get_drvdata(pdev);
1459 struct s3cmci_host *host = mmc_priv(mmc);
1460
1461 s3cmci_shutdown(pdev);
1462
1463 clk_put(host->clk);
1464
1465 tasklet_disable(&host->pio_tasklet);
1466 s3c2410_dma_free(S3CMCI_DMA, &s3cmci_dma_client);
1467
1468 free_irq(host->irq, host);
1469
1470 iounmap(host->base);
1471 release_mem_region(host->mem->start, RESSIZE(host->mem));
1472
1473 mmc_free_host(mmc);
1474 return 0;
1475 }
1476
1477 static int __devinit s3cmci_2410_probe(struct platform_device *dev)
1478 {
1479 return s3cmci_probe(dev, 0);
1480 }
1481
1482 static int __devinit s3cmci_2412_probe(struct platform_device *dev)
1483 {
1484 return s3cmci_probe(dev, 1);
1485 }
1486
1487 static int __devinit s3cmci_2440_probe(struct platform_device *dev)
1488 {
1489 return s3cmci_probe(dev, 1);
1490 }
1491
1492 #ifdef CONFIG_PM
1493
1494 static int s3cmci_suspend(struct platform_device *dev, pm_message_t state)
1495 {
1496 struct mmc_host *mmc = platform_get_drvdata(dev);
1497
1498 return mmc_suspend_host(mmc, state);
1499 }
1500
1501 static int s3cmci_resume(struct platform_device *dev)
1502 {
1503 struct mmc_host *mmc = platform_get_drvdata(dev);
1504
1505 return mmc_resume_host(mmc);
1506 }
1507
1508 #else /* CONFIG_PM */
1509 #define s3cmci_suspend NULL
1510 #define s3cmci_resume NULL
1511 #endif /* CONFIG_PM */
1512
1513
1514 static struct platform_driver s3cmci_2410_driver = {
1515 .driver.name = "s3c2410-sdi",
1516 .driver.owner = THIS_MODULE,
1517 .probe = s3cmci_2410_probe,
1518 .remove = __devexit_p(s3cmci_remove),
1519 .shutdown = s3cmci_shutdown,
1520 .suspend = s3cmci_suspend,
1521 .resume = s3cmci_resume,
1522 };
1523
1524 static struct platform_driver s3cmci_2412_driver = {
1525 .driver.name = "s3c2412-sdi",
1526 .driver.owner = THIS_MODULE,
1527 .probe = s3cmci_2412_probe,
1528 .remove = __devexit_p(s3cmci_remove),
1529 .shutdown = s3cmci_shutdown,
1530 .suspend = s3cmci_suspend,
1531 .resume = s3cmci_resume,
1532 };
1533
1534 static struct platform_driver s3cmci_2440_driver = {
1535 .driver.name = "s3c2440-sdi",
1536 .driver.owner = THIS_MODULE,
1537 .probe = s3cmci_2440_probe,
1538 .remove = __devexit_p(s3cmci_remove),
1539 .shutdown = s3cmci_shutdown,
1540 .suspend = s3cmci_suspend,
1541 .resume = s3cmci_resume,
1542 };
1543
1544
1545 static int __init s3cmci_init(void)
1546 {
1547 platform_driver_register(&s3cmci_2410_driver);
1548 platform_driver_register(&s3cmci_2412_driver);
1549 platform_driver_register(&s3cmci_2440_driver);
1550 return 0;
1551 }
1552
1553 static void __exit s3cmci_exit(void)
1554 {
1555 platform_driver_unregister(&s3cmci_2410_driver);
1556 platform_driver_unregister(&s3cmci_2412_driver);
1557 platform_driver_unregister(&s3cmci_2440_driver);
1558 }
1559
1560 module_init(s3cmci_init);
1561 module_exit(s3cmci_exit);
1562
1563 MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
1564 MODULE_LICENSE("GPL v2");
1565 MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>");
1566 MODULE_ALIAS("platform:s3c2410-sdi");
1567 MODULE_ALIAS("platform:s3c2412-sdi");
1568 MODULE_ALIAS("platform:s3c2440-sdi");
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