arch/powerpc/mm/ppc_mmu_32.c

   1 /*
   2  * This file contains the routines for handling the MMU on those
   3  * PowerPC implementations where the MMU substantially follows the
   4  * architecture specification.  This includes the 6xx, 7xx, 7xxx,
   5  * 8260, and POWER3 implementations but excludes the 8xx and 4xx.
   6  *  -- paulus
   7  *
   8  *  Derived from arch/ppc/mm/init.c:
   9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  10  *
  11  *  Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
  12  *  and Cort Dougan (PReP) (cort@cs.nmt.edu)
  13  *    Copyright (C) 1996 Paul Mackerras
  14  *
  15  *  Derived from "arch/i386/mm/init.c"
  16  *    Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
  17  *
  18  *  This program is free software; you can redistribute it and/or
  19  *  modify it under the terms of the GNU General Public License
  20  *  as published by the Free Software Foundation; either version
  21  *  2 of the License, or (at your option) any later version.
  22  *
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/init.h>
  28 #include <linux/highmem.h>
  29 #include <linux/lmb.h>
  30
  31 #include <asm/prom.h>
  32 #include <asm/mmu.h>
  33 #include <asm/machdep.h>
  34
  35 #include "mmu_decl.h"
  36
  37 struct hash_pte *Hash, *Hash_end;
  38 unsigned long Hash_size, Hash_mask;
  39 unsigned long _SDR1;
  40
  41 struct ppc_bat BATS[8][2];      /* 8 pairs of IBAT, DBAT */
  42
  43 struct batrange {               /* stores address ranges mapped by BATs */
  44         unsigned long start;
  45         unsigned long limit;
  46         phys_addr_t phys;
  47 } bat_addrs[8];
  48
  49 /*
  50  * Return PA for this VA if it is mapped by a BAT, or 0
  51  */
  52 phys_addr_t v_mapped_by_bats(unsigned long va)
  53 {
  54         int b;
  55         for (b = 0; b < 4; ++b)
  56                 if (va >= bat_addrs[b].start && va < bat_addrs[b].limit)
  57                         return bat_addrs[b].phys + (va - bat_addrs[b].start);
  58         return 0;
  59 }
  60
  61 /*
  62  * Return VA for a given PA or 0 if not mapped
  63  */
  64 unsigned long p_mapped_by_bats(phys_addr_t pa)
  65 {
  66         int b;
  67         for (b = 0; b < 4; ++b)
  68                 if (pa >= bat_addrs[b].phys
  69                     && pa < (bat_addrs[b].limit-bat_addrs[b].start)
  70                               +bat_addrs[b].phys)
  71                         return bat_addrs[b].start+(pa-bat_addrs[b].phys);
  72         return 0;
  73 }
  74
  75 unsigned long __init mmu_mapin_ram(void)
  76 {
  77 #ifdef CONFIG_POWER4
  78         return 0;
  79 #else
  80         unsigned long tot, bl, done;
  81         unsigned long max_size = (256<<20);
  82
  83         if (__map_without_bats) {
  84                 printk(KERN_DEBUG "RAM mapped without BATs\n");
  85                 return 0;
  86         }
  87
  88         /* Set up BAT2 and if necessary BAT3 to cover RAM. */
  89
  90         /* Make sure we don't map a block larger than the
  91            smallest alignment of the physical address. */
  92         tot = total_lowmem;
  93         for (bl = 128<<10; bl < max_size; bl <<= 1) {
  94                 if (bl * 2 > tot)
  95                         break;
  96         }
  97
  98         setbat(2, PAGE_OFFSET, 0, bl, _PAGE_RAM);
  99         done = (unsigned long)bat_addrs[2].limit - PAGE_OFFSET + 1;
 100         if ((done < tot) && !bat_addrs[3].limit) {
 101                 /* use BAT3 to cover a bit more */
 102                 tot -= done;
 103                 for (bl = 128<<10; bl < max_size; bl <<= 1)
 104                         if (bl * 2 > tot)
 105                                 break;
 106                 setbat(3, PAGE_OFFSET+done, done, bl, _PAGE_RAM);
 107                 done = (unsigned long)bat_addrs[3].limit - PAGE_OFFSET + 1;
 108         }
 109
 110         return done;
 111 #endif
 112 }
 113
 114 /*
 115  * Set up one of the I/D BAT (block address translation) register pairs.
 116  * The parameters are not checked; in particular size must be a power
 117  * of 2 between 128k and 256M.
 118  */
 119 void __init setbat(int index, unsigned long virt, phys_addr_t phys,
 120                    unsigned int size, int flags)
 121 {
 122         unsigned int bl;
 123         int wimgxpp;
 124         struct ppc_bat *bat = BATS[index];
 125
 126         if ((flags & _PAGE_NO_CACHE) ||
 127             (cpu_has_feature(CPU_FTR_NEED_COHERENT) == 0))
 128                 flags &= ~_PAGE_COHERENT;
 129
 130         bl = (size >> 17) - 1;
 131         if (PVR_VER(mfspr(SPRN_PVR)) != 1) {
 132                 /* 603, 604, etc. */
 133                 /* Do DBAT first */
 134                 wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE
 135                                    | _PAGE_COHERENT | _PAGE_GUARDED);
 136                 wimgxpp |= (flags & _PAGE_RW)? BPP_RW: BPP_RX;
 137                 bat[1].batu = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */
 138                 bat[1].batl = BAT_PHYS_ADDR(phys) | wimgxpp;
 139 #ifndef CONFIG_KGDB /* want user access for breakpoints */
 140                 if (flags & _PAGE_USER)
 141 #endif
 142                         bat[1].batu |= 1;       /* Vp = 1 */
 143                 if (flags & _PAGE_GUARDED) {
 144                         /* G bit must be zero in IBATs */
 145                         bat[0].batu = bat[0].batl = 0;
 146                 } else {
 147                         /* make IBAT same as DBAT */
 148                         bat[0] = bat[1];
 149                 }
 150         } else {
 151                 /* 601 cpu */
 152                 if (bl > BL_8M)
 153                         bl = BL_8M;
 154                 wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE
 155                                    | _PAGE_COHERENT);
 156                 wimgxpp |= (flags & _PAGE_RW)?
 157                         ((flags & _PAGE_USER)? PP_RWRW: PP_RWXX): PP_RXRX;
 158                 bat->batu = virt | wimgxpp | 4; /* Ks=0, Ku=1 */
 159                 bat->batl = phys | bl | 0x40;   /* V=1 */
 160         }
 161
 162         bat_addrs[index].start = virt;
 163         bat_addrs[index].limit = virt + ((bl + 1) << 17) - 1;
 164         bat_addrs[index].phys = phys;
 165 }
 166
 167 /*
 168  * Preload a translation in the hash table
 169  */
 170 void hash_preload(struct mm_struct *mm, unsigned long ea,
 171                   unsigned long access, unsigned long trap)
 172 {
 173         pmd_t *pmd;
 174
 175         if (Hash == 0)
 176                 return;
 177         pmd = pmd_offset(pud_offset(pgd_offset(mm, ea), ea), ea);
 178         if (!pmd_none(*pmd))
 179                 add_hash_page(mm->context.id, ea, pmd_val(*pmd));
 180 }
 181
 182 /*
 183  * Initialize the hash table and patch the instructions in hashtable.S.
 184  */
 185 void __init MMU_init_hw(void)
 186 {
 187         unsigned int hmask, mb, mb2;
 188         unsigned int n_hpteg, lg_n_hpteg;
 189
 190         extern unsigned int hash_page_patch_A[];
 191         extern unsigned int hash_page_patch_B[], hash_page_patch_C[];
 192         extern unsigned int hash_page[];
 193         extern unsigned int flush_hash_patch_A[], flush_hash_patch_B[];
 194
 195         if (!mmu_has_feature(MMU_FTR_HPTE_TABLE)) {
 196                 /*
 197                  * Put a blr (procedure return) instruction at the
 198                  * start of hash_page, since we can still get DSI
 199                  * exceptions on a 603.
 200                  */
 201                 hash_page[0] = 0x4e800020;
 202                 flush_icache_range((unsigned long) &hash_page[0],
 203                                    (unsigned long) &hash_page[1]);
 204                 return;
 205         }
 206
 207         if ( ppc_md.progress ) ppc_md.progress("hash:enter", 0x105);
 208
 209 #define LG_HPTEG_SIZE   6               /* 64 bytes per HPTEG */
 210 #define SDR1_LOW_BITS   ((n_hpteg - 1) >> 10)
 211 #define MIN_N_HPTEG     1024            /* min 64kB hash table */
 212
 213         /*
 214          * Allow 1 HPTE (1/8 HPTEG) for each page of memory.
 215          * This is less than the recommended amount, but then
 216          * Linux ain't AIX.
 217          */
 218         n_hpteg = total_memory / (PAGE_SIZE * 8);
 219         if (n_hpteg < MIN_N_HPTEG)
 220                 n_hpteg = MIN_N_HPTEG;
 221         lg_n_hpteg = __ilog2(n_hpteg);
 222         if (n_hpteg & (n_hpteg - 1)) {
 223                 ++lg_n_hpteg;           /* round up if not power of 2 */
 224                 n_hpteg = 1 << lg_n_hpteg;
 225         }
 226         Hash_size = n_hpteg << LG_HPTEG_SIZE;
 227
 228         /*
 229          * Find some memory for the hash table.
 230          */
 231         if ( ppc_md.progress ) ppc_md.progress("hash:find piece", 0x322);
 232         Hash = __va(lmb_alloc_base(Hash_size, Hash_size,
 233                                    __initial_memory_limit_addr));
 234         cacheable_memzero(Hash, Hash_size);
 235         _SDR1 = __pa(Hash) | SDR1_LOW_BITS;
 236
 237         Hash_end = (struct hash_pte *) ((unsigned long)Hash + Hash_size);
 238
 239         printk("Total memory = %lldMB; using %ldkB for hash table (at %p)\n",
 240                (unsigned long long)(total_memory >> 20), Hash_size >> 10, Hash);
 241
 242
 243         /*
 244          * Patch up the instructions in hashtable.S:create_hpte
 245          */
 246         if ( ppc_md.progress ) ppc_md.progress("hash:patch", 0x345);
 247         Hash_mask = n_hpteg - 1;
 248         hmask = Hash_mask >> (16 - LG_HPTEG_SIZE);
 249         mb2 = mb = 32 - LG_HPTEG_SIZE - lg_n_hpteg;
 250         if (lg_n_hpteg > 16)
 251                 mb2 = 16 - LG_HPTEG_SIZE;
 252
 253         hash_page_patch_A[0] = (hash_page_patch_A[0] & ~0xffff)
 254                 | ((unsigned int)(Hash) >> 16);
 255         hash_page_patch_A[1] = (hash_page_patch_A[1] & ~0x7c0) | (mb << 6);
 256         hash_page_patch_A[2] = (hash_page_patch_A[2] & ~0x7c0) | (mb2 << 6);
 257         hash_page_patch_B[0] = (hash_page_patch_B[0] & ~0xffff) | hmask;
 258         hash_page_patch_C[0] = (hash_page_patch_C[0] & ~0xffff) | hmask;
 259
 260         /*
 261          * Ensure that the locations we've patched have been written
 262          * out from the data cache and invalidated in the instruction
 263          * cache, on those machines with split caches.
 264          */
 265         flush_icache_range((unsigned long) &hash_page_patch_A[0],
 266                            (unsigned long) &hash_page_patch_C[1]);
 267
 268         /*
 269          * Patch up the instructions in hashtable.S:flush_hash_page
 270          */
 271         flush_hash_patch_A[0] = (flush_hash_patch_A[0] & ~0xffff)
 272                 | ((unsigned int)(Hash) >> 16);
 273         flush_hash_patch_A[1] = (flush_hash_patch_A[1] & ~0x7c0) | (mb << 6);
 274         flush_hash_patch_A[2] = (flush_hash_patch_A[2] & ~0x7c0) | (mb2 << 6);
 275         flush_hash_patch_B[0] = (flush_hash_patch_B[0] & ~0xffff) | hmask;
 276         flush_icache_range((unsigned long) &flush_hash_patch_A[0],
 277                            (unsigned long) &flush_hash_patch_B[1]);
 278
 279         if ( ppc_md.progress ) ppc_md.progress("hash:done", 0x205);
 280 }