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MERGE-master-patchset-edits
[linux-2.6/openmoko-kernel.git] / arch / arm / plat-omap / dma.c
blobe77373c39f8c8a3ac76cab7b4f5c336a02ecd947
1 /*
2 * linux/arch/arm/plat-omap/dma.c
3 *
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12 *
13 * Support functions for the OMAP internal DMA channels.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 *
19 */
20
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/sched.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
28 #include <linux/io.h>
29
30 #include <asm/system.h>
31 #include <mach/hardware.h>
32 #include <mach/dma.h>
33
34 #include <mach/tc.h>
35
36 #undef DEBUG
37
38 #ifndef CONFIG_ARCH_OMAP1
39 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
40 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
41 };
42
43 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
44 #endif
45
46 #define OMAP_DMA_ACTIVE 0x01
47 #define OMAP_DMA_CCR_EN (1 << 7)
48 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
49
50 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
51
52 static int enable_1510_mode;
53
54 struct omap_dma_lch {
55 int next_lch;
56 int dev_id;
57 u16 saved_csr;
58 u16 enabled_irqs;
59 const char *dev_name;
60 void (*callback)(int lch, u16 ch_status, void *data);
61 void *data;
62
63 #ifndef CONFIG_ARCH_OMAP1
64 /* required for Dynamic chaining */
65 int prev_linked_ch;
66 int next_linked_ch;
67 int state;
68 int chain_id;
69
70 int status;
71 #endif
72 long flags;
73 };
74
75 struct dma_link_info {
76 int *linked_dmach_q;
77 int no_of_lchs_linked;
78
79 int q_count;
80 int q_tail;
81 int q_head;
82
83 int chain_state;
84 int chain_mode;
85
86 };
87
88 static struct dma_link_info *dma_linked_lch;
89
90 #ifndef CONFIG_ARCH_OMAP1
91
92 /* Chain handling macros */
93 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
94 do { \
95 dma_linked_lch[chain_id].q_head = \
96 dma_linked_lch[chain_id].q_tail = \
97 dma_linked_lch[chain_id].q_count = 0; \
98 } while (0)
99 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
100 (dma_linked_lch[chain_id].no_of_lchs_linked == \
101 dma_linked_lch[chain_id].q_count)
102 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
103 do { \
104 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
105 dma_linked_lch[chain_id].q_count) \
106 } while (0)
107 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
108 (0 == dma_linked_lch[chain_id].q_count)
109 #define __OMAP_DMA_CHAIN_INCQ(end) \
110 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
111 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
112 do { \
113 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
114 dma_linked_lch[chain_id].q_count--; \
115 } while (0)
116
117 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
118 do { \
119 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
120 dma_linked_lch[chain_id].q_count++; \
121 } while (0)
122 #endif
123
124 static int dma_lch_count;
125 static int dma_chan_count;
126
127 static spinlock_t dma_chan_lock;
128 static struct omap_dma_lch *dma_chan;
129 static void __iomem *omap_dma_base;
130
131 static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
132 INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
133 INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
134 INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
135 INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
136 INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
137 };
138
139 static inline void disable_lnk(int lch);
140 static void omap_disable_channel_irq(int lch);
141 static inline void omap_enable_channel_irq(int lch);
142
143 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
144 __func__);
145
146 #define dma_read(reg) \
147 ({ \
148 u32 __val; \
149 if (cpu_class_is_omap1()) \
150 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg); \
151 else \
152 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg); \
153 __val; \
154 })
155
156 #define dma_write(val, reg) \
157 ({ \
158 if (cpu_class_is_omap1()) \
159 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
160 else \
161 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg); \
162 })
163
164 #ifdef CONFIG_ARCH_OMAP15XX
165 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
166 int omap_dma_in_1510_mode(void)
167 {
168 return enable_1510_mode;
169 }
170 #else
171 #define omap_dma_in_1510_mode() 0
172 #endif
173
174 #ifdef CONFIG_ARCH_OMAP1
175 static inline int get_gdma_dev(int req)
176 {
177 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
178 int shift = ((req - 1) % 5) * 6;
179
180 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
181 }
182
183 static inline void set_gdma_dev(int req, int dev)
184 {
185 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
186 int shift = ((req - 1) % 5) * 6;
187 u32 l;
188
189 l = omap_readl(reg);
190 l &= ~(0x3f << shift);
191 l |= (dev - 1) << shift;
192 omap_writel(l, reg);
193 }
194 #else
195 #define set_gdma_dev(req, dev) do {} while (0)
196 #endif
197
198 /* Omap1 only */
199 static void clear_lch_regs(int lch)
200 {
201 int i;
202 void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
203
204 for (i = 0; i < 0x2c; i += 2)
205 __raw_writew(0, lch_base + i);
206 }
207
208 void omap_set_dma_priority(int lch, int dst_port, int priority)
209 {
210 unsigned long reg;
211 u32 l;
212
213 if (cpu_class_is_omap1()) {
214 switch (dst_port) {
215 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
216 reg = OMAP_TC_OCPT1_PRIOR;
217 break;
218 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
219 reg = OMAP_TC_OCPT2_PRIOR;
220 break;
221 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
222 reg = OMAP_TC_EMIFF_PRIOR;
223 break;
224 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
225 reg = OMAP_TC_EMIFS_PRIOR;
226 break;
227 default:
228 BUG();
229 return;
230 }
231 l = omap_readl(reg);
232 l &= ~(0xf << 8);
233 l |= (priority & 0xf) << 8;
234 omap_writel(l, reg);
235 }
236
237 if (cpu_class_is_omap2()) {
238 u32 ccr;
239
240 ccr = dma_read(CCR(lch));
241 if (priority)
242 ccr |= (1 << 6);
243 else
244 ccr &= ~(1 << 6);
245 dma_write(ccr, CCR(lch));
246 }
247 }
248 EXPORT_SYMBOL(omap_set_dma_priority);
249
250 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
251 int frame_count, int sync_mode,
252 int dma_trigger, int src_or_dst_synch)
253 {
254 u32 l;
255
256 l = dma_read(CSDP(lch));
257 l &= ~0x03;
258 l |= data_type;
259 dma_write(l, CSDP(lch));
260
261 if (cpu_class_is_omap1()) {
262 u16 ccr;
263
264 ccr = dma_read(CCR(lch));
265 ccr &= ~(1 << 5);
266 if (sync_mode == OMAP_DMA_SYNC_FRAME)
267 ccr |= 1 << 5;
268 dma_write(ccr, CCR(lch));
269
270 ccr = dma_read(CCR2(lch));
271 ccr &= ~(1 << 2);
272 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
273 ccr |= 1 << 2;
274 dma_write(ccr, CCR2(lch));
275 }
276
277 if (cpu_class_is_omap2() && dma_trigger) {
278 u32 val;
279
280 val = dma_read(CCR(lch));
281
282 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
283 val &= ~((3 << 19) | 0x1f);
284 val |= (dma_trigger & ~0x1f) << 14;
285 val |= dma_trigger & 0x1f;
286
287 if (sync_mode & OMAP_DMA_SYNC_FRAME)
288 val |= 1 << 5;
289 else
290 val &= ~(1 << 5);
291
292 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
293 val |= 1 << 18;
294 else
295 val &= ~(1 << 18);
296
297 if (src_or_dst_synch)
298 val |= 1 << 24; /* source synch */
299 else
300 val &= ~(1 << 24); /* dest synch */
301
302 dma_write(val, CCR(lch));
303 }
304
305 dma_write(elem_count, CEN(lch));
306 dma_write(frame_count, CFN(lch));
307 }
308 EXPORT_SYMBOL(omap_set_dma_transfer_params);
309
310 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
311 {
312 u16 w;
313
314 BUG_ON(omap_dma_in_1510_mode());
315
316 if (cpu_class_is_omap2()) {
317 REVISIT_24XX();
318 return;
319 }
320
321 w = dma_read(CCR2(lch));
322 w &= ~0x03;
323
324 switch (mode) {
325 case OMAP_DMA_CONSTANT_FILL:
326 w |= 0x01;
327 break;
328 case OMAP_DMA_TRANSPARENT_COPY:
329 w |= 0x02;
330 break;
331 case OMAP_DMA_COLOR_DIS:
332 break;
333 default:
334 BUG();
335 }
336 dma_write(w, CCR2(lch));
337
338 w = dma_read(LCH_CTRL(lch));
339 w &= ~0x0f;
340 /* Default is channel type 2D */
341 if (mode) {
342 dma_write((u16)color, COLOR_L(lch));
343 dma_write((u16)(color >> 16), COLOR_U(lch));
344 w |= 1; /* Channel type G */
345 }
346 dma_write(w, LCH_CTRL(lch));
347 }
348 EXPORT_SYMBOL(omap_set_dma_color_mode);
349
350 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
351 {
352 if (cpu_class_is_omap2()) {
353 u32 csdp;
354
355 csdp = dma_read(CSDP(lch));
356 csdp &= ~(0x3 << 16);
357 csdp |= (mode << 16);
358 dma_write(csdp, CSDP(lch));
359 }
360 }
361 EXPORT_SYMBOL(omap_set_dma_write_mode);
362
363 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
364 {
365 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
366 u32 l;
367
368 l = dma_read(LCH_CTRL(lch));
369 l &= ~0x7;
370 l |= mode;
371 dma_write(l, LCH_CTRL(lch));
372 }
373 }
374 EXPORT_SYMBOL(omap_set_dma_channel_mode);
375
376 /* Note that src_port is only for omap1 */
377 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
378 unsigned long src_start,
379 int src_ei, int src_fi)
380 {
381 u32 l;
382
383 if (cpu_class_is_omap1()) {
384 u16 w;
385
386 w = dma_read(CSDP(lch));
387 w &= ~(0x1f << 2);
388 w |= src_port << 2;
389 dma_write(w, CSDP(lch));
390 }
391
392 l = dma_read(CCR(lch));
393 l &= ~(0x03 << 12);
394 l |= src_amode << 12;
395 dma_write(l, CCR(lch));
396
397 if (cpu_class_is_omap1()) {
398 dma_write(src_start >> 16, CSSA_U(lch));
399 dma_write((u16)src_start, CSSA_L(lch));
400 }
401
402 if (cpu_class_is_omap2())
403 dma_write(src_start, CSSA(lch));
404
405 dma_write(src_ei, CSEI(lch));
406 dma_write(src_fi, CSFI(lch));
407 }
408 EXPORT_SYMBOL(omap_set_dma_src_params);
409
410 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
411 {
412 omap_set_dma_transfer_params(lch, params->data_type,
413 params->elem_count, params->frame_count,
414 params->sync_mode, params->trigger,
415 params->src_or_dst_synch);
416 omap_set_dma_src_params(lch, params->src_port,
417 params->src_amode, params->src_start,
418 params->src_ei, params->src_fi);
419
420 omap_set_dma_dest_params(lch, params->dst_port,
421 params->dst_amode, params->dst_start,
422 params->dst_ei, params->dst_fi);
423 if (params->read_prio || params->write_prio)
424 omap_dma_set_prio_lch(lch, params->read_prio,
425 params->write_prio);
426 }
427 EXPORT_SYMBOL(omap_set_dma_params);
428
429 void omap_set_dma_src_index(int lch, int eidx, int fidx)
430 {
431 if (cpu_class_is_omap2())
432 return;
433
434 dma_write(eidx, CSEI(lch));
435 dma_write(fidx, CSFI(lch));
436 }
437 EXPORT_SYMBOL(omap_set_dma_src_index);
438
439 void omap_set_dma_src_data_pack(int lch, int enable)
440 {
441 u32 l;
442
443 l = dma_read(CSDP(lch));
444 l &= ~(1 << 6);
445 if (enable)
446 l |= (1 << 6);
447 dma_write(l, CSDP(lch));
448 }
449 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
450
451 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
452 {
453 unsigned int burst = 0;
454 u32 l;
455
456 l = dma_read(CSDP(lch));
457 l &= ~(0x03 << 7);
458
459 switch (burst_mode) {
460 case OMAP_DMA_DATA_BURST_DIS:
461 break;
462 case OMAP_DMA_DATA_BURST_4:
463 if (cpu_class_is_omap2())
464 burst = 0x1;
465 else
466 burst = 0x2;
467 break;
468 case OMAP_DMA_DATA_BURST_8:
469 if (cpu_class_is_omap2()) {
470 burst = 0x2;
471 break;
472 }
473 /* not supported by current hardware on OMAP1
474 * w |= (0x03 << 7);
475 * fall through
476 */
477 case OMAP_DMA_DATA_BURST_16:
478 if (cpu_class_is_omap2()) {
479 burst = 0x3;
480 break;
481 }
482 /* OMAP1 don't support burst 16
483 * fall through
484 */
485 default:
486 BUG();
487 }
488
489 l |= (burst << 7);
490 dma_write(l, CSDP(lch));
491 }
492 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
493
494 /* Note that dest_port is only for OMAP1 */
495 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
496 unsigned long dest_start,
497 int dst_ei, int dst_fi)
498 {
499 u32 l;
500
501 if (cpu_class_is_omap1()) {
502 l = dma_read(CSDP(lch));
503 l &= ~(0x1f << 9);
504 l |= dest_port << 9;
505 dma_write(l, CSDP(lch));
506 }
507
508 l = dma_read(CCR(lch));
509 l &= ~(0x03 << 14);
510 l |= dest_amode << 14;
511 dma_write(l, CCR(lch));
512
513 if (cpu_class_is_omap1()) {
514 dma_write(dest_start >> 16, CDSA_U(lch));
515 dma_write(dest_start, CDSA_L(lch));
516 }
517
518 if (cpu_class_is_omap2())
519 dma_write(dest_start, CDSA(lch));
520
521 dma_write(dst_ei, CDEI(lch));
522 dma_write(dst_fi, CDFI(lch));
523 }
524 EXPORT_SYMBOL(omap_set_dma_dest_params);
525
526 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
527 {
528 if (cpu_class_is_omap2())
529 return;
530
531 dma_write(eidx, CDEI(lch));
532 dma_write(fidx, CDFI(lch));
533 }
534 EXPORT_SYMBOL(omap_set_dma_dest_index);
535
536 void omap_set_dma_dest_data_pack(int lch, int enable)
537 {
538 u32 l;
539
540 l = dma_read(CSDP(lch));
541 l &= ~(1 << 13);
542 if (enable)
543 l |= 1 << 13;
544 dma_write(l, CSDP(lch));
545 }
546 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
547
548 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
549 {
550 unsigned int burst = 0;
551 u32 l;
552
553 l = dma_read(CSDP(lch));
554 l &= ~(0x03 << 14);
555
556 switch (burst_mode) {
557 case OMAP_DMA_DATA_BURST_DIS:
558 break;
559 case OMAP_DMA_DATA_BURST_4:
560 if (cpu_class_is_omap2())
561 burst = 0x1;
562 else
563 burst = 0x2;
564 break;
565 case OMAP_DMA_DATA_BURST_8:
566 if (cpu_class_is_omap2())
567 burst = 0x2;
568 else
569 burst = 0x3;
570 break;
571 case OMAP_DMA_DATA_BURST_16:
572 if (cpu_class_is_omap2()) {
573 burst = 0x3;
574 break;
575 }
576 /* OMAP1 don't support burst 16
577 * fall through
578 */
579 default:
580 printk(KERN_ERR "Invalid DMA burst mode\n");
581 BUG();
582 return;
583 }
584 l |= (burst << 14);
585 dma_write(l, CSDP(lch));
586 }
587 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
588
589 static inline void omap_enable_channel_irq(int lch)
590 {
591 u32 status;
592
593 /* Clear CSR */
594 if (cpu_class_is_omap1())
595 status = dma_read(CSR(lch));
596 else if (cpu_class_is_omap2())
597 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
598
599 /* Enable some nice interrupts. */
600 dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
601 }
602
603 static void omap_disable_channel_irq(int lch)
604 {
605 if (cpu_class_is_omap2())
606 dma_write(0, CICR(lch));
607 }
608
609 void omap_enable_dma_irq(int lch, u16 bits)
610 {
611 dma_chan[lch].enabled_irqs |= bits;
612 }
613 EXPORT_SYMBOL(omap_enable_dma_irq);
614
615 void omap_disable_dma_irq(int lch, u16 bits)
616 {
617 dma_chan[lch].enabled_irqs &= ~bits;
618 }
619 EXPORT_SYMBOL(omap_disable_dma_irq);
620
621 static inline void enable_lnk(int lch)
622 {
623 u32 l;
624
625 l = dma_read(CLNK_CTRL(lch));
626
627 if (cpu_class_is_omap1())
628 l &= ~(1 << 14);
629
630 /* Set the ENABLE_LNK bits */
631 if (dma_chan[lch].next_lch != -1)
632 l = dma_chan[lch].next_lch | (1 << 15);
633
634 #ifndef CONFIG_ARCH_OMAP1
635 if (cpu_class_is_omap2())
636 if (dma_chan[lch].next_linked_ch != -1)
637 l = dma_chan[lch].next_linked_ch | (1 << 15);
638 #endif
639
640 dma_write(l, CLNK_CTRL(lch));
641 }
642
643 static inline void disable_lnk(int lch)
644 {
645 u32 l;
646
647 l = dma_read(CLNK_CTRL(lch));
648
649 /* Disable interrupts */
650 if (cpu_class_is_omap1()) {
651 dma_write(0, CICR(lch));
652 /* Set the STOP_LNK bit */
653 l |= 1 << 14;
654 }
655
656 if (cpu_class_is_omap2()) {
657 omap_disable_channel_irq(lch);
658 /* Clear the ENABLE_LNK bit */
659 l &= ~(1 << 15);
660 }
661
662 dma_write(l, CLNK_CTRL(lch));
663 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
664 }
665
666 static inline void omap2_enable_irq_lch(int lch)
667 {
668 u32 val;
669
670 if (!cpu_class_is_omap2())
671 return;
672
673 val = dma_read(IRQENABLE_L0);
674 val |= 1 << lch;
675 dma_write(val, IRQENABLE_L0);
676 }
677
678 int omap_request_dma(int dev_id, const char *dev_name,
679 void (*callback)(int lch, u16 ch_status, void *data),
680 void *data, int *dma_ch_out)
681 {
682 int ch, free_ch = -1;
683 unsigned long flags;
684 struct omap_dma_lch *chan;
685
686 spin_lock_irqsave(&dma_chan_lock, flags);
687 for (ch = 0; ch < dma_chan_count; ch++) {
688 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
689 free_ch = ch;
690 if (dev_id == 0)
691 break;
692 }
693 }
694 if (free_ch == -1) {
695 spin_unlock_irqrestore(&dma_chan_lock, flags);
696 return -EBUSY;
697 }
698 chan = dma_chan + free_ch;
699 chan->dev_id = dev_id;
700
701 if (cpu_class_is_omap1())
702 clear_lch_regs(free_ch);
703
704 if (cpu_class_is_omap2())
705 omap_clear_dma(free_ch);
706
707 spin_unlock_irqrestore(&dma_chan_lock, flags);
708
709 chan->dev_name = dev_name;
710 chan->callback = callback;
711 chan->data = data;
712
713 #ifndef CONFIG_ARCH_OMAP1
714 if (cpu_class_is_omap2()) {
715 chan->chain_id = -1;
716 chan->next_linked_ch = -1;
717 }
718 #endif
719
720 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
721
722 if (cpu_class_is_omap1())
723 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
724 else if (cpu_class_is_omap2())
725 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
726 OMAP2_DMA_TRANS_ERR_IRQ;
727
728 if (cpu_is_omap16xx()) {
729 /* If the sync device is set, configure it dynamically. */
730 if (dev_id != 0) {
731 set_gdma_dev(free_ch + 1, dev_id);
732 dev_id = free_ch + 1;
733 }
734 /*
735 * Disable the 1510 compatibility mode and set the sync device
736 * id.
737 */
738 dma_write(dev_id | (1 << 10), CCR(free_ch));
739 } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
740 dma_write(dev_id, CCR(free_ch));
741 }
742
743 if (cpu_class_is_omap2()) {
744 omap2_enable_irq_lch(free_ch);
745 omap_enable_channel_irq(free_ch);
746 /* Clear the CSR register and IRQ status register */
747 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
748 dma_write(1 << free_ch, IRQSTATUS_L0);
749 }
750
751 *dma_ch_out = free_ch;
752
753 return 0;
754 }
755 EXPORT_SYMBOL(omap_request_dma);
756
757 void omap_free_dma(int lch)
758 {
759 unsigned long flags;
760
761 spin_lock_irqsave(&dma_chan_lock, flags);
762 if (dma_chan[lch].dev_id == -1) {
763 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
764 lch);
765 spin_unlock_irqrestore(&dma_chan_lock, flags);
766 return;
767 }
768
769 dma_chan[lch].dev_id = -1;
770 dma_chan[lch].next_lch = -1;
771 dma_chan[lch].callback = NULL;
772 spin_unlock_irqrestore(&dma_chan_lock, flags);
773
774 if (cpu_class_is_omap1()) {
775 /* Disable all DMA interrupts for the channel. */
776 dma_write(0, CICR(lch));
777 /* Make sure the DMA transfer is stopped. */
778 dma_write(0, CCR(lch));
779 }
780
781 if (cpu_class_is_omap2()) {
782 u32 val;
783 /* Disable interrupts */
784 val = dma_read(IRQENABLE_L0);
785 val &= ~(1 << lch);
786 dma_write(val, IRQENABLE_L0);
787
788 /* Clear the CSR register and IRQ status register */
789 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
790 dma_write(1 << lch, IRQSTATUS_L0);
791
792 /* Disable all DMA interrupts for the channel. */
793 dma_write(0, CICR(lch));
794
795 /* Make sure the DMA transfer is stopped. */
796 dma_write(0, CCR(lch));
797 omap_clear_dma(lch);
798 }
799 }
800 EXPORT_SYMBOL(omap_free_dma);
801
802 /**
803 * @brief omap_dma_set_global_params : Set global priority settings for dma
804 *
805 * @param arb_rate
806 * @param max_fifo_depth
807 * @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
808 * DMA_THREAD_RESERVE_ONET
809 * DMA_THREAD_RESERVE_TWOT
810 * DMA_THREAD_RESERVE_THREET
811 */
812 void
813 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
814 {
815 u32 reg;
816
817 if (!cpu_class_is_omap2()) {
818 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
819 return;
820 }
821
822 if (arb_rate == 0)
823 arb_rate = 1;
824
825 reg = (arb_rate & 0xff) << 16;
826 reg |= (0xff & max_fifo_depth);
827
828 dma_write(reg, GCR);
829 }
830 EXPORT_SYMBOL(omap_dma_set_global_params);
831
832 /**
833 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
834 *
835 * @param lch
836 * @param read_prio - Read priority
837 * @param write_prio - Write priority
838 * Both of the above can be set with one of the following values :
839 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
840 */
841 int
842 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
843 unsigned char write_prio)
844 {
845 u32 l;
846
847 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
848 printk(KERN_ERR "Invalid channel id\n");
849 return -EINVAL;
850 }
851 l = dma_read(CCR(lch));
852 l &= ~((1 << 6) | (1 << 26));
853 if (cpu_is_omap2430() || cpu_is_omap34xx())
854 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
855 else
856 l |= ((read_prio & 0x1) << 6);
857
858 dma_write(l, CCR(lch));
859
860 return 0;
861 }
862 EXPORT_SYMBOL(omap_dma_set_prio_lch);
863
864 /*
865 * Clears any DMA state so the DMA engine is ready to restart with new buffers
866 * through omap_start_dma(). Any buffers in flight are discarded.
867 */
868 void omap_clear_dma(int lch)
869 {
870 unsigned long flags;
871
872 local_irq_save(flags);
873
874 if (cpu_class_is_omap1()) {
875 u32 l;
876
877 l = dma_read(CCR(lch));
878 l &= ~OMAP_DMA_CCR_EN;
879 dma_write(l, CCR(lch));
880
881 /* Clear pending interrupts */
882 l = dma_read(CSR(lch));
883 }
884
885 if (cpu_class_is_omap2()) {
886 int i;
887 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
888 for (i = 0; i < 0x44; i += 4)
889 __raw_writel(0, lch_base + i);
890 }
891
892 local_irq_restore(flags);
893 }
894 EXPORT_SYMBOL(omap_clear_dma);
895
896 void omap_start_dma(int lch)
897 {
898 u32 l;
899
900 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
901 int next_lch, cur_lch;
902 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
903
904 dma_chan_link_map[lch] = 1;
905 /* Set the link register of the first channel */
906 enable_lnk(lch);
907
908 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
909 cur_lch = dma_chan[lch].next_lch;
910 do {
911 next_lch = dma_chan[cur_lch].next_lch;
912
913 /* The loop case: we've been here already */
914 if (dma_chan_link_map[cur_lch])
915 break;
916 /* Mark the current channel */
917 dma_chan_link_map[cur_lch] = 1;
918
919 enable_lnk(cur_lch);
920 omap_enable_channel_irq(cur_lch);
921
922 cur_lch = next_lch;
923 } while (next_lch != -1);
924 } else if (cpu_class_is_omap2()) {
925 /* Errata: Need to write lch even if not using chaining */
926 dma_write(lch, CLNK_CTRL(lch));
927 }
928
929 omap_enable_channel_irq(lch);
930
931 l = dma_read(CCR(lch));
932
933 /*
934 * Errata: On ES2.0 BUFFERING disable must be set.
935 * This will always fail on ES1.0
936 */
937 if (cpu_is_omap24xx())
938 l |= OMAP_DMA_CCR_EN;
939
940 l |= OMAP_DMA_CCR_EN;
941 dma_write(l, CCR(lch));
942
943 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
944 }
945 EXPORT_SYMBOL(omap_start_dma);
946
947 void omap_stop_dma(int lch)
948 {
949 u32 l;
950
951 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
952 int next_lch, cur_lch = lch;
953 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
954
955 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
956 do {
957 /* The loop case: we've been here already */
958 if (dma_chan_link_map[cur_lch])
959 break;
960 /* Mark the current channel */
961 dma_chan_link_map[cur_lch] = 1;
962
963 disable_lnk(cur_lch);
964
965 next_lch = dma_chan[cur_lch].next_lch;
966 cur_lch = next_lch;
967 } while (next_lch != -1);
968
969 return;
970 }
971
972 /* Disable all interrupts on the channel */
973 if (cpu_class_is_omap1())
974 dma_write(0, CICR(lch));
975
976 l = dma_read(CCR(lch));
977 l &= ~OMAP_DMA_CCR_EN;
978 dma_write(l, CCR(lch));
979
980 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
981 }
982 EXPORT_SYMBOL(omap_stop_dma);
983
984 /*
985 * Allows changing the DMA callback function or data. This may be needed if
986 * the driver shares a single DMA channel for multiple dma triggers.
987 */
988 int omap_set_dma_callback(int lch,
989 void (*callback)(int lch, u16 ch_status, void *data),
990 void *data)
991 {
992 unsigned long flags;
993
994 if (lch < 0)
995 return -ENODEV;
996
997 spin_lock_irqsave(&dma_chan_lock, flags);
998 if (dma_chan[lch].dev_id == -1) {
999 printk(KERN_ERR "DMA callback for not set for free channel\n");
1000 spin_unlock_irqrestore(&dma_chan_lock, flags);
1001 return -EINVAL;
1002 }
1003 dma_chan[lch].callback = callback;
1004 dma_chan[lch].data = data;
1005 spin_unlock_irqrestore(&dma_chan_lock, flags);
1006
1007 return 0;
1008 }
1009 EXPORT_SYMBOL(omap_set_dma_callback);
1010
1011 /*
1012 * Returns current physical source address for the given DMA channel.
1013 * If the channel is running the caller must disable interrupts prior calling
1014 * this function and process the returned value before re-enabling interrupt to
1015 * prevent races with the interrupt handler. Note that in continuous mode there
1016 * is a chance for CSSA_L register overflow inbetween the two reads resulting
1017 * in incorrect return value.
1018 */
1019 dma_addr_t omap_get_dma_src_pos(int lch)
1020 {
1021 dma_addr_t offset = 0;
1022
1023 if (cpu_is_omap15xx())
1024 offset = dma_read(CPC(lch));
1025 else
1026 offset = dma_read(CSAC(lch));
1027
1028 /*
1029 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1030 * read before the DMA controller finished disabling the channel.
1031 */
1032 if (!cpu_is_omap15xx() && offset == 0)
1033 offset = dma_read(CSAC(lch));
1034
1035 if (cpu_class_is_omap1())
1036 offset |= (dma_read(CSSA_U(lch)) << 16);
1037
1038 return offset;
1039 }
1040 EXPORT_SYMBOL(omap_get_dma_src_pos);
1041
1042 /*
1043 * Returns current physical destination address for the given DMA channel.
1044 * If the channel is running the caller must disable interrupts prior calling
1045 * this function and process the returned value before re-enabling interrupt to
1046 * prevent races with the interrupt handler. Note that in continuous mode there
1047 * is a chance for CDSA_L register overflow inbetween the two reads resulting
1048 * in incorrect return value.
1049 */
1050 dma_addr_t omap_get_dma_dst_pos(int lch)
1051 {
1052 dma_addr_t offset = 0;
1053
1054 if (cpu_is_omap15xx())
1055 offset = dma_read(CPC(lch));
1056 else
1057 offset = dma_read(CDAC(lch));
1058
1059 /*
1060 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1061 * read before the DMA controller finished disabling the channel.
1062 */
1063 if (!cpu_is_omap15xx() && offset == 0)
1064 offset = dma_read(CDAC(lch));
1065
1066 if (cpu_class_is_omap1())
1067 offset |= (dma_read(CDSA_U(lch)) << 16);
1068
1069 return offset;
1070 }
1071 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1072
1073 int omap_get_dma_active_status(int lch)
1074 {
1075 return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
1076 }
1077 EXPORT_SYMBOL(omap_get_dma_active_status);
1078
1079 int omap_dma_running(void)
1080 {
1081 int lch;
1082
1083 /* Check if LCD DMA is running */
1084 if (cpu_is_omap16xx())
1085 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
1086 return 1;
1087
1088 for (lch = 0; lch < dma_chan_count; lch++)
1089 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1090 return 1;
1091
1092 return 0;
1093 }
1094
1095 /*
1096 * lch_queue DMA will start right after lch_head one is finished.
1097 * For this DMA link to start, you still need to start (see omap_start_dma)
1098 * the first one. That will fire up the entire queue.
1099 */
1100 void omap_dma_link_lch(int lch_head, int lch_queue)
1101 {
1102 if (omap_dma_in_1510_mode()) {
1103 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1104 BUG();
1105 return;
1106 }
1107
1108 if ((dma_chan[lch_head].dev_id == -1) ||
1109 (dma_chan[lch_queue].dev_id == -1)) {
1110 printk(KERN_ERR "omap_dma: trying to link "
1111 "non requested channels\n");
1112 dump_stack();
1113 }
1114
1115 dma_chan[lch_head].next_lch = lch_queue;
1116 }
1117 EXPORT_SYMBOL(omap_dma_link_lch);
1118
1119 /*
1120 * Once the DMA queue is stopped, we can destroy it.
1121 */
1122 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1123 {
1124 if (omap_dma_in_1510_mode()) {
1125 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1126 BUG();
1127 return;
1128 }
1129
1130 if (dma_chan[lch_head].next_lch != lch_queue ||
1131 dma_chan[lch_head].next_lch == -1) {
1132 printk(KERN_ERR "omap_dma: trying to unlink "
1133 "non linked channels\n");
1134 dump_stack();
1135 }
1136
1137 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1138 (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
1139 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1140 "before unlinking\n");
1141 dump_stack();
1142 }
1143
1144 dma_chan[lch_head].next_lch = -1;
1145 }
1146 EXPORT_SYMBOL(omap_dma_unlink_lch);
1147
1148 /*----------------------------------------------------------------------------*/
1149
1150 #ifndef CONFIG_ARCH_OMAP1
1151 /* Create chain of DMA channesls */
1152 static void create_dma_lch_chain(int lch_head, int lch_queue)
1153 {
1154 u32 l;
1155
1156 /* Check if this is the first link in chain */
1157 if (dma_chan[lch_head].next_linked_ch == -1) {
1158 dma_chan[lch_head].next_linked_ch = lch_queue;
1159 dma_chan[lch_head].prev_linked_ch = lch_queue;
1160 dma_chan[lch_queue].next_linked_ch = lch_head;
1161 dma_chan[lch_queue].prev_linked_ch = lch_head;
1162 }
1163
1164 /* a link exists, link the new channel in circular chain */
1165 else {
1166 dma_chan[lch_queue].next_linked_ch =
1167 dma_chan[lch_head].next_linked_ch;
1168 dma_chan[lch_queue].prev_linked_ch = lch_head;
1169 dma_chan[lch_head].next_linked_ch = lch_queue;
1170 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1171 lch_queue;
1172 }
1173
1174 l = dma_read(CLNK_CTRL(lch_head));
1175 l &= ~(0x1f);
1176 l |= lch_queue;
1177 dma_write(l, CLNK_CTRL(lch_head));
1178
1179 l = dma_read(CLNK_CTRL(lch_queue));
1180 l &= ~(0x1f);
1181 l |= (dma_chan[lch_queue].next_linked_ch);
1182 dma_write(l, CLNK_CTRL(lch_queue));
1183 }
1184
1185 /**
1186 * @brief omap_request_dma_chain : Request a chain of DMA channels
1187 *
1188 * @param dev_id - Device id using the dma channel
1189 * @param dev_name - Device name
1190 * @param callback - Call back function
1191 * @chain_id -
1192 * @no_of_chans - Number of channels requested
1193 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1194 * OMAP_DMA_DYNAMIC_CHAIN
1195 * @params - Channel parameters
1196 *
1197 * @return - Succes : 0
1198 * Failure: -EINVAL/-ENOMEM
1199 */
1200 int omap_request_dma_chain(int dev_id, const char *dev_name,
1201 void (*callback) (int chain_id, u16 ch_status,
1202 void *data),
1203 int *chain_id, int no_of_chans, int chain_mode,
1204 struct omap_dma_channel_params params)
1205 {
1206 int *channels;
1207 int i, err;
1208
1209 /* Is the chain mode valid ? */
1210 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1211 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1212 printk(KERN_ERR "Invalid chain mode requested\n");
1213 return -EINVAL;
1214 }
1215
1216 if (unlikely((no_of_chans < 1
1217 || no_of_chans > dma_lch_count))) {
1218 printk(KERN_ERR "Invalid Number of channels requested\n");
1219 return -EINVAL;
1220 }
1221
1222 /* Allocate a queue to maintain the status of the channels
1223 * in the chain */
1224 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1225 if (channels == NULL) {
1226 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1227 return -ENOMEM;
1228 }
1229
1230 /* request and reserve DMA channels for the chain */
1231 for (i = 0; i < no_of_chans; i++) {
1232 err = omap_request_dma(dev_id, dev_name,
1233 callback, NULL, &channels[i]);
1234 if (err < 0) {
1235 int j;
1236 for (j = 0; j < i; j++)
1237 omap_free_dma(channels[j]);
1238 kfree(channels);
1239 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1240 return err;
1241 }
1242 dma_chan[channels[i]].prev_linked_ch = -1;
1243 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1244
1245 /*
1246 * Allowing client drivers to set common parameters now,
1247 * so that later only relevant (src_start, dest_start
1248 * and element count) can be set
1249 */
1250 omap_set_dma_params(channels[i], &params);
1251 }
1252
1253 *chain_id = channels[0];
1254 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1255 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1256 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1257 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1258
1259 for (i = 0; i < no_of_chans; i++)
1260 dma_chan[channels[i]].chain_id = *chain_id;
1261
1262 /* Reset the Queue pointers */
1263 OMAP_DMA_CHAIN_QINIT(*chain_id);
1264
1265 /* Set up the chain */
1266 if (no_of_chans == 1)
1267 create_dma_lch_chain(channels[0], channels[0]);
1268 else {
1269 for (i = 0; i < (no_of_chans - 1); i++)
1270 create_dma_lch_chain(channels[i], channels[i + 1]);
1271 }
1272
1273 return 0;
1274 }
1275 EXPORT_SYMBOL(omap_request_dma_chain);
1276
1277 /**
1278 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1279 * params after setting it. Dont do this while dma is running!!
1280 *
1281 * @param chain_id - Chained logical channel id.
1282 * @param params
1283 *
1284 * @return - Success : 0
1285 * Failure : -EINVAL
1286 */
1287 int omap_modify_dma_chain_params(int chain_id,
1288 struct omap_dma_channel_params params)
1289 {
1290 int *channels;
1291 u32 i;
1292
1293 /* Check for input params */
1294 if (unlikely((chain_id < 0
1295 || chain_id >= dma_lch_count))) {
1296 printk(KERN_ERR "Invalid chain id\n");
1297 return -EINVAL;
1298 }
1299
1300 /* Check if the chain exists */
1301 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1302 printk(KERN_ERR "Chain doesn't exists\n");
1303 return -EINVAL;
1304 }
1305 channels = dma_linked_lch[chain_id].linked_dmach_q;
1306
1307 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1308 /*
1309 * Allowing client drivers to set common parameters now,
1310 * so that later only relevant (src_start, dest_start
1311 * and element count) can be set
1312 */
1313 omap_set_dma_params(channels[i], &params);
1314 }
1315
1316 return 0;
1317 }
1318 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1319
1320 /**
1321 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1322 *
1323 * @param chain_id
1324 *
1325 * @return - Success : 0
1326 * Failure : -EINVAL
1327 */
1328 int omap_free_dma_chain(int chain_id)
1329 {
1330 int *channels;
1331 u32 i;
1332
1333 /* Check for input params */
1334 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1335 printk(KERN_ERR "Invalid chain id\n");
1336 return -EINVAL;
1337 }
1338
1339 /* Check if the chain exists */
1340 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1341 printk(KERN_ERR "Chain doesn't exists\n");
1342 return -EINVAL;
1343 }
1344
1345 channels = dma_linked_lch[chain_id].linked_dmach_q;
1346 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1347 dma_chan[channels[i]].next_linked_ch = -1;
1348 dma_chan[channels[i]].prev_linked_ch = -1;
1349 dma_chan[channels[i]].chain_id = -1;
1350 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1351 omap_free_dma(channels[i]);
1352 }
1353
1354 kfree(channels);
1355
1356 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1357 dma_linked_lch[chain_id].chain_mode = -1;
1358 dma_linked_lch[chain_id].chain_state = -1;
1359
1360 return (0);
1361 }
1362 EXPORT_SYMBOL(omap_free_dma_chain);
1363
1364 /**
1365 * @brief omap_dma_chain_status - Check if the chain is in
1366 * active / inactive state.
1367 * @param chain_id
1368 *
1369 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1370 * Failure : -EINVAL
1371 */
1372 int omap_dma_chain_status(int chain_id)
1373 {
1374 /* Check for input params */
1375 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1376 printk(KERN_ERR "Invalid chain id\n");
1377 return -EINVAL;
1378 }
1379
1380 /* Check if the chain exists */
1381 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1382 printk(KERN_ERR "Chain doesn't exists\n");
1383 return -EINVAL;
1384 }
1385 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1386 dma_linked_lch[chain_id].q_count);
1387
1388 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1389 return OMAP_DMA_CHAIN_INACTIVE;
1390
1391 return OMAP_DMA_CHAIN_ACTIVE;
1392 }
1393 EXPORT_SYMBOL(omap_dma_chain_status);
1394
1395 /**
1396 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1397 * set the params and start the transfer.
1398 *
1399 * @param chain_id
1400 * @param src_start - buffer start address
1401 * @param dest_start - Dest address
1402 * @param elem_count
1403 * @param frame_count
1404 * @param callbk_data - channel callback parameter data.
1405 *
1406 * @return - Success : 0
1407 * Failure: -EINVAL/-EBUSY
1408 */
1409 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1410 int elem_count, int frame_count, void *callbk_data)
1411 {
1412 int *channels;
1413 u32 l, lch;
1414 int start_dma = 0;
1415
1416 /*
1417 * if buffer size is less than 1 then there is
1418 * no use of starting the chain
1419 */
1420 if (elem_count < 1) {
1421 printk(KERN_ERR "Invalid buffer size\n");
1422 return -EINVAL;
1423 }
1424
1425 /* Check for input params */
1426 if (unlikely((chain_id < 0
1427 || chain_id >= dma_lch_count))) {
1428 printk(KERN_ERR "Invalid chain id\n");
1429 return -EINVAL;
1430 }
1431
1432 /* Check if the chain exists */
1433 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1434 printk(KERN_ERR "Chain doesn't exist\n");
1435 return -EINVAL;
1436 }
1437
1438 /* Check if all the channels in chain are in use */
1439 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1440 return -EBUSY;
1441
1442 /* Frame count may be negative in case of indexed transfers */
1443 channels = dma_linked_lch[chain_id].linked_dmach_q;
1444
1445 /* Get a free channel */
1446 lch = channels[dma_linked_lch[chain_id].q_tail];
1447
1448 /* Store the callback data */
1449 dma_chan[lch].data = callbk_data;
1450
1451 /* Increment the q_tail */
1452 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1453
1454 /* Set the params to the free channel */
1455 if (src_start != 0)
1456 dma_write(src_start, CSSA(lch));
1457 if (dest_start != 0)
1458 dma_write(dest_start, CDSA(lch));
1459
1460 /* Write the buffer size */
1461 dma_write(elem_count, CEN(lch));
1462 dma_write(frame_count, CFN(lch));
1463
1464 /*
1465 * If the chain is dynamically linked,
1466 * then we may have to start the chain if its not active
1467 */
1468 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1469
1470 /*
1471 * In Dynamic chain, if the chain is not started,
1472 * queue the channel
1473 */
1474 if (dma_linked_lch[chain_id].chain_state ==
1475 DMA_CHAIN_NOTSTARTED) {
1476 /* Enable the link in previous channel */
1477 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1478 DMA_CH_QUEUED)
1479 enable_lnk(dma_chan[lch].prev_linked_ch);
1480 dma_chan[lch].state = DMA_CH_QUEUED;
1481 }
1482
1483 /*
1484 * Chain is already started, make sure its active,
1485 * if not then start the chain
1486 */
1487 else {
1488 start_dma = 1;
1489
1490 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1491 DMA_CH_STARTED) {
1492 enable_lnk(dma_chan[lch].prev_linked_ch);
1493 dma_chan[lch].state = DMA_CH_QUEUED;
1494 start_dma = 0;
1495 if (0 == ((1 << 7) & dma_read(
1496 CCR(dma_chan[lch].prev_linked_ch)))) {
1497 disable_lnk(dma_chan[lch].
1498 prev_linked_ch);
1499 pr_debug("\n prev ch is stopped\n");
1500 start_dma = 1;
1501 }
1502 }
1503
1504 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1505 == DMA_CH_QUEUED) {
1506 enable_lnk(dma_chan[lch].prev_linked_ch);
1507 dma_chan[lch].state = DMA_CH_QUEUED;
1508 start_dma = 0;
1509 }
1510 omap_enable_channel_irq(lch);
1511
1512 l = dma_read(CCR(lch));
1513
1514 if ((0 == (l & (1 << 24))))
1515 l &= ~(1 << 25);
1516 else
1517 l |= (1 << 25);
1518 if (start_dma == 1) {
1519 if (0 == (l & (1 << 7))) {
1520 l |= (1 << 7);
1521 dma_chan[lch].state = DMA_CH_STARTED;
1522 pr_debug("starting %d\n", lch);
1523 dma_write(l, CCR(lch));
1524 } else
1525 start_dma = 0;
1526 } else {
1527 if (0 == (l & (1 << 7)))
1528 dma_write(l, CCR(lch));
1529 }
1530 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1531 }
1532 }
1533
1534 return 0;
1535 }
1536 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1537
1538 /**
1539 * @brief omap_start_dma_chain_transfers - Start the chain
1540 *
1541 * @param chain_id
1542 *
1543 * @return - Success : 0
1544 * Failure : -EINVAL/-EBUSY
1545 */
1546 int omap_start_dma_chain_transfers(int chain_id)
1547 {
1548 int *channels;
1549 u32 l, i;
1550
1551 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1552 printk(KERN_ERR "Invalid chain id\n");
1553 return -EINVAL;
1554 }
1555
1556 channels = dma_linked_lch[chain_id].linked_dmach_q;
1557
1558 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1559 printk(KERN_ERR "Chain is already started\n");
1560 return -EBUSY;
1561 }
1562
1563 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1564 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1565 i++) {
1566 enable_lnk(channels[i]);
1567 omap_enable_channel_irq(channels[i]);
1568 }
1569 } else {
1570 omap_enable_channel_irq(channels[0]);
1571 }
1572
1573 l = dma_read(CCR(channels[0]));
1574 l |= (1 << 7);
1575 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1576 dma_chan[channels[0]].state = DMA_CH_STARTED;
1577
1578 if ((0 == (l & (1 << 24))))
1579 l &= ~(1 << 25);
1580 else
1581 l |= (1 << 25);
1582 dma_write(l, CCR(channels[0]));
1583
1584 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1585
1586 return 0;
1587 }
1588 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1589
1590 /**
1591 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1592 *
1593 * @param chain_id
1594 *
1595 * @return - Success : 0
1596 * Failure : EINVAL
1597 */
1598 int omap_stop_dma_chain_transfers(int chain_id)
1599 {
1600 int *channels;
1601 u32 l, i;
1602 u32 sys_cf;
1603
1604 /* Check for input params */
1605 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1606 printk(KERN_ERR "Invalid chain id\n");
1607 return -EINVAL;
1608 }
1609
1610 /* Check if the chain exists */
1611 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1612 printk(KERN_ERR "Chain doesn't exists\n");
1613 return -EINVAL;
1614 }
1615 channels = dma_linked_lch[chain_id].linked_dmach_q;
1616
1617 /*
1618 * DMA Errata:
1619 * Special programming model needed to disable DMA before end of block
1620 */
1621 sys_cf = dma_read(OCP_SYSCONFIG);
1622 l = sys_cf;
1623 /* Middle mode reg set no Standby */
1624 l &= ~((1 << 12)|(1 << 13));
1625 dma_write(l, OCP_SYSCONFIG);
1626
1627 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1628
1629 /* Stop the Channel transmission */
1630 l = dma_read(CCR(channels[i]));
1631 l &= ~(1 << 7);
1632 dma_write(l, CCR(channels[i]));
1633
1634 /* Disable the link in all the channels */
1635 disable_lnk(channels[i]);
1636 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1637
1638 }
1639 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1640
1641 /* Reset the Queue pointers */
1642 OMAP_DMA_CHAIN_QINIT(chain_id);
1643
1644 /* Errata - put in the old value */
1645 dma_write(sys_cf, OCP_SYSCONFIG);
1646
1647 return 0;
1648 }
1649 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1650
1651 /* Get the index of the ongoing DMA in chain */
1652 /**
1653 * @brief omap_get_dma_chain_index - Get the element and frame index
1654 * of the ongoing DMA in chain
1655 *
1656 * @param chain_id
1657 * @param ei - Element index
1658 * @param fi - Frame index
1659 *
1660 * @return - Success : 0
1661 * Failure : -EINVAL
1662 */
1663 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1664 {
1665 int lch;
1666 int *channels;
1667
1668 /* Check for input params */
1669 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1670 printk(KERN_ERR "Invalid chain id\n");
1671 return -EINVAL;
1672 }
1673
1674 /* Check if the chain exists */
1675 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1676 printk(KERN_ERR "Chain doesn't exists\n");
1677 return -EINVAL;
1678 }
1679 if ((!ei) || (!fi))
1680 return -EINVAL;
1681
1682 channels = dma_linked_lch[chain_id].linked_dmach_q;
1683
1684 /* Get the current channel */
1685 lch = channels[dma_linked_lch[chain_id].q_head];
1686
1687 *ei = dma_read(CCEN(lch));
1688 *fi = dma_read(CCFN(lch));
1689
1690 return 0;
1691 }
1692 EXPORT_SYMBOL(omap_get_dma_chain_index);
1693
1694 /**
1695 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1696 * ongoing DMA in chain
1697 *
1698 * @param chain_id
1699 *
1700 * @return - Success : Destination position
1701 * Failure : -EINVAL
1702 */
1703 int omap_get_dma_chain_dst_pos(int chain_id)
1704 {
1705 int lch;
1706 int *channels;
1707
1708 /* Check for input params */
1709 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1710 printk(KERN_ERR "Invalid chain id\n");
1711 return -EINVAL;
1712 }
1713
1714 /* Check if the chain exists */
1715 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1716 printk(KERN_ERR "Chain doesn't exists\n");
1717 return -EINVAL;
1718 }
1719
1720 channels = dma_linked_lch[chain_id].linked_dmach_q;
1721
1722 /* Get the current channel */
1723 lch = channels[dma_linked_lch[chain_id].q_head];
1724
1725 return dma_read(CDAC(lch));
1726 }
1727 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1728
1729 /**
1730 * @brief omap_get_dma_chain_src_pos - Get the source position
1731 * of the ongoing DMA in chain
1732 * @param chain_id
1733 *
1734 * @return - Success : Destination position
1735 * Failure : -EINVAL
1736 */
1737 int omap_get_dma_chain_src_pos(int chain_id)
1738 {
1739 int lch;
1740 int *channels;
1741
1742 /* Check for input params */
1743 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1744 printk(KERN_ERR "Invalid chain id\n");
1745 return -EINVAL;
1746 }
1747
1748 /* Check if the chain exists */
1749 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1750 printk(KERN_ERR "Chain doesn't exists\n");
1751 return -EINVAL;
1752 }
1753
1754 channels = dma_linked_lch[chain_id].linked_dmach_q;
1755
1756 /* Get the current channel */
1757 lch = channels[dma_linked_lch[chain_id].q_head];
1758
1759 return dma_read(CSAC(lch));
1760 }
1761 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1762 #endif /* ifndef CONFIG_ARCH_OMAP1 */
1763
1764 /*----------------------------------------------------------------------------*/
1765
1766 #ifdef CONFIG_ARCH_OMAP1
1767
1768 static int omap1_dma_handle_ch(int ch)
1769 {
1770 u32 csr;
1771
1772 if (enable_1510_mode && ch >= 6) {
1773 csr = dma_chan[ch].saved_csr;
1774 dma_chan[ch].saved_csr = 0;
1775 } else
1776 csr = dma_read(CSR(ch));
1777 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1778 dma_chan[ch + 6].saved_csr = csr >> 7;
1779 csr &= 0x7f;
1780 }
1781 if ((csr & 0x3f) == 0)
1782 return 0;
1783 if (unlikely(dma_chan[ch].dev_id == -1)) {
1784 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1785 "%d (CSR %04x)\n", ch, csr);
1786 return 0;
1787 }
1788 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1789 printk(KERN_WARNING "DMA timeout with device %d\n",
1790 dma_chan[ch].dev_id);
1791 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1792 printk(KERN_WARNING "DMA synchronization event drop occurred "
1793 "with device %d\n", dma_chan[ch].dev_id);
1794 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1795 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1796 if (likely(dma_chan[ch].callback != NULL))
1797 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1798
1799 return 1;
1800 }
1801
1802 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1803 {
1804 int ch = ((int) dev_id) - 1;
1805 int handled = 0;
1806
1807 for (;;) {
1808 int handled_now = 0;
1809
1810 handled_now += omap1_dma_handle_ch(ch);
1811 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1812 handled_now += omap1_dma_handle_ch(ch + 6);
1813 if (!handled_now)
1814 break;
1815 handled += handled_now;
1816 }
1817
1818 return handled ? IRQ_HANDLED : IRQ_NONE;
1819 }
1820
1821 #else
1822 #define omap1_dma_irq_handler NULL
1823 #endif
1824
1825 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1826
1827 static int omap2_dma_handle_ch(int ch)
1828 {
1829 u32 status = dma_read(CSR(ch));
1830
1831 if (!status) {
1832 if (printk_ratelimit())
1833 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1834 ch);
1835 dma_write(1 << ch, IRQSTATUS_L0);
1836 return 0;
1837 }
1838 if (unlikely(dma_chan[ch].dev_id == -1)) {
1839 if (printk_ratelimit())
1840 printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1841 "channel %d\n", status, ch);
1842 return 0;
1843 }
1844 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1845 printk(KERN_INFO
1846 "DMA synchronization event drop occurred with device "
1847 "%d\n", dma_chan[ch].dev_id);
1848 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1849 printk(KERN_INFO "DMA transaction error with device %d\n",
1850 dma_chan[ch].dev_id);
1851 if (cpu_class_is_omap2()) {
1852 /* Errata: sDMA Channel is not disabled
1853 * after a transaction error. So we explicitely
1854 * disable the channel
1855 */
1856 u32 ccr;
1857
1858 ccr = dma_read(CCR(ch));
1859 ccr &= ~OMAP_DMA_CCR_EN;
1860 dma_write(ccr, CCR(ch));
1861 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1862 }
1863 }
1864 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1865 printk(KERN_INFO "DMA secure error with device %d\n",
1866 dma_chan[ch].dev_id);
1867 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1868 printk(KERN_INFO "DMA misaligned error with device %d\n",
1869 dma_chan[ch].dev_id);
1870
1871 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1872 dma_write(1 << ch, IRQSTATUS_L0);
1873
1874 /* If the ch is not chained then chain_id will be -1 */
1875 if (dma_chan[ch].chain_id != -1) {
1876 int chain_id = dma_chan[ch].chain_id;
1877 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1878 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
1879 dma_chan[dma_chan[ch].next_linked_ch].state =
1880 DMA_CH_STARTED;
1881 if (dma_linked_lch[chain_id].chain_mode ==
1882 OMAP_DMA_DYNAMIC_CHAIN)
1883 disable_lnk(ch);
1884
1885 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1886 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1887
1888 status = dma_read(CSR(ch));
1889 }
1890
1891 if (likely(dma_chan[ch].callback != NULL))
1892 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1893
1894 dma_write(status, CSR(ch));
1895
1896 return 0;
1897 }
1898
1899 /* STATUS register count is from 1-32 while our is 0-31 */
1900 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1901 {
1902 u32 val;
1903 int i;
1904
1905 val = dma_read(IRQSTATUS_L0);
1906 if (val == 0) {
1907 if (printk_ratelimit())
1908 printk(KERN_WARNING "Spurious DMA IRQ\n");
1909 return IRQ_HANDLED;
1910 }
1911 for (i = 0; i < dma_lch_count && val != 0; i++) {
1912 if (val & 1)
1913 omap2_dma_handle_ch(i);
1914 val >>= 1;
1915 }
1916
1917 return IRQ_HANDLED;
1918 }
1919
1920 static struct irqaction omap24xx_dma_irq = {
1921 .name = "DMA",
1922 .handler = omap2_dma_irq_handler,
1923 .flags = IRQF_DISABLED
1924 };
1925
1926 #else
1927 static struct irqaction omap24xx_dma_irq;
1928 #endif
1929
1930 /*----------------------------------------------------------------------------*/
1931
1932 static struct lcd_dma_info {
1933 spinlock_t lock;
1934 int reserved;
1935 void (*callback)(u16 status, void *data);
1936 void *cb_data;
1937
1938 int active;
1939 unsigned long addr, size;
1940 int rotate, data_type, xres, yres;
1941 int vxres;
1942 int mirror;
1943 int xscale, yscale;
1944 int ext_ctrl;
1945 int src_port;
1946 int single_transfer;
1947 } lcd_dma;
1948
1949 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1950 int data_type)
1951 {
1952 lcd_dma.addr = addr;
1953 lcd_dma.data_type = data_type;
1954 lcd_dma.xres = fb_xres;
1955 lcd_dma.yres = fb_yres;
1956 }
1957 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
1958
1959 void omap_set_lcd_dma_src_port(int port)
1960 {
1961 lcd_dma.src_port = port;
1962 }
1963
1964 void omap_set_lcd_dma_ext_controller(int external)
1965 {
1966 lcd_dma.ext_ctrl = external;
1967 }
1968 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
1969
1970 void omap_set_lcd_dma_single_transfer(int single)
1971 {
1972 lcd_dma.single_transfer = single;
1973 }
1974 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
1975
1976 void omap_set_lcd_dma_b1_rotation(int rotate)
1977 {
1978 if (omap_dma_in_1510_mode()) {
1979 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
1980 BUG();
1981 return;
1982 }
1983 lcd_dma.rotate = rotate;
1984 }
1985 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
1986
1987 void omap_set_lcd_dma_b1_mirror(int mirror)
1988 {
1989 if (omap_dma_in_1510_mode()) {
1990 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
1991 BUG();
1992 }
1993 lcd_dma.mirror = mirror;
1994 }
1995 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
1996
1997 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
1998 {
1999 if (omap_dma_in_1510_mode()) {
2000 printk(KERN_ERR "DMA virtual resulotion is not supported "
2001 "in 1510 mode\n");
2002 BUG();
2003 }
2004 lcd_dma.vxres = vxres;
2005 }
2006 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
2007
2008 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
2009 {
2010 if (omap_dma_in_1510_mode()) {
2011 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
2012 BUG();
2013 }
2014 lcd_dma.xscale = xscale;
2015 lcd_dma.yscale = yscale;
2016 }
2017 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
2018
2019 static void set_b1_regs(void)
2020 {
2021 unsigned long top, bottom;
2022 int es;
2023 u16 w;
2024 unsigned long en, fn;
2025 long ei, fi;
2026 unsigned long vxres;
2027 unsigned int xscale, yscale;
2028
2029 switch (lcd_dma.data_type) {
2030 case OMAP_DMA_DATA_TYPE_S8:
2031 es = 1;
2032 break;
2033 case OMAP_DMA_DATA_TYPE_S16:
2034 es = 2;
2035 break;
2036 case OMAP_DMA_DATA_TYPE_S32:
2037 es = 4;
2038 break;
2039 default:
2040 BUG();
2041 return;
2042 }
2043
2044 vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
2045 xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
2046 yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
2047 BUG_ON(vxres < lcd_dma.xres);
2048
2049 #define PIXADDR(x, y) (lcd_dma.addr + \
2050 ((y) * vxres * yscale + (x) * xscale) * es)
2051 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
2052
2053 switch (lcd_dma.rotate) {
2054 case 0:
2055 if (!lcd_dma.mirror) {
2056 top = PIXADDR(0, 0);
2057 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2058 /* 1510 DMA requires the bottom address to be 2 more
2059 * than the actual last memory access location. */
2060 if (omap_dma_in_1510_mode() &&
2061 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
2062 bottom += 2;
2063 ei = PIXSTEP(0, 0, 1, 0);
2064 fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
2065 } else {
2066 top = PIXADDR(lcd_dma.xres - 1, 0);
2067 bottom = PIXADDR(0, lcd_dma.yres - 1);
2068 ei = PIXSTEP(1, 0, 0, 0);
2069 fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
2070 }
2071 en = lcd_dma.xres;
2072 fn = lcd_dma.yres;
2073 break;
2074 case 90:
2075 if (!lcd_dma.mirror) {
2076 top = PIXADDR(0, lcd_dma.yres - 1);
2077 bottom = PIXADDR(lcd_dma.xres - 1, 0);
2078 ei = PIXSTEP(0, 1, 0, 0);
2079 fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
2080 } else {
2081 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2082 bottom = PIXADDR(0, 0);
2083 ei = PIXSTEP(0, 1, 0, 0);
2084 fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
2085 }
2086 en = lcd_dma.yres;
2087 fn = lcd_dma.xres;
2088 break;
2089 case 180:
2090 if (!lcd_dma.mirror) {
2091 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2092 bottom = PIXADDR(0, 0);
2093 ei = PIXSTEP(1, 0, 0, 0);
2094 fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
2095 } else {
2096 top = PIXADDR(0, lcd_dma.yres - 1);
2097 bottom = PIXADDR(lcd_dma.xres - 1, 0);
2098 ei = PIXSTEP(0, 0, 1, 0);
2099 fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
2100 }
2101 en = lcd_dma.xres;
2102 fn = lcd_dma.yres;
2103 break;
2104 case 270:
2105 if (!lcd_dma.mirror) {
2106 top = PIXADDR(lcd_dma.xres - 1, 0);
2107 bottom = PIXADDR(0, lcd_dma.yres - 1);
2108 ei = PIXSTEP(0, 0, 0, 1);
2109 fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
2110 } else {
2111 top = PIXADDR(0, 0);
2112 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2113 ei = PIXSTEP(0, 0, 0, 1);
2114 fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
2115 }
2116 en = lcd_dma.yres;
2117 fn = lcd_dma.xres;
2118 break;
2119 default:
2120 BUG();
2121 return; /* Suppress warning about uninitialized vars */
2122 }
2123
2124 if (omap_dma_in_1510_mode()) {
2125 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
2126 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
2127 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
2128 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
2129
2130 return;
2131 }
2132
2133 /* 1610 regs */
2134 omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
2135 omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
2136 omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
2137 omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
2138
2139 omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
2140 omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
2141
2142 w = omap_readw(OMAP1610_DMA_LCD_CSDP);
2143 w &= ~0x03;
2144 w |= lcd_dma.data_type;
2145 omap_writew(w, OMAP1610_DMA_LCD_CSDP);
2146
2147 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2148 /* Always set the source port as SDRAM for now*/
2149 w &= ~(0x03 << 6);
2150 if (lcd_dma.callback != NULL)
2151 w |= 1 << 1; /* Block interrupt enable */
2152 else
2153 w &= ~(1 << 1);
2154 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2155
2156 if (!(lcd_dma.rotate || lcd_dma.mirror ||
2157 lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
2158 return;
2159
2160 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2161 /* Set the double-indexed addressing mode */
2162 w |= (0x03 << 12);
2163 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2164
2165 omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
2166 omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
2167 omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
2168 }
2169
2170 static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
2171 {
2172 u16 w;
2173
2174 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2175 if (unlikely(!(w & (1 << 3)))) {
2176 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
2177 return IRQ_NONE;
2178 }
2179 /* Ack the IRQ */
2180 w |= (1 << 3);
2181 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2182 lcd_dma.active = 0;
2183 if (lcd_dma.callback != NULL)
2184 lcd_dma.callback(w, lcd_dma.cb_data);
2185
2186 return IRQ_HANDLED;
2187 }
2188
2189 int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
2190 void *data)
2191 {
2192 spin_lock_irq(&lcd_dma.lock);
2193 if (lcd_dma.reserved) {
2194 spin_unlock_irq(&lcd_dma.lock);
2195 printk(KERN_ERR "LCD DMA channel already reserved\n");
2196 BUG();
2197 return -EBUSY;
2198 }
2199 lcd_dma.reserved = 1;
2200 spin_unlock_irq(&lcd_dma.lock);
2201 lcd_dma.callback = callback;
2202 lcd_dma.cb_data = data;
2203 lcd_dma.active = 0;
2204 lcd_dma.single_transfer = 0;
2205 lcd_dma.rotate = 0;
2206 lcd_dma.vxres = 0;
2207 lcd_dma.mirror = 0;
2208 lcd_dma.xscale = 0;
2209 lcd_dma.yscale = 0;
2210 lcd_dma.ext_ctrl = 0;
2211 lcd_dma.src_port = 0;
2212
2213 return 0;
2214 }
2215 EXPORT_SYMBOL(omap_request_lcd_dma);
2216
2217 void omap_free_lcd_dma(void)
2218 {
2219 spin_lock(&lcd_dma.lock);
2220 if (!lcd_dma.reserved) {
2221 spin_unlock(&lcd_dma.lock);
2222 printk(KERN_ERR "LCD DMA is not reserved\n");
2223 BUG();
2224 return;
2225 }
2226 if (!enable_1510_mode)
2227 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2228 OMAP1610_DMA_LCD_CCR);
2229 lcd_dma.reserved = 0;
2230 spin_unlock(&lcd_dma.lock);
2231 }
2232 EXPORT_SYMBOL(omap_free_lcd_dma);
2233
2234 void omap_enable_lcd_dma(void)
2235 {
2236 u16 w;
2237
2238 /*
2239 * Set the Enable bit only if an external controller is
2240 * connected. Otherwise the OMAP internal controller will
2241 * start the transfer when it gets enabled.
2242 */
2243 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2244 return;
2245
2246 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2247 w |= 1 << 8;
2248 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2249
2250 lcd_dma.active = 1;
2251
2252 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2253 w |= 1 << 7;
2254 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2255 }
2256 EXPORT_SYMBOL(omap_enable_lcd_dma);
2257
2258 void omap_setup_lcd_dma(void)
2259 {
2260 BUG_ON(lcd_dma.active);
2261 if (!enable_1510_mode) {
2262 /* Set some reasonable defaults */
2263 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2264 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2265 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2266 }
2267 set_b1_regs();
2268 if (!enable_1510_mode) {
2269 u16 w;
2270
2271 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2272 /*
2273 * If DMA was already active set the end_prog bit to have
2274 * the programmed register set loaded into the active
2275 * register set.
2276 */
2277 w |= 1 << 11; /* End_prog */
2278 if (!lcd_dma.single_transfer)
2279 w |= (3 << 8); /* Auto_init, repeat */
2280 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2281 }
2282 }
2283 EXPORT_SYMBOL(omap_setup_lcd_dma);
2284
2285 void omap_stop_lcd_dma(void)
2286 {
2287 u16 w;
2288
2289 lcd_dma.active = 0;
2290 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2291 return;
2292
2293 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2294 w &= ~(1 << 7);
2295 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2296
2297 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2298 w &= ~(1 << 8);
2299 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2300 }
2301 EXPORT_SYMBOL(omap_stop_lcd_dma);
2302
2303 /*----------------------------------------------------------------------------*/
2304
2305 static int __init omap_init_dma(void)
2306 {
2307 int ch, r;
2308
2309 if (cpu_class_is_omap1()) {
2310 omap_dma_base = IO_ADDRESS(OMAP1_DMA_BASE);
2311 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2312 } else if (cpu_is_omap24xx()) {
2313 omap_dma_base = IO_ADDRESS(OMAP24XX_DMA4_BASE);
2314 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2315 } else if (cpu_is_omap34xx()) {
2316 omap_dma_base = IO_ADDRESS(OMAP34XX_DMA4_BASE);
2317 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2318 } else {
2319 pr_err("DMA init failed for unsupported omap\n");
2320 return -ENODEV;
2321 }
2322
2323 dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2324 GFP_KERNEL);
2325 if (!dma_chan)
2326 return -ENOMEM;
2327
2328 if (cpu_class_is_omap2()) {
2329 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2330 dma_lch_count, GFP_KERNEL);
2331 if (!dma_linked_lch) {
2332 kfree(dma_chan);
2333 return -ENOMEM;
2334 }
2335 }
2336
2337 if (cpu_is_omap15xx()) {
2338 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2339 dma_chan_count = 9;
2340 enable_1510_mode = 1;
2341 } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
2342 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2343 dma_read(HW_ID));
2344 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2345 (dma_read(CAPS_0_U) << 16) |
2346 dma_read(CAPS_0_L),
2347 (dma_read(CAPS_1_U) << 16) |
2348 dma_read(CAPS_1_L),
2349 dma_read(CAPS_2), dma_read(CAPS_3),
2350 dma_read(CAPS_4));
2351 if (!enable_1510_mode) {
2352 u16 w;
2353
2354 /* Disable OMAP 3.0/3.1 compatibility mode. */
2355 w = dma_read(GSCR);
2356 w |= 1 << 3;
2357 dma_write(w, GSCR);
2358 dma_chan_count = 16;
2359 } else
2360 dma_chan_count = 9;
2361 if (cpu_is_omap16xx()) {
2362 u16 w;
2363
2364 /* this would prevent OMAP sleep */
2365 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2366 w &= ~(1 << 8);
2367 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2368 }
2369 } else if (cpu_class_is_omap2()) {
2370 u8 revision = dma_read(REVISION) & 0xff;
2371 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2372 revision >> 4, revision & 0xf);
2373 dma_chan_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2374 } else {
2375 dma_chan_count = 0;
2376 return 0;
2377 }
2378
2379 spin_lock_init(&lcd_dma.lock);
2380 spin_lock_init(&dma_chan_lock);
2381
2382 for (ch = 0; ch < dma_chan_count; ch++) {
2383 omap_clear_dma(ch);
2384 dma_chan[ch].dev_id = -1;
2385 dma_chan[ch].next_lch = -1;
2386
2387 if (ch >= 6 && enable_1510_mode)
2388 continue;
2389
2390 if (cpu_class_is_omap1()) {
2391 /*
2392 * request_irq() doesn't like dev_id (ie. ch) being
2393 * zero, so we have to kludge around this.
2394 */
2395 r = request_irq(omap1_dma_irq[ch],
2396 omap1_dma_irq_handler, 0, "DMA",
2397 (void *) (ch + 1));
2398 if (r != 0) {
2399 int i;
2400
2401 printk(KERN_ERR "unable to request IRQ %d "
2402 "for DMA (error %d)\n",
2403 omap1_dma_irq[ch], r);
2404 for (i = 0; i < ch; i++)
2405 free_irq(omap1_dma_irq[i],
2406 (void *) (i + 1));
2407 return r;
2408 }
2409 }
2410 }
2411
2412 if (cpu_is_omap2430() || cpu_is_omap34xx())
2413 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2414 DMA_DEFAULT_FIFO_DEPTH, 0);
2415
2416 if (cpu_class_is_omap2())
2417 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
2418
2419 /* FIXME: Update LCD DMA to work on 24xx */
2420 if (cpu_class_is_omap1()) {
2421 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2422 "LCD DMA", NULL);
2423 if (r != 0) {
2424 int i;
2425
2426 printk(KERN_ERR "unable to request IRQ for LCD DMA "
2427 "(error %d)\n", r);
2428 for (i = 0; i < dma_chan_count; i++)
2429 free_irq(omap1_dma_irq[i], (void *) (i + 1));
2430 return r;
2431 }
2432 }
2433
2434 return 0;
2435 }
2436
2437 arch_initcall(omap_init_dma);
2438
2439
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