1 #include "amd64_edac.h"
4 static struct edac_pci_ctl_info
*amd64_ctl_pci
;
6 static int report_gart_errors
;
7 module_param(report_gart_errors
, int, 0644);
10 * Set by command line parameter. If BIOS has enabled the ECC, this override is
11 * cleared to prevent re-enabling the hardware by this driver.
13 static int ecc_enable_override
;
14 module_param(ecc_enable_override
, int, 0644);
16 /* Lookup table for all possible MC control instances */
18 static struct mem_ctl_info
*mci_lookup
[MAX_NUMNODES
];
19 static struct amd64_pvt
*pvt_lookup
[MAX_NUMNODES
];
22 * Memory scrubber control interface. For K8, memory scrubbing is handled by
23 * hardware and can involve L2 cache, dcache as well as the main memory. With
24 * F10, this is extended to L3 cache scrubbing on CPU models sporting that
27 * This causes the "units" for the scrubbing speed to vary from 64 byte blocks
28 * (dram) over to cache lines. This is nasty, so we will use bandwidth in
29 * bytes/sec for the setting.
31 * Currently, we only do dram scrubbing. If the scrubbing is done in software on
32 * other archs, we might not have access to the caches directly.
36 * scan the scrub rate mapping table for a close or matching bandwidth value to
37 * issue. If requested is too big, then use last maximum value found.
39 static int amd64_search_set_scrub_rate(struct pci_dev
*ctl
, u32 new_bw
,
46 * map the configured rate (new_bw) to a value specific to the AMD64
47 * memory controller and apply to register. Search for the first
48 * bandwidth entry that is greater or equal than the setting requested
49 * and program that. If at last entry, turn off DRAM scrubbing.
51 for (i
= 0; i
< ARRAY_SIZE(scrubrates
); i
++) {
53 * skip scrub rates which aren't recommended
54 * (see F10 BKDG, F3x58)
56 if (scrubrates
[i
].scrubval
< min_scrubrate
)
59 if (scrubrates
[i
].bandwidth
<= new_bw
)
63 * if no suitable bandwidth found, turn off DRAM scrubbing
64 * entirely by falling back to the last element in the
69 scrubval
= scrubrates
[i
].scrubval
;
71 edac_printk(KERN_DEBUG
, EDAC_MC
,
72 "Setting scrub rate bandwidth: %u\n",
73 scrubrates
[i
].bandwidth
);
75 edac_printk(KERN_DEBUG
, EDAC_MC
, "Turning scrubbing off.\n");
77 pci_write_bits32(ctl
, K8_SCRCTRL
, scrubval
, 0x001F);
82 static int amd64_set_scrub_rate(struct mem_ctl_info
*mci
, u32
*bandwidth
)
84 struct amd64_pvt
*pvt
= mci
->pvt_info
;
85 u32 min_scrubrate
= 0x0;
87 switch (boot_cpu_data
.x86
) {
89 min_scrubrate
= K8_MIN_SCRUB_RATE_BITS
;
92 min_scrubrate
= F10_MIN_SCRUB_RATE_BITS
;
95 min_scrubrate
= F11_MIN_SCRUB_RATE_BITS
;
99 amd64_printk(KERN_ERR
, "Unsupported family!\n");
102 return amd64_search_set_scrub_rate(pvt
->misc_f3_ctl
, *bandwidth
,
106 static int amd64_get_scrub_rate(struct mem_ctl_info
*mci
, u32
*bw
)
108 struct amd64_pvt
*pvt
= mci
->pvt_info
;
110 int status
= -1, i
, ret
= 0;
112 ret
= pci_read_config_dword(pvt
->misc_f3_ctl
, K8_SCRCTRL
, &scrubval
);
114 debugf0("Reading K8_SCRCTRL failed\n");
116 scrubval
= scrubval
& 0x001F;
118 edac_printk(KERN_DEBUG
, EDAC_MC
,
119 "pci-read, sdram scrub control value: %d \n", scrubval
);
121 for (i
= 0; ARRAY_SIZE(scrubrates
); i
++) {
122 if (scrubrates
[i
].scrubval
== scrubval
) {
123 *bw
= scrubrates
[i
].bandwidth
;
132 /* Map from a CSROW entry to the mask entry that operates on it */
133 static inline u32
amd64_map_to_dcs_mask(struct amd64_pvt
*pvt
, int csrow
)
135 return csrow
>> (pvt
->num_dcsm
>> 3);
138 /* return the 'base' address the i'th CS entry of the 'dct' DRAM controller */
139 static u32
amd64_get_dct_base(struct amd64_pvt
*pvt
, int dct
, int csrow
)
142 return pvt
->dcsb0
[csrow
];
144 return pvt
->dcsb1
[csrow
];
148 * Return the 'mask' address the i'th CS entry. This function is needed because
149 * there number of DCSM registers on Rev E and prior vs Rev F and later is
152 static u32
amd64_get_dct_mask(struct amd64_pvt
*pvt
, int dct
, int csrow
)
155 return pvt
->dcsm0
[amd64_map_to_dcs_mask(pvt
, csrow
)];
157 return pvt
->dcsm1
[amd64_map_to_dcs_mask(pvt
, csrow
)];
162 * In *base and *limit, pass back the full 40-bit base and limit physical
163 * addresses for the node given by node_id. This information is obtained from
164 * DRAM Base (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers. The
165 * base and limit addresses are of type SysAddr, as defined at the start of
166 * section 3.4.4 (p. 70). They are the lowest and highest physical addresses
167 * in the address range they represent.
169 static void amd64_get_base_and_limit(struct amd64_pvt
*pvt
, int node_id
,
170 u64
*base
, u64
*limit
)
172 *base
= pvt
->dram_base
[node_id
];
173 *limit
= pvt
->dram_limit
[node_id
];
177 * Return 1 if the SysAddr given by sys_addr matches the base/limit associated
180 static int amd64_base_limit_match(struct amd64_pvt
*pvt
,
181 u64 sys_addr
, int node_id
)
183 u64 base
, limit
, addr
;
185 amd64_get_base_and_limit(pvt
, node_id
, &base
, &limit
);
187 /* The K8 treats this as a 40-bit value. However, bits 63-40 will be
188 * all ones if the most significant implemented address bit is 1.
189 * Here we discard bits 63-40. See section 3.4.2 of AMD publication
190 * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1
191 * Application Programming.
193 addr
= sys_addr
& 0x000000ffffffffffull
;
195 return (addr
>= base
) && (addr
<= limit
);
199 * Attempt to map a SysAddr to a node. On success, return a pointer to the
200 * mem_ctl_info structure for the node that the SysAddr maps to.
202 * On failure, return NULL.
204 static struct mem_ctl_info
*find_mc_by_sys_addr(struct mem_ctl_info
*mci
,
207 struct amd64_pvt
*pvt
;
212 * Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section
213 * 3.4.4.2) registers to map the SysAddr to a node ID.
218 * The value of this field should be the same for all DRAM Base
219 * registers. Therefore we arbitrarily choose to read it from the
220 * register for node 0.
222 intlv_en
= pvt
->dram_IntlvEn
[0];
225 for (node_id
= 0; ; ) {
226 if (amd64_base_limit_match(pvt
, sys_addr
, node_id
))
229 if (++node_id
>= DRAM_REG_COUNT
)
235 if (unlikely((intlv_en
!= (0x01 << 8)) &&
236 (intlv_en
!= (0x03 << 8)) &&
237 (intlv_en
!= (0x07 << 8)))) {
238 amd64_printk(KERN_WARNING
, "junk value of 0x%x extracted from "
239 "IntlvEn field of DRAM Base Register for node 0: "
240 "This probably indicates a BIOS bug.\n", intlv_en
);
244 bits
= (((u32
) sys_addr
) >> 12) & intlv_en
;
246 for (node_id
= 0; ; ) {
247 if ((pvt
->dram_limit
[node_id
] & intlv_en
) == bits
)
248 break; /* intlv_sel field matches */
250 if (++node_id
>= DRAM_REG_COUNT
)
254 /* sanity test for sys_addr */
255 if (unlikely(!amd64_base_limit_match(pvt
, sys_addr
, node_id
))) {
256 amd64_printk(KERN_WARNING
,
257 "%s(): sys_addr 0x%lx falls outside base/limit "
258 "address range for node %d with node interleaving "
259 "enabled.\n", __func__
, (unsigned long)sys_addr
,
265 return edac_mc_find(node_id
);
268 debugf2("sys_addr 0x%lx doesn't match any node\n",
269 (unsigned long)sys_addr
);
275 * Extract the DRAM CS base address from selected csrow register.
277 static u64
base_from_dct_base(struct amd64_pvt
*pvt
, int csrow
)
279 return ((u64
) (amd64_get_dct_base(pvt
, 0, csrow
) & pvt
->dcsb_base
)) <<
284 * Extract the mask from the dcsb0[csrow] entry in a CPU revision-specific way.
286 static u64
mask_from_dct_mask(struct amd64_pvt
*pvt
, int csrow
)
288 u64 dcsm_bits
, other_bits
;
291 /* Extract bits from DRAM CS Mask. */
292 dcsm_bits
= amd64_get_dct_mask(pvt
, 0, csrow
) & pvt
->dcsm_mask
;
294 other_bits
= pvt
->dcsm_mask
;
295 other_bits
= ~(other_bits
<< pvt
->dcs_shift
);
298 * The extracted bits from DCSM belong in the spaces represented by
299 * the cleared bits in other_bits.
301 mask
= (dcsm_bits
<< pvt
->dcs_shift
) | other_bits
;
307 * @input_addr is an InputAddr associated with the node given by mci. Return the
308 * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr).
310 static int input_addr_to_csrow(struct mem_ctl_info
*mci
, u64 input_addr
)
312 struct amd64_pvt
*pvt
;
319 * Here we use the DRAM CS Base and DRAM CS Mask registers. For each CS
320 * base/mask register pair, test the condition shown near the start of
321 * section 3.5.4 (p. 84, BKDG #26094, K8, revA-E).
323 for (csrow
= 0; csrow
< CHIPSELECT_COUNT
; csrow
++) {
325 /* This DRAM chip select is disabled on this node */
326 if ((pvt
->dcsb0
[csrow
] & K8_DCSB_CS_ENABLE
) == 0)
329 base
= base_from_dct_base(pvt
, csrow
);
330 mask
= ~mask_from_dct_mask(pvt
, csrow
);
332 if ((input_addr
& mask
) == (base
& mask
)) {
333 debugf2("InputAddr 0x%lx matches csrow %d (node %d)\n",
334 (unsigned long)input_addr
, csrow
,
341 debugf2("no matching csrow for InputAddr 0x%lx (MC node %d)\n",
342 (unsigned long)input_addr
, pvt
->mc_node_id
);
348 * Return the base value defined by the DRAM Base register for the node
349 * represented by mci. This function returns the full 40-bit value despite the
350 * fact that the register only stores bits 39-24 of the value. See section
351 * 3.4.4.1 (BKDG #26094, K8, revA-E)
353 static inline u64
get_dram_base(struct mem_ctl_info
*mci
)
355 struct amd64_pvt
*pvt
= mci
->pvt_info
;
357 return pvt
->dram_base
[pvt
->mc_node_id
];
361 * Obtain info from the DRAM Hole Address Register (section 3.4.8, pub #26094)
362 * for the node represented by mci. Info is passed back in *hole_base,
363 * *hole_offset, and *hole_size. Function returns 0 if info is valid or 1 if
364 * info is invalid. Info may be invalid for either of the following reasons:
366 * - The revision of the node is not E or greater. In this case, the DRAM Hole
367 * Address Register does not exist.
369 * - The DramHoleValid bit is cleared in the DRAM Hole Address Register,
370 * indicating that its contents are not valid.
372 * The values passed back in *hole_base, *hole_offset, and *hole_size are
373 * complete 32-bit values despite the fact that the bitfields in the DHAR
374 * only represent bits 31-24 of the base and offset values.
376 int amd64_get_dram_hole_info(struct mem_ctl_info
*mci
, u64
*hole_base
,
377 u64
*hole_offset
, u64
*hole_size
)
379 struct amd64_pvt
*pvt
= mci
->pvt_info
;
382 /* only revE and later have the DRAM Hole Address Register */
383 if (boot_cpu_data
.x86
== 0xf && pvt
->ext_model
< OPTERON_CPU_REV_E
) {
384 debugf1(" revision %d for node %d does not support DHAR\n",
385 pvt
->ext_model
, pvt
->mc_node_id
);
389 /* only valid for Fam10h */
390 if (boot_cpu_data
.x86
== 0x10 &&
391 (pvt
->dhar
& F10_DRAM_MEM_HOIST_VALID
) == 0) {
392 debugf1(" Dram Memory Hoisting is DISABLED on this system\n");
396 if ((pvt
->dhar
& DHAR_VALID
) == 0) {
397 debugf1(" Dram Memory Hoisting is DISABLED on this node %d\n",
402 /* This node has Memory Hoisting */
404 /* +------------------+--------------------+--------------------+-----
405 * | memory | DRAM hole | relocated |
406 * | [0, (x - 1)] | [x, 0xffffffff] | addresses from |
408 * | | | [0x100000000, |
409 * | | | (0x100000000+ |
410 * | | | (0xffffffff-x))] |
411 * +------------------+--------------------+--------------------+-----
413 * Above is a diagram of physical memory showing the DRAM hole and the
414 * relocated addresses from the DRAM hole. As shown, the DRAM hole
415 * starts at address x (the base address) and extends through address
416 * 0xffffffff. The DRAM Hole Address Register (DHAR) relocates the
417 * addresses in the hole so that they start at 0x100000000.
420 base
= dhar_base(pvt
->dhar
);
423 *hole_size
= (0x1ull
<< 32) - base
;
425 if (boot_cpu_data
.x86
> 0xf)
426 *hole_offset
= f10_dhar_offset(pvt
->dhar
);
428 *hole_offset
= k8_dhar_offset(pvt
->dhar
);
430 debugf1(" DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n",
431 pvt
->mc_node_id
, (unsigned long)*hole_base
,
432 (unsigned long)*hole_offset
, (unsigned long)*hole_size
);
436 EXPORT_SYMBOL_GPL(amd64_get_dram_hole_info
);
439 * Return the DramAddr that the SysAddr given by @sys_addr maps to. It is
440 * assumed that sys_addr maps to the node given by mci.
442 * The first part of section 3.4.4 (p. 70) shows how the DRAM Base (section
443 * 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are used to translate a
444 * SysAddr to a DramAddr. If the DRAM Hole Address Register (DHAR) is enabled,
445 * then it is also involved in translating a SysAddr to a DramAddr. Sections
446 * 3.4.8 and 3.5.8.2 describe the DHAR and how it is used for memory hoisting.
447 * These parts of the documentation are unclear. I interpret them as follows:
449 * When node n receives a SysAddr, it processes the SysAddr as follows:
451 * 1. It extracts the DRAMBase and DRAMLimit values from the DRAM Base and DRAM
452 * Limit registers for node n. If the SysAddr is not within the range
453 * specified by the base and limit values, then node n ignores the Sysaddr
454 * (since it does not map to node n). Otherwise continue to step 2 below.
456 * 2. If the DramHoleValid bit of the DHAR for node n is clear, the DHAR is
457 * disabled so skip to step 3 below. Otherwise see if the SysAddr is within
458 * the range of relocated addresses (starting at 0x100000000) from the DRAM
459 * hole. If not, skip to step 3 below. Else get the value of the
460 * DramHoleOffset field from the DHAR. To obtain the DramAddr, subtract the
461 * offset defined by this value from the SysAddr.
463 * 3. Obtain the base address for node n from the DRAMBase field of the DRAM
464 * Base register for node n. To obtain the DramAddr, subtract the base
465 * address from the SysAddr, as shown near the start of section 3.4.4 (p.70).
467 static u64
sys_addr_to_dram_addr(struct mem_ctl_info
*mci
, u64 sys_addr
)
469 u64 dram_base
, hole_base
, hole_offset
, hole_size
, dram_addr
;
472 dram_base
= get_dram_base(mci
);
474 ret
= amd64_get_dram_hole_info(mci
, &hole_base
, &hole_offset
,
477 if ((sys_addr
>= (1ull << 32)) &&
478 (sys_addr
< ((1ull << 32) + hole_size
))) {
479 /* use DHAR to translate SysAddr to DramAddr */
480 dram_addr
= sys_addr
- hole_offset
;
482 debugf2("using DHAR to translate SysAddr 0x%lx to "
484 (unsigned long)sys_addr
,
485 (unsigned long)dram_addr
);
492 * Translate the SysAddr to a DramAddr as shown near the start of
493 * section 3.4.4 (p. 70). Although sys_addr is a 64-bit value, the k8
494 * only deals with 40-bit values. Therefore we discard bits 63-40 of
495 * sys_addr below. If bit 39 of sys_addr is 1 then the bits we
496 * discard are all 1s. Otherwise the bits we discard are all 0s. See
497 * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture
498 * Programmer's Manual Volume 1 Application Programming.
500 dram_addr
= (sys_addr
& 0xffffffffffull
) - dram_base
;
502 debugf2("using DRAM Base register to translate SysAddr 0x%lx to "
503 "DramAddr 0x%lx\n", (unsigned long)sys_addr
,
504 (unsigned long)dram_addr
);
509 * @intlv_en is the value of the IntlvEn field from a DRAM Base register
510 * (section 3.4.4.1). Return the number of bits from a SysAddr that are used
511 * for node interleaving.
513 static int num_node_interleave_bits(unsigned intlv_en
)
515 static const int intlv_shift_table
[] = { 0, 1, 0, 2, 0, 0, 0, 3 };
518 BUG_ON(intlv_en
> 7);
519 n
= intlv_shift_table
[intlv_en
];
523 /* Translate the DramAddr given by @dram_addr to an InputAddr. */
524 static u64
dram_addr_to_input_addr(struct mem_ctl_info
*mci
, u64 dram_addr
)
526 struct amd64_pvt
*pvt
;
533 * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E)
534 * concerning translating a DramAddr to an InputAddr.
536 intlv_shift
= num_node_interleave_bits(pvt
->dram_IntlvEn
[0]);
537 input_addr
= ((dram_addr
>> intlv_shift
) & 0xffffff000ull
) +
540 debugf2(" Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n",
541 intlv_shift
, (unsigned long)dram_addr
,
542 (unsigned long)input_addr
);
548 * Translate the SysAddr represented by @sys_addr to an InputAddr. It is
549 * assumed that @sys_addr maps to the node given by mci.
551 static u64
sys_addr_to_input_addr(struct mem_ctl_info
*mci
, u64 sys_addr
)
556 dram_addr_to_input_addr(mci
, sys_addr_to_dram_addr(mci
, sys_addr
));
558 debugf2("SysAdddr 0x%lx translates to InputAddr 0x%lx\n",
559 (unsigned long)sys_addr
, (unsigned long)input_addr
);
566 * @input_addr is an InputAddr associated with the node represented by mci.
567 * Translate @input_addr to a DramAddr and return the result.
569 static u64
input_addr_to_dram_addr(struct mem_ctl_info
*mci
, u64 input_addr
)
571 struct amd64_pvt
*pvt
;
572 int node_id
, intlv_shift
;
577 * Near the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E)
578 * shows how to translate a DramAddr to an InputAddr. Here we reverse
579 * this procedure. When translating from a DramAddr to an InputAddr, the
580 * bits used for node interleaving are discarded. Here we recover these
581 * bits from the IntlvSel field of the DRAM Limit register (section
582 * 3.4.4.2) for the node that input_addr is associated with.
585 node_id
= pvt
->mc_node_id
;
586 BUG_ON((node_id
< 0) || (node_id
> 7));
588 intlv_shift
= num_node_interleave_bits(pvt
->dram_IntlvEn
[0]);
590 if (intlv_shift
== 0) {
591 debugf1(" InputAddr 0x%lx translates to DramAddr of "
592 "same value\n", (unsigned long)input_addr
);
597 bits
= ((input_addr
& 0xffffff000ull
) << intlv_shift
) +
598 (input_addr
& 0xfff);
600 intlv_sel
= pvt
->dram_IntlvSel
[node_id
] & ((1 << intlv_shift
) - 1);
601 dram_addr
= bits
+ (intlv_sel
<< 12);
603 debugf1("InputAddr 0x%lx translates to DramAddr 0x%lx "
604 "(%d node interleave bits)\n", (unsigned long)input_addr
,
605 (unsigned long)dram_addr
, intlv_shift
);
611 * @dram_addr is a DramAddr that maps to the node represented by mci. Convert
612 * @dram_addr to a SysAddr.
614 static u64
dram_addr_to_sys_addr(struct mem_ctl_info
*mci
, u64 dram_addr
)
616 struct amd64_pvt
*pvt
= mci
->pvt_info
;
617 u64 hole_base
, hole_offset
, hole_size
, base
, limit
, sys_addr
;
620 ret
= amd64_get_dram_hole_info(mci
, &hole_base
, &hole_offset
,
623 if ((dram_addr
>= hole_base
) &&
624 (dram_addr
< (hole_base
+ hole_size
))) {
625 sys_addr
= dram_addr
+ hole_offset
;
627 debugf1("using DHAR to translate DramAddr 0x%lx to "
628 "SysAddr 0x%lx\n", (unsigned long)dram_addr
,
629 (unsigned long)sys_addr
);
635 amd64_get_base_and_limit(pvt
, pvt
->mc_node_id
, &base
, &limit
);
636 sys_addr
= dram_addr
+ base
;
639 * The sys_addr we have computed up to this point is a 40-bit value
640 * because the k8 deals with 40-bit values. However, the value we are
641 * supposed to return is a full 64-bit physical address. The AMD
642 * x86-64 architecture specifies that the most significant implemented
643 * address bit through bit 63 of a physical address must be either all
644 * 0s or all 1s. Therefore we sign-extend the 40-bit sys_addr to a
645 * 64-bit value below. See section 3.4.2 of AMD publication 24592:
646 * AMD x86-64 Architecture Programmer's Manual Volume 1 Application
649 sys_addr
|= ~((sys_addr
& (1ull << 39)) - 1);
651 debugf1(" Node %d, DramAddr 0x%lx to SysAddr 0x%lx\n",
652 pvt
->mc_node_id
, (unsigned long)dram_addr
,
653 (unsigned long)sys_addr
);
659 * @input_addr is an InputAddr associated with the node given by mci. Translate
660 * @input_addr to a SysAddr.
662 static inline u64
input_addr_to_sys_addr(struct mem_ctl_info
*mci
,
665 return dram_addr_to_sys_addr(mci
,
666 input_addr_to_dram_addr(mci
, input_addr
));
670 * Find the minimum and maximum InputAddr values that map to the given @csrow.
671 * Pass back these values in *input_addr_min and *input_addr_max.
673 static void find_csrow_limits(struct mem_ctl_info
*mci
, int csrow
,
674 u64
*input_addr_min
, u64
*input_addr_max
)
676 struct amd64_pvt
*pvt
;
680 BUG_ON((csrow
< 0) || (csrow
>= CHIPSELECT_COUNT
));
682 base
= base_from_dct_base(pvt
, csrow
);
683 mask
= mask_from_dct_mask(pvt
, csrow
);
685 *input_addr_min
= base
& ~mask
;
686 *input_addr_max
= base
| mask
| pvt
->dcs_mask_notused
;
690 * Extract error address from MCA NB Address Low (section 3.6.4.5) and MCA NB
691 * Address High (section 3.6.4.6) register values and return the result. Address
692 * is located in the info structure (nbeah and nbeal), the encoding is device
695 static u64
extract_error_address(struct mem_ctl_info
*mci
,
696 struct amd64_error_info_regs
*info
)
698 struct amd64_pvt
*pvt
= mci
->pvt_info
;
700 return pvt
->ops
->get_error_address(mci
, info
);
704 /* Map the Error address to a PAGE and PAGE OFFSET. */
705 static inline void error_address_to_page_and_offset(u64 error_address
,
706 u32
*page
, u32
*offset
)
708 *page
= (u32
) (error_address
>> PAGE_SHIFT
);
709 *offset
= ((u32
) error_address
) & ~PAGE_MASK
;
713 * @sys_addr is an error address (a SysAddr) extracted from the MCA NB Address
714 * Low (section 3.6.4.5) and MCA NB Address High (section 3.6.4.6) registers
715 * of a node that detected an ECC memory error. mci represents the node that
716 * the error address maps to (possibly different from the node that detected
717 * the error). Return the number of the csrow that sys_addr maps to, or -1 on
720 static int sys_addr_to_csrow(struct mem_ctl_info
*mci
, u64 sys_addr
)
724 csrow
= input_addr_to_csrow(mci
, sys_addr_to_input_addr(mci
, sys_addr
));
727 amd64_mc_printk(mci
, KERN_ERR
,
728 "Failed to translate InputAddr to csrow for "
729 "address 0x%lx\n", (unsigned long)sys_addr
);
733 static int get_channel_from_ecc_syndrome(unsigned short syndrome
);
735 static void amd64_cpu_display_info(struct amd64_pvt
*pvt
)
737 if (boot_cpu_data
.x86
== 0x11)
738 edac_printk(KERN_DEBUG
, EDAC_MC
, "F11h CPU detected\n");
739 else if (boot_cpu_data
.x86
== 0x10)
740 edac_printk(KERN_DEBUG
, EDAC_MC
, "F10h CPU detected\n");
741 else if (boot_cpu_data
.x86
== 0xf)
742 edac_printk(KERN_DEBUG
, EDAC_MC
, "%s detected\n",
743 (pvt
->ext_model
>= OPTERON_CPU_REV_F
) ?
744 "Rev F or later" : "Rev E or earlier");
746 /* we'll hardly ever ever get here */
747 edac_printk(KERN_ERR
, EDAC_MC
, "Unknown cpu!\n");
751 * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs
754 static enum edac_type
amd64_determine_edac_cap(struct amd64_pvt
*pvt
)
757 enum dev_type edac_cap
= EDAC_FLAG_NONE
;
759 bit
= (boot_cpu_data
.x86
> 0xf || pvt
->ext_model
>= OPTERON_CPU_REV_F
)
763 if (pvt
->dclr0
& BIT(bit
))
764 edac_cap
= EDAC_FLAG_SECDED
;
770 static void f10_debug_display_dimm_sizes(int ctrl
, struct amd64_pvt
*pvt
,
773 /* Display and decode various NB registers for debug purposes. */
774 static void amd64_dump_misc_regs(struct amd64_pvt
*pvt
)
778 debugf1(" nbcap:0x%8.08x DctDualCap=%s DualNode=%s 8-Node=%s\n",
780 (pvt
->nbcap
& K8_NBCAP_DCT_DUAL
) ? "True" : "False",
781 (pvt
->nbcap
& K8_NBCAP_DUAL_NODE
) ? "True" : "False",
782 (pvt
->nbcap
& K8_NBCAP_8_NODE
) ? "True" : "False");
783 debugf1(" ECC Capable=%s ChipKill Capable=%s\n",
784 (pvt
->nbcap
& K8_NBCAP_SECDED
) ? "True" : "False",
785 (pvt
->nbcap
& K8_NBCAP_CHIPKILL
) ? "True" : "False");
786 debugf1(" DramCfg0-low=0x%08x DIMM-ECC=%s Parity=%s Width=%s\n",
788 (pvt
->dclr0
& BIT(19)) ? "Enabled" : "Disabled",
789 (pvt
->dclr0
& BIT(8)) ? "Enabled" : "Disabled",
790 (pvt
->dclr0
& BIT(11)) ? "128b" : "64b");
791 debugf1(" DIMM x4 Present: L0=%s L1=%s L2=%s L3=%s DIMM Type=%s\n",
792 (pvt
->dclr0
& BIT(12)) ? "Y" : "N",
793 (pvt
->dclr0
& BIT(13)) ? "Y" : "N",
794 (pvt
->dclr0
& BIT(14)) ? "Y" : "N",
795 (pvt
->dclr0
& BIT(15)) ? "Y" : "N",
796 (pvt
->dclr0
& BIT(16)) ? "UN-Buffered" : "Buffered");
799 debugf1(" online-spare: 0x%8.08x\n", pvt
->online_spare
);
801 if (boot_cpu_data
.x86
== 0xf) {
802 debugf1(" dhar: 0x%8.08x Base=0x%08x Offset=0x%08x\n",
803 pvt
->dhar
, dhar_base(pvt
->dhar
),
804 k8_dhar_offset(pvt
->dhar
));
805 debugf1(" DramHoleValid=%s\n",
806 (pvt
->dhar
& DHAR_VALID
) ? "True" : "False");
808 debugf1(" dbam-dkt: 0x%8.08x\n", pvt
->dbam0
);
810 /* everything below this point is Fam10h and above */
814 debugf1(" dhar: 0x%8.08x Base=0x%08x Offset=0x%08x\n",
815 pvt
->dhar
, dhar_base(pvt
->dhar
),
816 f10_dhar_offset(pvt
->dhar
));
817 debugf1(" DramMemHoistValid=%s DramHoleValid=%s\n",
818 (pvt
->dhar
& F10_DRAM_MEM_HOIST_VALID
) ?
820 (pvt
->dhar
& DHAR_VALID
) ?
824 /* Only if NOT ganged does dcl1 have valid info */
825 if (!dct_ganging_enabled(pvt
)) {
826 debugf1(" DramCfg1-low=0x%08x DIMM-ECC=%s Parity=%s "
827 "Width=%s\n", pvt
->dclr1
,
828 (pvt
->dclr1
& BIT(19)) ? "Enabled" : "Disabled",
829 (pvt
->dclr1
& BIT(8)) ? "Enabled" : "Disabled",
830 (pvt
->dclr1
& BIT(11)) ? "128b" : "64b");
831 debugf1(" DIMM x4 Present: L0=%s L1=%s L2=%s L3=%s "
833 (pvt
->dclr1
& BIT(12)) ? "Y" : "N",
834 (pvt
->dclr1
& BIT(13)) ? "Y" : "N",
835 (pvt
->dclr1
& BIT(14)) ? "Y" : "N",
836 (pvt
->dclr1
& BIT(15)) ? "Y" : "N",
837 (pvt
->dclr1
& BIT(16)) ? "UN-Buffered" : "Buffered");
841 * Determine if ganged and then dump memory sizes for first controller,
842 * and if NOT ganged dump info for 2nd controller.
844 ganged
= dct_ganging_enabled(pvt
);
846 f10_debug_display_dimm_sizes(0, pvt
, ganged
);
849 f10_debug_display_dimm_sizes(1, pvt
, ganged
);
852 /* Read in both of DBAM registers */
853 static void amd64_read_dbam_reg(struct amd64_pvt
*pvt
)
859 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, reg
, &pvt
->dbam0
);
863 if (boot_cpu_data
.x86
>= 0x10) {
865 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, reg
, &pvt
->dbam1
);
874 debugf0("Error reading F2x%03x.\n", reg
);
878 * NOTE: CPU Revision Dependent code: Rev E and Rev F
880 * Set the DCSB and DCSM mask values depending on the CPU revision value. Also
881 * set the shift factor for the DCSB and DCSM values.
883 * ->dcs_mask_notused, RevE:
885 * To find the max InputAddr for the csrow, start with the base address and set
886 * all bits that are "don't care" bits in the test at the start of section
889 * The "don't care" bits are all set bits in the mask and all bits in the gaps
890 * between bit ranges [35:25] and [19:13]. The value REV_E_DCS_NOTUSED_BITS
891 * represents bits [24:20] and [12:0], which are all bits in the above-mentioned
894 * ->dcs_mask_notused, RevF and later:
896 * To find the max InputAddr for the csrow, start with the base address and set
897 * all bits that are "don't care" bits in the test at the start of NPT section
900 * The "don't care" bits are all set bits in the mask and all bits in the gaps
901 * between bit ranges [36:27] and [21:13].
903 * The value REV_F_F1Xh_DCS_NOTUSED_BITS represents bits [26:22] and [12:0],
904 * which are all bits in the above-mentioned gaps.
906 static void amd64_set_dct_base_and_mask(struct amd64_pvt
*pvt
)
908 if (pvt
->ext_model
>= OPTERON_CPU_REV_F
) {
909 pvt
->dcsb_base
= REV_F_F1Xh_DCSB_BASE_BITS
;
910 pvt
->dcsm_mask
= REV_F_F1Xh_DCSM_MASK_BITS
;
911 pvt
->dcs_mask_notused
= REV_F_F1Xh_DCS_NOTUSED_BITS
;
912 pvt
->dcs_shift
= REV_F_F1Xh_DCS_SHIFT
;
914 switch (boot_cpu_data
.x86
) {
916 pvt
->num_dcsm
= REV_F_DCSM_COUNT
;
920 pvt
->num_dcsm
= F10_DCSM_COUNT
;
924 pvt
->num_dcsm
= F11_DCSM_COUNT
;
928 amd64_printk(KERN_ERR
, "Unsupported family!\n");
932 pvt
->dcsb_base
= REV_E_DCSB_BASE_BITS
;
933 pvt
->dcsm_mask
= REV_E_DCSM_MASK_BITS
;
934 pvt
->dcs_mask_notused
= REV_E_DCS_NOTUSED_BITS
;
935 pvt
->dcs_shift
= REV_E_DCS_SHIFT
;
936 pvt
->num_dcsm
= REV_E_DCSM_COUNT
;
941 * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask hw registers
943 static void amd64_read_dct_base_mask(struct amd64_pvt
*pvt
)
945 int cs
, reg
, err
= 0;
947 amd64_set_dct_base_and_mask(pvt
);
949 for (cs
= 0; cs
< CHIPSELECT_COUNT
; cs
++) {
950 reg
= K8_DCSB0
+ (cs
* 4);
951 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, reg
,
954 debugf0("Reading K8_DCSB0[%d] failed\n", cs
);
956 debugf0(" DCSB0[%d]=0x%08x reg: F2x%x\n",
957 cs
, pvt
->dcsb0
[cs
], reg
);
959 /* If DCT are NOT ganged, then read in DCT1's base */
960 if (boot_cpu_data
.x86
>= 0x10 && !dct_ganging_enabled(pvt
)) {
961 reg
= F10_DCSB1
+ (cs
* 4);
962 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, reg
,
965 debugf0("Reading F10_DCSB1[%d] failed\n", cs
);
967 debugf0(" DCSB1[%d]=0x%08x reg: F2x%x\n",
968 cs
, pvt
->dcsb1
[cs
], reg
);
974 for (cs
= 0; cs
< pvt
->num_dcsm
; cs
++) {
975 reg
= K8_DCSM0
+ (cs
* 4);
976 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, reg
,
979 debugf0("Reading K8_DCSM0 failed\n");
981 debugf0(" DCSM0[%d]=0x%08x reg: F2x%x\n",
982 cs
, pvt
->dcsm0
[cs
], reg
);
984 /* If DCT are NOT ganged, then read in DCT1's mask */
985 if (boot_cpu_data
.x86
>= 0x10 && !dct_ganging_enabled(pvt
)) {
986 reg
= F10_DCSM1
+ (cs
* 4);
987 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, reg
,
990 debugf0("Reading F10_DCSM1[%d] failed\n", cs
);
992 debugf0(" DCSM1[%d]=0x%08x reg: F2x%x\n",
993 cs
, pvt
->dcsm1
[cs
], reg
);
999 static enum mem_type
amd64_determine_memory_type(struct amd64_pvt
*pvt
)
1003 if (boot_cpu_data
.x86
>= 0x10 || pvt
->ext_model
>= OPTERON_CPU_REV_F
) {
1004 /* Rev F and later */
1005 type
= (pvt
->dclr0
& BIT(16)) ? MEM_DDR2
: MEM_RDDR2
;
1007 /* Rev E and earlier */
1008 type
= (pvt
->dclr0
& BIT(18)) ? MEM_DDR
: MEM_RDDR
;
1011 debugf1(" Memory type is: %s\n",
1012 (type
== MEM_DDR2
) ? "MEM_DDR2" :
1013 (type
== MEM_RDDR2
) ? "MEM_RDDR2" :
1014 (type
== MEM_DDR
) ? "MEM_DDR" : "MEM_RDDR");
1020 * Read the DRAM Configuration Low register. It differs between CG, D & E revs
1021 * and the later RevF memory controllers (DDR vs DDR2)
1024 * number of memory channels in operation
1026 * contents of the DCL0_LOW register
1028 static int k8_early_channel_count(struct amd64_pvt
*pvt
)
1032 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, F10_DCLR_0
, &pvt
->dclr0
);
1036 if ((boot_cpu_data
.x86_model
>> 4) >= OPTERON_CPU_REV_F
) {
1037 /* RevF (NPT) and later */
1038 flag
= pvt
->dclr0
& F10_WIDTH_128
;
1040 /* RevE and earlier */
1041 flag
= pvt
->dclr0
& REVE_WIDTH_128
;
1047 return (flag
) ? 2 : 1;
1050 /* extract the ERROR ADDRESS for the K8 CPUs */
1051 static u64
k8_get_error_address(struct mem_ctl_info
*mci
,
1052 struct amd64_error_info_regs
*info
)
1054 return (((u64
) (info
->nbeah
& 0xff)) << 32) +
1055 (info
->nbeal
& ~0x03);
1059 * Read the Base and Limit registers for K8 based Memory controllers; extract
1060 * fields from the 'raw' reg into separate data fields
1062 * Isolates: BASE, LIMIT, IntlvEn, IntlvSel, RW_EN
1064 static void k8_read_dram_base_limit(struct amd64_pvt
*pvt
, int dram
)
1067 u32 off
= dram
<< 3; /* 8 bytes between DRAM entries */
1070 err
= pci_read_config_dword(pvt
->addr_f1_ctl
,
1071 K8_DRAM_BASE_LOW
+ off
, &low
);
1073 debugf0("Reading K8_DRAM_BASE_LOW failed\n");
1075 /* Extract parts into separate data entries */
1076 pvt
->dram_base
[dram
] = ((u64
) low
& 0xFFFF0000) << 8;
1077 pvt
->dram_IntlvEn
[dram
] = (low
>> 8) & 0x7;
1078 pvt
->dram_rw_en
[dram
] = (low
& 0x3);
1080 err
= pci_read_config_dword(pvt
->addr_f1_ctl
,
1081 K8_DRAM_LIMIT_LOW
+ off
, &low
);
1083 debugf0("Reading K8_DRAM_LIMIT_LOW failed\n");
1086 * Extract parts into separate data entries. Limit is the HIGHEST memory
1087 * location of the region, so lower 24 bits need to be all ones
1089 pvt
->dram_limit
[dram
] = (((u64
) low
& 0xFFFF0000) << 8) | 0x00FFFFFF;
1090 pvt
->dram_IntlvSel
[dram
] = (low
>> 8) & 0x7;
1091 pvt
->dram_DstNode
[dram
] = (low
& 0x7);
1094 static void k8_map_sysaddr_to_csrow(struct mem_ctl_info
*mci
,
1095 struct amd64_error_info_regs
*info
,
1098 struct mem_ctl_info
*src_mci
;
1099 unsigned short syndrome
;
1103 /* Extract the syndrome parts and form a 16-bit syndrome */
1104 syndrome
= EXTRACT_HIGH_SYNDROME(info
->nbsl
) << 8;
1105 syndrome
|= EXTRACT_LOW_SYNDROME(info
->nbsh
);
1107 /* CHIPKILL enabled */
1108 if (info
->nbcfg
& K8_NBCFG_CHIPKILL
) {
1109 channel
= get_channel_from_ecc_syndrome(syndrome
);
1112 * Syndrome didn't map, so we don't know which of the
1113 * 2 DIMMs is in error. So we need to ID 'both' of them
1116 amd64_mc_printk(mci
, KERN_WARNING
,
1117 "unknown syndrome 0x%x - possible error "
1118 "reporting race\n", syndrome
);
1119 edac_mc_handle_ce_no_info(mci
, EDAC_MOD_STR
);
1124 * non-chipkill ecc mode
1126 * The k8 documentation is unclear about how to determine the
1127 * channel number when using non-chipkill memory. This method
1128 * was obtained from email communication with someone at AMD.
1129 * (Wish the email was placed in this comment - norsk)
1131 channel
= ((SystemAddress
& BIT(3)) != 0);
1135 * Find out which node the error address belongs to. This may be
1136 * different from the node that detected the error.
1138 src_mci
= find_mc_by_sys_addr(mci
, SystemAddress
);
1140 amd64_mc_printk(mci
, KERN_ERR
,
1141 "failed to map error address 0x%lx to a node\n",
1142 (unsigned long)SystemAddress
);
1143 edac_mc_handle_ce_no_info(mci
, EDAC_MOD_STR
);
1147 /* Now map the SystemAddress to a CSROW */
1148 csrow
= sys_addr_to_csrow(src_mci
, SystemAddress
);
1150 edac_mc_handle_ce_no_info(src_mci
, EDAC_MOD_STR
);
1152 error_address_to_page_and_offset(SystemAddress
, &page
, &offset
);
1154 edac_mc_handle_ce(src_mci
, page
, offset
, syndrome
, csrow
,
1155 channel
, EDAC_MOD_STR
);
1160 * determrine the number of PAGES in for this DIMM's size based on its DRAM
1163 * First step is to calc the number of bits to shift a value of 1 left to
1164 * indicate show many pages. Start with the DBAM value as the starting bits,
1165 * then proceed to adjust those shift bits, based on CPU rev and the table.
1166 * See BKDG on the DBAM
1168 static int k8_dbam_map_to_pages(struct amd64_pvt
*pvt
, int dram_map
)
1172 if (pvt
->ext_model
>= OPTERON_CPU_REV_F
) {
1173 nr_pages
= 1 << (revf_quad_ddr2_shift
[dram_map
] - PAGE_SHIFT
);
1176 * RevE and less section; this line is tricky. It collapses the
1177 * table used by RevD and later to one that matches revisions CG
1180 dram_map
-= (pvt
->ext_model
>= OPTERON_CPU_REV_D
) ?
1181 (dram_map
> 8 ? 4 : (dram_map
> 5 ?
1182 3 : (dram_map
> 2 ? 1 : 0))) : 0;
1184 /* 25 shift is 32MiB minimum DIMM size in RevE and prior */
1185 nr_pages
= 1 << (dram_map
+ 25 - PAGE_SHIFT
);
1192 * Get the number of DCT channels in use.
1195 * number of Memory Channels in operation
1197 * contents of the DCL0_LOW register
1199 static int f10_early_channel_count(struct amd64_pvt
*pvt
)
1201 int err
= 0, channels
= 0;
1204 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, F10_DCLR_0
, &pvt
->dclr0
);
1208 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, F10_DCLR_1
, &pvt
->dclr1
);
1212 /* If we are in 128 bit mode, then we are using 2 channels */
1213 if (pvt
->dclr0
& F10_WIDTH_128
) {
1214 debugf0("Data WIDTH is 128 bits - 2 channels\n");
1220 * Need to check if in UN-ganged mode: In such, there are 2 channels,
1221 * but they are NOT in 128 bit mode and thus the above 'dcl0' status bit
1224 * Need to check DCT0[0] and DCT1[0] to see if only one of them has
1225 * their CSEnable bit on. If so, then SINGLE DIMM case.
1227 debugf0("Data WIDTH is NOT 128 bits - need more decoding\n");
1230 * Check DRAM Bank Address Mapping values for each DIMM to see if there
1231 * is more than just one DIMM present in unganged mode. Need to check
1232 * both controllers since DIMMs can be placed in either one.
1235 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, DBAM0
, &dbam
);
1239 if (DBAM_DIMM(0, dbam
) > 0)
1241 if (DBAM_DIMM(1, dbam
) > 0)
1243 if (DBAM_DIMM(2, dbam
) > 0)
1245 if (DBAM_DIMM(3, dbam
) > 0)
1248 /* If more than 2 DIMMs are present, then we have 2 channels */
1251 else if (channels
== 0) {
1252 /* No DIMMs on DCT0, so look at DCT1 */
1253 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, DBAM1
, &dbam
);
1257 if (DBAM_DIMM(0, dbam
) > 0)
1259 if (DBAM_DIMM(1, dbam
) > 0)
1261 if (DBAM_DIMM(2, dbam
) > 0)
1263 if (DBAM_DIMM(3, dbam
) > 0)
1270 /* If we found ALL 0 values, then assume just ONE DIMM-ONE Channel */
1274 debugf0("MCT channel count: %d\n", channels
);
1283 static int f10_dbam_map_to_pages(struct amd64_pvt
*pvt
, int dram_map
)
1285 return 1 << (revf_quad_ddr2_shift
[dram_map
] - PAGE_SHIFT
);
1288 /* Enable extended configuration access via 0xCF8 feature */
1289 static void amd64_setup(struct amd64_pvt
*pvt
)
1293 pci_read_config_dword(pvt
->misc_f3_ctl
, F10_NB_CFG_HIGH
, ®
);
1295 pvt
->flags
.cf8_extcfg
= !!(reg
& F10_NB_CFG_LOW_ENABLE_EXT_CFG
);
1296 reg
|= F10_NB_CFG_LOW_ENABLE_EXT_CFG
;
1297 pci_write_config_dword(pvt
->misc_f3_ctl
, F10_NB_CFG_HIGH
, reg
);
1300 /* Restore the extended configuration access via 0xCF8 feature */
1301 static void amd64_teardown(struct amd64_pvt
*pvt
)
1305 pci_read_config_dword(pvt
->misc_f3_ctl
, F10_NB_CFG_HIGH
, ®
);
1307 reg
&= ~F10_NB_CFG_LOW_ENABLE_EXT_CFG
;
1308 if (pvt
->flags
.cf8_extcfg
)
1309 reg
|= F10_NB_CFG_LOW_ENABLE_EXT_CFG
;
1310 pci_write_config_dword(pvt
->misc_f3_ctl
, F10_NB_CFG_HIGH
, reg
);
1313 static u64
f10_get_error_address(struct mem_ctl_info
*mci
,
1314 struct amd64_error_info_regs
*info
)
1316 return (((u64
) (info
->nbeah
& 0xffff)) << 32) +
1317 (info
->nbeal
& ~0x01);
1321 * Read the Base and Limit registers for F10 based Memory controllers. Extract
1322 * fields from the 'raw' reg into separate data fields.
1324 * Isolates: BASE, LIMIT, IntlvEn, IntlvSel, RW_EN.
1326 static void f10_read_dram_base_limit(struct amd64_pvt
*pvt
, int dram
)
1328 u32 high_offset
, low_offset
, high_base
, low_base
, high_limit
, low_limit
;
1330 low_offset
= K8_DRAM_BASE_LOW
+ (dram
<< 3);
1331 high_offset
= F10_DRAM_BASE_HIGH
+ (dram
<< 3);
1333 /* read the 'raw' DRAM BASE Address register */
1334 pci_read_config_dword(pvt
->addr_f1_ctl
, low_offset
, &low_base
);
1336 /* Read from the ECS data register */
1337 pci_read_config_dword(pvt
->addr_f1_ctl
, high_offset
, &high_base
);
1339 /* Extract parts into separate data entries */
1340 pvt
->dram_rw_en
[dram
] = (low_base
& 0x3);
1342 if (pvt
->dram_rw_en
[dram
] == 0)
1345 pvt
->dram_IntlvEn
[dram
] = (low_base
>> 8) & 0x7;
1347 pvt
->dram_base
[dram
] = (((((u64
) high_base
& 0x000000FF) << 32) |
1348 ((u64
) low_base
& 0xFFFF0000))) << 8;
1350 low_offset
= K8_DRAM_LIMIT_LOW
+ (dram
<< 3);
1351 high_offset
= F10_DRAM_LIMIT_HIGH
+ (dram
<< 3);
1353 /* read the 'raw' LIMIT registers */
1354 pci_read_config_dword(pvt
->addr_f1_ctl
, low_offset
, &low_limit
);
1356 /* Read from the ECS data register for the HIGH portion */
1357 pci_read_config_dword(pvt
->addr_f1_ctl
, high_offset
, &high_limit
);
1359 debugf0(" HW Regs: BASE=0x%08x-%08x LIMIT= 0x%08x-%08x\n",
1360 high_base
, low_base
, high_limit
, low_limit
);
1362 pvt
->dram_DstNode
[dram
] = (low_limit
& 0x7);
1363 pvt
->dram_IntlvSel
[dram
] = (low_limit
>> 8) & 0x7;
1366 * Extract address values and form a LIMIT address. Limit is the HIGHEST
1367 * memory location of the region, so low 24 bits need to be all ones.
1369 low_limit
|= 0x0000FFFF;
1370 pvt
->dram_limit
[dram
] =
1371 ((((u64
) high_limit
<< 32) + (u64
) low_limit
) << 8) | (0xFF);
1374 static void f10_read_dram_ctl_register(struct amd64_pvt
*pvt
)
1378 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, F10_DCTL_SEL_LOW
,
1379 &pvt
->dram_ctl_select_low
);
1381 debugf0("Reading F10_DCTL_SEL_LOW failed\n");
1383 debugf0("DRAM_DCTL_SEL_LOW=0x%x DctSelBaseAddr=0x%x\n",
1384 pvt
->dram_ctl_select_low
, dct_sel_baseaddr(pvt
));
1386 debugf0(" DRAM DCTs are=%s DRAM Is=%s DRAM-Ctl-"
1387 "sel-hi-range=%s\n",
1388 (dct_ganging_enabled(pvt
) ? "GANGED" : "NOT GANGED"),
1389 (dct_dram_enabled(pvt
) ? "Enabled" : "Disabled"),
1390 (dct_high_range_enabled(pvt
) ? "Enabled" : "Disabled"));
1392 debugf0(" DctDatIntLv=%s MemCleared=%s DctSelIntLvAddr=0x%x\n",
1393 (dct_data_intlv_enabled(pvt
) ? "Enabled" : "Disabled"),
1394 (dct_memory_cleared(pvt
) ? "True " : "False "),
1395 dct_sel_interleave_addr(pvt
));
1398 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, F10_DCTL_SEL_HIGH
,
1399 &pvt
->dram_ctl_select_high
);
1401 debugf0("Reading F10_DCTL_SEL_HIGH failed\n");
1405 * determine channel based on the interleaving mode: F10h BKDG, 2.8.9 Memory
1406 * Interleaving Modes.
1408 static u32
f10_determine_channel(struct amd64_pvt
*pvt
, u64 sys_addr
,
1409 int hi_range_sel
, u32 intlv_en
)
1411 u32 cs
, temp
, dct_sel_high
= (pvt
->dram_ctl_select_low
>> 1) & 1;
1413 if (dct_ganging_enabled(pvt
))
1415 else if (hi_range_sel
)
1417 else if (dct_interleave_enabled(pvt
)) {
1419 * see F2x110[DctSelIntLvAddr] - channel interleave mode
1421 if (dct_sel_interleave_addr(pvt
) == 0)
1422 cs
= sys_addr
>> 6 & 1;
1423 else if ((dct_sel_interleave_addr(pvt
) >> 1) & 1) {
1424 temp
= hweight_long((u32
) ((sys_addr
>> 16) & 0x1F)) % 2;
1426 if (dct_sel_interleave_addr(pvt
) & 1)
1427 cs
= (sys_addr
>> 9 & 1) ^ temp
;
1429 cs
= (sys_addr
>> 6 & 1) ^ temp
;
1430 } else if (intlv_en
& 4)
1431 cs
= sys_addr
>> 15 & 1;
1432 else if (intlv_en
& 2)
1433 cs
= sys_addr
>> 14 & 1;
1434 else if (intlv_en
& 1)
1435 cs
= sys_addr
>> 13 & 1;
1437 cs
= sys_addr
>> 12 & 1;
1438 } else if (dct_high_range_enabled(pvt
) && !dct_ganging_enabled(pvt
))
1439 cs
= ~dct_sel_high
& 1;
1446 static inline u32
f10_map_intlv_en_to_shift(u32 intlv_en
)
1450 else if (intlv_en
== 3)
1452 else if (intlv_en
== 7)
1458 /* See F10h BKDG, 2.8.10.2 DctSelBaseOffset Programming */
1459 static inline u64
f10_get_base_addr_offset(u64 sys_addr
, int hi_range_sel
,
1460 u32 dct_sel_base_addr
,
1461 u64 dct_sel_base_off
,
1462 u32 hole_valid
, u32 hole_off
,
1468 if (!(dct_sel_base_addr
& 0xFFFFF800) &&
1469 hole_valid
&& (sys_addr
>= 0x100000000ULL
))
1470 chan_off
= hole_off
<< 16;
1472 chan_off
= dct_sel_base_off
;
1474 if (hole_valid
&& (sys_addr
>= 0x100000000ULL
))
1475 chan_off
= hole_off
<< 16;
1477 chan_off
= dram_base
& 0xFFFFF8000000ULL
;
1480 return (sys_addr
& 0x0000FFFFFFFFFFC0ULL
) -
1481 (chan_off
& 0x0000FFFFFF800000ULL
);
1484 /* Hack for the time being - Can we get this from BIOS?? */
1485 #define CH0SPARE_RANK 0
1486 #define CH1SPARE_RANK 1
1489 * checks if the csrow passed in is marked as SPARED, if so returns the new
1492 static inline int f10_process_possible_spare(int csrow
,
1493 u32 cs
, struct amd64_pvt
*pvt
)
1498 /* Depending on channel, isolate respective SPARING info */
1500 swap_done
= F10_ONLINE_SPARE_SWAPDONE1(pvt
->online_spare
);
1501 bad_dram_cs
= F10_ONLINE_SPARE_BADDRAM_CS1(pvt
->online_spare
);
1502 if (swap_done
&& (csrow
== bad_dram_cs
))
1503 csrow
= CH1SPARE_RANK
;
1505 swap_done
= F10_ONLINE_SPARE_SWAPDONE0(pvt
->online_spare
);
1506 bad_dram_cs
= F10_ONLINE_SPARE_BADDRAM_CS0(pvt
->online_spare
);
1507 if (swap_done
&& (csrow
== bad_dram_cs
))
1508 csrow
= CH0SPARE_RANK
;
1514 * Iterate over the DRAM DCT "base" and "mask" registers looking for a
1515 * SystemAddr match on the specified 'ChannelSelect' and 'NodeID'
1518 * -EINVAL: NOT FOUND
1519 * 0..csrow = Chip-Select Row
1521 static int f10_lookup_addr_in_dct(u32 in_addr
, u32 nid
, u32 cs
)
1523 struct mem_ctl_info
*mci
;
1524 struct amd64_pvt
*pvt
;
1525 u32 cs_base
, cs_mask
;
1526 int cs_found
= -EINVAL
;
1529 mci
= mci_lookup
[nid
];
1533 pvt
= mci
->pvt_info
;
1535 debugf1("InputAddr=0x%x channelselect=%d\n", in_addr
, cs
);
1537 for (csrow
= 0; csrow
< CHIPSELECT_COUNT
; csrow
++) {
1539 cs_base
= amd64_get_dct_base(pvt
, cs
, csrow
);
1540 if (!(cs_base
& K8_DCSB_CS_ENABLE
))
1544 * We have an ENABLED CSROW, Isolate just the MASK bits of the
1545 * target: [28:19] and [13:5], which map to [36:27] and [21:13]
1546 * of the actual address.
1548 cs_base
&= REV_F_F1Xh_DCSB_BASE_BITS
;
1551 * Get the DCT Mask, and ENABLE the reserved bits: [18:16] and
1552 * [4:0] to become ON. Then mask off bits [28:0] ([36:8])
1554 cs_mask
= amd64_get_dct_mask(pvt
, cs
, csrow
);
1556 debugf1(" CSROW=%d CSBase=0x%x RAW CSMask=0x%x\n",
1557 csrow
, cs_base
, cs_mask
);
1559 cs_mask
= (cs_mask
| 0x0007C01F) & 0x1FFFFFFF;
1561 debugf1(" Final CSMask=0x%x\n", cs_mask
);
1562 debugf1(" (InputAddr & ~CSMask)=0x%x "
1563 "(CSBase & ~CSMask)=0x%x\n",
1564 (in_addr
& ~cs_mask
), (cs_base
& ~cs_mask
));
1566 if ((in_addr
& ~cs_mask
) == (cs_base
& ~cs_mask
)) {
1567 cs_found
= f10_process_possible_spare(csrow
, cs
, pvt
);
1569 debugf1(" MATCH csrow=%d\n", cs_found
);
1576 /* For a given @dram_range, check if @sys_addr falls within it. */
1577 static int f10_match_to_this_node(struct amd64_pvt
*pvt
, int dram_range
,
1578 u64 sys_addr
, int *nid
, int *chan_sel
)
1580 int node_id
, cs_found
= -EINVAL
, high_range
= 0;
1581 u32 intlv_en
, intlv_sel
, intlv_shift
, hole_off
;
1582 u32 hole_valid
, tmp
, dct_sel_base
, channel
;
1583 u64 dram_base
, chan_addr
, dct_sel_base_off
;
1585 dram_base
= pvt
->dram_base
[dram_range
];
1586 intlv_en
= pvt
->dram_IntlvEn
[dram_range
];
1588 node_id
= pvt
->dram_DstNode
[dram_range
];
1589 intlv_sel
= pvt
->dram_IntlvSel
[dram_range
];
1591 debugf1("(dram=%d) Base=0x%llx SystemAddr= 0x%llx Limit=0x%llx\n",
1592 dram_range
, dram_base
, sys_addr
, pvt
->dram_limit
[dram_range
]);
1595 * This assumes that one node's DHAR is the same as all the other
1598 hole_off
= (pvt
->dhar
& 0x0000FF80);
1599 hole_valid
= (pvt
->dhar
& 0x1);
1600 dct_sel_base_off
= (pvt
->dram_ctl_select_high
& 0xFFFFFC00) << 16;
1602 debugf1(" HoleOffset=0x%x HoleValid=0x%x IntlvSel=0x%x\n",
1603 hole_off
, hole_valid
, intlv_sel
);
1606 (intlv_sel
!= ((sys_addr
>> 12) & intlv_en
)))
1609 dct_sel_base
= dct_sel_baseaddr(pvt
);
1612 * check whether addresses >= DctSelBaseAddr[47:27] are to be used to
1613 * select between DCT0 and DCT1.
1615 if (dct_high_range_enabled(pvt
) &&
1616 !dct_ganging_enabled(pvt
) &&
1617 ((sys_addr
>> 27) >= (dct_sel_base
>> 11)))
1620 channel
= f10_determine_channel(pvt
, sys_addr
, high_range
, intlv_en
);
1622 chan_addr
= f10_get_base_addr_offset(sys_addr
, high_range
, dct_sel_base
,
1623 dct_sel_base_off
, hole_valid
,
1624 hole_off
, dram_base
);
1626 intlv_shift
= f10_map_intlv_en_to_shift(intlv_en
);
1628 /* remove Node ID (in case of memory interleaving) */
1629 tmp
= chan_addr
& 0xFC0;
1631 chan_addr
= ((chan_addr
>> intlv_shift
) & 0xFFFFFFFFF000ULL
) | tmp
;
1633 /* remove channel interleave and hash */
1634 if (dct_interleave_enabled(pvt
) &&
1635 !dct_high_range_enabled(pvt
) &&
1636 !dct_ganging_enabled(pvt
)) {
1637 if (dct_sel_interleave_addr(pvt
) != 1)
1638 chan_addr
= (chan_addr
>> 1) & 0xFFFFFFFFFFFFFFC0ULL
;
1640 tmp
= chan_addr
& 0xFC0;
1641 chan_addr
= ((chan_addr
& 0xFFFFFFFFFFFFC000ULL
) >> 1)
1646 debugf1(" (ChannelAddrLong=0x%llx) >> 8 becomes InputAddr=0x%x\n",
1647 chan_addr
, (u32
)(chan_addr
>> 8));
1649 cs_found
= f10_lookup_addr_in_dct(chan_addr
>> 8, node_id
, channel
);
1651 if (cs_found
>= 0) {
1653 *chan_sel
= channel
;
1658 static int f10_translate_sysaddr_to_cs(struct amd64_pvt
*pvt
, u64 sys_addr
,
1659 int *node
, int *chan_sel
)
1661 int dram_range
, cs_found
= -EINVAL
;
1662 u64 dram_base
, dram_limit
;
1664 for (dram_range
= 0; dram_range
< DRAM_REG_COUNT
; dram_range
++) {
1666 if (!pvt
->dram_rw_en
[dram_range
])
1669 dram_base
= pvt
->dram_base
[dram_range
];
1670 dram_limit
= pvt
->dram_limit
[dram_range
];
1672 if ((dram_base
<= sys_addr
) && (sys_addr
<= dram_limit
)) {
1674 cs_found
= f10_match_to_this_node(pvt
, dram_range
,
1685 * This the F10h reference code from AMD to map a @sys_addr to NodeID,
1688 * The @sys_addr is usually an error address received from the hardware.
1690 static void f10_map_sysaddr_to_csrow(struct mem_ctl_info
*mci
,
1691 struct amd64_error_info_regs
*info
,
1694 struct amd64_pvt
*pvt
= mci
->pvt_info
;
1696 unsigned short syndrome
;
1697 int nid
, csrow
, chan
= 0;
1699 csrow
= f10_translate_sysaddr_to_cs(pvt
, sys_addr
, &nid
, &chan
);
1702 error_address_to_page_and_offset(sys_addr
, &page
, &offset
);
1704 syndrome
= EXTRACT_HIGH_SYNDROME(info
->nbsl
) << 8;
1705 syndrome
|= EXTRACT_LOW_SYNDROME(info
->nbsh
);
1708 * Is CHIPKILL on? If so, then we can attempt to use the
1709 * syndrome to isolate which channel the error was on.
1711 if (pvt
->nbcfg
& K8_NBCFG_CHIPKILL
)
1712 chan
= get_channel_from_ecc_syndrome(syndrome
);
1715 edac_mc_handle_ce(mci
, page
, offset
, syndrome
,
1716 csrow
, chan
, EDAC_MOD_STR
);
1719 * Channel unknown, report all channels on this
1722 for (chan
= 0; chan
< mci
->csrows
[csrow
].nr_channels
;
1724 edac_mc_handle_ce(mci
, page
, offset
,
1732 edac_mc_handle_ce_no_info(mci
, EDAC_MOD_STR
);
1737 * Input (@index) is the DBAM DIMM value (1 of 4) used as an index into a shift
1738 * table (revf_quad_ddr2_shift) which starts at 128MB DIMM size. Index of 0
1739 * indicates an empty DIMM slot, as reported by Hardware on empty slots.
1741 * Normalize to 128MB by subracting 27 bit shift.
1743 static int map_dbam_to_csrow_size(int index
)
1747 if (index
> 0 && index
<= DBAM_MAX_VALUE
)
1748 mega_bytes
= ((128 << (revf_quad_ddr2_shift
[index
]-27)));
1754 * debug routine to display the memory sizes of a DIMM (ganged or not) and it
1757 static void f10_debug_display_dimm_sizes(int ctrl
, struct amd64_pvt
*pvt
,
1760 int dimm
, size0
, size1
;
1764 debugf1(" dbam%d: 0x%8.08x CSROW is %s\n", ctrl
,
1765 ctrl
? pvt
->dbam1
: pvt
->dbam0
,
1766 ganged
? "GANGED - dbam1 not used" : "NON-GANGED");
1768 dbam
= ctrl
? pvt
->dbam1
: pvt
->dbam0
;
1769 dcsb
= ctrl
? pvt
->dcsb1
: pvt
->dcsb0
;
1771 /* Dump memory sizes for DIMM and its CSROWs */
1772 for (dimm
= 0; dimm
< 4; dimm
++) {
1775 if (dcsb
[dimm
*2] & K8_DCSB_CS_ENABLE
)
1776 size0
= map_dbam_to_csrow_size(DBAM_DIMM(dimm
, dbam
));
1779 if (dcsb
[dimm
*2 + 1] & K8_DCSB_CS_ENABLE
)
1780 size1
= map_dbam_to_csrow_size(DBAM_DIMM(dimm
, dbam
));
1782 debugf1(" CTRL-%d DIMM-%d=%5dMB CSROW-%d=%5dMB "
1795 * Very early hardware probe on pci_probe thread to determine if this module
1796 * supports the hardware.
1802 static int f10_probe_valid_hardware(struct amd64_pvt
*pvt
)
1807 * If we are on a DDR3 machine, we don't know yet if
1808 * we support that properly at this time
1810 if ((pvt
->dchr0
& F10_DCHR_Ddr3Mode
) ||
1811 (pvt
->dchr1
& F10_DCHR_Ddr3Mode
)) {
1813 amd64_printk(KERN_WARNING
,
1814 "%s() This machine is running with DDR3 memory. "
1815 "This is not currently supported. "
1816 "DCHR0=0x%x DCHR1=0x%x\n",
1817 __func__
, pvt
->dchr0
, pvt
->dchr1
);
1819 amd64_printk(KERN_WARNING
,
1820 " Contact '%s' module MAINTAINER to help add"
1831 * There currently are 3 types type of MC devices for AMD Athlon/Opterons
1832 * (as per PCI DEVICE_IDs):
1834 * Family K8: That is the Athlon64 and Opteron CPUs. They all have the same PCI
1835 * DEVICE ID, even though there is differences between the different Revisions
1838 * Family F10h and F11h.
1841 static struct amd64_family_type amd64_family_types
[] = {
1844 .addr_f1_ctl
= PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP
,
1845 .misc_f3_ctl
= PCI_DEVICE_ID_AMD_K8_NB_MISC
,
1847 .early_channel_count
= k8_early_channel_count
,
1848 .get_error_address
= k8_get_error_address
,
1849 .read_dram_base_limit
= k8_read_dram_base_limit
,
1850 .map_sysaddr_to_csrow
= k8_map_sysaddr_to_csrow
,
1851 .dbam_map_to_pages
= k8_dbam_map_to_pages
,
1855 .ctl_name
= "Family 10h",
1856 .addr_f1_ctl
= PCI_DEVICE_ID_AMD_10H_NB_MAP
,
1857 .misc_f3_ctl
= PCI_DEVICE_ID_AMD_10H_NB_MISC
,
1859 .probe_valid_hardware
= f10_probe_valid_hardware
,
1860 .early_channel_count
= f10_early_channel_count
,
1861 .get_error_address
= f10_get_error_address
,
1862 .read_dram_base_limit
= f10_read_dram_base_limit
,
1863 .read_dram_ctl_register
= f10_read_dram_ctl_register
,
1864 .map_sysaddr_to_csrow
= f10_map_sysaddr_to_csrow
,
1865 .dbam_map_to_pages
= f10_dbam_map_to_pages
,
1869 .ctl_name
= "Family 11h",
1870 .addr_f1_ctl
= PCI_DEVICE_ID_AMD_11H_NB_MAP
,
1871 .misc_f3_ctl
= PCI_DEVICE_ID_AMD_11H_NB_MISC
,
1873 .probe_valid_hardware
= f10_probe_valid_hardware
,
1874 .early_channel_count
= f10_early_channel_count
,
1875 .get_error_address
= f10_get_error_address
,
1876 .read_dram_base_limit
= f10_read_dram_base_limit
,
1877 .read_dram_ctl_register
= f10_read_dram_ctl_register
,
1878 .map_sysaddr_to_csrow
= f10_map_sysaddr_to_csrow
,
1879 .dbam_map_to_pages
= f10_dbam_map_to_pages
,
1884 static struct pci_dev
*pci_get_related_function(unsigned int vendor
,
1885 unsigned int device
,
1886 struct pci_dev
*related
)
1888 struct pci_dev
*dev
= NULL
;
1890 dev
= pci_get_device(vendor
, device
, dev
);
1892 if ((dev
->bus
->number
== related
->bus
->number
) &&
1893 (PCI_SLOT(dev
->devfn
) == PCI_SLOT(related
->devfn
)))
1895 dev
= pci_get_device(vendor
, device
, dev
);
1902 * syndrome mapping table for ECC ChipKill devices
1904 * The comment in each row is the token (nibble) number that is in error.
1905 * The least significant nibble of the syndrome is the mask for the bits
1906 * that are in error (need to be toggled) for the particular nibble.
1908 * Each row contains 16 entries.
1909 * The first entry (0th) is the channel number for that row of syndromes.
1910 * The remaining 15 entries are the syndromes for the respective Error
1913 * 1st index entry is 0x0001 mask, indicating that the rightmost bit is the
1915 * The 2nd index entry is 0x0010 that the second bit is damaged.
1916 * The 3rd index entry is 0x0011 indicating that the rightmost 2 bits
1918 * Thus so on until index 15, 0x1111, whose entry has the syndrome
1919 * indicating that all 4 bits are damaged.
1921 * A search is performed on this table looking for a given syndrome.
1923 * See the AMD documentation for ECC syndromes. This ECC table is valid
1924 * across all the versions of the AMD64 processors.
1926 * A fast lookup is to use the LAST four bits of the 16-bit syndrome as a
1927 * COLUMN index, then search all ROWS of that column, looking for a match
1928 * with the input syndrome. The ROW value will be the token number.
1930 * The 0'th entry on that row, can be returned as the CHANNEL (0 or 1) of this
1933 #define NUMBER_ECC_ROWS 36
1934 static const unsigned short ecc_chipkill_syndromes
[NUMBER_ECC_ROWS
][16] = {
1935 /* Channel 0 syndromes */
1936 {/*0*/ 0, 0xe821, 0x7c32, 0x9413, 0xbb44, 0x5365, 0xc776, 0x2f57,
1937 0xdd88, 0x35a9, 0xa1ba, 0x499b, 0x66cc, 0x8eed, 0x1afe, 0xf2df },
1938 {/*1*/ 0, 0x5d31, 0xa612, 0xfb23, 0x9584, 0xc8b5, 0x3396, 0x6ea7,
1939 0xeac8, 0xb7f9, 0x4cda, 0x11eb, 0x7f4c, 0x227d, 0xd95e, 0x846f },
1940 {/*2*/ 0, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
1941 0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f },
1942 {/*3*/ 0, 0x2021, 0x3032, 0x1013, 0x4044, 0x6065, 0x7076, 0x5057,
1943 0x8088, 0xa0a9, 0xb0ba, 0x909b, 0xc0cc, 0xe0ed, 0xf0fe, 0xd0df },
1944 {/*4*/ 0, 0x5041, 0xa082, 0xf0c3, 0x9054, 0xc015, 0x30d6, 0x6097,
1945 0xe0a8, 0xb0e9, 0x402a, 0x106b, 0x70fc, 0x20bd, 0xd07e, 0x803f },
1946 {/*5*/ 0, 0xbe21, 0xd732, 0x6913, 0x2144, 0x9f65, 0xf676, 0x4857,
1947 0x3288, 0x8ca9, 0xe5ba, 0x5b9b, 0x13cc, 0xaded, 0xc4fe, 0x7adf },
1948 {/*6*/ 0, 0x4951, 0x8ea2, 0xc7f3, 0x5394, 0x1ac5, 0xdd36, 0x9467,
1949 0xa1e8, 0xe8b9, 0x2f4a, 0x661b, 0xf27c, 0xbb2d, 0x7cde, 0x358f },
1950 {/*7*/ 0, 0x74e1, 0x9872, 0xec93, 0xd6b4, 0xa255, 0x4ec6, 0x3a27,
1951 0x6bd8, 0x1f39, 0xf3aa, 0x874b, 0xbd6c, 0xc98d, 0x251e, 0x51ff },
1952 {/*8*/ 0, 0x15c1, 0x2a42, 0x3f83, 0xcef4, 0xdb35, 0xe4b6, 0xf177,
1953 0x4758, 0x5299, 0x6d1a, 0x78db, 0x89ac, 0x9c6d, 0xa3ee, 0xb62f },
1954 {/*9*/ 0, 0x3d01, 0x1602, 0x2b03, 0x8504, 0xb805, 0x9306, 0xae07,
1955 0xca08, 0xf709, 0xdc0a, 0xe10b, 0x4f0c, 0x720d, 0x590e, 0x640f },
1956 {/*a*/ 0, 0x9801, 0xec02, 0x7403, 0x6b04, 0xf305, 0x8706, 0x1f07,
1957 0xbd08, 0x2509, 0x510a, 0xc90b, 0xd60c, 0x4e0d, 0x3a0e, 0xa20f },
1958 {/*b*/ 0, 0xd131, 0x6212, 0xb323, 0x3884, 0xe9b5, 0x5a96, 0x8ba7,
1959 0x1cc8, 0xcdf9, 0x7eda, 0xafeb, 0x244c, 0xf57d, 0x465e, 0x976f },
1960 {/*c*/ 0, 0xe1d1, 0x7262, 0x93b3, 0xb834, 0x59e5, 0xca56, 0x2b87,
1961 0xdc18, 0x3dc9, 0xae7a, 0x4fab, 0x542c, 0x85fd, 0x164e, 0xf79f },
1962 {/*d*/ 0, 0x6051, 0xb0a2, 0xd0f3, 0x1094, 0x70c5, 0xa036, 0xc067,
1963 0x20e8, 0x40b9, 0x904a, 0x601b, 0x307c, 0x502d, 0x80de, 0xe08f },
1964 {/*e*/ 0, 0xa4c1, 0xf842, 0x5c83, 0xe6f4, 0x4235, 0x1eb6, 0xba77,
1965 0x7b58, 0xdf99, 0x831a, 0x27db, 0x9dac, 0x396d, 0x65ee, 0xc12f },
1966 {/*f*/ 0, 0x11c1, 0x2242, 0x3383, 0xc8f4, 0xd935, 0xeab6, 0xfb77,
1967 0x4c58, 0x5d99, 0x6e1a, 0x7fdb, 0x84ac, 0x956d, 0xa6ee, 0xb72f },
1969 /* Channel 1 syndromes */
1970 {/*10*/ 1, 0x45d1, 0x8a62, 0xcfb3, 0x5e34, 0x1be5, 0xd456, 0x9187,
1971 0xa718, 0xe2c9, 0x2d7a, 0x68ab, 0xf92c, 0xbcfd, 0x734e, 0x369f },
1972 {/*11*/ 1, 0x63e1, 0xb172, 0xd293, 0x14b4, 0x7755, 0xa5c6, 0xc627,
1973 0x28d8, 0x4b39, 0x99aa, 0xfa4b, 0x3c6c, 0x5f8d, 0x8d1e, 0xeeff },
1974 {/*12*/ 1, 0xb741, 0xd982, 0x6ec3, 0x2254, 0x9515, 0xfbd6, 0x4c97,
1975 0x33a8, 0x84e9, 0xea2a, 0x5d6b, 0x11fc, 0xa6bd, 0xc87e, 0x7f3f },
1976 {/*13*/ 1, 0xdd41, 0x6682, 0xbbc3, 0x3554, 0xe815, 0x53d6, 0xce97,
1977 0x1aa8, 0xc7e9, 0x7c2a, 0xa1fb, 0x2ffc, 0xf2bd, 0x497e, 0x943f },
1978 {/*14*/ 1, 0x2bd1, 0x3d62, 0x16b3, 0x4f34, 0x64e5, 0x7256, 0x5987,
1979 0x8518, 0xaec9, 0xb87a, 0x93ab, 0xca2c, 0xe1fd, 0xf74e, 0xdc9f },
1980 {/*15*/ 1, 0x83c1, 0xc142, 0x4283, 0xa4f4, 0x2735, 0x65b6, 0xe677,
1981 0xf858, 0x7b99, 0x391a, 0xbadb, 0x5cac, 0xdf6d, 0x9dee, 0x1e2f },
1982 {/*16*/ 1, 0x8fd1, 0xc562, 0x4ab3, 0xa934, 0x26e5, 0x6c56, 0xe387,
1983 0xfe18, 0x71c9, 0x3b7a, 0xb4ab, 0x572c, 0xd8fd, 0x924e, 0x1d9f },
1984 {/*17*/ 1, 0x4791, 0x89e2, 0xce73, 0x5264, 0x15f5, 0xdb86, 0x9c17,
1985 0xa3b8, 0xe429, 0x2a5a, 0x6dcb, 0xf1dc, 0xb64d, 0x783e, 0x3faf },
1986 {/*18*/ 1, 0x5781, 0xa9c2, 0xfe43, 0x92a4, 0xc525, 0x3b66, 0x6ce7,
1987 0xe3f8, 0xb479, 0x4a3a, 0x1dbb, 0x715c, 0x26dd, 0xd89e, 0x8f1f },
1988 {/*19*/ 1, 0xbf41, 0xd582, 0x6ac3, 0x2954, 0x9615, 0xfcd6, 0x4397,
1989 0x3ea8, 0x81e9, 0xeb2a, 0x546b, 0x17fc, 0xa8bd, 0xc27e, 0x7d3f },
1990 {/*1a*/ 1, 0x9891, 0xe1e2, 0x7273, 0x6464, 0xf7f5, 0x8586, 0x1617,
1991 0xb8b8, 0x2b29, 0x595a, 0xcacb, 0xdcdc, 0x4f4d, 0x3d3e, 0xaeaf },
1992 {/*1b*/ 1, 0xcce1, 0x4472, 0x8893, 0xfdb4, 0x3f55, 0xb9c6, 0x7527,
1993 0x56d8, 0x9a39, 0x12aa, 0xde4b, 0xab6c, 0x678d, 0xef1e, 0x23ff },
1994 {/*1c*/ 1, 0xa761, 0xf9b2, 0x5ed3, 0xe214, 0x4575, 0x1ba6, 0xbcc7,
1995 0x7328, 0xd449, 0x8a9a, 0x2dfb, 0x913c, 0x365d, 0x688e, 0xcfef },
1996 {/*1d*/ 1, 0xff61, 0x55b2, 0xaad3, 0x7914, 0x8675, 0x2ca6, 0xd3c7,
1997 0x9e28, 0x6149, 0xcb9a, 0x34fb, 0xe73c, 0x185d, 0xb28e, 0x4def },
1998 {/*1e*/ 1, 0x5451, 0xa8a2, 0xfcf3, 0x9694, 0xc2c5, 0x3e36, 0x6a67,
1999 0xebe8, 0xbfb9, 0x434a, 0x171b, 0x7d7c, 0x292d, 0xd5de, 0x818f },
2000 {/*1f*/ 1, 0x6fc1, 0xb542, 0xda83, 0x19f4, 0x7635, 0xacb6, 0xc377,
2001 0x2e58, 0x4199, 0x9b1a, 0xf4db, 0x37ac, 0x586d, 0x82ee, 0xed2f },
2003 /* ECC bits are also in the set of tokens and they too can go bad
2004 * first 2 cover channel 0, while the second 2 cover channel 1
2006 {/*20*/ 0, 0xbe01, 0xd702, 0x6903, 0x2104, 0x9f05, 0xf606, 0x4807,
2007 0x3208, 0x8c09, 0xe50a, 0x5b0b, 0x130c, 0xad0d, 0xc40e, 0x7a0f },
2008 {/*21*/ 0, 0x4101, 0x8202, 0xc303, 0x5804, 0x1905, 0xda06, 0x9b07,
2009 0xac08, 0xed09, 0x2e0a, 0x6f0b, 0x640c, 0xb50d, 0x760e, 0x370f },
2010 {/*22*/ 1, 0xc441, 0x4882, 0x8cc3, 0xf654, 0x3215, 0xbed6, 0x7a97,
2011 0x5ba8, 0x9fe9, 0x132a, 0xd76b, 0xadfc, 0x69bd, 0xe57e, 0x213f },
2012 {/*23*/ 1, 0x7621, 0x9b32, 0xed13, 0xda44, 0xac65, 0x4176, 0x3757,
2013 0x6f88, 0x19a9, 0xf4ba, 0x829b, 0xb5cc, 0xc3ed, 0x2efe, 0x58df }
2017 * Given the syndrome argument, scan each of the channel tables for a syndrome
2018 * match. Depending on which table it is found, return the channel number.
2020 static int get_channel_from_ecc_syndrome(unsigned short syndrome
)
2025 /* Determine column to scan */
2026 column
= syndrome
& 0xF;
2028 /* Scan all rows, looking for syndrome, or end of table */
2029 for (row
= 0; row
< NUMBER_ECC_ROWS
; row
++) {
2030 if (ecc_chipkill_syndromes
[row
][column
] == syndrome
)
2031 return ecc_chipkill_syndromes
[row
][0];
2034 debugf0("syndrome(%x) not found\n", syndrome
);
2039 * Check for valid error in the NB Status High register. If so, proceed to read
2040 * NB Status Low, NB Address Low and NB Address High registers and store data
2041 * into error structure.
2044 * - 1: if hardware regs contains valid error info
2045 * - 0: if no valid error is indicated
2047 static int amd64_get_error_info_regs(struct mem_ctl_info
*mci
,
2048 struct amd64_error_info_regs
*regs
)
2050 struct amd64_pvt
*pvt
;
2051 struct pci_dev
*misc_f3_ctl
;
2054 pvt
= mci
->pvt_info
;
2055 misc_f3_ctl
= pvt
->misc_f3_ctl
;
2057 err
= pci_read_config_dword(misc_f3_ctl
, K8_NBSH
, ®s
->nbsh
);
2061 if (!(regs
->nbsh
& K8_NBSH_VALID_BIT
))
2064 /* valid error, read remaining error information registers */
2065 err
= pci_read_config_dword(misc_f3_ctl
, K8_NBSL
, ®s
->nbsl
);
2069 err
= pci_read_config_dword(misc_f3_ctl
, K8_NBEAL
, ®s
->nbeal
);
2073 err
= pci_read_config_dword(misc_f3_ctl
, K8_NBEAH
, ®s
->nbeah
);
2077 err
= pci_read_config_dword(misc_f3_ctl
, K8_NBCFG
, ®s
->nbcfg
);
2084 debugf0("Reading error info register failed\n");
2089 * This function is called to retrieve the error data from hardware and store it
2090 * in the info structure.
2093 * - 1: if a valid error is found
2094 * - 0: if no error is found
2096 static int amd64_get_error_info(struct mem_ctl_info
*mci
,
2097 struct amd64_error_info_regs
*info
)
2099 struct amd64_pvt
*pvt
;
2100 struct amd64_error_info_regs regs
;
2102 pvt
= mci
->pvt_info
;
2104 if (!amd64_get_error_info_regs(mci
, info
))
2108 * Here's the problem with the K8's EDAC reporting: There are four
2109 * registers which report pieces of error information. They are shared
2110 * between CEs and UEs. Furthermore, contrary to what is stated in the
2111 * BKDG, the overflow bit is never used! Every error always updates the
2112 * reporting registers.
2114 * Can you see the race condition? All four error reporting registers
2115 * must be read before a new error updates them! There is no way to read
2116 * all four registers atomically. The best than can be done is to detect
2117 * that a race has occured and then report the error without any kind of
2120 * What is still positive is that errors are still reported and thus
2121 * problems can still be detected - just not localized because the
2122 * syndrome and address are spread out across registers.
2124 * Grrrrr!!!!! Here's hoping that AMD fixes this in some future K8 rev.
2125 * UEs and CEs should have separate register sets with proper overflow
2126 * bits that are used! At very least the problem can be fixed by
2127 * honoring the ErrValid bit in 'nbsh' and not updating registers - just
2128 * set the overflow bit - unless the current error is CE and the new
2129 * error is UE which would be the only situation for overwriting the
2135 /* Use info from the second read - most current */
2136 if (unlikely(!amd64_get_error_info_regs(mci
, info
)))
2139 /* clear the error bits in hardware */
2140 pci_write_bits32(pvt
->misc_f3_ctl
, K8_NBSH
, 0, K8_NBSH_VALID_BIT
);
2142 /* Check for the possible race condition */
2143 if ((regs
.nbsh
!= info
->nbsh
) ||
2144 (regs
.nbsl
!= info
->nbsl
) ||
2145 (regs
.nbeah
!= info
->nbeah
) ||
2146 (regs
.nbeal
!= info
->nbeal
)) {
2147 amd64_mc_printk(mci
, KERN_WARNING
,
2148 "hardware STATUS read access race condition "
2155 static inline void amd64_decode_gart_tlb_error(struct mem_ctl_info
*mci
,
2156 struct amd64_error_info_regs
*info
)
2159 u32 ec_tt
; /* error code transaction type (2b) */
2160 u32 ec_ll
; /* error code cache level (2b) */
2162 err_code
= EXTRACT_ERROR_CODE(info
->nbsl
);
2163 ec_ll
= EXTRACT_LL_CODE(err_code
);
2164 ec_tt
= EXTRACT_TT_CODE(err_code
);
2166 amd64_mc_printk(mci
, KERN_ERR
,
2167 "GART TLB event: transaction type(%s), "
2168 "cache level(%s)\n", tt_msgs
[ec_tt
], ll_msgs
[ec_ll
]);
2171 static inline void amd64_decode_mem_cache_error(struct mem_ctl_info
*mci
,
2172 struct amd64_error_info_regs
*info
)
2175 u32 ec_rrrr
; /* error code memory transaction (4b) */
2176 u32 ec_tt
; /* error code transaction type (2b) */
2177 u32 ec_ll
; /* error code cache level (2b) */
2179 err_code
= EXTRACT_ERROR_CODE(info
->nbsl
);
2180 ec_ll
= EXTRACT_LL_CODE(err_code
);
2181 ec_tt
= EXTRACT_TT_CODE(err_code
);
2182 ec_rrrr
= EXTRACT_RRRR_CODE(err_code
);
2184 amd64_mc_printk(mci
, KERN_ERR
,
2185 "cache hierarchy error: memory transaction type(%s), "
2186 "transaction type(%s), cache level(%s)\n",
2187 rrrr_msgs
[ec_rrrr
], tt_msgs
[ec_tt
], ll_msgs
[ec_ll
]);
2192 * Handle any Correctable Errors (CEs) that have occurred. Check for valid ERROR
2193 * ADDRESS and process.
2195 static void amd64_handle_ce(struct mem_ctl_info
*mci
,
2196 struct amd64_error_info_regs
*info
)
2198 struct amd64_pvt
*pvt
= mci
->pvt_info
;
2201 /* Ensure that the Error Address is VALID */
2202 if ((info
->nbsh
& K8_NBSH_VALID_ERROR_ADDR
) == 0) {
2203 amd64_mc_printk(mci
, KERN_ERR
,
2204 "HW has no ERROR_ADDRESS available\n");
2205 edac_mc_handle_ce_no_info(mci
, EDAC_MOD_STR
);
2209 SystemAddress
= extract_error_address(mci
, info
);
2211 amd64_mc_printk(mci
, KERN_ERR
,
2212 "CE ERROR_ADDRESS= 0x%llx\n", SystemAddress
);
2214 pvt
->ops
->map_sysaddr_to_csrow(mci
, info
, SystemAddress
);
2217 /* Handle any Un-correctable Errors (UEs) */
2218 static void amd64_handle_ue(struct mem_ctl_info
*mci
,
2219 struct amd64_error_info_regs
*info
)
2224 struct mem_ctl_info
*log_mci
, *src_mci
= NULL
;
2228 if ((info
->nbsh
& K8_NBSH_VALID_ERROR_ADDR
) == 0) {
2229 amd64_mc_printk(mci
, KERN_CRIT
,
2230 "HW has no ERROR_ADDRESS available\n");
2231 edac_mc_handle_ue_no_info(log_mci
, EDAC_MOD_STR
);
2235 SystemAddress
= extract_error_address(mci
, info
);
2238 * Find out which node the error address belongs to. This may be
2239 * different from the node that detected the error.
2241 src_mci
= find_mc_by_sys_addr(mci
, SystemAddress
);
2243 amd64_mc_printk(mci
, KERN_CRIT
,
2244 "ERROR ADDRESS (0x%lx) value NOT mapped to a MC\n",
2245 (unsigned long)SystemAddress
);
2246 edac_mc_handle_ue_no_info(log_mci
, EDAC_MOD_STR
);
2252 csrow
= sys_addr_to_csrow(log_mci
, SystemAddress
);
2254 amd64_mc_printk(mci
, KERN_CRIT
,
2255 "ERROR_ADDRESS (0x%lx) value NOT mapped to 'csrow'\n",
2256 (unsigned long)SystemAddress
);
2257 edac_mc_handle_ue_no_info(log_mci
, EDAC_MOD_STR
);
2259 error_address_to_page_and_offset(SystemAddress
, &page
, &offset
);
2260 edac_mc_handle_ue(log_mci
, page
, offset
, csrow
, EDAC_MOD_STR
);
2264 static void amd64_decode_bus_error(struct mem_ctl_info
*mci
,
2265 struct amd64_error_info_regs
*info
)
2267 u32 err_code
, ext_ec
;
2268 u32 ec_pp
; /* error code participating processor (2p) */
2269 u32 ec_to
; /* error code timed out (1b) */
2270 u32 ec_rrrr
; /* error code memory transaction (4b) */
2271 u32 ec_ii
; /* error code memory or I/O (2b) */
2272 u32 ec_ll
; /* error code cache level (2b) */
2274 ext_ec
= EXTRACT_EXT_ERROR_CODE(info
->nbsl
);
2275 err_code
= EXTRACT_ERROR_CODE(info
->nbsl
);
2277 ec_ll
= EXTRACT_LL_CODE(err_code
);
2278 ec_ii
= EXTRACT_II_CODE(err_code
);
2279 ec_rrrr
= EXTRACT_RRRR_CODE(err_code
);
2280 ec_to
= EXTRACT_TO_CODE(err_code
);
2281 ec_pp
= EXTRACT_PP_CODE(err_code
);
2283 amd64_mc_printk(mci
, KERN_ERR
,
2285 " time-out(%s) mem or i/o(%s)\n"
2286 " participating processor(%s)\n"
2287 " memory transaction type(%s)\n"
2288 " cache level(%s) Error Found by: %s\n",
2294 (info
->nbsh
& K8_NBSH_ERR_SCRUBER
) ?
2295 "Scrubber" : "Normal Operation");
2297 /* If this was an 'observed' error, early out */
2298 if (ec_pp
== K8_NBSL_PP_OBS
)
2299 return; /* We aren't the node involved */
2301 /* Parse out the extended error code for ECC events */
2303 /* F10 changed to one Extended ECC error code */
2304 case F10_NBSL_EXT_ERR_RES
: /* Reserved field */
2305 case F10_NBSL_EXT_ERR_ECC
: /* F10 ECC ext err code */
2309 amd64_mc_printk(mci
, KERN_ERR
, "NOT ECC: no special error "
2310 "handling for this error\n");
2314 if (info
->nbsh
& K8_NBSH_CECC
)
2315 amd64_handle_ce(mci
, info
);
2316 else if (info
->nbsh
& K8_NBSH_UECC
)
2317 amd64_handle_ue(mci
, info
);
2320 * If main error is CE then overflow must be CE. If main error is UE
2321 * then overflow is unknown. We'll call the overflow a CE - if
2322 * panic_on_ue is set then we're already panic'ed and won't arrive
2323 * here. Else, then apparently someone doesn't think that UE's are
2326 if (info
->nbsh
& K8_NBSH_OVERFLOW
)
2327 edac_mc_handle_ce_no_info(mci
, EDAC_MOD_STR
2328 "Error Overflow set");
2331 int amd64_process_error_info(struct mem_ctl_info
*mci
,
2332 struct amd64_error_info_regs
*info
,
2335 struct amd64_pvt
*pvt
;
2336 struct amd64_error_info_regs
*regs
;
2337 u32 err_code
, ext_ec
;
2338 int gart_tlb_error
= 0;
2340 pvt
= mci
->pvt_info
;
2342 /* If caller doesn't want us to process the error, return */
2348 debugf1("NorthBridge ERROR: mci(0x%p)\n", mci
);
2349 debugf1(" MC node(%d) Error-Address(0x%.8x-%.8x)\n",
2350 pvt
->mc_node_id
, regs
->nbeah
, regs
->nbeal
);
2351 debugf1(" nbsh(0x%.8x) nbsl(0x%.8x)\n",
2352 regs
->nbsh
, regs
->nbsl
);
2353 debugf1(" Valid Error=%s Overflow=%s\n",
2354 (regs
->nbsh
& K8_NBSH_VALID_BIT
) ? "True" : "False",
2355 (regs
->nbsh
& K8_NBSH_OVERFLOW
) ? "True" : "False");
2356 debugf1(" Err Uncorrected=%s MCA Error Reporting=%s\n",
2357 (regs
->nbsh
& K8_NBSH_UNCORRECTED_ERR
) ?
2359 (regs
->nbsh
& K8_NBSH_ERR_ENABLE
) ?
2361 debugf1(" MiscErr Valid=%s ErrAddr Valid=%s PCC=%s\n",
2362 (regs
->nbsh
& K8_NBSH_MISC_ERR_VALID
) ?
2364 (regs
->nbsh
& K8_NBSH_VALID_ERROR_ADDR
) ?
2366 (regs
->nbsh
& K8_NBSH_PCC
) ?
2368 debugf1(" CECC=%s UECC=%s Found by Scruber=%s\n",
2369 (regs
->nbsh
& K8_NBSH_CECC
) ?
2371 (regs
->nbsh
& K8_NBSH_UECC
) ?
2373 (regs
->nbsh
& K8_NBSH_ERR_SCRUBER
) ?
2375 debugf1(" CORE0=%s CORE1=%s CORE2=%s CORE3=%s\n",
2376 (regs
->nbsh
& K8_NBSH_CORE0
) ? "True" : "False",
2377 (regs
->nbsh
& K8_NBSH_CORE1
) ? "True" : "False",
2378 (regs
->nbsh
& K8_NBSH_CORE2
) ? "True" : "False",
2379 (regs
->nbsh
& K8_NBSH_CORE3
) ? "True" : "False");
2382 err_code
= EXTRACT_ERROR_CODE(regs
->nbsl
);
2384 /* Determine which error type:
2385 * 1) GART errors - non-fatal, developmental events
2390 if (TEST_TLB_ERROR(err_code
)) {
2392 * GART errors are intended to help graphics driver developers
2393 * to detect bad GART PTEs. It is recommended by AMD to disable
2394 * GART table walk error reporting by default[1] (currently
2395 * being disabled in mce_cpu_quirks()) and according to the
2396 * comment in mce_cpu_quirks(), such GART errors can be
2397 * incorrectly triggered. We may see these errors anyway and
2398 * unless requested by the user, they won't be reported.
2400 * [1] section 13.10.1 on BIOS and Kernel Developers Guide for
2401 * AMD NPT family 0Fh processors
2403 if (report_gart_errors
== 0)
2407 * Only if GART error reporting is requested should we generate
2412 debugf1("GART TLB error\n");
2413 amd64_decode_gart_tlb_error(mci
, info
);
2414 } else if (TEST_MEM_ERROR(err_code
)) {
2415 debugf1("Memory/Cache error\n");
2416 amd64_decode_mem_cache_error(mci
, info
);
2417 } else if (TEST_BUS_ERROR(err_code
)) {
2418 debugf1("Bus (Link/DRAM) error\n");
2419 amd64_decode_bus_error(mci
, info
);
2421 /* shouldn't reach here! */
2422 amd64_mc_printk(mci
, KERN_WARNING
,
2423 "%s(): unknown MCE error 0x%x\n", __func__
,
2427 ext_ec
= EXTRACT_EXT_ERROR_CODE(regs
->nbsl
);
2428 amd64_mc_printk(mci
, KERN_ERR
,
2429 "ExtErr=(0x%x) %s\n", ext_ec
, ext_msgs
[ext_ec
]);
2431 if (((ext_ec
>= F10_NBSL_EXT_ERR_CRC
&&
2432 ext_ec
<= F10_NBSL_EXT_ERR_TGT
) ||
2433 (ext_ec
== F10_NBSL_EXT_ERR_RMW
)) &&
2434 EXTRACT_LDT_LINK(info
->nbsh
)) {
2436 amd64_mc_printk(mci
, KERN_ERR
,
2437 "Error on hypertransport link: %s\n",
2439 EXTRACT_LDT_LINK(info
->nbsh
)]);
2443 * Check the UE bit of the NB status high register, if set generate some
2444 * logs. If NOT a GART error, then process the event as a NO-INFO event.
2445 * If it was a GART error, skip that process.
2447 if (regs
->nbsh
& K8_NBSH_UNCORRECTED_ERR
) {
2448 amd64_mc_printk(mci
, KERN_CRIT
, "uncorrected error\n");
2449 if (!gart_tlb_error
)
2450 edac_mc_handle_ue_no_info(mci
, "UE bit is set\n");
2453 if (regs
->nbsh
& K8_NBSH_PCC
)
2454 amd64_mc_printk(mci
, KERN_CRIT
,
2455 "PCC (processor context corrupt) set\n");
2459 EXPORT_SYMBOL_GPL(amd64_process_error_info
);
2462 * The main polling 'check' function, called FROM the edac core to perform the
2463 * error checking and if an error is encountered, error processing.
2465 static void amd64_check(struct mem_ctl_info
*mci
)
2467 struct amd64_error_info_regs info
;
2469 if (amd64_get_error_info(mci
, &info
))
2470 amd64_process_error_info(mci
, &info
, 1);
2475 * 1) struct amd64_pvt which contains pvt->dram_f2_ctl pointer
2476 * 2) AMD Family index value
2479 * Upon return of 0, the following filled in:
2481 * struct pvt->addr_f1_ctl
2482 * struct pvt->misc_f3_ctl
2484 * Filled in with related device funcitions of 'dram_f2_ctl'
2485 * These devices are "reserved" via the pci_get_device()
2487 * Upon return of 1 (error status):
2491 static int amd64_reserve_mc_sibling_devices(struct amd64_pvt
*pvt
, int mc_idx
)
2493 const struct amd64_family_type
*amd64_dev
= &amd64_family_types
[mc_idx
];
2495 /* Reserve the ADDRESS MAP Device */
2496 pvt
->addr_f1_ctl
= pci_get_related_function(pvt
->dram_f2_ctl
->vendor
,
2497 amd64_dev
->addr_f1_ctl
,
2500 if (!pvt
->addr_f1_ctl
) {
2501 amd64_printk(KERN_ERR
, "error address map device not found: "
2502 "vendor %x device 0x%x (broken BIOS?)\n",
2503 PCI_VENDOR_ID_AMD
, amd64_dev
->addr_f1_ctl
);
2507 /* Reserve the MISC Device */
2508 pvt
->misc_f3_ctl
= pci_get_related_function(pvt
->dram_f2_ctl
->vendor
,
2509 amd64_dev
->misc_f3_ctl
,
2512 if (!pvt
->misc_f3_ctl
) {
2513 pci_dev_put(pvt
->addr_f1_ctl
);
2514 pvt
->addr_f1_ctl
= NULL
;
2516 amd64_printk(KERN_ERR
, "error miscellaneous device not found: "
2517 "vendor %x device 0x%x (broken BIOS?)\n",
2518 PCI_VENDOR_ID_AMD
, amd64_dev
->misc_f3_ctl
);
2522 debugf1(" Addr Map device PCI Bus ID:\t%s\n",
2523 pci_name(pvt
->addr_f1_ctl
));
2524 debugf1(" DRAM MEM-CTL PCI Bus ID:\t%s\n",
2525 pci_name(pvt
->dram_f2_ctl
));
2526 debugf1(" Misc device PCI Bus ID:\t%s\n",
2527 pci_name(pvt
->misc_f3_ctl
));
2532 static void amd64_free_mc_sibling_devices(struct amd64_pvt
*pvt
)
2534 pci_dev_put(pvt
->addr_f1_ctl
);
2535 pci_dev_put(pvt
->misc_f3_ctl
);
2539 * Retrieve the hardware registers of the memory controller (this includes the
2540 * 'Address Map' and 'Misc' device regs)
2542 static void amd64_read_mc_registers(struct amd64_pvt
*pvt
)
2548 * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since
2549 * those are Read-As-Zero
2551 rdmsrl(MSR_K8_TOP_MEM1
, msr_val
);
2552 pvt
->top_mem
= msr_val
>> 23;
2553 debugf0(" TOP_MEM=0x%08llx\n", pvt
->top_mem
);
2555 /* check first whether TOP_MEM2 is enabled */
2556 rdmsrl(MSR_K8_SYSCFG
, msr_val
);
2557 if (msr_val
& (1U << 21)) {
2558 rdmsrl(MSR_K8_TOP_MEM2
, msr_val
);
2559 pvt
->top_mem2
= msr_val
>> 23;
2560 debugf0(" TOP_MEM2=0x%08llx\n", pvt
->top_mem2
);
2562 debugf0(" TOP_MEM2 disabled.\n");
2564 amd64_cpu_display_info(pvt
);
2566 err
= pci_read_config_dword(pvt
->misc_f3_ctl
, K8_NBCAP
, &pvt
->nbcap
);
2570 if (pvt
->ops
->read_dram_ctl_register
)
2571 pvt
->ops
->read_dram_ctl_register(pvt
);
2573 for (dram
= 0; dram
< DRAM_REG_COUNT
; dram
++) {
2575 * Call CPU specific READ function to get the DRAM Base and
2576 * Limit values from the DCT.
2578 pvt
->ops
->read_dram_base_limit(pvt
, dram
);
2581 * Only print out debug info on rows with both R and W Enabled.
2582 * Normal processing, compiler should optimize this whole 'if'
2583 * debug output block away.
2585 if (pvt
->dram_rw_en
[dram
] != 0) {
2586 debugf1(" DRAM_BASE[%d]: 0x%8.08x-%8.08x "
2587 "DRAM_LIMIT: 0x%8.08x-%8.08x\n",
2589 (u32
)(pvt
->dram_base
[dram
] >> 32),
2590 (u32
)(pvt
->dram_base
[dram
] & 0xFFFFFFFF),
2591 (u32
)(pvt
->dram_limit
[dram
] >> 32),
2592 (u32
)(pvt
->dram_limit
[dram
] & 0xFFFFFFFF));
2593 debugf1(" IntlvEn=%s %s %s "
2594 "IntlvSel=%d DstNode=%d\n",
2595 pvt
->dram_IntlvEn
[dram
] ?
2596 "Enabled" : "Disabled",
2597 (pvt
->dram_rw_en
[dram
] & 0x2) ? "W" : "!W",
2598 (pvt
->dram_rw_en
[dram
] & 0x1) ? "R" : "!R",
2599 pvt
->dram_IntlvSel
[dram
],
2600 pvt
->dram_DstNode
[dram
]);
2604 amd64_read_dct_base_mask(pvt
);
2606 err
= pci_read_config_dword(pvt
->addr_f1_ctl
, K8_DHAR
, &pvt
->dhar
);
2610 amd64_read_dbam_reg(pvt
);
2612 err
= pci_read_config_dword(pvt
->misc_f3_ctl
,
2613 F10_ONLINE_SPARE
, &pvt
->online_spare
);
2617 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, F10_DCLR_0
, &pvt
->dclr0
);
2621 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, F10_DCHR_0
, &pvt
->dchr0
);
2625 if (!dct_ganging_enabled(pvt
)) {
2626 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, F10_DCLR_1
,
2631 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, F10_DCHR_1
,
2637 amd64_dump_misc_regs(pvt
);
2642 debugf0("Reading an MC register failed\n");
2647 * NOTE: CPU Revision Dependent code
2650 * @csrow_nr ChipSelect Row Number (0..CHIPSELECT_COUNT-1)
2651 * k8 private pointer to -->
2652 * DRAM Bank Address mapping register
2654 * DCL register where dual_channel_active is
2656 * The DBAM register consists of 4 sets of 4 bits each definitions:
2659 * 0-3 CSROWs 0 and 1
2660 * 4-7 CSROWs 2 and 3
2661 * 8-11 CSROWs 4 and 5
2662 * 12-15 CSROWs 6 and 7
2664 * Values range from: 0 to 15
2665 * The meaning of the values depends on CPU revision and dual-channel state,
2666 * see relevant BKDG more info.
2668 * The memory controller provides for total of only 8 CSROWs in its current
2669 * architecture. Each "pair" of CSROWs normally represents just one DIMM in
2670 * single channel or two (2) DIMMs in dual channel mode.
2672 * The following code logic collapses the various tables for CSROW based on CPU
2676 * The number of PAGE_SIZE pages on the specified CSROW number it
2680 static u32
amd64_csrow_nr_pages(int csrow_nr
, struct amd64_pvt
*pvt
)
2682 u32 dram_map
, nr_pages
;
2685 * The math on this doesn't look right on the surface because x/2*4 can
2686 * be simplified to x*2 but this expression makes use of the fact that
2687 * it is integral math where 1/2=0. This intermediate value becomes the
2688 * number of bits to shift the DBAM register to extract the proper CSROW
2691 dram_map
= (pvt
->dbam0
>> ((csrow_nr
/ 2) * 4)) & 0xF;
2693 nr_pages
= pvt
->ops
->dbam_map_to_pages(pvt
, dram_map
);
2696 * If dual channel then double the memory size of single channel.
2697 * Channel count is 1 or 2
2699 nr_pages
<<= (pvt
->channel_count
- 1);
2701 debugf0(" (csrow=%d) DBAM map index= %d\n", csrow_nr
, dram_map
);
2702 debugf0(" nr_pages= %u channel-count = %d\n",
2703 nr_pages
, pvt
->channel_count
);
2709 * Initialize the array of csrow attribute instances, based on the values
2710 * from pci config hardware registers.
2712 static int amd64_init_csrows(struct mem_ctl_info
*mci
)
2714 struct csrow_info
*csrow
;
2715 struct amd64_pvt
*pvt
;
2716 u64 input_addr_min
, input_addr_max
, sys_addr
;
2717 int i
, err
= 0, empty
= 1;
2719 pvt
= mci
->pvt_info
;
2721 err
= pci_read_config_dword(pvt
->misc_f3_ctl
, K8_NBCFG
, &pvt
->nbcfg
);
2723 debugf0("Reading K8_NBCFG failed\n");
2725 debugf0("NBCFG= 0x%x CHIPKILL= %s DRAM ECC= %s\n", pvt
->nbcfg
,
2726 (pvt
->nbcfg
& K8_NBCFG_CHIPKILL
) ? "Enabled" : "Disabled",
2727 (pvt
->nbcfg
& K8_NBCFG_ECC_ENABLE
) ? "Enabled" : "Disabled"
2730 for (i
= 0; i
< CHIPSELECT_COUNT
; i
++) {
2731 csrow
= &mci
->csrows
[i
];
2733 if ((pvt
->dcsb0
[i
] & K8_DCSB_CS_ENABLE
) == 0) {
2734 debugf1("----CSROW %d EMPTY for node %d\n", i
,
2739 debugf1("----CSROW %d VALID for MC node %d\n",
2740 i
, pvt
->mc_node_id
);
2743 csrow
->nr_pages
= amd64_csrow_nr_pages(i
, pvt
);
2744 find_csrow_limits(mci
, i
, &input_addr_min
, &input_addr_max
);
2745 sys_addr
= input_addr_to_sys_addr(mci
, input_addr_min
);
2746 csrow
->first_page
= (u32
) (sys_addr
>> PAGE_SHIFT
);
2747 sys_addr
= input_addr_to_sys_addr(mci
, input_addr_max
);
2748 csrow
->last_page
= (u32
) (sys_addr
>> PAGE_SHIFT
);
2749 csrow
->page_mask
= ~mask_from_dct_mask(pvt
, i
);
2750 /* 8 bytes of resolution */
2752 csrow
->mtype
= amd64_determine_memory_type(pvt
);
2754 debugf1(" for MC node %d csrow %d:\n", pvt
->mc_node_id
, i
);
2755 debugf1(" input_addr_min: 0x%lx input_addr_max: 0x%lx\n",
2756 (unsigned long)input_addr_min
,
2757 (unsigned long)input_addr_max
);
2758 debugf1(" sys_addr: 0x%lx page_mask: 0x%lx\n",
2759 (unsigned long)sys_addr
, csrow
->page_mask
);
2760 debugf1(" nr_pages: %u first_page: 0x%lx "
2761 "last_page: 0x%lx\n",
2762 (unsigned)csrow
->nr_pages
,
2763 csrow
->first_page
, csrow
->last_page
);
2766 * determine whether CHIPKILL or JUST ECC or NO ECC is operating
2768 if (pvt
->nbcfg
& K8_NBCFG_ECC_ENABLE
)
2770 (pvt
->nbcfg
& K8_NBCFG_CHIPKILL
) ?
2771 EDAC_S4ECD4ED
: EDAC_SECDED
;
2773 csrow
->edac_mode
= EDAC_NONE
;
2780 * Only if 'ecc_enable_override' is set AND BIOS had ECC disabled, do "we"
2783 static void amd64_enable_ecc_error_reporting(struct mem_ctl_info
*mci
)
2785 struct amd64_pvt
*pvt
= mci
->pvt_info
;
2786 const cpumask_t
*cpumask
= cpumask_of_node(pvt
->mc_node_id
);
2787 int cpu
, idx
= 0, err
= 0;
2788 struct msr msrs
[cpumask_weight(cpumask
)];
2790 u32 mask
= K8_NBCTL_CECCEn
| K8_NBCTL_UECCEn
;
2792 if (!ecc_enable_override
)
2795 memset(msrs
, 0, sizeof(msrs
));
2797 amd64_printk(KERN_WARNING
,
2798 "'ecc_enable_override' parameter is active, "
2799 "Enabling AMD ECC hardware now: CAUTION\n");
2801 err
= pci_read_config_dword(pvt
->misc_f3_ctl
, K8_NBCTL
, &value
);
2803 debugf0("Reading K8_NBCTL failed\n");
2805 /* turn on UECCn and CECCEn bits */
2806 pvt
->old_nbctl
= value
& mask
;
2807 pvt
->nbctl_mcgctl_saved
= 1;
2810 pci_write_config_dword(pvt
->misc_f3_ctl
, K8_NBCTL
, value
);
2812 rdmsr_on_cpus(cpumask
, K8_MSR_MCGCTL
, msrs
);
2814 for_each_cpu(cpu
, cpumask
) {
2815 if (msrs
[idx
].l
& K8_MSR_MCGCTL_NBE
)
2816 set_bit(idx
, &pvt
->old_mcgctl
);
2818 msrs
[idx
].l
|= K8_MSR_MCGCTL_NBE
;
2821 wrmsr_on_cpus(cpumask
, K8_MSR_MCGCTL
, msrs
);
2823 err
= pci_read_config_dword(pvt
->misc_f3_ctl
, K8_NBCFG
, &value
);
2825 debugf0("Reading K8_NBCFG failed\n");
2827 debugf0("NBCFG(1)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value
,
2828 (value
& K8_NBCFG_CHIPKILL
) ? "Enabled" : "Disabled",
2829 (value
& K8_NBCFG_ECC_ENABLE
) ? "Enabled" : "Disabled");
2831 if (!(value
& K8_NBCFG_ECC_ENABLE
)) {
2832 amd64_printk(KERN_WARNING
,
2833 "This node reports that DRAM ECC is "
2834 "currently Disabled; ENABLING now\n");
2836 /* Attempt to turn on DRAM ECC Enable */
2837 value
|= K8_NBCFG_ECC_ENABLE
;
2838 pci_write_config_dword(pvt
->misc_f3_ctl
, K8_NBCFG
, value
);
2840 err
= pci_read_config_dword(pvt
->misc_f3_ctl
, K8_NBCFG
, &value
);
2842 debugf0("Reading K8_NBCFG failed\n");
2844 if (!(value
& K8_NBCFG_ECC_ENABLE
)) {
2845 amd64_printk(KERN_WARNING
,
2846 "Hardware rejects Enabling DRAM ECC checking\n"
2847 "Check memory DIMM configuration\n");
2849 amd64_printk(KERN_DEBUG
,
2850 "Hardware accepted DRAM ECC Enable\n");
2853 debugf0("NBCFG(2)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value
,
2854 (value
& K8_NBCFG_CHIPKILL
) ? "Enabled" : "Disabled",
2855 (value
& K8_NBCFG_ECC_ENABLE
) ? "Enabled" : "Disabled");
2857 pvt
->ctl_error_info
.nbcfg
= value
;
2860 static void amd64_restore_ecc_error_reporting(struct amd64_pvt
*pvt
)
2862 const cpumask_t
*cpumask
= cpumask_of_node(pvt
->mc_node_id
);
2863 int cpu
, idx
= 0, err
= 0;
2864 struct msr msrs
[cpumask_weight(cpumask
)];
2866 u32 mask
= K8_NBCTL_CECCEn
| K8_NBCTL_UECCEn
;
2868 if (!pvt
->nbctl_mcgctl_saved
)
2871 memset(msrs
, 0, sizeof(msrs
));
2873 err
= pci_read_config_dword(pvt
->misc_f3_ctl
, K8_NBCTL
, &value
);
2875 debugf0("Reading K8_NBCTL failed\n");
2877 value
|= pvt
->old_nbctl
;
2879 /* restore the NB Enable MCGCTL bit */
2880 pci_write_config_dword(pvt
->misc_f3_ctl
, K8_NBCTL
, value
);
2882 rdmsr_on_cpus(cpumask
, K8_MSR_MCGCTL
, msrs
);
2884 for_each_cpu(cpu
, cpumask
) {
2885 msrs
[idx
].l
&= ~K8_MSR_MCGCTL_NBE
;
2887 test_bit(idx
, &pvt
->old_mcgctl
) << K8_MSR_MCGCTL_NBE
;
2891 wrmsr_on_cpus(cpumask
, K8_MSR_MCGCTL
, msrs
);
2894 static void check_mcg_ctl(void *ret
)
2899 rdmsrl(MSR_IA32_MCG_CTL
, msr_val
);
2900 nbe
= msr_val
& K8_MSR_MCGCTL_NBE
;
2902 debugf0("core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",
2903 raw_smp_processor_id(), msr_val
,
2904 (nbe
? "enabled" : "disabled"));
2910 /* check MCG_CTL on all the cpus on this node */
2911 static int amd64_mcg_ctl_enabled_on_cpus(const cpumask_t
*mask
)
2915 smp_call_function_many(mask
, check_mcg_ctl
, &ret
, 1);
2922 * EDAC requires that the BIOS have ECC enabled before taking over the
2923 * processing of ECC errors. This is because the BIOS can properly initialize
2924 * the memory system completely. A command line option allows to force-enable
2925 * hardware ECC later in amd64_enable_ecc_error_reporting().
2927 static int amd64_check_ecc_enabled(struct amd64_pvt
*pvt
)
2930 int err
= 0, ret
= 0;
2933 err
= pci_read_config_dword(pvt
->misc_f3_ctl
, K8_NBCFG
, &value
);
2935 debugf0("Reading K8_NBCTL failed\n");
2937 ecc_enabled
= !!(value
& K8_NBCFG_ECC_ENABLE
);
2939 ret
= amd64_mcg_ctl_enabled_on_cpus(cpumask_of_node(pvt
->mc_node_id
));
2941 debugf0("K8_NBCFG=0x%x, DRAM ECC is %s\n", value
,
2942 (value
& K8_NBCFG_ECC_ENABLE
? "enabled" : "disabled"));
2944 if (!ecc_enabled
|| !ret
) {
2946 amd64_printk(KERN_WARNING
, "This node reports that "
2947 "Memory ECC is currently "
2950 amd64_printk(KERN_WARNING
, "bit 0x%lx in register "
2951 "F3x%x of the MISC_CONTROL device (%s) "
2952 "should be enabled\n", K8_NBCFG_ECC_ENABLE
,
2953 K8_NBCFG
, pci_name(pvt
->misc_f3_ctl
));
2956 amd64_printk(KERN_WARNING
, "bit 0x%016lx in MSR 0x%08x "
2957 "of node %d should be enabled\n",
2958 K8_MSR_MCGCTL_NBE
, MSR_IA32_MCG_CTL
,
2961 if (!ecc_enable_override
) {
2962 amd64_printk(KERN_WARNING
, "WARNING: ECC is NOT "
2963 "currently enabled by the BIOS. Module "
2964 "will NOT be loaded.\n"
2965 " Either Enable ECC in the BIOS, "
2966 "or use the 'ecc_enable_override' "
2968 " Might be a BIOS bug, if BIOS says "
2970 " Use of the override can cause "
2971 "unknown side effects.\n");
2975 * enable further driver loading if ECC enable is
2980 amd64_printk(KERN_INFO
,
2981 "ECC is enabled by BIOS, Proceeding "
2982 "with EDAC module initialization\n");
2984 /* Signal good ECC status */
2987 /* CLEAR the override, since BIOS controlled it */
2988 ecc_enable_override
= 0;
2994 struct mcidev_sysfs_attribute sysfs_attrs
[ARRAY_SIZE(amd64_dbg_attrs
) +
2995 ARRAY_SIZE(amd64_inj_attrs
) +
2998 struct mcidev_sysfs_attribute terminator
= { .attr
= { .name
= NULL
} };
3000 static void amd64_set_mc_sysfs_attributes(struct mem_ctl_info
*mci
)
3002 unsigned int i
= 0, j
= 0;
3004 for (; i
< ARRAY_SIZE(amd64_dbg_attrs
); i
++)
3005 sysfs_attrs
[i
] = amd64_dbg_attrs
[i
];
3007 for (j
= 0; j
< ARRAY_SIZE(amd64_inj_attrs
); j
++, i
++)
3008 sysfs_attrs
[i
] = amd64_inj_attrs
[j
];
3010 sysfs_attrs
[i
] = terminator
;
3012 mci
->mc_driver_sysfs_attributes
= sysfs_attrs
;
3015 static void amd64_setup_mci_misc_attributes(struct mem_ctl_info
*mci
)
3017 struct amd64_pvt
*pvt
= mci
->pvt_info
;
3019 mci
->mtype_cap
= MEM_FLAG_DDR2
| MEM_FLAG_RDDR2
;
3020 mci
->edac_ctl_cap
= EDAC_FLAG_NONE
;
3022 if (pvt
->nbcap
& K8_NBCAP_SECDED
)
3023 mci
->edac_ctl_cap
|= EDAC_FLAG_SECDED
;
3025 if (pvt
->nbcap
& K8_NBCAP_CHIPKILL
)
3026 mci
->edac_ctl_cap
|= EDAC_FLAG_S4ECD4ED
;
3028 mci
->edac_cap
= amd64_determine_edac_cap(pvt
);
3029 mci
->mod_name
= EDAC_MOD_STR
;
3030 mci
->mod_ver
= EDAC_AMD64_VERSION
;
3031 mci
->ctl_name
= get_amd_family_name(pvt
->mc_type_index
);
3032 mci
->dev_name
= pci_name(pvt
->dram_f2_ctl
);
3033 mci
->ctl_page_to_phys
= NULL
;
3035 /* IMPORTANT: Set the polling 'check' function in this module */
3036 mci
->edac_check
= amd64_check
;
3038 /* memory scrubber interface */
3039 mci
->set_sdram_scrub_rate
= amd64_set_scrub_rate
;
3040 mci
->get_sdram_scrub_rate
= amd64_get_scrub_rate
;
3044 * Init stuff for this DRAM Controller device.
3046 * Due to a hardware feature on Fam10h CPUs, the Enable Extended Configuration
3047 * Space feature MUST be enabled on ALL Processors prior to actually reading
3048 * from the ECS registers. Since the loading of the module can occur on any
3049 * 'core', and cores don't 'see' all the other processors ECS data when the
3050 * others are NOT enabled. Our solution is to first enable ECS access in this
3051 * routine on all processors, gather some data in a amd64_pvt structure and
3052 * later come back in a finish-setup function to perform that final
3053 * initialization. See also amd64_init_2nd_stage() for that.
3055 static int amd64_probe_one_instance(struct pci_dev
*dram_f2_ctl
,
3058 struct amd64_pvt
*pvt
= NULL
;
3062 pvt
= kzalloc(sizeof(struct amd64_pvt
), GFP_KERNEL
);
3066 pvt
->mc_node_id
= get_node_id(dram_f2_ctl
);
3068 pvt
->dram_f2_ctl
= dram_f2_ctl
;
3069 pvt
->ext_model
= boot_cpu_data
.x86_model
>> 4;
3070 pvt
->mc_type_index
= mc_type_index
;
3071 pvt
->ops
= family_ops(mc_type_index
);
3072 pvt
->old_mcgctl
= 0;
3075 * We have the dram_f2_ctl device as an argument, now go reserve its
3076 * sibling devices from the PCI system.
3079 err
= amd64_reserve_mc_sibling_devices(pvt
, mc_type_index
);
3084 err
= amd64_check_ecc_enabled(pvt
);
3089 * Key operation here: setup of HW prior to performing ops on it. Some
3090 * setup is required to access ECS data. After this is performed, the
3091 * 'teardown' function must be called upon error and normal exit paths.
3093 if (boot_cpu_data
.x86
>= 0x10)
3097 * Save the pointer to the private data for use in 2nd initialization
3100 pvt_lookup
[pvt
->mc_node_id
] = pvt
;
3105 amd64_free_mc_sibling_devices(pvt
);
3115 * This is the finishing stage of the init code. Needs to be performed after all
3116 * MCs' hardware have been prepped for accessing extended config space.
3118 static int amd64_init_2nd_stage(struct amd64_pvt
*pvt
)
3120 int node_id
= pvt
->mc_node_id
;
3121 struct mem_ctl_info
*mci
;
3124 amd64_read_mc_registers(pvt
);
3127 if (pvt
->ops
->probe_valid_hardware
) {
3128 err
= pvt
->ops
->probe_valid_hardware(pvt
);
3134 * We need to determine how many memory channels there are. Then use
3135 * that information for calculating the size of the dynamic instance
3136 * tables in the 'mci' structure
3138 pvt
->channel_count
= pvt
->ops
->early_channel_count(pvt
);
3139 if (pvt
->channel_count
< 0)
3143 mci
= edac_mc_alloc(0, CHIPSELECT_COUNT
, pvt
->channel_count
, node_id
);
3147 mci
->pvt_info
= pvt
;
3149 mci
->dev
= &pvt
->dram_f2_ctl
->dev
;
3150 amd64_setup_mci_misc_attributes(mci
);
3152 if (amd64_init_csrows(mci
))
3153 mci
->edac_cap
= EDAC_FLAG_NONE
;
3155 amd64_enable_ecc_error_reporting(mci
);
3156 amd64_set_mc_sysfs_attributes(mci
);
3159 if (edac_mc_add_mc(mci
)) {
3160 debugf1("failed edac_mc_add_mc()\n");
3164 mci_lookup
[node_id
] = mci
;
3165 pvt_lookup
[node_id
] = NULL
;
3172 debugf0("failure to init 2nd stage: ret=%d\n", ret
);
3174 amd64_restore_ecc_error_reporting(pvt
);
3176 if (boot_cpu_data
.x86
> 0xf)
3177 amd64_teardown(pvt
);
3179 amd64_free_mc_sibling_devices(pvt
);
3181 kfree(pvt_lookup
[pvt
->mc_node_id
]);
3182 pvt_lookup
[node_id
] = NULL
;
3188 static int __devinit
amd64_init_one_instance(struct pci_dev
*pdev
,
3189 const struct pci_device_id
*mc_type
)
3193 debugf0("(MC node=%d,mc_type='%s')\n", get_node_id(pdev
),
3194 get_amd_family_name(mc_type
->driver_data
));
3196 ret
= pci_enable_device(pdev
);
3200 ret
= amd64_probe_one_instance(pdev
, mc_type
->driver_data
);
3203 debugf0("ret=%d\n", ret
);
3208 static void __devexit
amd64_remove_one_instance(struct pci_dev
*pdev
)
3210 struct mem_ctl_info
*mci
;
3211 struct amd64_pvt
*pvt
;
3213 /* Remove from EDAC CORE tracking list */
3214 mci
= edac_mc_del_mc(&pdev
->dev
);
3218 pvt
= mci
->pvt_info
;
3220 amd64_restore_ecc_error_reporting(pvt
);
3222 if (boot_cpu_data
.x86
> 0xf)
3223 amd64_teardown(pvt
);
3225 amd64_free_mc_sibling_devices(pvt
);
3228 mci
->pvt_info
= NULL
;
3230 mci_lookup
[pvt
->mc_node_id
] = NULL
;
3232 /* Free the EDAC CORE resources */
3237 * This table is part of the interface for loading drivers for PCI devices. The
3238 * PCI core identifies what devices are on a system during boot, and then
3239 * inquiry this table to see if this driver is for a given device found.
3241 static const struct pci_device_id amd64_pci_table
[] __devinitdata
= {
3243 .vendor
= PCI_VENDOR_ID_AMD
,
3244 .device
= PCI_DEVICE_ID_AMD_K8_NB_MEMCTL
,
3245 .subvendor
= PCI_ANY_ID
,
3246 .subdevice
= PCI_ANY_ID
,
3249 .driver_data
= K8_CPUS
3252 .vendor
= PCI_VENDOR_ID_AMD
,
3253 .device
= PCI_DEVICE_ID_AMD_10H_NB_DRAM
,
3254 .subvendor
= PCI_ANY_ID
,
3255 .subdevice
= PCI_ANY_ID
,
3258 .driver_data
= F10_CPUS
3261 .vendor
= PCI_VENDOR_ID_AMD
,
3262 .device
= PCI_DEVICE_ID_AMD_11H_NB_DRAM
,
3263 .subvendor
= PCI_ANY_ID
,
3264 .subdevice
= PCI_ANY_ID
,
3267 .driver_data
= F11_CPUS
3271 MODULE_DEVICE_TABLE(pci
, amd64_pci_table
);
3273 static struct pci_driver amd64_pci_driver
= {
3274 .name
= EDAC_MOD_STR
,
3275 .probe
= amd64_init_one_instance
,
3276 .remove
= __devexit_p(amd64_remove_one_instance
),
3277 .id_table
= amd64_pci_table
,
3280 static void amd64_setup_pci_device(void)
3282 struct mem_ctl_info
*mci
;
3283 struct amd64_pvt
*pvt
;
3288 mci
= mci_lookup
[0];
3291 pvt
= mci
->pvt_info
;
3293 edac_pci_create_generic_ctl(&pvt
->dram_f2_ctl
->dev
,
3296 if (!amd64_ctl_pci
) {
3297 pr_warning("%s(): Unable to create PCI control\n",
3300 pr_warning("%s(): PCI error report via EDAC not set\n",
3306 static int __init
amd64_edac_init(void)
3308 int nb
, err
= -ENODEV
;
3310 edac_printk(KERN_INFO
, EDAC_MOD_STR
, EDAC_AMD64_VERSION
"\n");
3314 if (cache_k8_northbridges() < 0)
3317 err
= pci_register_driver(&amd64_pci_driver
);
3322 * At this point, the array 'pvt_lookup[]' contains pointers to alloc'd
3323 * amd64_pvt structs. These will be used in the 2nd stage init function
3324 * to finish initialization of the MC instances.
3326 for (nb
= 0; nb
< num_k8_northbridges
; nb
++) {
3327 if (!pvt_lookup
[nb
])
3330 err
= amd64_init_2nd_stage(pvt_lookup
[nb
]);
3335 amd64_setup_pci_device();
3340 debugf0("2nd stage failed\n");
3343 pci_unregister_driver(&amd64_pci_driver
);
3348 static void __exit
amd64_edac_exit(void)
3351 edac_pci_release_generic_ctl(amd64_ctl_pci
);
3353 pci_unregister_driver(&amd64_pci_driver
);
3356 module_init(amd64_edac_init
);
3357 module_exit(amd64_edac_exit
);
3359 MODULE_LICENSE("GPL");
3360 MODULE_AUTHOR("SoftwareBitMaker: Doug Thompson, "
3361 "Dave Peterson, Thayne Harbaugh");
3362 MODULE_DESCRIPTION("MC support for AMD64 memory controllers - "
3363 EDAC_AMD64_VERSION
);
3365 module_param(edac_op_state
, int, 0444);
3366 MODULE_PARM_DESC(edac_op_state
, "EDAC Error Reporting state: 0=Poll,1=NMI");