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Merge commit 'v2.6.32.11' into mini2440-stable-v2.6.32
[linux-2.6/mini2440.git] / drivers / mfd / wm8350-core.c
blobca6b098a8fd697f56ba563120c346179fec9c7a9
1 /*
2 * wm8350-core.c -- Device access for Wolfson WM8350
3 *
4 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
5 *
6 * Author: Liam Girdwood, Mark Brown
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/bug.h>
19 #include <linux/device.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/workqueue.h>
23
24 #include <linux/mfd/wm8350/core.h>
25 #include <linux/mfd/wm8350/audio.h>
26 #include <linux/mfd/wm8350/comparator.h>
27 #include <linux/mfd/wm8350/gpio.h>
28 #include <linux/mfd/wm8350/pmic.h>
29 #include <linux/mfd/wm8350/rtc.h>
30 #include <linux/mfd/wm8350/supply.h>
31 #include <linux/mfd/wm8350/wdt.h>
32
33 #define WM8350_UNLOCK_KEY 0x0013
34 #define WM8350_LOCK_KEY 0x0000
35
36 #define WM8350_CLOCK_CONTROL_1 0x28
37 #define WM8350_AIF_TEST 0x74
38
39 /* debug */
40 #define WM8350_BUS_DEBUG 0
41 #if WM8350_BUS_DEBUG
42 #define dump(regs, src) do { \
43 int i_; \
44 u16 *src_ = src; \
45 printk(KERN_DEBUG); \
46 for (i_ = 0; i_ < regs; i_++) \
47 printk(" 0x%4.4x", *src_++); \
48 printk("\n"); \
49 } while (0);
50 #else
51 #define dump(bytes, src)
52 #endif
53
54 #define WM8350_LOCK_DEBUG 0
55 #if WM8350_LOCK_DEBUG
56 #define ldbg(format, arg...) printk(format, ## arg)
57 #else
58 #define ldbg(format, arg...)
59 #endif
60
61 /*
62 * WM8350 Device IO
63 */
64 static DEFINE_MUTEX(io_mutex);
65 static DEFINE_MUTEX(reg_lock_mutex);
66
67 /* Perform a physical read from the device.
68 */
69 static int wm8350_phys_read(struct wm8350 *wm8350, u8 reg, int num_regs,
70 u16 *dest)
71 {
72 int i, ret;
73 int bytes = num_regs * 2;
74
75 dev_dbg(wm8350->dev, "volatile read\n");
76 ret = wm8350->read_dev(wm8350, reg, bytes, (char *)dest);
77
78 for (i = reg; i < reg + num_regs; i++) {
79 /* Cache is CPU endian */
80 dest[i - reg] = be16_to_cpu(dest[i - reg]);
81
82 /* Mask out non-readable bits */
83 dest[i - reg] &= wm8350_reg_io_map[i].readable;
84 }
85
86 dump(num_regs, dest);
87
88 return ret;
89 }
90
91 static int wm8350_read(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *dest)
92 {
93 int i;
94 int end = reg + num_regs;
95 int ret = 0;
96 int bytes = num_regs * 2;
97
98 if (wm8350->read_dev == NULL)
99 return -ENODEV;
100
101 if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
102 dev_err(wm8350->dev, "invalid reg %x\n",
103 reg + num_regs - 1);
104 return -EINVAL;
105 }
106
107 dev_dbg(wm8350->dev,
108 "%s R%d(0x%2.2x) %d regs\n", __func__, reg, reg, num_regs);
109
110 #if WM8350_BUS_DEBUG
111 /* we can _safely_ read any register, but warn if read not supported */
112 for (i = reg; i < end; i++) {
113 if (!wm8350_reg_io_map[i].readable)
114 dev_warn(wm8350->dev,
115 "reg R%d is not readable\n", i);
116 }
117 #endif
118
119 /* if any volatile registers are required, then read back all */
120 for (i = reg; i < end; i++)
121 if (wm8350_reg_io_map[i].vol)
122 return wm8350_phys_read(wm8350, reg, num_regs, dest);
123
124 /* no volatiles, then cache is good */
125 dev_dbg(wm8350->dev, "cache read\n");
126 memcpy(dest, &wm8350->reg_cache[reg], bytes);
127 dump(num_regs, dest);
128 return ret;
129 }
130
131 static inline int is_reg_locked(struct wm8350 *wm8350, u8 reg)
132 {
133 if (reg == WM8350_SECURITY ||
134 wm8350->reg_cache[WM8350_SECURITY] == WM8350_UNLOCK_KEY)
135 return 0;
136
137 if ((reg >= WM8350_GPIO_FUNCTION_SELECT_1 &&
138 reg <= WM8350_GPIO_FUNCTION_SELECT_4) ||
139 (reg >= WM8350_BATTERY_CHARGER_CONTROL_1 &&
140 reg <= WM8350_BATTERY_CHARGER_CONTROL_3))
141 return 1;
142 return 0;
143 }
144
145 static int wm8350_write(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *src)
146 {
147 int i;
148 int end = reg + num_regs;
149 int bytes = num_regs * 2;
150
151 if (wm8350->write_dev == NULL)
152 return -ENODEV;
153
154 if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
155 dev_err(wm8350->dev, "invalid reg %x\n",
156 reg + num_regs - 1);
157 return -EINVAL;
158 }
159
160 /* it's generally not a good idea to write to RO or locked registers */
161 for (i = reg; i < end; i++) {
162 if (!wm8350_reg_io_map[i].writable) {
163 dev_err(wm8350->dev,
164 "attempted write to read only reg R%d\n", i);
165 return -EINVAL;
166 }
167
168 if (is_reg_locked(wm8350, i)) {
169 dev_err(wm8350->dev,
170 "attempted write to locked reg R%d\n", i);
171 return -EINVAL;
172 }
173
174 src[i - reg] &= wm8350_reg_io_map[i].writable;
175
176 wm8350->reg_cache[i] =
177 (wm8350->reg_cache[i] & ~wm8350_reg_io_map[i].writable)
178 | src[i - reg];
179
180 src[i - reg] = cpu_to_be16(src[i - reg]);
181 }
182
183 /* Actually write it out */
184 return wm8350->write_dev(wm8350, reg, bytes, (char *)src);
185 }
186
187 /*
188 * Safe read, modify, write methods
189 */
190 int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
191 {
192 u16 data;
193 int err;
194
195 mutex_lock(&io_mutex);
196 err = wm8350_read(wm8350, reg, 1, &data);
197 if (err) {
198 dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
199 goto out;
200 }
201
202 data &= ~mask;
203 err = wm8350_write(wm8350, reg, 1, &data);
204 if (err)
205 dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
206 out:
207 mutex_unlock(&io_mutex);
208 return err;
209 }
210 EXPORT_SYMBOL_GPL(wm8350_clear_bits);
211
212 int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
213 {
214 u16 data;
215 int err;
216
217 mutex_lock(&io_mutex);
218 err = wm8350_read(wm8350, reg, 1, &data);
219 if (err) {
220 dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
221 goto out;
222 }
223
224 data |= mask;
225 err = wm8350_write(wm8350, reg, 1, &data);
226 if (err)
227 dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
228 out:
229 mutex_unlock(&io_mutex);
230 return err;
231 }
232 EXPORT_SYMBOL_GPL(wm8350_set_bits);
233
234 u16 wm8350_reg_read(struct wm8350 *wm8350, int reg)
235 {
236 u16 data;
237 int err;
238
239 mutex_lock(&io_mutex);
240 err = wm8350_read(wm8350, reg, 1, &data);
241 if (err)
242 dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
243
244 mutex_unlock(&io_mutex);
245 return data;
246 }
247 EXPORT_SYMBOL_GPL(wm8350_reg_read);
248
249 int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val)
250 {
251 int ret;
252 u16 data = val;
253
254 mutex_lock(&io_mutex);
255 ret = wm8350_write(wm8350, reg, 1, &data);
256 if (ret)
257 dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
258 mutex_unlock(&io_mutex);
259 return ret;
260 }
261 EXPORT_SYMBOL_GPL(wm8350_reg_write);
262
263 int wm8350_block_read(struct wm8350 *wm8350, int start_reg, int regs,
264 u16 *dest)
265 {
266 int err = 0;
267
268 mutex_lock(&io_mutex);
269 err = wm8350_read(wm8350, start_reg, regs, dest);
270 if (err)
271 dev_err(wm8350->dev, "block read starting from R%d failed\n",
272 start_reg);
273 mutex_unlock(&io_mutex);
274 return err;
275 }
276 EXPORT_SYMBOL_GPL(wm8350_block_read);
277
278 int wm8350_block_write(struct wm8350 *wm8350, int start_reg, int regs,
279 u16 *src)
280 {
281 int ret = 0;
282
283 mutex_lock(&io_mutex);
284 ret = wm8350_write(wm8350, start_reg, regs, src);
285 if (ret)
286 dev_err(wm8350->dev, "block write starting at R%d failed\n",
287 start_reg);
288 mutex_unlock(&io_mutex);
289 return ret;
290 }
291 EXPORT_SYMBOL_GPL(wm8350_block_write);
292
293 /**
294 * wm8350_reg_lock()
295 *
296 * The WM8350 has a hardware lock which can be used to prevent writes to
297 * some registers (generally those which can cause particularly serious
298 * problems if misused). This function enables that lock.
299 */
300 int wm8350_reg_lock(struct wm8350 *wm8350)
301 {
302 u16 key = WM8350_LOCK_KEY;
303 int ret;
304
305 ldbg(__func__);
306 mutex_lock(&io_mutex);
307 ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key);
308 if (ret)
309 dev_err(wm8350->dev, "lock failed\n");
310 mutex_unlock(&io_mutex);
311 return ret;
312 }
313 EXPORT_SYMBOL_GPL(wm8350_reg_lock);
314
315 /**
316 * wm8350_reg_unlock()
317 *
318 * The WM8350 has a hardware lock which can be used to prevent writes to
319 * some registers (generally those which can cause particularly serious
320 * problems if misused). This function disables that lock so updates
321 * can be performed. For maximum safety this should be done only when
322 * required.
323 */
324 int wm8350_reg_unlock(struct wm8350 *wm8350)
325 {
326 u16 key = WM8350_UNLOCK_KEY;
327 int ret;
328
329 ldbg(__func__);
330 mutex_lock(&io_mutex);
331 ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key);
332 if (ret)
333 dev_err(wm8350->dev, "unlock failed\n");
334 mutex_unlock(&io_mutex);
335 return ret;
336 }
337 EXPORT_SYMBOL_GPL(wm8350_reg_unlock);
338
339 static void wm8350_irq_call_handler(struct wm8350 *wm8350, int irq)
340 {
341 mutex_lock(&wm8350->irq_mutex);
342
343 if (wm8350->irq[irq].handler)
344 wm8350->irq[irq].handler(wm8350, irq, wm8350->irq[irq].data);
345 else {
346 dev_err(wm8350->dev, "irq %d nobody cared. now masked.\n",
347 irq);
348 wm8350_mask_irq(wm8350, irq);
349 }
350
351 mutex_unlock(&wm8350->irq_mutex);
352 }
353
354 /*
355 * This is a threaded IRQ handler so can access I2C/SPI. Since all
356 * interrupts are clear on read the IRQ line will be reasserted and
357 * the physical IRQ will be handled again if another interrupt is
358 * asserted while we run - in the normal course of events this is a
359 * rare occurrence so we save I2C/SPI reads.
360 */
361 static irqreturn_t wm8350_irq(int irq, void *data)
362 {
363 struct wm8350 *wm8350 = data;
364 u16 level_one, status1, status2, comp;
365
366 /* TODO: Use block reads to improve performance? */
367 level_one = wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS)
368 & ~wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK);
369 status1 = wm8350_reg_read(wm8350, WM8350_INT_STATUS_1)
370 & ~wm8350_reg_read(wm8350, WM8350_INT_STATUS_1_MASK);
371 status2 = wm8350_reg_read(wm8350, WM8350_INT_STATUS_2)
372 & ~wm8350_reg_read(wm8350, WM8350_INT_STATUS_2_MASK);
373 comp = wm8350_reg_read(wm8350, WM8350_COMPARATOR_INT_STATUS)
374 & ~wm8350_reg_read(wm8350, WM8350_COMPARATOR_INT_STATUS_MASK);
375
376 /* over current */
377 if (level_one & WM8350_OC_INT) {
378 u16 oc;
379
380 oc = wm8350_reg_read(wm8350, WM8350_OVER_CURRENT_INT_STATUS);
381 oc &= ~wm8350_reg_read(wm8350,
382 WM8350_OVER_CURRENT_INT_STATUS_MASK);
383
384 if (oc & WM8350_OC_LS_EINT) /* limit switch */
385 wm8350_irq_call_handler(wm8350, WM8350_IRQ_OC_LS);
386 }
387
388 /* under voltage */
389 if (level_one & WM8350_UV_INT) {
390 u16 uv;
391
392 uv = wm8350_reg_read(wm8350, WM8350_UNDER_VOLTAGE_INT_STATUS);
393 uv &= ~wm8350_reg_read(wm8350,
394 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK);
395
396 if (uv & WM8350_UV_DC1_EINT)
397 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC1);
398 if (uv & WM8350_UV_DC2_EINT)
399 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC2);
400 if (uv & WM8350_UV_DC3_EINT)
401 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC3);
402 if (uv & WM8350_UV_DC4_EINT)
403 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC4);
404 if (uv & WM8350_UV_DC5_EINT)
405 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC5);
406 if (uv & WM8350_UV_DC6_EINT)
407 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC6);
408 if (uv & WM8350_UV_LDO1_EINT)
409 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO1);
410 if (uv & WM8350_UV_LDO2_EINT)
411 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO2);
412 if (uv & WM8350_UV_LDO3_EINT)
413 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO3);
414 if (uv & WM8350_UV_LDO4_EINT)
415 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO4);
416 }
417
418 /* charger, RTC */
419 if (status1) {
420 if (status1 & WM8350_CHG_BAT_HOT_EINT)
421 wm8350_irq_call_handler(wm8350,
422 WM8350_IRQ_CHG_BAT_HOT);
423 if (status1 & WM8350_CHG_BAT_COLD_EINT)
424 wm8350_irq_call_handler(wm8350,
425 WM8350_IRQ_CHG_BAT_COLD);
426 if (status1 & WM8350_CHG_BAT_FAIL_EINT)
427 wm8350_irq_call_handler(wm8350,
428 WM8350_IRQ_CHG_BAT_FAIL);
429 if (status1 & WM8350_CHG_TO_EINT)
430 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_TO);
431 if (status1 & WM8350_CHG_END_EINT)
432 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_END);
433 if (status1 & WM8350_CHG_START_EINT)
434 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_START);
435 if (status1 & WM8350_CHG_FAST_RDY_EINT)
436 wm8350_irq_call_handler(wm8350,
437 WM8350_IRQ_CHG_FAST_RDY);
438 if (status1 & WM8350_CHG_VBATT_LT_3P9_EINT)
439 wm8350_irq_call_handler(wm8350,
440 WM8350_IRQ_CHG_VBATT_LT_3P9);
441 if (status1 & WM8350_CHG_VBATT_LT_3P1_EINT)
442 wm8350_irq_call_handler(wm8350,
443 WM8350_IRQ_CHG_VBATT_LT_3P1);
444 if (status1 & WM8350_CHG_VBATT_LT_2P85_EINT)
445 wm8350_irq_call_handler(wm8350,
446 WM8350_IRQ_CHG_VBATT_LT_2P85);
447 if (status1 & WM8350_RTC_ALM_EINT)
448 wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_ALM);
449 if (status1 & WM8350_RTC_SEC_EINT)
450 wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_SEC);
451 if (status1 & WM8350_RTC_PER_EINT)
452 wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_PER);
453 }
454
455 /* current sink, system, aux adc */
456 if (status2) {
457 if (status2 & WM8350_CS1_EINT)
458 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CS1);
459 if (status2 & WM8350_CS2_EINT)
460 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CS2);
461
462 if (status2 & WM8350_SYS_HYST_COMP_FAIL_EINT)
463 wm8350_irq_call_handler(wm8350,
464 WM8350_IRQ_SYS_HYST_COMP_FAIL);
465 if (status2 & WM8350_SYS_CHIP_GT115_EINT)
466 wm8350_irq_call_handler(wm8350,
467 WM8350_IRQ_SYS_CHIP_GT115);
468 if (status2 & WM8350_SYS_CHIP_GT140_EINT)
469 wm8350_irq_call_handler(wm8350,
470 WM8350_IRQ_SYS_CHIP_GT140);
471 if (status2 & WM8350_SYS_WDOG_TO_EINT)
472 wm8350_irq_call_handler(wm8350,
473 WM8350_IRQ_SYS_WDOG_TO);
474
475 if (status2 & WM8350_AUXADC_DATARDY_EINT)
476 wm8350_irq_call_handler(wm8350,
477 WM8350_IRQ_AUXADC_DATARDY);
478 if (status2 & WM8350_AUXADC_DCOMP4_EINT)
479 wm8350_irq_call_handler(wm8350,
480 WM8350_IRQ_AUXADC_DCOMP4);
481 if (status2 & WM8350_AUXADC_DCOMP3_EINT)
482 wm8350_irq_call_handler(wm8350,
483 WM8350_IRQ_AUXADC_DCOMP3);
484 if (status2 & WM8350_AUXADC_DCOMP2_EINT)
485 wm8350_irq_call_handler(wm8350,
486 WM8350_IRQ_AUXADC_DCOMP2);
487 if (status2 & WM8350_AUXADC_DCOMP1_EINT)
488 wm8350_irq_call_handler(wm8350,
489 WM8350_IRQ_AUXADC_DCOMP1);
490
491 if (status2 & WM8350_USB_LIMIT_EINT)
492 wm8350_irq_call_handler(wm8350, WM8350_IRQ_USB_LIMIT);
493 }
494
495 /* wake, codec, ext */
496 if (comp) {
497 if (comp & WM8350_WKUP_OFF_STATE_EINT)
498 wm8350_irq_call_handler(wm8350,
499 WM8350_IRQ_WKUP_OFF_STATE);
500 if (comp & WM8350_WKUP_HIB_STATE_EINT)
501 wm8350_irq_call_handler(wm8350,
502 WM8350_IRQ_WKUP_HIB_STATE);
503 if (comp & WM8350_WKUP_CONV_FAULT_EINT)
504 wm8350_irq_call_handler(wm8350,
505 WM8350_IRQ_WKUP_CONV_FAULT);
506 if (comp & WM8350_WKUP_WDOG_RST_EINT)
507 wm8350_irq_call_handler(wm8350,
508 WM8350_IRQ_WKUP_WDOG_RST);
509 if (comp & WM8350_WKUP_GP_PWR_ON_EINT)
510 wm8350_irq_call_handler(wm8350,
511 WM8350_IRQ_WKUP_GP_PWR_ON);
512 if (comp & WM8350_WKUP_ONKEY_EINT)
513 wm8350_irq_call_handler(wm8350, WM8350_IRQ_WKUP_ONKEY);
514 if (comp & WM8350_WKUP_GP_WAKEUP_EINT)
515 wm8350_irq_call_handler(wm8350,
516 WM8350_IRQ_WKUP_GP_WAKEUP);
517
518 if (comp & WM8350_CODEC_JCK_DET_L_EINT)
519 wm8350_irq_call_handler(wm8350,
520 WM8350_IRQ_CODEC_JCK_DET_L);
521 if (comp & WM8350_CODEC_JCK_DET_R_EINT)
522 wm8350_irq_call_handler(wm8350,
523 WM8350_IRQ_CODEC_JCK_DET_R);
524 if (comp & WM8350_CODEC_MICSCD_EINT)
525 wm8350_irq_call_handler(wm8350,
526 WM8350_IRQ_CODEC_MICSCD);
527 if (comp & WM8350_CODEC_MICD_EINT)
528 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CODEC_MICD);
529
530 if (comp & WM8350_EXT_USB_FB_EINT)
531 wm8350_irq_call_handler(wm8350, WM8350_IRQ_EXT_USB_FB);
532 if (comp & WM8350_EXT_WALL_FB_EINT)
533 wm8350_irq_call_handler(wm8350,
534 WM8350_IRQ_EXT_WALL_FB);
535 if (comp & WM8350_EXT_BAT_FB_EINT)
536 wm8350_irq_call_handler(wm8350, WM8350_IRQ_EXT_BAT_FB);
537 }
538
539 if (level_one & WM8350_GP_INT) {
540 int i;
541 u16 gpio;
542
543 gpio = wm8350_reg_read(wm8350, WM8350_GPIO_INT_STATUS);
544 gpio &= ~wm8350_reg_read(wm8350,
545 WM8350_GPIO_INT_STATUS_MASK);
546
547 for (i = 0; i < 12; i++) {
548 if (gpio & (1 << i))
549 wm8350_irq_call_handler(wm8350,
550 WM8350_IRQ_GPIO(i));
551 }
552 }
553
554 return IRQ_HANDLED;
555 }
556
557 int wm8350_register_irq(struct wm8350 *wm8350, int irq,
558 void (*handler) (struct wm8350 *, int, void *),
559 void *data)
560 {
561 if (irq < 0 || irq > WM8350_NUM_IRQ || !handler)
562 return -EINVAL;
563
564 if (wm8350->irq[irq].handler)
565 return -EBUSY;
566
567 mutex_lock(&wm8350->irq_mutex);
568 wm8350->irq[irq].handler = handler;
569 wm8350->irq[irq].data = data;
570 mutex_unlock(&wm8350->irq_mutex);
571
572 return 0;
573 }
574 EXPORT_SYMBOL_GPL(wm8350_register_irq);
575
576 int wm8350_free_irq(struct wm8350 *wm8350, int irq)
577 {
578 if (irq < 0 || irq > WM8350_NUM_IRQ)
579 return -EINVAL;
580
581 mutex_lock(&wm8350->irq_mutex);
582 wm8350->irq[irq].handler = NULL;
583 mutex_unlock(&wm8350->irq_mutex);
584 return 0;
585 }
586 EXPORT_SYMBOL_GPL(wm8350_free_irq);
587
588 int wm8350_mask_irq(struct wm8350 *wm8350, int irq)
589 {
590 switch (irq) {
591 case WM8350_IRQ_CHG_BAT_HOT:
592 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
593 WM8350_IM_CHG_BAT_HOT_EINT);
594 case WM8350_IRQ_CHG_BAT_COLD:
595 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
596 WM8350_IM_CHG_BAT_COLD_EINT);
597 case WM8350_IRQ_CHG_BAT_FAIL:
598 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
599 WM8350_IM_CHG_BAT_FAIL_EINT);
600 case WM8350_IRQ_CHG_TO:
601 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
602 WM8350_IM_CHG_TO_EINT);
603 case WM8350_IRQ_CHG_END:
604 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
605 WM8350_IM_CHG_END_EINT);
606 case WM8350_IRQ_CHG_START:
607 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
608 WM8350_IM_CHG_START_EINT);
609 case WM8350_IRQ_CHG_FAST_RDY:
610 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
611 WM8350_IM_CHG_FAST_RDY_EINT);
612 case WM8350_IRQ_RTC_PER:
613 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
614 WM8350_IM_RTC_PER_EINT);
615 case WM8350_IRQ_RTC_SEC:
616 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
617 WM8350_IM_RTC_SEC_EINT);
618 case WM8350_IRQ_RTC_ALM:
619 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
620 WM8350_IM_RTC_ALM_EINT);
621 case WM8350_IRQ_CHG_VBATT_LT_3P9:
622 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
623 WM8350_IM_CHG_VBATT_LT_3P9_EINT);
624 case WM8350_IRQ_CHG_VBATT_LT_3P1:
625 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
626 WM8350_IM_CHG_VBATT_LT_3P1_EINT);
627 case WM8350_IRQ_CHG_VBATT_LT_2P85:
628 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
629 WM8350_IM_CHG_VBATT_LT_2P85_EINT);
630 case WM8350_IRQ_CS1:
631 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
632 WM8350_IM_CS1_EINT);
633 case WM8350_IRQ_CS2:
634 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
635 WM8350_IM_CS2_EINT);
636 case WM8350_IRQ_USB_LIMIT:
637 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
638 WM8350_IM_USB_LIMIT_EINT);
639 case WM8350_IRQ_AUXADC_DATARDY:
640 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
641 WM8350_IM_AUXADC_DATARDY_EINT);
642 case WM8350_IRQ_AUXADC_DCOMP4:
643 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
644 WM8350_IM_AUXADC_DCOMP4_EINT);
645 case WM8350_IRQ_AUXADC_DCOMP3:
646 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
647 WM8350_IM_AUXADC_DCOMP3_EINT);
648 case WM8350_IRQ_AUXADC_DCOMP2:
649 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
650 WM8350_IM_AUXADC_DCOMP2_EINT);
651 case WM8350_IRQ_AUXADC_DCOMP1:
652 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
653 WM8350_IM_AUXADC_DCOMP1_EINT);
654 case WM8350_IRQ_SYS_HYST_COMP_FAIL:
655 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
656 WM8350_IM_SYS_HYST_COMP_FAIL_EINT);
657 case WM8350_IRQ_SYS_CHIP_GT115:
658 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
659 WM8350_IM_SYS_CHIP_GT115_EINT);
660 case WM8350_IRQ_SYS_CHIP_GT140:
661 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
662 WM8350_IM_SYS_CHIP_GT140_EINT);
663 case WM8350_IRQ_SYS_WDOG_TO:
664 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
665 WM8350_IM_SYS_WDOG_TO_EINT);
666 case WM8350_IRQ_UV_LDO4:
667 return wm8350_set_bits(wm8350,
668 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
669 WM8350_IM_UV_LDO4_EINT);
670 case WM8350_IRQ_UV_LDO3:
671 return wm8350_set_bits(wm8350,
672 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
673 WM8350_IM_UV_LDO3_EINT);
674 case WM8350_IRQ_UV_LDO2:
675 return wm8350_set_bits(wm8350,
676 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
677 WM8350_IM_UV_LDO2_EINT);
678 case WM8350_IRQ_UV_LDO1:
679 return wm8350_set_bits(wm8350,
680 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
681 WM8350_IM_UV_LDO1_EINT);
682 case WM8350_IRQ_UV_DC6:
683 return wm8350_set_bits(wm8350,
684 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
685 WM8350_IM_UV_DC6_EINT);
686 case WM8350_IRQ_UV_DC5:
687 return wm8350_set_bits(wm8350,
688 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
689 WM8350_IM_UV_DC5_EINT);
690 case WM8350_IRQ_UV_DC4:
691 return wm8350_set_bits(wm8350,
692 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
693 WM8350_IM_UV_DC4_EINT);
694 case WM8350_IRQ_UV_DC3:
695 return wm8350_set_bits(wm8350,
696 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
697 WM8350_IM_UV_DC3_EINT);
698 case WM8350_IRQ_UV_DC2:
699 return wm8350_set_bits(wm8350,
700 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
701 WM8350_IM_UV_DC2_EINT);
702 case WM8350_IRQ_UV_DC1:
703 return wm8350_set_bits(wm8350,
704 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
705 WM8350_IM_UV_DC1_EINT);
706 case WM8350_IRQ_OC_LS:
707 return wm8350_set_bits(wm8350,
708 WM8350_OVER_CURRENT_INT_STATUS_MASK,
709 WM8350_IM_OC_LS_EINT);
710 case WM8350_IRQ_EXT_USB_FB:
711 return wm8350_set_bits(wm8350,
712 WM8350_COMPARATOR_INT_STATUS_MASK,
713 WM8350_IM_EXT_USB_FB_EINT);
714 case WM8350_IRQ_EXT_WALL_FB:
715 return wm8350_set_bits(wm8350,
716 WM8350_COMPARATOR_INT_STATUS_MASK,
717 WM8350_IM_EXT_WALL_FB_EINT);
718 case WM8350_IRQ_EXT_BAT_FB:
719 return wm8350_set_bits(wm8350,
720 WM8350_COMPARATOR_INT_STATUS_MASK,
721 WM8350_IM_EXT_BAT_FB_EINT);
722 case WM8350_IRQ_CODEC_JCK_DET_L:
723 return wm8350_set_bits(wm8350,
724 WM8350_COMPARATOR_INT_STATUS_MASK,
725 WM8350_IM_CODEC_JCK_DET_L_EINT);
726 case WM8350_IRQ_CODEC_JCK_DET_R:
727 return wm8350_set_bits(wm8350,
728 WM8350_COMPARATOR_INT_STATUS_MASK,
729 WM8350_IM_CODEC_JCK_DET_R_EINT);
730 case WM8350_IRQ_CODEC_MICSCD:
731 return wm8350_set_bits(wm8350,
732 WM8350_COMPARATOR_INT_STATUS_MASK,
733 WM8350_IM_CODEC_MICSCD_EINT);
734 case WM8350_IRQ_CODEC_MICD:
735 return wm8350_set_bits(wm8350,
736 WM8350_COMPARATOR_INT_STATUS_MASK,
737 WM8350_IM_CODEC_MICD_EINT);
738 case WM8350_IRQ_WKUP_OFF_STATE:
739 return wm8350_set_bits(wm8350,
740 WM8350_COMPARATOR_INT_STATUS_MASK,
741 WM8350_IM_WKUP_OFF_STATE_EINT);
742 case WM8350_IRQ_WKUP_HIB_STATE:
743 return wm8350_set_bits(wm8350,
744 WM8350_COMPARATOR_INT_STATUS_MASK,
745 WM8350_IM_WKUP_HIB_STATE_EINT);
746 case WM8350_IRQ_WKUP_CONV_FAULT:
747 return wm8350_set_bits(wm8350,
748 WM8350_COMPARATOR_INT_STATUS_MASK,
749 WM8350_IM_WKUP_CONV_FAULT_EINT);
750 case WM8350_IRQ_WKUP_WDOG_RST:
751 return wm8350_set_bits(wm8350,
752 WM8350_COMPARATOR_INT_STATUS_MASK,
753 WM8350_IM_WKUP_OFF_STATE_EINT);
754 case WM8350_IRQ_WKUP_GP_PWR_ON:
755 return wm8350_set_bits(wm8350,
756 WM8350_COMPARATOR_INT_STATUS_MASK,
757 WM8350_IM_WKUP_GP_PWR_ON_EINT);
758 case WM8350_IRQ_WKUP_ONKEY:
759 return wm8350_set_bits(wm8350,
760 WM8350_COMPARATOR_INT_STATUS_MASK,
761 WM8350_IM_WKUP_ONKEY_EINT);
762 case WM8350_IRQ_WKUP_GP_WAKEUP:
763 return wm8350_set_bits(wm8350,
764 WM8350_COMPARATOR_INT_STATUS_MASK,
765 WM8350_IM_WKUP_GP_WAKEUP_EINT);
766 case WM8350_IRQ_GPIO(0):
767 return wm8350_set_bits(wm8350,
768 WM8350_GPIO_INT_STATUS_MASK,
769 WM8350_IM_GP0_EINT);
770 case WM8350_IRQ_GPIO(1):
771 return wm8350_set_bits(wm8350,
772 WM8350_GPIO_INT_STATUS_MASK,
773 WM8350_IM_GP1_EINT);
774 case WM8350_IRQ_GPIO(2):
775 return wm8350_set_bits(wm8350,
776 WM8350_GPIO_INT_STATUS_MASK,
777 WM8350_IM_GP2_EINT);
778 case WM8350_IRQ_GPIO(3):
779 return wm8350_set_bits(wm8350,
780 WM8350_GPIO_INT_STATUS_MASK,
781 WM8350_IM_GP3_EINT);
782 case WM8350_IRQ_GPIO(4):
783 return wm8350_set_bits(wm8350,
784 WM8350_GPIO_INT_STATUS_MASK,
785 WM8350_IM_GP4_EINT);
786 case WM8350_IRQ_GPIO(5):
787 return wm8350_set_bits(wm8350,
788 WM8350_GPIO_INT_STATUS_MASK,
789 WM8350_IM_GP5_EINT);
790 case WM8350_IRQ_GPIO(6):
791 return wm8350_set_bits(wm8350,
792 WM8350_GPIO_INT_STATUS_MASK,
793 WM8350_IM_GP6_EINT);
794 case WM8350_IRQ_GPIO(7):
795 return wm8350_set_bits(wm8350,
796 WM8350_GPIO_INT_STATUS_MASK,
797 WM8350_IM_GP7_EINT);
798 case WM8350_IRQ_GPIO(8):
799 return wm8350_set_bits(wm8350,
800 WM8350_GPIO_INT_STATUS_MASK,
801 WM8350_IM_GP8_EINT);
802 case WM8350_IRQ_GPIO(9):
803 return wm8350_set_bits(wm8350,
804 WM8350_GPIO_INT_STATUS_MASK,
805 WM8350_IM_GP9_EINT);
806 case WM8350_IRQ_GPIO(10):
807 return wm8350_set_bits(wm8350,
808 WM8350_GPIO_INT_STATUS_MASK,
809 WM8350_IM_GP10_EINT);
810 case WM8350_IRQ_GPIO(11):
811 return wm8350_set_bits(wm8350,
812 WM8350_GPIO_INT_STATUS_MASK,
813 WM8350_IM_GP11_EINT);
814 case WM8350_IRQ_GPIO(12):
815 return wm8350_set_bits(wm8350,
816 WM8350_GPIO_INT_STATUS_MASK,
817 WM8350_IM_GP12_EINT);
818 default:
819 dev_warn(wm8350->dev, "Attempting to mask unknown IRQ %d\n",
820 irq);
821 return -EINVAL;
822 }
823 return 0;
824 }
825 EXPORT_SYMBOL_GPL(wm8350_mask_irq);
826
827 int wm8350_unmask_irq(struct wm8350 *wm8350, int irq)
828 {
829 switch (irq) {
830 case WM8350_IRQ_CHG_BAT_HOT:
831 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
832 WM8350_IM_CHG_BAT_HOT_EINT);
833 case WM8350_IRQ_CHG_BAT_COLD:
834 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
835 WM8350_IM_CHG_BAT_COLD_EINT);
836 case WM8350_IRQ_CHG_BAT_FAIL:
837 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
838 WM8350_IM_CHG_BAT_FAIL_EINT);
839 case WM8350_IRQ_CHG_TO:
840 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
841 WM8350_IM_CHG_TO_EINT);
842 case WM8350_IRQ_CHG_END:
843 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
844 WM8350_IM_CHG_END_EINT);
845 case WM8350_IRQ_CHG_START:
846 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
847 WM8350_IM_CHG_START_EINT);
848 case WM8350_IRQ_CHG_FAST_RDY:
849 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
850 WM8350_IM_CHG_FAST_RDY_EINT);
851 case WM8350_IRQ_RTC_PER:
852 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
853 WM8350_IM_RTC_PER_EINT);
854 case WM8350_IRQ_RTC_SEC:
855 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
856 WM8350_IM_RTC_SEC_EINT);
857 case WM8350_IRQ_RTC_ALM:
858 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
859 WM8350_IM_RTC_ALM_EINT);
860 case WM8350_IRQ_CHG_VBATT_LT_3P9:
861 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
862 WM8350_IM_CHG_VBATT_LT_3P9_EINT);
863 case WM8350_IRQ_CHG_VBATT_LT_3P1:
864 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
865 WM8350_IM_CHG_VBATT_LT_3P1_EINT);
866 case WM8350_IRQ_CHG_VBATT_LT_2P85:
867 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
868 WM8350_IM_CHG_VBATT_LT_2P85_EINT);
869 case WM8350_IRQ_CS1:
870 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
871 WM8350_IM_CS1_EINT);
872 case WM8350_IRQ_CS2:
873 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
874 WM8350_IM_CS2_EINT);
875 case WM8350_IRQ_USB_LIMIT:
876 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
877 WM8350_IM_USB_LIMIT_EINT);
878 case WM8350_IRQ_AUXADC_DATARDY:
879 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
880 WM8350_IM_AUXADC_DATARDY_EINT);
881 case WM8350_IRQ_AUXADC_DCOMP4:
882 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
883 WM8350_IM_AUXADC_DCOMP4_EINT);
884 case WM8350_IRQ_AUXADC_DCOMP3:
885 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
886 WM8350_IM_AUXADC_DCOMP3_EINT);
887 case WM8350_IRQ_AUXADC_DCOMP2:
888 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
889 WM8350_IM_AUXADC_DCOMP2_EINT);
890 case WM8350_IRQ_AUXADC_DCOMP1:
891 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
892 WM8350_IM_AUXADC_DCOMP1_EINT);
893 case WM8350_IRQ_SYS_HYST_COMP_FAIL:
894 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
895 WM8350_IM_SYS_HYST_COMP_FAIL_EINT);
896 case WM8350_IRQ_SYS_CHIP_GT115:
897 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
898 WM8350_IM_SYS_CHIP_GT115_EINT);
899 case WM8350_IRQ_SYS_CHIP_GT140:
900 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
901 WM8350_IM_SYS_CHIP_GT140_EINT);
902 case WM8350_IRQ_SYS_WDOG_TO:
903 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
904 WM8350_IM_SYS_WDOG_TO_EINT);
905 case WM8350_IRQ_UV_LDO4:
906 return wm8350_clear_bits(wm8350,
907 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
908 WM8350_IM_UV_LDO4_EINT);
909 case WM8350_IRQ_UV_LDO3:
910 return wm8350_clear_bits(wm8350,
911 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
912 WM8350_IM_UV_LDO3_EINT);
913 case WM8350_IRQ_UV_LDO2:
914 return wm8350_clear_bits(wm8350,
915 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
916 WM8350_IM_UV_LDO2_EINT);
917 case WM8350_IRQ_UV_LDO1:
918 return wm8350_clear_bits(wm8350,
919 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
920 WM8350_IM_UV_LDO1_EINT);
921 case WM8350_IRQ_UV_DC6:
922 return wm8350_clear_bits(wm8350,
923 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
924 WM8350_IM_UV_DC6_EINT);
925 case WM8350_IRQ_UV_DC5:
926 return wm8350_clear_bits(wm8350,
927 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
928 WM8350_IM_UV_DC5_EINT);
929 case WM8350_IRQ_UV_DC4:
930 return wm8350_clear_bits(wm8350,
931 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
932 WM8350_IM_UV_DC4_EINT);
933 case WM8350_IRQ_UV_DC3:
934 return wm8350_clear_bits(wm8350,
935 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
936 WM8350_IM_UV_DC3_EINT);
937 case WM8350_IRQ_UV_DC2:
938 return wm8350_clear_bits(wm8350,
939 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
940 WM8350_IM_UV_DC2_EINT);
941 case WM8350_IRQ_UV_DC1:
942 return wm8350_clear_bits(wm8350,
943 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
944 WM8350_IM_UV_DC1_EINT);
945 case WM8350_IRQ_OC_LS:
946 return wm8350_clear_bits(wm8350,
947 WM8350_OVER_CURRENT_INT_STATUS_MASK,
948 WM8350_IM_OC_LS_EINT);
949 case WM8350_IRQ_EXT_USB_FB:
950 return wm8350_clear_bits(wm8350,
951 WM8350_COMPARATOR_INT_STATUS_MASK,
952 WM8350_IM_EXT_USB_FB_EINT);
953 case WM8350_IRQ_EXT_WALL_FB:
954 return wm8350_clear_bits(wm8350,
955 WM8350_COMPARATOR_INT_STATUS_MASK,
956 WM8350_IM_EXT_WALL_FB_EINT);
957 case WM8350_IRQ_EXT_BAT_FB:
958 return wm8350_clear_bits(wm8350,
959 WM8350_COMPARATOR_INT_STATUS_MASK,
960 WM8350_IM_EXT_BAT_FB_EINT);
961 case WM8350_IRQ_CODEC_JCK_DET_L:
962 return wm8350_clear_bits(wm8350,
963 WM8350_COMPARATOR_INT_STATUS_MASK,
964 WM8350_IM_CODEC_JCK_DET_L_EINT);
965 case WM8350_IRQ_CODEC_JCK_DET_R:
966 return wm8350_clear_bits(wm8350,
967 WM8350_COMPARATOR_INT_STATUS_MASK,
968 WM8350_IM_CODEC_JCK_DET_R_EINT);
969 case WM8350_IRQ_CODEC_MICSCD:
970 return wm8350_clear_bits(wm8350,
971 WM8350_COMPARATOR_INT_STATUS_MASK,
972 WM8350_IM_CODEC_MICSCD_EINT);
973 case WM8350_IRQ_CODEC_MICD:
974 return wm8350_clear_bits(wm8350,
975 WM8350_COMPARATOR_INT_STATUS_MASK,
976 WM8350_IM_CODEC_MICD_EINT);
977 case WM8350_IRQ_WKUP_OFF_STATE:
978 return wm8350_clear_bits(wm8350,
979 WM8350_COMPARATOR_INT_STATUS_MASK,
980 WM8350_IM_WKUP_OFF_STATE_EINT);
981 case WM8350_IRQ_WKUP_HIB_STATE:
982 return wm8350_clear_bits(wm8350,
983 WM8350_COMPARATOR_INT_STATUS_MASK,
984 WM8350_IM_WKUP_HIB_STATE_EINT);
985 case WM8350_IRQ_WKUP_CONV_FAULT:
986 return wm8350_clear_bits(wm8350,
987 WM8350_COMPARATOR_INT_STATUS_MASK,
988 WM8350_IM_WKUP_CONV_FAULT_EINT);
989 case WM8350_IRQ_WKUP_WDOG_RST:
990 return wm8350_clear_bits(wm8350,
991 WM8350_COMPARATOR_INT_STATUS_MASK,
992 WM8350_IM_WKUP_OFF_STATE_EINT);
993 case WM8350_IRQ_WKUP_GP_PWR_ON:
994 return wm8350_clear_bits(wm8350,
995 WM8350_COMPARATOR_INT_STATUS_MASK,
996 WM8350_IM_WKUP_GP_PWR_ON_EINT);
997 case WM8350_IRQ_WKUP_ONKEY:
998 return wm8350_clear_bits(wm8350,
999 WM8350_COMPARATOR_INT_STATUS_MASK,
1000 WM8350_IM_WKUP_ONKEY_EINT);
1001 case WM8350_IRQ_WKUP_GP_WAKEUP:
1002 return wm8350_clear_bits(wm8350,
1003 WM8350_COMPARATOR_INT_STATUS_MASK,
1004 WM8350_IM_WKUP_GP_WAKEUP_EINT);
1005 case WM8350_IRQ_GPIO(0):
1006 return wm8350_clear_bits(wm8350,
1007 WM8350_GPIO_INT_STATUS_MASK,
1008 WM8350_IM_GP0_EINT);
1009 case WM8350_IRQ_GPIO(1):
1010 return wm8350_clear_bits(wm8350,
1011 WM8350_GPIO_INT_STATUS_MASK,
1012 WM8350_IM_GP1_EINT);
1013 case WM8350_IRQ_GPIO(2):
1014 return wm8350_clear_bits(wm8350,
1015 WM8350_GPIO_INT_STATUS_MASK,
1016 WM8350_IM_GP2_EINT);
1017 case WM8350_IRQ_GPIO(3):
1018 return wm8350_clear_bits(wm8350,
1019 WM8350_GPIO_INT_STATUS_MASK,
1020 WM8350_IM_GP3_EINT);
1021 case WM8350_IRQ_GPIO(4):
1022 return wm8350_clear_bits(wm8350,
1023 WM8350_GPIO_INT_STATUS_MASK,
1024 WM8350_IM_GP4_EINT);
1025 case WM8350_IRQ_GPIO(5):
1026 return wm8350_clear_bits(wm8350,
1027 WM8350_GPIO_INT_STATUS_MASK,
1028 WM8350_IM_GP5_EINT);
1029 case WM8350_IRQ_GPIO(6):
1030 return wm8350_clear_bits(wm8350,
1031 WM8350_GPIO_INT_STATUS_MASK,
1032 WM8350_IM_GP6_EINT);
1033 case WM8350_IRQ_GPIO(7):
1034 return wm8350_clear_bits(wm8350,
1035 WM8350_GPIO_INT_STATUS_MASK,
1036 WM8350_IM_GP7_EINT);
1037 case WM8350_IRQ_GPIO(8):
1038 return wm8350_clear_bits(wm8350,
1039 WM8350_GPIO_INT_STATUS_MASK,
1040 WM8350_IM_GP8_EINT);
1041 case WM8350_IRQ_GPIO(9):
1042 return wm8350_clear_bits(wm8350,
1043 WM8350_GPIO_INT_STATUS_MASK,
1044 WM8350_IM_GP9_EINT);
1045 case WM8350_IRQ_GPIO(10):
1046 return wm8350_clear_bits(wm8350,
1047 WM8350_GPIO_INT_STATUS_MASK,
1048 WM8350_IM_GP10_EINT);
1049 case WM8350_IRQ_GPIO(11):
1050 return wm8350_clear_bits(wm8350,
1051 WM8350_GPIO_INT_STATUS_MASK,
1052 WM8350_IM_GP11_EINT);
1053 case WM8350_IRQ_GPIO(12):
1054 return wm8350_clear_bits(wm8350,
1055 WM8350_GPIO_INT_STATUS_MASK,
1056 WM8350_IM_GP12_EINT);
1057 default:
1058 dev_warn(wm8350->dev, "Attempting to unmask unknown IRQ %d\n",
1059 irq);
1060 return -EINVAL;
1061 }
1062 return 0;
1063 }
1064 EXPORT_SYMBOL_GPL(wm8350_unmask_irq);
1065
1066 int wm8350_read_auxadc(struct wm8350 *wm8350, int channel, int scale, int vref)
1067 {
1068 u16 reg, result = 0;
1069 int tries = 5;
1070
1071 if (channel < WM8350_AUXADC_AUX1 || channel > WM8350_AUXADC_TEMP)
1072 return -EINVAL;
1073 if (channel >= WM8350_AUXADC_USB && channel <= WM8350_AUXADC_TEMP
1074 && (scale != 0 || vref != 0))
1075 return -EINVAL;
1076
1077 mutex_lock(&wm8350->auxadc_mutex);
1078
1079 /* Turn on the ADC */
1080 reg = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_5);
1081 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_5, reg | WM8350_AUXADC_ENA);
1082
1083 if (scale || vref) {
1084 reg = scale << 13;
1085 reg |= vref << 12;
1086 wm8350_reg_write(wm8350, WM8350_AUX1_READBACK + channel, reg);
1087 }
1088
1089 reg = wm8350_reg_read(wm8350, WM8350_DIGITISER_CONTROL_1);
1090 reg |= 1 << channel | WM8350_AUXADC_POLL;
1091 wm8350_reg_write(wm8350, WM8350_DIGITISER_CONTROL_1, reg);
1092
1093 do {
1094 schedule_timeout_interruptible(1);
1095 reg = wm8350_reg_read(wm8350, WM8350_DIGITISER_CONTROL_1);
1096 } while ((reg & WM8350_AUXADC_POLL) && --tries);
1097
1098 if (!tries)
1099 dev_err(wm8350->dev, "adc chn %d read timeout\n", channel);
1100 else
1101 result = wm8350_reg_read(wm8350,
1102 WM8350_AUX1_READBACK + channel);
1103
1104 /* Turn off the ADC */
1105 reg = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_5);
1106 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_5,
1107 reg & ~WM8350_AUXADC_ENA);
1108
1109 mutex_unlock(&wm8350->auxadc_mutex);
1110
1111 return result & WM8350_AUXADC_DATA1_MASK;
1112 }
1113 EXPORT_SYMBOL_GPL(wm8350_read_auxadc);
1114
1115 /*
1116 * Cache is always host endian.
1117 */
1118 static int wm8350_create_cache(struct wm8350 *wm8350, int type, int mode)
1119 {
1120 int i, ret = 0;
1121 u16 value;
1122 const u16 *reg_map;
1123
1124 switch (type) {
1125 case 0:
1126 switch (mode) {
1127 #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_0
1128 case 0:
1129 reg_map = wm8350_mode0_defaults;
1130 break;
1131 #endif
1132 #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_1
1133 case 1:
1134 reg_map = wm8350_mode1_defaults;
1135 break;
1136 #endif
1137 #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_2
1138 case 2:
1139 reg_map = wm8350_mode2_defaults;
1140 break;
1141 #endif
1142 #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_3
1143 case 3:
1144 reg_map = wm8350_mode3_defaults;
1145 break;
1146 #endif
1147 default:
1148 dev_err(wm8350->dev,
1149 "WM8350 configuration mode %d not supported\n",
1150 mode);
1151 return -EINVAL;
1152 }
1153 break;
1154
1155 case 1:
1156 switch (mode) {
1157 #ifdef CONFIG_MFD_WM8351_CONFIG_MODE_0
1158 case 0:
1159 reg_map = wm8351_mode0_defaults;
1160 break;
1161 #endif
1162 #ifdef CONFIG_MFD_WM8351_CONFIG_MODE_1
1163 case 1:
1164 reg_map = wm8351_mode1_defaults;
1165 break;
1166 #endif
1167 #ifdef CONFIG_MFD_WM8351_CONFIG_MODE_2
1168 case 2:
1169 reg_map = wm8351_mode2_defaults;
1170 break;
1171 #endif
1172 #ifdef CONFIG_MFD_WM8351_CONFIG_MODE_3
1173 case 3:
1174 reg_map = wm8351_mode3_defaults;
1175 break;
1176 #endif
1177 default:
1178 dev_err(wm8350->dev,
1179 "WM8351 configuration mode %d not supported\n",
1180 mode);
1181 return -EINVAL;
1182 }
1183 break;
1184
1185 case 2:
1186 switch (mode) {
1187 #ifdef CONFIG_MFD_WM8352_CONFIG_MODE_0
1188 case 0:
1189 reg_map = wm8352_mode0_defaults;
1190 break;
1191 #endif
1192 #ifdef CONFIG_MFD_WM8352_CONFIG_MODE_1
1193 case 1:
1194 reg_map = wm8352_mode1_defaults;
1195 break;
1196 #endif
1197 #ifdef CONFIG_MFD_WM8352_CONFIG_MODE_2
1198 case 2:
1199 reg_map = wm8352_mode2_defaults;
1200 break;
1201 #endif
1202 #ifdef CONFIG_MFD_WM8352_CONFIG_MODE_3
1203 case 3:
1204 reg_map = wm8352_mode3_defaults;
1205 break;
1206 #endif
1207 default:
1208 dev_err(wm8350->dev,
1209 "WM8352 configuration mode %d not supported\n",
1210 mode);
1211 return -EINVAL;
1212 }
1213 break;
1214
1215 default:
1216 dev_err(wm8350->dev,
1217 "WM835x configuration mode %d not supported\n",
1218 mode);
1219 return -EINVAL;
1220 }
1221
1222 wm8350->reg_cache =
1223 kmalloc(sizeof(u16) * (WM8350_MAX_REGISTER + 1), GFP_KERNEL);
1224 if (wm8350->reg_cache == NULL)
1225 return -ENOMEM;
1226
1227 /* Read the initial cache state back from the device - this is
1228 * a PMIC so the device many not be in a virgin state and we
1229 * can't rely on the silicon values.
1230 */
1231 ret = wm8350->read_dev(wm8350, 0,
1232 sizeof(u16) * (WM8350_MAX_REGISTER + 1),
1233 wm8350->reg_cache);
1234 if (ret < 0) {
1235 dev_err(wm8350->dev,
1236 "failed to read initial cache values\n");
1237 goto out;
1238 }
1239
1240 /* Mask out uncacheable/unreadable bits and the audio. */
1241 for (i = 0; i < WM8350_MAX_REGISTER; i++) {
1242 if (wm8350_reg_io_map[i].readable &&
1243 (i < WM8350_CLOCK_CONTROL_1 || i > WM8350_AIF_TEST)) {
1244 value = be16_to_cpu(wm8350->reg_cache[i]);
1245 value &= wm8350_reg_io_map[i].readable;
1246 wm8350->reg_cache[i] = value;
1247 } else
1248 wm8350->reg_cache[i] = reg_map[i];
1249 }
1250
1251 out:
1252 return ret;
1253 }
1254
1255 /*
1256 * Register a client device. This is non-fatal since there is no need to
1257 * fail the entire device init due to a single platform device failing.
1258 */
1259 static void wm8350_client_dev_register(struct wm8350 *wm8350,
1260 const char *name,
1261 struct platform_device **pdev)
1262 {
1263 int ret;
1264
1265 *pdev = platform_device_alloc(name, -1);
1266 if (pdev == NULL) {
1267 dev_err(wm8350->dev, "Failed to allocate %s\n", name);
1268 return;
1269 }
1270
1271 (*pdev)->dev.parent = wm8350->dev;
1272 platform_set_drvdata(*pdev, wm8350);
1273 ret = platform_device_add(*pdev);
1274 if (ret != 0) {
1275 dev_err(wm8350->dev, "Failed to register %s: %d\n", name, ret);
1276 platform_device_put(*pdev);
1277 *pdev = NULL;
1278 }
1279 }
1280
1281 int wm8350_device_init(struct wm8350 *wm8350, int irq,
1282 struct wm8350_platform_data *pdata)
1283 {
1284 int ret;
1285 u16 id1, id2, mask_rev;
1286 u16 cust_id, mode, chip_rev;
1287
1288 /* get WM8350 revision and config mode */
1289 ret = wm8350->read_dev(wm8350, WM8350_RESET_ID, sizeof(id1), &id1);
1290 if (ret != 0) {
1291 dev_err(wm8350->dev, "Failed to read ID: %d\n", ret);
1292 goto err;
1293 }
1294
1295 ret = wm8350->read_dev(wm8350, WM8350_ID, sizeof(id2), &id2);
1296 if (ret != 0) {
1297 dev_err(wm8350->dev, "Failed to read ID: %d\n", ret);
1298 goto err;
1299 }
1300
1301 ret = wm8350->read_dev(wm8350, WM8350_REVISION, sizeof(mask_rev),
1302 &mask_rev);
1303 if (ret != 0) {
1304 dev_err(wm8350->dev, "Failed to read revision: %d\n", ret);
1305 goto err;
1306 }
1307
1308 id1 = be16_to_cpu(id1);
1309 id2 = be16_to_cpu(id2);
1310 mask_rev = be16_to_cpu(mask_rev);
1311
1312 if (id1 != 0x6143) {
1313 dev_err(wm8350->dev,
1314 "Device with ID %x is not a WM8350\n", id1);
1315 ret = -ENODEV;
1316 goto err;
1317 }
1318
1319 mode = id2 & WM8350_CONF_STS_MASK >> 10;
1320 cust_id = id2 & WM8350_CUST_ID_MASK;
1321 chip_rev = (id2 & WM8350_CHIP_REV_MASK) >> 12;
1322 dev_info(wm8350->dev,
1323 "CONF_STS %d, CUST_ID %d, MASK_REV %d, CHIP_REV %d\n",
1324 mode, cust_id, mask_rev, chip_rev);
1325
1326 if (cust_id != 0) {
1327 dev_err(wm8350->dev, "Unsupported CUST_ID\n");
1328 ret = -ENODEV;
1329 goto err;
1330 }
1331
1332 switch (mask_rev) {
1333 case 0:
1334 wm8350->pmic.max_dcdc = WM8350_DCDC_6;
1335 wm8350->pmic.max_isink = WM8350_ISINK_B;
1336
1337 switch (chip_rev) {
1338 case WM8350_REV_E:
1339 dev_info(wm8350->dev, "WM8350 Rev E\n");
1340 break;
1341 case WM8350_REV_F:
1342 dev_info(wm8350->dev, "WM8350 Rev F\n");
1343 break;
1344 case WM8350_REV_G:
1345 dev_info(wm8350->dev, "WM8350 Rev G\n");
1346 wm8350->power.rev_g_coeff = 1;
1347 break;
1348 case WM8350_REV_H:
1349 dev_info(wm8350->dev, "WM8350 Rev H\n");
1350 wm8350->power.rev_g_coeff = 1;
1351 break;
1352 default:
1353 /* For safety we refuse to run on unknown hardware */
1354 dev_err(wm8350->dev, "Unknown WM8350 CHIP_REV\n");
1355 ret = -ENODEV;
1356 goto err;
1357 }
1358 break;
1359
1360 case 1:
1361 wm8350->pmic.max_dcdc = WM8350_DCDC_4;
1362 wm8350->pmic.max_isink = WM8350_ISINK_A;
1363
1364 switch (chip_rev) {
1365 case 0:
1366 dev_info(wm8350->dev, "WM8351 Rev A\n");
1367 wm8350->power.rev_g_coeff = 1;
1368 break;
1369
1370 case 1:
1371 dev_info(wm8350->dev, "WM8351 Rev B\n");
1372 wm8350->power.rev_g_coeff = 1;
1373 break;
1374
1375 default:
1376 dev_err(wm8350->dev, "Unknown WM8351 CHIP_REV\n");
1377 ret = -ENODEV;
1378 goto err;
1379 }
1380 break;
1381
1382 case 2:
1383 wm8350->pmic.max_dcdc = WM8350_DCDC_6;
1384 wm8350->pmic.max_isink = WM8350_ISINK_B;
1385
1386 switch (chip_rev) {
1387 case 0:
1388 dev_info(wm8350->dev, "WM8352 Rev A\n");
1389 wm8350->power.rev_g_coeff = 1;
1390 break;
1391
1392 default:
1393 dev_err(wm8350->dev, "Unknown WM8352 CHIP_REV\n");
1394 ret = -ENODEV;
1395 goto err;
1396 }
1397 break;
1398
1399 default:
1400 dev_err(wm8350->dev, "Unknown MASK_REV\n");
1401 ret = -ENODEV;
1402 goto err;
1403 }
1404
1405 ret = wm8350_create_cache(wm8350, mask_rev, mode);
1406 if (ret < 0) {
1407 dev_err(wm8350->dev, "Failed to create register cache\n");
1408 return ret;
1409 }
1410
1411 wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0xFFFF);
1412 wm8350_reg_write(wm8350, WM8350_INT_STATUS_1_MASK, 0xFFFF);
1413 wm8350_reg_write(wm8350, WM8350_INT_STATUS_2_MASK, 0xFFFF);
1414 wm8350_reg_write(wm8350, WM8350_UNDER_VOLTAGE_INT_STATUS_MASK, 0xFFFF);
1415 wm8350_reg_write(wm8350, WM8350_GPIO_INT_STATUS_MASK, 0xFFFF);
1416 wm8350_reg_write(wm8350, WM8350_COMPARATOR_INT_STATUS_MASK, 0xFFFF);
1417
1418 mutex_init(&wm8350->auxadc_mutex);
1419 mutex_init(&wm8350->irq_mutex);
1420 if (irq) {
1421 int flags = IRQF_ONESHOT;
1422
1423 if (pdata && pdata->irq_high) {
1424 flags |= IRQF_TRIGGER_HIGH;
1425
1426 wm8350_set_bits(wm8350, WM8350_SYSTEM_CONTROL_1,
1427 WM8350_IRQ_POL);
1428 } else {
1429 flags |= IRQF_TRIGGER_LOW;
1430
1431 wm8350_clear_bits(wm8350, WM8350_SYSTEM_CONTROL_1,
1432 WM8350_IRQ_POL);
1433 }
1434
1435 ret = request_threaded_irq(irq, NULL, wm8350_irq, flags,
1436 "wm8350", wm8350);
1437 if (ret != 0) {
1438 dev_err(wm8350->dev, "Failed to request IRQ: %d\n",
1439 ret);
1440 goto err;
1441 }
1442 } else {
1443 dev_err(wm8350->dev, "No IRQ configured\n");
1444 goto err;
1445 }
1446 wm8350->chip_irq = irq;
1447
1448 if (pdata && pdata->init) {
1449 ret = pdata->init(wm8350);
1450 if (ret != 0) {
1451 dev_err(wm8350->dev, "Platform init() failed: %d\n",
1452 ret);
1453 goto err;
1454 }
1455 }
1456
1457 wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0x0);
1458
1459 wm8350_client_dev_register(wm8350, "wm8350-codec",
1460 &(wm8350->codec.pdev));
1461 wm8350_client_dev_register(wm8350, "wm8350-gpio",
1462 &(wm8350->gpio.pdev));
1463 wm8350_client_dev_register(wm8350, "wm8350-hwmon",
1464 &(wm8350->hwmon.pdev));
1465 wm8350_client_dev_register(wm8350, "wm8350-power",
1466 &(wm8350->power.pdev));
1467 wm8350_client_dev_register(wm8350, "wm8350-rtc", &(wm8350->rtc.pdev));
1468 wm8350_client_dev_register(wm8350, "wm8350-wdt", &(wm8350->wdt.pdev));
1469
1470 return 0;
1471
1472 err:
1473 kfree(wm8350->reg_cache);
1474 return ret;
1475 }
1476 EXPORT_SYMBOL_GPL(wm8350_device_init);
1477
1478 void wm8350_device_exit(struct wm8350 *wm8350)
1479 {
1480 int i;
1481
1482 for (i = 0; i < ARRAY_SIZE(wm8350->pmic.led); i++)
1483 platform_device_unregister(wm8350->pmic.led[i].pdev);
1484
1485 for (i = 0; i < ARRAY_SIZE(wm8350->pmic.pdev); i++)
1486 platform_device_unregister(wm8350->pmic.pdev[i]);
1487
1488 platform_device_unregister(wm8350->wdt.pdev);
1489 platform_device_unregister(wm8350->rtc.pdev);
1490 platform_device_unregister(wm8350->power.pdev);
1491 platform_device_unregister(wm8350->hwmon.pdev);
1492 platform_device_unregister(wm8350->gpio.pdev);
1493 platform_device_unregister(wm8350->codec.pdev);
1494
1495 free_irq(wm8350->chip_irq, wm8350);
1496 kfree(wm8350->reg_cache);
1497 }
1498 EXPORT_SYMBOL_GPL(wm8350_device_exit);
1499
1500 MODULE_DESCRIPTION("WM8350 AudioPlus PMIC core driver");
1501 MODULE_LICENSE("GPL");
Support for the Chinese Samsung S3C2440 based development boards