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firewire: ohci: fix Agere FW643 and multiple cameras
[linux-2.6/mini2440.git] / drivers / firewire / ohci.c
blob3486bc49c177b5de82f0de8c52b5ee8708e40628
1 /*
2 * Driver for OHCI 1394 controllers
3 *
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/firewire.h>
26 #include <linux/firewire-constants.h>
27 #include <linux/gfp.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/io.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
33 #include <linux/mm.h>
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/pci.h>
37 #include <linux/pci_ids.h>
38 #include <linux/spinlock.h>
39 #include <linux/string.h>
40
41 #include <asm/atomic.h>
42 #include <asm/byteorder.h>
43 #include <asm/page.h>
44 #include <asm/system.h>
45
46 #ifdef CONFIG_PPC_PMAC
47 #include <asm/pmac_feature.h>
48 #endif
49
50 #include "core.h"
51 #include "ohci.h"
52
53 #define DESCRIPTOR_OUTPUT_MORE 0
54 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
55 #define DESCRIPTOR_INPUT_MORE (2 << 12)
56 #define DESCRIPTOR_INPUT_LAST (3 << 12)
57 #define DESCRIPTOR_STATUS (1 << 11)
58 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
59 #define DESCRIPTOR_PING (1 << 7)
60 #define DESCRIPTOR_YY (1 << 6)
61 #define DESCRIPTOR_NO_IRQ (0 << 4)
62 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
63 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
64 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
65 #define DESCRIPTOR_WAIT (3 << 0)
66
67 struct descriptor {
68 __le16 req_count;
69 __le16 control;
70 __le32 data_address;
71 __le32 branch_address;
72 __le16 res_count;
73 __le16 transfer_status;
74 } __attribute__((aligned(16)));
75
76 struct db_descriptor {
77 __le16 first_size;
78 __le16 control;
79 __le16 second_req_count;
80 __le16 first_req_count;
81 __le32 branch_address;
82 __le16 second_res_count;
83 __le16 first_res_count;
84 __le32 reserved0;
85 __le32 first_buffer;
86 __le32 second_buffer;
87 __le32 reserved1;
88 } __attribute__((aligned(16)));
89
90 #define CONTROL_SET(regs) (regs)
91 #define CONTROL_CLEAR(regs) ((regs) + 4)
92 #define COMMAND_PTR(regs) ((regs) + 12)
93 #define CONTEXT_MATCH(regs) ((regs) + 16)
94
95 struct ar_buffer {
96 struct descriptor descriptor;
97 struct ar_buffer *next;
98 __le32 data[0];
99 };
100
101 struct ar_context {
102 struct fw_ohci *ohci;
103 struct ar_buffer *current_buffer;
104 struct ar_buffer *last_buffer;
105 void *pointer;
106 u32 regs;
107 struct tasklet_struct tasklet;
108 };
109
110 struct context;
111
112 typedef int (*descriptor_callback_t)(struct context *ctx,
113 struct descriptor *d,
114 struct descriptor *last);
115
116 /*
117 * A buffer that contains a block of DMA-able coherent memory used for
118 * storing a portion of a DMA descriptor program.
119 */
120 struct descriptor_buffer {
121 struct list_head list;
122 dma_addr_t buffer_bus;
123 size_t buffer_size;
124 size_t used;
125 struct descriptor buffer[0];
126 };
127
128 struct context {
129 struct fw_ohci *ohci;
130 u32 regs;
131 int total_allocation;
132
133 /*
134 * List of page-sized buffers for storing DMA descriptors.
135 * Head of list contains buffers in use and tail of list contains
136 * free buffers.
137 */
138 struct list_head buffer_list;
139
140 /*
141 * Pointer to a buffer inside buffer_list that contains the tail
142 * end of the current DMA program.
143 */
144 struct descriptor_buffer *buffer_tail;
145
146 /*
147 * The descriptor containing the branch address of the first
148 * descriptor that has not yet been filled by the device.
149 */
150 struct descriptor *last;
151
152 /*
153 * The last descriptor in the DMA program. It contains the branch
154 * address that must be updated upon appending a new descriptor.
155 */
156 struct descriptor *prev;
157
158 descriptor_callback_t callback;
159
160 struct tasklet_struct tasklet;
161 };
162
163 #define IT_HEADER_SY(v) ((v) << 0)
164 #define IT_HEADER_TCODE(v) ((v) << 4)
165 #define IT_HEADER_CHANNEL(v) ((v) << 8)
166 #define IT_HEADER_TAG(v) ((v) << 14)
167 #define IT_HEADER_SPEED(v) ((v) << 16)
168 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
169
170 struct iso_context {
171 struct fw_iso_context base;
172 struct context context;
173 int excess_bytes;
174 void *header;
175 size_t header_length;
176 };
177
178 #define CONFIG_ROM_SIZE 1024
179
180 struct fw_ohci {
181 struct fw_card card;
182
183 __iomem char *registers;
184 dma_addr_t self_id_bus;
185 __le32 *self_id_cpu;
186 struct tasklet_struct bus_reset_tasklet;
187 int node_id;
188 int generation;
189 int request_generation; /* for timestamping incoming requests */
190 atomic_t bus_seconds;
191
192 bool use_dualbuffer;
193 bool old_uninorth;
194 bool bus_reset_packet_quirk;
195
196 /*
197 * Spinlock for accessing fw_ohci data. Never call out of
198 * this driver with this lock held.
199 */
200 spinlock_t lock;
201 u32 self_id_buffer[512];
202
203 /* Config rom buffers */
204 __be32 *config_rom;
205 dma_addr_t config_rom_bus;
206 __be32 *next_config_rom;
207 dma_addr_t next_config_rom_bus;
208 u32 next_header;
209
210 struct ar_context ar_request_ctx;
211 struct ar_context ar_response_ctx;
212 struct context at_request_ctx;
213 struct context at_response_ctx;
214
215 u32 it_context_mask;
216 struct iso_context *it_context_list;
217 u64 ir_context_channels;
218 u32 ir_context_mask;
219 struct iso_context *ir_context_list;
220 };
221
222 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
223 {
224 return container_of(card, struct fw_ohci, card);
225 }
226
227 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
228 #define IR_CONTEXT_BUFFER_FILL 0x80000000
229 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
230 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
231 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
232 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
233
234 #define CONTEXT_RUN 0x8000
235 #define CONTEXT_WAKE 0x1000
236 #define CONTEXT_DEAD 0x0800
237 #define CONTEXT_ACTIVE 0x0400
238
239 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
240 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
241 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
242
243 #define OHCI1394_REGISTER_SIZE 0x800
244 #define OHCI_LOOP_COUNT 500
245 #define OHCI1394_PCI_HCI_Control 0x40
246 #define SELF_ID_BUF_SIZE 0x800
247 #define OHCI_TCODE_PHY_PACKET 0x0e
248 #define OHCI_VERSION_1_1 0x010010
249
250 static char ohci_driver_name[] = KBUILD_MODNAME;
251
252 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
253
254 #define OHCI_PARAM_DEBUG_AT_AR 1
255 #define OHCI_PARAM_DEBUG_SELFIDS 2
256 #define OHCI_PARAM_DEBUG_IRQS 4
257 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
258
259 static int param_debug;
260 module_param_named(debug, param_debug, int, 0644);
261 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
262 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
263 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
264 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
265 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
266 ", or a combination, or all = -1)");
267
268 static void log_irqs(u32 evt)
269 {
270 if (likely(!(param_debug &
271 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
272 return;
273
274 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
275 !(evt & OHCI1394_busReset))
276 return;
277
278 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
279 evt & OHCI1394_selfIDComplete ? " selfID" : "",
280 evt & OHCI1394_RQPkt ? " AR_req" : "",
281 evt & OHCI1394_RSPkt ? " AR_resp" : "",
282 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
283 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
284 evt & OHCI1394_isochRx ? " IR" : "",
285 evt & OHCI1394_isochTx ? " IT" : "",
286 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
287 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
288 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
289 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
290 evt & OHCI1394_busReset ? " busReset" : "",
291 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
292 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
293 OHCI1394_respTxComplete | OHCI1394_isochRx |
294 OHCI1394_isochTx | OHCI1394_postedWriteErr |
295 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
296 OHCI1394_regAccessFail | OHCI1394_busReset)
297 ? " ?" : "");
298 }
299
300 static const char *speed[] = {
301 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
302 };
303 static const char *power[] = {
304 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
305 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
306 };
307 static const char port[] = { '.', '-', 'p', 'c', };
308
309 static char _p(u32 *s, int shift)
310 {
311 return port[*s >> shift & 3];
312 }
313
314 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
315 {
316 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
317 return;
318
319 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
320 self_id_count, generation, node_id);
321
322 for (; self_id_count--; ++s)
323 if ((*s & 1 << 23) == 0)
324 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
325 "%s gc=%d %s %s%s%s\n",
326 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
327 speed[*s >> 14 & 3], *s >> 16 & 63,
328 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
329 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
330 else
331 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
332 *s, *s >> 24 & 63,
333 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
334 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
335 }
336
337 static const char *evts[] = {
338 [0x00] = "evt_no_status", [0x01] = "-reserved-",
339 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
340 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
341 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
342 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
343 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
344 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
345 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
346 [0x10] = "-reserved-", [0x11] = "ack_complete",
347 [0x12] = "ack_pending ", [0x13] = "-reserved-",
348 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
349 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
350 [0x18] = "-reserved-", [0x19] = "-reserved-",
351 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
352 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
353 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
354 [0x20] = "pending/cancelled",
355 };
356 static const char *tcodes[] = {
357 [0x0] = "QW req", [0x1] = "BW req",
358 [0x2] = "W resp", [0x3] = "-reserved-",
359 [0x4] = "QR req", [0x5] = "BR req",
360 [0x6] = "QR resp", [0x7] = "BR resp",
361 [0x8] = "cycle start", [0x9] = "Lk req",
362 [0xa] = "async stream packet", [0xb] = "Lk resp",
363 [0xc] = "-reserved-", [0xd] = "-reserved-",
364 [0xe] = "link internal", [0xf] = "-reserved-",
365 };
366 static const char *phys[] = {
367 [0x0] = "phy config packet", [0x1] = "link-on packet",
368 [0x2] = "self-id packet", [0x3] = "-reserved-",
369 };
370
371 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
372 {
373 int tcode = header[0] >> 4 & 0xf;
374 char specific[12];
375
376 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
377 return;
378
379 if (unlikely(evt >= ARRAY_SIZE(evts)))
380 evt = 0x1f;
381
382 if (evt == OHCI1394_evt_bus_reset) {
383 fw_notify("A%c evt_bus_reset, generation %d\n",
384 dir, (header[2] >> 16) & 0xff);
385 return;
386 }
387
388 if (header[0] == ~header[1]) {
389 fw_notify("A%c %s, %s, %08x\n",
390 dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
391 return;
392 }
393
394 switch (tcode) {
395 case 0x0: case 0x6: case 0x8:
396 snprintf(specific, sizeof(specific), " = %08x",
397 be32_to_cpu((__force __be32)header[3]));
398 break;
399 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
400 snprintf(specific, sizeof(specific), " %x,%x",
401 header[3] >> 16, header[3] & 0xffff);
402 break;
403 default:
404 specific[0] = '\0';
405 }
406
407 switch (tcode) {
408 case 0xe: case 0xa:
409 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
410 break;
411 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
412 fw_notify("A%c spd %x tl %02x, "
413 "%04x -> %04x, %s, "
414 "%s, %04x%08x%s\n",
415 dir, speed, header[0] >> 10 & 0x3f,
416 header[1] >> 16, header[0] >> 16, evts[evt],
417 tcodes[tcode], header[1] & 0xffff, header[2], specific);
418 break;
419 default:
420 fw_notify("A%c spd %x tl %02x, "
421 "%04x -> %04x, %s, "
422 "%s%s\n",
423 dir, speed, header[0] >> 10 & 0x3f,
424 header[1] >> 16, header[0] >> 16, evts[evt],
425 tcodes[tcode], specific);
426 }
427 }
428
429 #else
430
431 #define log_irqs(evt)
432 #define log_selfids(node_id, generation, self_id_count, sid)
433 #define log_ar_at_event(dir, speed, header, evt)
434
435 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
436
437 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
438 {
439 writel(data, ohci->registers + offset);
440 }
441
442 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
443 {
444 return readl(ohci->registers + offset);
445 }
446
447 static inline void flush_writes(const struct fw_ohci *ohci)
448 {
449 /* Do a dummy read to flush writes. */
450 reg_read(ohci, OHCI1394_Version);
451 }
452
453 static int ohci_update_phy_reg(struct fw_card *card, int addr,
454 int clear_bits, int set_bits)
455 {
456 struct fw_ohci *ohci = fw_ohci(card);
457 u32 val, old;
458
459 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
460 flush_writes(ohci);
461 msleep(2);
462 val = reg_read(ohci, OHCI1394_PhyControl);
463 if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
464 fw_error("failed to set phy reg bits.\n");
465 return -EBUSY;
466 }
467
468 old = OHCI1394_PhyControl_ReadData(val);
469 old = (old & ~clear_bits) | set_bits;
470 reg_write(ohci, OHCI1394_PhyControl,
471 OHCI1394_PhyControl_Write(addr, old));
472
473 return 0;
474 }
475
476 static int ar_context_add_page(struct ar_context *ctx)
477 {
478 struct device *dev = ctx->ohci->card.device;
479 struct ar_buffer *ab;
480 dma_addr_t uninitialized_var(ab_bus);
481 size_t offset;
482
483 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
484 if (ab == NULL)
485 return -ENOMEM;
486
487 ab->next = NULL;
488 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
489 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
490 DESCRIPTOR_STATUS |
491 DESCRIPTOR_BRANCH_ALWAYS);
492 offset = offsetof(struct ar_buffer, data);
493 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
494 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
495 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
496 ab->descriptor.branch_address = 0;
497
498 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
499 ctx->last_buffer->next = ab;
500 ctx->last_buffer = ab;
501
502 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
503 flush_writes(ctx->ohci);
504
505 return 0;
506 }
507
508 static void ar_context_release(struct ar_context *ctx)
509 {
510 struct ar_buffer *ab, *ab_next;
511 size_t offset;
512 dma_addr_t ab_bus;
513
514 for (ab = ctx->current_buffer; ab; ab = ab_next) {
515 ab_next = ab->next;
516 offset = offsetof(struct ar_buffer, data);
517 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
518 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
519 ab, ab_bus);
520 }
521 }
522
523 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
524 #define cond_le32_to_cpu(v) \
525 (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
526 #else
527 #define cond_le32_to_cpu(v) le32_to_cpu(v)
528 #endif
529
530 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
531 {
532 struct fw_ohci *ohci = ctx->ohci;
533 struct fw_packet p;
534 u32 status, length, tcode;
535 int evt;
536
537 p.header[0] = cond_le32_to_cpu(buffer[0]);
538 p.header[1] = cond_le32_to_cpu(buffer[1]);
539 p.header[2] = cond_le32_to_cpu(buffer[2]);
540
541 tcode = (p.header[0] >> 4) & 0x0f;
542 switch (tcode) {
543 case TCODE_WRITE_QUADLET_REQUEST:
544 case TCODE_READ_QUADLET_RESPONSE:
545 p.header[3] = (__force __u32) buffer[3];
546 p.header_length = 16;
547 p.payload_length = 0;
548 break;
549
550 case TCODE_READ_BLOCK_REQUEST :
551 p.header[3] = cond_le32_to_cpu(buffer[3]);
552 p.header_length = 16;
553 p.payload_length = 0;
554 break;
555
556 case TCODE_WRITE_BLOCK_REQUEST:
557 case TCODE_READ_BLOCK_RESPONSE:
558 case TCODE_LOCK_REQUEST:
559 case TCODE_LOCK_RESPONSE:
560 p.header[3] = cond_le32_to_cpu(buffer[3]);
561 p.header_length = 16;
562 p.payload_length = p.header[3] >> 16;
563 break;
564
565 case TCODE_WRITE_RESPONSE:
566 case TCODE_READ_QUADLET_REQUEST:
567 case OHCI_TCODE_PHY_PACKET:
568 p.header_length = 12;
569 p.payload_length = 0;
570 break;
571
572 default:
573 /* FIXME: Stop context, discard everything, and restart? */
574 p.header_length = 0;
575 p.payload_length = 0;
576 }
577
578 p.payload = (void *) buffer + p.header_length;
579
580 /* FIXME: What to do about evt_* errors? */
581 length = (p.header_length + p.payload_length + 3) / 4;
582 status = cond_le32_to_cpu(buffer[length]);
583 evt = (status >> 16) & 0x1f;
584
585 p.ack = evt - 16;
586 p.speed = (status >> 21) & 0x7;
587 p.timestamp = status & 0xffff;
588 p.generation = ohci->request_generation;
589
590 log_ar_at_event('R', p.speed, p.header, evt);
591
592 /*
593 * The OHCI bus reset handler synthesizes a phy packet with
594 * the new generation number when a bus reset happens (see
595 * section 8.4.2.3). This helps us determine when a request
596 * was received and make sure we send the response in the same
597 * generation. We only need this for requests; for responses
598 * we use the unique tlabel for finding the matching
599 * request.
600 *
601 * Alas some chips sometimes emit bus reset packets with a
602 * wrong generation. We set the correct generation for these
603 * at a slightly incorrect time (in bus_reset_tasklet).
604 */
605 if (evt == OHCI1394_evt_bus_reset) {
606 if (!ohci->bus_reset_packet_quirk)
607 ohci->request_generation = (p.header[2] >> 16) & 0xff;
608 } else if (ctx == &ohci->ar_request_ctx) {
609 fw_core_handle_request(&ohci->card, &p);
610 } else {
611 fw_core_handle_response(&ohci->card, &p);
612 }
613
614 return buffer + length + 1;
615 }
616
617 static void ar_context_tasklet(unsigned long data)
618 {
619 struct ar_context *ctx = (struct ar_context *)data;
620 struct fw_ohci *ohci = ctx->ohci;
621 struct ar_buffer *ab;
622 struct descriptor *d;
623 void *buffer, *end;
624
625 ab = ctx->current_buffer;
626 d = &ab->descriptor;
627
628 if (d->res_count == 0) {
629 size_t size, rest, offset;
630 dma_addr_t start_bus;
631 void *start;
632
633 /*
634 * This descriptor is finished and we may have a
635 * packet split across this and the next buffer. We
636 * reuse the page for reassembling the split packet.
637 */
638
639 offset = offsetof(struct ar_buffer, data);
640 start = buffer = ab;
641 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
642
643 ab = ab->next;
644 d = &ab->descriptor;
645 size = buffer + PAGE_SIZE - ctx->pointer;
646 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
647 memmove(buffer, ctx->pointer, size);
648 memcpy(buffer + size, ab->data, rest);
649 ctx->current_buffer = ab;
650 ctx->pointer = (void *) ab->data + rest;
651 end = buffer + size + rest;
652
653 while (buffer < end)
654 buffer = handle_ar_packet(ctx, buffer);
655
656 dma_free_coherent(ohci->card.device, PAGE_SIZE,
657 start, start_bus);
658 ar_context_add_page(ctx);
659 } else {
660 buffer = ctx->pointer;
661 ctx->pointer = end =
662 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
663
664 while (buffer < end)
665 buffer = handle_ar_packet(ctx, buffer);
666 }
667 }
668
669 static int ar_context_init(struct ar_context *ctx,
670 struct fw_ohci *ohci, u32 regs)
671 {
672 struct ar_buffer ab;
673
674 ctx->regs = regs;
675 ctx->ohci = ohci;
676 ctx->last_buffer = &ab;
677 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
678
679 ar_context_add_page(ctx);
680 ar_context_add_page(ctx);
681 ctx->current_buffer = ab.next;
682 ctx->pointer = ctx->current_buffer->data;
683
684 return 0;
685 }
686
687 static void ar_context_run(struct ar_context *ctx)
688 {
689 struct ar_buffer *ab = ctx->current_buffer;
690 dma_addr_t ab_bus;
691 size_t offset;
692
693 offset = offsetof(struct ar_buffer, data);
694 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
695
696 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
697 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
698 flush_writes(ctx->ohci);
699 }
700
701 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
702 {
703 int b, key;
704
705 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
706 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
707
708 /* figure out which descriptor the branch address goes in */
709 if (z == 2 && (b == 3 || key == 2))
710 return d;
711 else
712 return d + z - 1;
713 }
714
715 static void context_tasklet(unsigned long data)
716 {
717 struct context *ctx = (struct context *) data;
718 struct descriptor *d, *last;
719 u32 address;
720 int z;
721 struct descriptor_buffer *desc;
722
723 desc = list_entry(ctx->buffer_list.next,
724 struct descriptor_buffer, list);
725 last = ctx->last;
726 while (last->branch_address != 0) {
727 struct descriptor_buffer *old_desc = desc;
728 address = le32_to_cpu(last->branch_address);
729 z = address & 0xf;
730 address &= ~0xf;
731
732 /* If the branch address points to a buffer outside of the
733 * current buffer, advance to the next buffer. */
734 if (address < desc->buffer_bus ||
735 address >= desc->buffer_bus + desc->used)
736 desc = list_entry(desc->list.next,
737 struct descriptor_buffer, list);
738 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
739 last = find_branch_descriptor(d, z);
740
741 if (!ctx->callback(ctx, d, last))
742 break;
743
744 if (old_desc != desc) {
745 /* If we've advanced to the next buffer, move the
746 * previous buffer to the free list. */
747 unsigned long flags;
748 old_desc->used = 0;
749 spin_lock_irqsave(&ctx->ohci->lock, flags);
750 list_move_tail(&old_desc->list, &ctx->buffer_list);
751 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
752 }
753 ctx->last = last;
754 }
755 }
756
757 /*
758 * Allocate a new buffer and add it to the list of free buffers for this
759 * context. Must be called with ohci->lock held.
760 */
761 static int context_add_buffer(struct context *ctx)
762 {
763 struct descriptor_buffer *desc;
764 dma_addr_t uninitialized_var(bus_addr);
765 int offset;
766
767 /*
768 * 16MB of descriptors should be far more than enough for any DMA
769 * program. This will catch run-away userspace or DoS attacks.
770 */
771 if (ctx->total_allocation >= 16*1024*1024)
772 return -ENOMEM;
773
774 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
775 &bus_addr, GFP_ATOMIC);
776 if (!desc)
777 return -ENOMEM;
778
779 offset = (void *)&desc->buffer - (void *)desc;
780 desc->buffer_size = PAGE_SIZE - offset;
781 desc->buffer_bus = bus_addr + offset;
782 desc->used = 0;
783
784 list_add_tail(&desc->list, &ctx->buffer_list);
785 ctx->total_allocation += PAGE_SIZE;
786
787 return 0;
788 }
789
790 static int context_init(struct context *ctx, struct fw_ohci *ohci,
791 u32 regs, descriptor_callback_t callback)
792 {
793 ctx->ohci = ohci;
794 ctx->regs = regs;
795 ctx->total_allocation = 0;
796
797 INIT_LIST_HEAD(&ctx->buffer_list);
798 if (context_add_buffer(ctx) < 0)
799 return -ENOMEM;
800
801 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
802 struct descriptor_buffer, list);
803
804 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
805 ctx->callback = callback;
806
807 /*
808 * We put a dummy descriptor in the buffer that has a NULL
809 * branch address and looks like it's been sent. That way we
810 * have a descriptor to append DMA programs to.
811 */
812 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
813 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
814 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
815 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
816 ctx->last = ctx->buffer_tail->buffer;
817 ctx->prev = ctx->buffer_tail->buffer;
818
819 return 0;
820 }
821
822 static void context_release(struct context *ctx)
823 {
824 struct fw_card *card = &ctx->ohci->card;
825 struct descriptor_buffer *desc, *tmp;
826
827 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
828 dma_free_coherent(card->device, PAGE_SIZE, desc,
829 desc->buffer_bus -
830 ((void *)&desc->buffer - (void *)desc));
831 }
832
833 /* Must be called with ohci->lock held */
834 static struct descriptor *context_get_descriptors(struct context *ctx,
835 int z, dma_addr_t *d_bus)
836 {
837 struct descriptor *d = NULL;
838 struct descriptor_buffer *desc = ctx->buffer_tail;
839
840 if (z * sizeof(*d) > desc->buffer_size)
841 return NULL;
842
843 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
844 /* No room for the descriptor in this buffer, so advance to the
845 * next one. */
846
847 if (desc->list.next == &ctx->buffer_list) {
848 /* If there is no free buffer next in the list,
849 * allocate one. */
850 if (context_add_buffer(ctx) < 0)
851 return NULL;
852 }
853 desc = list_entry(desc->list.next,
854 struct descriptor_buffer, list);
855 ctx->buffer_tail = desc;
856 }
857
858 d = desc->buffer + desc->used / sizeof(*d);
859 memset(d, 0, z * sizeof(*d));
860 *d_bus = desc->buffer_bus + desc->used;
861
862 return d;
863 }
864
865 static void context_run(struct context *ctx, u32 extra)
866 {
867 struct fw_ohci *ohci = ctx->ohci;
868
869 reg_write(ohci, COMMAND_PTR(ctx->regs),
870 le32_to_cpu(ctx->last->branch_address));
871 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
872 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
873 flush_writes(ohci);
874 }
875
876 static void context_append(struct context *ctx,
877 struct descriptor *d, int z, int extra)
878 {
879 dma_addr_t d_bus;
880 struct descriptor_buffer *desc = ctx->buffer_tail;
881
882 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
883
884 desc->used += (z + extra) * sizeof(*d);
885 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
886 ctx->prev = find_branch_descriptor(d, z);
887
888 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
889 flush_writes(ctx->ohci);
890 }
891
892 static void context_stop(struct context *ctx)
893 {
894 u32 reg;
895 int i;
896
897 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
898 flush_writes(ctx->ohci);
899
900 for (i = 0; i < 10; i++) {
901 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
902 if ((reg & CONTEXT_ACTIVE) == 0)
903 return;
904
905 mdelay(1);
906 }
907 fw_error("Error: DMA context still active (0x%08x)\n", reg);
908 }
909
910 struct driver_data {
911 struct fw_packet *packet;
912 };
913
914 /*
915 * This function apppends a packet to the DMA queue for transmission.
916 * Must always be called with the ochi->lock held to ensure proper
917 * generation handling and locking around packet queue manipulation.
918 */
919 static int at_context_queue_packet(struct context *ctx,
920 struct fw_packet *packet)
921 {
922 struct fw_ohci *ohci = ctx->ohci;
923 dma_addr_t d_bus, uninitialized_var(payload_bus);
924 struct driver_data *driver_data;
925 struct descriptor *d, *last;
926 __le32 *header;
927 int z, tcode;
928 u32 reg;
929
930 d = context_get_descriptors(ctx, 4, &d_bus);
931 if (d == NULL) {
932 packet->ack = RCODE_SEND_ERROR;
933 return -1;
934 }
935
936 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
937 d[0].res_count = cpu_to_le16(packet->timestamp);
938
939 /*
940 * The DMA format for asyncronous link packets is different
941 * from the IEEE1394 layout, so shift the fields around
942 * accordingly. If header_length is 8, it's a PHY packet, to
943 * which we need to prepend an extra quadlet.
944 */
945
946 header = (__le32 *) &d[1];
947 switch (packet->header_length) {
948 case 16:
949 case 12:
950 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
951 (packet->speed << 16));
952 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
953 (packet->header[0] & 0xffff0000));
954 header[2] = cpu_to_le32(packet->header[2]);
955
956 tcode = (packet->header[0] >> 4) & 0x0f;
957 if (TCODE_IS_BLOCK_PACKET(tcode))
958 header[3] = cpu_to_le32(packet->header[3]);
959 else
960 header[3] = (__force __le32) packet->header[3];
961
962 d[0].req_count = cpu_to_le16(packet->header_length);
963 break;
964
965 case 8:
966 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
967 (packet->speed << 16));
968 header[1] = cpu_to_le32(packet->header[0]);
969 header[2] = cpu_to_le32(packet->header[1]);
970 d[0].req_count = cpu_to_le16(12);
971 break;
972
973 case 4:
974 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
975 (packet->speed << 16));
976 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
977 d[0].req_count = cpu_to_le16(8);
978 break;
979
980 default:
981 /* BUG(); */
982 packet->ack = RCODE_SEND_ERROR;
983 return -1;
984 }
985
986 driver_data = (struct driver_data *) &d[3];
987 driver_data->packet = packet;
988 packet->driver_data = driver_data;
989
990 if (packet->payload_length > 0) {
991 payload_bus =
992 dma_map_single(ohci->card.device, packet->payload,
993 packet->payload_length, DMA_TO_DEVICE);
994 if (dma_mapping_error(ohci->card.device, payload_bus)) {
995 packet->ack = RCODE_SEND_ERROR;
996 return -1;
997 }
998 packet->payload_bus = payload_bus;
999
1000 d[2].req_count = cpu_to_le16(packet->payload_length);
1001 d[2].data_address = cpu_to_le32(payload_bus);
1002 last = &d[2];
1003 z = 3;
1004 } else {
1005 last = &d[0];
1006 z = 2;
1007 }
1008
1009 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1010 DESCRIPTOR_IRQ_ALWAYS |
1011 DESCRIPTOR_BRANCH_ALWAYS);
1012
1013 /*
1014 * If the controller and packet generations don't match, we need to
1015 * bail out and try again. If IntEvent.busReset is set, the AT context
1016 * is halted, so appending to the context and trying to run it is
1017 * futile. Most controllers do the right thing and just flush the AT
1018 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1019 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1020 * up stalling out. So we just bail out in software and try again
1021 * later, and everyone is happy.
1022 * FIXME: Document how the locking works.
1023 */
1024 if (ohci->generation != packet->generation ||
1025 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1026 if (packet->payload_length > 0)
1027 dma_unmap_single(ohci->card.device, payload_bus,
1028 packet->payload_length, DMA_TO_DEVICE);
1029 packet->ack = RCODE_GENERATION;
1030 return -1;
1031 }
1032
1033 context_append(ctx, d, z, 4 - z);
1034
1035 /* If the context isn't already running, start it up. */
1036 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1037 if ((reg & CONTEXT_RUN) == 0)
1038 context_run(ctx, 0);
1039
1040 return 0;
1041 }
1042
1043 static int handle_at_packet(struct context *context,
1044 struct descriptor *d,
1045 struct descriptor *last)
1046 {
1047 struct driver_data *driver_data;
1048 struct fw_packet *packet;
1049 struct fw_ohci *ohci = context->ohci;
1050 int evt;
1051
1052 if (last->transfer_status == 0)
1053 /* This descriptor isn't done yet, stop iteration. */
1054 return 0;
1055
1056 driver_data = (struct driver_data *) &d[3];
1057 packet = driver_data->packet;
1058 if (packet == NULL)
1059 /* This packet was cancelled, just continue. */
1060 return 1;
1061
1062 if (packet->payload_bus)
1063 dma_unmap_single(ohci->card.device, packet->payload_bus,
1064 packet->payload_length, DMA_TO_DEVICE);
1065
1066 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1067 packet->timestamp = le16_to_cpu(last->res_count);
1068
1069 log_ar_at_event('T', packet->speed, packet->header, evt);
1070
1071 switch (evt) {
1072 case OHCI1394_evt_timeout:
1073 /* Async response transmit timed out. */
1074 packet->ack = RCODE_CANCELLED;
1075 break;
1076
1077 case OHCI1394_evt_flushed:
1078 /*
1079 * The packet was flushed should give same error as
1080 * when we try to use a stale generation count.
1081 */
1082 packet->ack = RCODE_GENERATION;
1083 break;
1084
1085 case OHCI1394_evt_missing_ack:
1086 /*
1087 * Using a valid (current) generation count, but the
1088 * node is not on the bus or not sending acks.
1089 */
1090 packet->ack = RCODE_NO_ACK;
1091 break;
1092
1093 case ACK_COMPLETE + 0x10:
1094 case ACK_PENDING + 0x10:
1095 case ACK_BUSY_X + 0x10:
1096 case ACK_BUSY_A + 0x10:
1097 case ACK_BUSY_B + 0x10:
1098 case ACK_DATA_ERROR + 0x10:
1099 case ACK_TYPE_ERROR + 0x10:
1100 packet->ack = evt - 0x10;
1101 break;
1102
1103 default:
1104 packet->ack = RCODE_SEND_ERROR;
1105 break;
1106 }
1107
1108 packet->callback(packet, &ohci->card, packet->ack);
1109
1110 return 1;
1111 }
1112
1113 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1114 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1115 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1116 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1117 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1118
1119 static void handle_local_rom(struct fw_ohci *ohci,
1120 struct fw_packet *packet, u32 csr)
1121 {
1122 struct fw_packet response;
1123 int tcode, length, i;
1124
1125 tcode = HEADER_GET_TCODE(packet->header[0]);
1126 if (TCODE_IS_BLOCK_PACKET(tcode))
1127 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1128 else
1129 length = 4;
1130
1131 i = csr - CSR_CONFIG_ROM;
1132 if (i + length > CONFIG_ROM_SIZE) {
1133 fw_fill_response(&response, packet->header,
1134 RCODE_ADDRESS_ERROR, NULL, 0);
1135 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1136 fw_fill_response(&response, packet->header,
1137 RCODE_TYPE_ERROR, NULL, 0);
1138 } else {
1139 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1140 (void *) ohci->config_rom + i, length);
1141 }
1142
1143 fw_core_handle_response(&ohci->card, &response);
1144 }
1145
1146 static void handle_local_lock(struct fw_ohci *ohci,
1147 struct fw_packet *packet, u32 csr)
1148 {
1149 struct fw_packet response;
1150 int tcode, length, ext_tcode, sel;
1151 __be32 *payload, lock_old;
1152 u32 lock_arg, lock_data;
1153
1154 tcode = HEADER_GET_TCODE(packet->header[0]);
1155 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1156 payload = packet->payload;
1157 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1158
1159 if (tcode == TCODE_LOCK_REQUEST &&
1160 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1161 lock_arg = be32_to_cpu(payload[0]);
1162 lock_data = be32_to_cpu(payload[1]);
1163 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1164 lock_arg = 0;
1165 lock_data = 0;
1166 } else {
1167 fw_fill_response(&response, packet->header,
1168 RCODE_TYPE_ERROR, NULL, 0);
1169 goto out;
1170 }
1171
1172 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1173 reg_write(ohci, OHCI1394_CSRData, lock_data);
1174 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1175 reg_write(ohci, OHCI1394_CSRControl, sel);
1176
1177 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1178 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1179 else
1180 fw_notify("swap not done yet\n");
1181
1182 fw_fill_response(&response, packet->header,
1183 RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1184 out:
1185 fw_core_handle_response(&ohci->card, &response);
1186 }
1187
1188 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1189 {
1190 u64 offset;
1191 u32 csr;
1192
1193 if (ctx == &ctx->ohci->at_request_ctx) {
1194 packet->ack = ACK_PENDING;
1195 packet->callback(packet, &ctx->ohci->card, packet->ack);
1196 }
1197
1198 offset =
1199 ((unsigned long long)
1200 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1201 packet->header[2];
1202 csr = offset - CSR_REGISTER_BASE;
1203
1204 /* Handle config rom reads. */
1205 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1206 handle_local_rom(ctx->ohci, packet, csr);
1207 else switch (csr) {
1208 case CSR_BUS_MANAGER_ID:
1209 case CSR_BANDWIDTH_AVAILABLE:
1210 case CSR_CHANNELS_AVAILABLE_HI:
1211 case CSR_CHANNELS_AVAILABLE_LO:
1212 handle_local_lock(ctx->ohci, packet, csr);
1213 break;
1214 default:
1215 if (ctx == &ctx->ohci->at_request_ctx)
1216 fw_core_handle_request(&ctx->ohci->card, packet);
1217 else
1218 fw_core_handle_response(&ctx->ohci->card, packet);
1219 break;
1220 }
1221
1222 if (ctx == &ctx->ohci->at_response_ctx) {
1223 packet->ack = ACK_COMPLETE;
1224 packet->callback(packet, &ctx->ohci->card, packet->ack);
1225 }
1226 }
1227
1228 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1229 {
1230 unsigned long flags;
1231 int ret;
1232
1233 spin_lock_irqsave(&ctx->ohci->lock, flags);
1234
1235 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1236 ctx->ohci->generation == packet->generation) {
1237 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1238 handle_local_request(ctx, packet);
1239 return;
1240 }
1241
1242 ret = at_context_queue_packet(ctx, packet);
1243 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1244
1245 if (ret < 0)
1246 packet->callback(packet, &ctx->ohci->card, packet->ack);
1247
1248 }
1249
1250 static void bus_reset_tasklet(unsigned long data)
1251 {
1252 struct fw_ohci *ohci = (struct fw_ohci *)data;
1253 int self_id_count, i, j, reg;
1254 int generation, new_generation;
1255 unsigned long flags;
1256 void *free_rom = NULL;
1257 dma_addr_t free_rom_bus = 0;
1258
1259 reg = reg_read(ohci, OHCI1394_NodeID);
1260 if (!(reg & OHCI1394_NodeID_idValid)) {
1261 fw_notify("node ID not valid, new bus reset in progress\n");
1262 return;
1263 }
1264 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1265 fw_notify("malconfigured bus\n");
1266 return;
1267 }
1268 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1269 OHCI1394_NodeID_nodeNumber);
1270
1271 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1272 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1273 fw_notify("inconsistent self IDs\n");
1274 return;
1275 }
1276 /*
1277 * The count in the SelfIDCount register is the number of
1278 * bytes in the self ID receive buffer. Since we also receive
1279 * the inverted quadlets and a header quadlet, we shift one
1280 * bit extra to get the actual number of self IDs.
1281 */
1282 self_id_count = (reg >> 3) & 0x3ff;
1283 if (self_id_count == 0) {
1284 fw_notify("inconsistent self IDs\n");
1285 return;
1286 }
1287 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1288 rmb();
1289
1290 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1291 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1292 fw_notify("inconsistent self IDs\n");
1293 return;
1294 }
1295 ohci->self_id_buffer[j] =
1296 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1297 }
1298 rmb();
1299
1300 /*
1301 * Check the consistency of the self IDs we just read. The
1302 * problem we face is that a new bus reset can start while we
1303 * read out the self IDs from the DMA buffer. If this happens,
1304 * the DMA buffer will be overwritten with new self IDs and we
1305 * will read out inconsistent data. The OHCI specification
1306 * (section 11.2) recommends a technique similar to
1307 * linux/seqlock.h, where we remember the generation of the
1308 * self IDs in the buffer before reading them out and compare
1309 * it to the current generation after reading them out. If
1310 * the two generations match we know we have a consistent set
1311 * of self IDs.
1312 */
1313
1314 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1315 if (new_generation != generation) {
1316 fw_notify("recursive bus reset detected, "
1317 "discarding self ids\n");
1318 return;
1319 }
1320
1321 /* FIXME: Document how the locking works. */
1322 spin_lock_irqsave(&ohci->lock, flags);
1323
1324 ohci->generation = generation;
1325 context_stop(&ohci->at_request_ctx);
1326 context_stop(&ohci->at_response_ctx);
1327 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1328
1329 if (ohci->bus_reset_packet_quirk)
1330 ohci->request_generation = generation;
1331
1332 /*
1333 * This next bit is unrelated to the AT context stuff but we
1334 * have to do it under the spinlock also. If a new config rom
1335 * was set up before this reset, the old one is now no longer
1336 * in use and we can free it. Update the config rom pointers
1337 * to point to the current config rom and clear the
1338 * next_config_rom pointer so a new udpate can take place.
1339 */
1340
1341 if (ohci->next_config_rom != NULL) {
1342 if (ohci->next_config_rom != ohci->config_rom) {
1343 free_rom = ohci->config_rom;
1344 free_rom_bus = ohci->config_rom_bus;
1345 }
1346 ohci->config_rom = ohci->next_config_rom;
1347 ohci->config_rom_bus = ohci->next_config_rom_bus;
1348 ohci->next_config_rom = NULL;
1349
1350 /*
1351 * Restore config_rom image and manually update
1352 * config_rom registers. Writing the header quadlet
1353 * will indicate that the config rom is ready, so we
1354 * do that last.
1355 */
1356 reg_write(ohci, OHCI1394_BusOptions,
1357 be32_to_cpu(ohci->config_rom[2]));
1358 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
1359 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
1360 }
1361
1362 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1363 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1364 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1365 #endif
1366
1367 spin_unlock_irqrestore(&ohci->lock, flags);
1368
1369 if (free_rom)
1370 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1371 free_rom, free_rom_bus);
1372
1373 log_selfids(ohci->node_id, generation,
1374 self_id_count, ohci->self_id_buffer);
1375
1376 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1377 self_id_count, ohci->self_id_buffer);
1378 }
1379
1380 static irqreturn_t irq_handler(int irq, void *data)
1381 {
1382 struct fw_ohci *ohci = data;
1383 u32 event, iso_event, cycle_time;
1384 int i;
1385
1386 event = reg_read(ohci, OHCI1394_IntEventClear);
1387
1388 if (!event || !~event)
1389 return IRQ_NONE;
1390
1391 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1392 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1393 log_irqs(event);
1394
1395 if (event & OHCI1394_selfIDComplete)
1396 tasklet_schedule(&ohci->bus_reset_tasklet);
1397
1398 if (event & OHCI1394_RQPkt)
1399 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1400
1401 if (event & OHCI1394_RSPkt)
1402 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1403
1404 if (event & OHCI1394_reqTxComplete)
1405 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1406
1407 if (event & OHCI1394_respTxComplete)
1408 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1409
1410 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1411 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1412
1413 while (iso_event) {
1414 i = ffs(iso_event) - 1;
1415 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1416 iso_event &= ~(1 << i);
1417 }
1418
1419 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1420 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1421
1422 while (iso_event) {
1423 i = ffs(iso_event) - 1;
1424 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1425 iso_event &= ~(1 << i);
1426 }
1427
1428 if (unlikely(event & OHCI1394_regAccessFail))
1429 fw_error("Register access failure - "
1430 "please notify linux1394-devel@lists.sf.net\n");
1431
1432 if (unlikely(event & OHCI1394_postedWriteErr))
1433 fw_error("PCI posted write error\n");
1434
1435 if (unlikely(event & OHCI1394_cycleTooLong)) {
1436 if (printk_ratelimit())
1437 fw_notify("isochronous cycle too long\n");
1438 reg_write(ohci, OHCI1394_LinkControlSet,
1439 OHCI1394_LinkControl_cycleMaster);
1440 }
1441
1442 if (event & OHCI1394_cycle64Seconds) {
1443 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1444 if ((cycle_time & 0x80000000) == 0)
1445 atomic_inc(&ohci->bus_seconds);
1446 }
1447
1448 return IRQ_HANDLED;
1449 }
1450
1451 static int software_reset(struct fw_ohci *ohci)
1452 {
1453 int i;
1454
1455 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1456
1457 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1458 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1459 OHCI1394_HCControl_softReset) == 0)
1460 return 0;
1461 msleep(1);
1462 }
1463
1464 return -EBUSY;
1465 }
1466
1467 static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1468 {
1469 struct fw_ohci *ohci = fw_ohci(card);
1470 struct pci_dev *dev = to_pci_dev(card->device);
1471 u32 lps;
1472 int i;
1473
1474 if (software_reset(ohci)) {
1475 fw_error("Failed to reset ohci card.\n");
1476 return -EBUSY;
1477 }
1478
1479 /*
1480 * Now enable LPS, which we need in order to start accessing
1481 * most of the registers. In fact, on some cards (ALI M5251),
1482 * accessing registers in the SClk domain without LPS enabled
1483 * will lock up the machine. Wait 50msec to make sure we have
1484 * full link enabled. However, with some cards (well, at least
1485 * a JMicron PCIe card), we have to try again sometimes.
1486 */
1487 reg_write(ohci, OHCI1394_HCControlSet,
1488 OHCI1394_HCControl_LPS |
1489 OHCI1394_HCControl_postedWriteEnable);
1490 flush_writes(ohci);
1491
1492 for (lps = 0, i = 0; !lps && i < 3; i++) {
1493 msleep(50);
1494 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1495 OHCI1394_HCControl_LPS;
1496 }
1497
1498 if (!lps) {
1499 fw_error("Failed to set Link Power Status\n");
1500 return -EIO;
1501 }
1502
1503 reg_write(ohci, OHCI1394_HCControlClear,
1504 OHCI1394_HCControl_noByteSwapData);
1505
1506 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1507 reg_write(ohci, OHCI1394_LinkControlClear,
1508 OHCI1394_LinkControl_rcvPhyPkt);
1509 reg_write(ohci, OHCI1394_LinkControlSet,
1510 OHCI1394_LinkControl_rcvSelfID |
1511 OHCI1394_LinkControl_cycleTimerEnable |
1512 OHCI1394_LinkControl_cycleMaster);
1513
1514 reg_write(ohci, OHCI1394_ATRetries,
1515 OHCI1394_MAX_AT_REQ_RETRIES |
1516 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1517 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1518
1519 ar_context_run(&ohci->ar_request_ctx);
1520 ar_context_run(&ohci->ar_response_ctx);
1521
1522 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1523 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1524 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1525 reg_write(ohci, OHCI1394_IntMaskSet,
1526 OHCI1394_selfIDComplete |
1527 OHCI1394_RQPkt | OHCI1394_RSPkt |
1528 OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1529 OHCI1394_isochRx | OHCI1394_isochTx |
1530 OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
1531 OHCI1394_cycle64Seconds | OHCI1394_regAccessFail |
1532 OHCI1394_masterIntEnable);
1533 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1534 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
1535
1536 /* Activate link_on bit and contender bit in our self ID packets.*/
1537 if (ohci_update_phy_reg(card, 4, 0,
1538 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1539 return -EIO;
1540
1541 /*
1542 * When the link is not yet enabled, the atomic config rom
1543 * update mechanism described below in ohci_set_config_rom()
1544 * is not active. We have to update ConfigRomHeader and
1545 * BusOptions manually, and the write to ConfigROMmap takes
1546 * effect immediately. We tie this to the enabling of the
1547 * link, so we have a valid config rom before enabling - the
1548 * OHCI requires that ConfigROMhdr and BusOptions have valid
1549 * values before enabling.
1550 *
1551 * However, when the ConfigROMmap is written, some controllers
1552 * always read back quadlets 0 and 2 from the config rom to
1553 * the ConfigRomHeader and BusOptions registers on bus reset.
1554 * They shouldn't do that in this initial case where the link
1555 * isn't enabled. This means we have to use the same
1556 * workaround here, setting the bus header to 0 and then write
1557 * the right values in the bus reset tasklet.
1558 */
1559
1560 if (config_rom) {
1561 ohci->next_config_rom =
1562 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1563 &ohci->next_config_rom_bus,
1564 GFP_KERNEL);
1565 if (ohci->next_config_rom == NULL)
1566 return -ENOMEM;
1567
1568 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1569 fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
1570 } else {
1571 /*
1572 * In the suspend case, config_rom is NULL, which
1573 * means that we just reuse the old config rom.
1574 */
1575 ohci->next_config_rom = ohci->config_rom;
1576 ohci->next_config_rom_bus = ohci->config_rom_bus;
1577 }
1578
1579 ohci->next_header = be32_to_cpu(ohci->next_config_rom[0]);
1580 ohci->next_config_rom[0] = 0;
1581 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1582 reg_write(ohci, OHCI1394_BusOptions,
1583 be32_to_cpu(ohci->next_config_rom[2]));
1584 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1585
1586 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1587
1588 if (request_irq(dev->irq, irq_handler,
1589 IRQF_SHARED, ohci_driver_name, ohci)) {
1590 fw_error("Failed to allocate shared interrupt %d.\n",
1591 dev->irq);
1592 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1593 ohci->config_rom, ohci->config_rom_bus);
1594 return -EIO;
1595 }
1596
1597 reg_write(ohci, OHCI1394_HCControlSet,
1598 OHCI1394_HCControl_linkEnable |
1599 OHCI1394_HCControl_BIBimageValid);
1600 flush_writes(ohci);
1601
1602 /*
1603 * We are ready to go, initiate bus reset to finish the
1604 * initialization.
1605 */
1606
1607 fw_core_initiate_bus_reset(&ohci->card, 1);
1608
1609 return 0;
1610 }
1611
1612 static int ohci_set_config_rom(struct fw_card *card,
1613 u32 *config_rom, size_t length)
1614 {
1615 struct fw_ohci *ohci;
1616 unsigned long flags;
1617 int ret = -EBUSY;
1618 __be32 *next_config_rom;
1619 dma_addr_t uninitialized_var(next_config_rom_bus);
1620
1621 ohci = fw_ohci(card);
1622
1623 /*
1624 * When the OHCI controller is enabled, the config rom update
1625 * mechanism is a bit tricky, but easy enough to use. See
1626 * section 5.5.6 in the OHCI specification.
1627 *
1628 * The OHCI controller caches the new config rom address in a
1629 * shadow register (ConfigROMmapNext) and needs a bus reset
1630 * for the changes to take place. When the bus reset is
1631 * detected, the controller loads the new values for the
1632 * ConfigRomHeader and BusOptions registers from the specified
1633 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1634 * shadow register. All automatically and atomically.
1635 *
1636 * Now, there's a twist to this story. The automatic load of
1637 * ConfigRomHeader and BusOptions doesn't honor the
1638 * noByteSwapData bit, so with a be32 config rom, the
1639 * controller will load be32 values in to these registers
1640 * during the atomic update, even on litte endian
1641 * architectures. The workaround we use is to put a 0 in the
1642 * header quadlet; 0 is endian agnostic and means that the
1643 * config rom isn't ready yet. In the bus reset tasklet we
1644 * then set up the real values for the two registers.
1645 *
1646 * We use ohci->lock to avoid racing with the code that sets
1647 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1648 */
1649
1650 next_config_rom =
1651 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1652 &next_config_rom_bus, GFP_KERNEL);
1653 if (next_config_rom == NULL)
1654 return -ENOMEM;
1655
1656 spin_lock_irqsave(&ohci->lock, flags);
1657
1658 if (ohci->next_config_rom == NULL) {
1659 ohci->next_config_rom = next_config_rom;
1660 ohci->next_config_rom_bus = next_config_rom_bus;
1661
1662 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1663 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
1664 length * 4);
1665
1666 ohci->next_header = config_rom[0];
1667 ohci->next_config_rom[0] = 0;
1668
1669 reg_write(ohci, OHCI1394_ConfigROMmap,
1670 ohci->next_config_rom_bus);
1671 ret = 0;
1672 }
1673
1674 spin_unlock_irqrestore(&ohci->lock, flags);
1675
1676 /*
1677 * Now initiate a bus reset to have the changes take
1678 * effect. We clean up the old config rom memory and DMA
1679 * mappings in the bus reset tasklet, since the OHCI
1680 * controller could need to access it before the bus reset
1681 * takes effect.
1682 */
1683 if (ret == 0)
1684 fw_core_initiate_bus_reset(&ohci->card, 1);
1685 else
1686 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1687 next_config_rom, next_config_rom_bus);
1688
1689 return ret;
1690 }
1691
1692 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1693 {
1694 struct fw_ohci *ohci = fw_ohci(card);
1695
1696 at_context_transmit(&ohci->at_request_ctx, packet);
1697 }
1698
1699 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1700 {
1701 struct fw_ohci *ohci = fw_ohci(card);
1702
1703 at_context_transmit(&ohci->at_response_ctx, packet);
1704 }
1705
1706 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1707 {
1708 struct fw_ohci *ohci = fw_ohci(card);
1709 struct context *ctx = &ohci->at_request_ctx;
1710 struct driver_data *driver_data = packet->driver_data;
1711 int ret = -ENOENT;
1712
1713 tasklet_disable(&ctx->tasklet);
1714
1715 if (packet->ack != 0)
1716 goto out;
1717
1718 if (packet->payload_bus)
1719 dma_unmap_single(ohci->card.device, packet->payload_bus,
1720 packet->payload_length, DMA_TO_DEVICE);
1721
1722 log_ar_at_event('T', packet->speed, packet->header, 0x20);
1723 driver_data->packet = NULL;
1724 packet->ack = RCODE_CANCELLED;
1725 packet->callback(packet, &ohci->card, packet->ack);
1726 ret = 0;
1727 out:
1728 tasklet_enable(&ctx->tasklet);
1729
1730 return ret;
1731 }
1732
1733 static int ohci_enable_phys_dma(struct fw_card *card,
1734 int node_id, int generation)
1735 {
1736 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1737 return 0;
1738 #else
1739 struct fw_ohci *ohci = fw_ohci(card);
1740 unsigned long flags;
1741 int n, ret = 0;
1742
1743 /*
1744 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1745 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1746 */
1747
1748 spin_lock_irqsave(&ohci->lock, flags);
1749
1750 if (ohci->generation != generation) {
1751 ret = -ESTALE;
1752 goto out;
1753 }
1754
1755 /*
1756 * Note, if the node ID contains a non-local bus ID, physical DMA is
1757 * enabled for _all_ nodes on remote buses.
1758 */
1759
1760 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1761 if (n < 32)
1762 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1763 else
1764 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1765
1766 flush_writes(ohci);
1767 out:
1768 spin_unlock_irqrestore(&ohci->lock, flags);
1769
1770 return ret;
1771 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1772 }
1773
1774 static u64 ohci_get_bus_time(struct fw_card *card)
1775 {
1776 struct fw_ohci *ohci = fw_ohci(card);
1777 u32 cycle_time;
1778 u64 bus_time;
1779
1780 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1781 bus_time = ((u64)atomic_read(&ohci->bus_seconds) << 32) | cycle_time;
1782
1783 return bus_time;
1784 }
1785
1786 static void copy_iso_headers(struct iso_context *ctx, void *p)
1787 {
1788 int i = ctx->header_length;
1789
1790 if (i + ctx->base.header_size > PAGE_SIZE)
1791 return;
1792
1793 /*
1794 * The iso header is byteswapped to little endian by
1795 * the controller, but the remaining header quadlets
1796 * are big endian. We want to present all the headers
1797 * as big endian, so we have to swap the first quadlet.
1798 */
1799 if (ctx->base.header_size > 0)
1800 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1801 if (ctx->base.header_size > 4)
1802 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
1803 if (ctx->base.header_size > 8)
1804 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
1805 ctx->header_length += ctx->base.header_size;
1806 }
1807
1808 static int handle_ir_dualbuffer_packet(struct context *context,
1809 struct descriptor *d,
1810 struct descriptor *last)
1811 {
1812 struct iso_context *ctx =
1813 container_of(context, struct iso_context, context);
1814 struct db_descriptor *db = (struct db_descriptor *) d;
1815 __le32 *ir_header;
1816 size_t header_length;
1817 void *p, *end;
1818
1819 if (db->first_res_count != 0 && db->second_res_count != 0) {
1820 if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) {
1821 /* This descriptor isn't done yet, stop iteration. */
1822 return 0;
1823 }
1824 ctx->excess_bytes -= le16_to_cpu(db->second_req_count);
1825 }
1826
1827 header_length = le16_to_cpu(db->first_req_count) -
1828 le16_to_cpu(db->first_res_count);
1829
1830 p = db + 1;
1831 end = p + header_length;
1832 while (p < end) {
1833 copy_iso_headers(ctx, p);
1834 ctx->excess_bytes +=
1835 (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff;
1836 p += max(ctx->base.header_size, (size_t)8);
1837 }
1838
1839 ctx->excess_bytes -= le16_to_cpu(db->second_req_count) -
1840 le16_to_cpu(db->second_res_count);
1841
1842 if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
1843 ir_header = (__le32 *) (db + 1);
1844 ctx->base.callback(&ctx->base,
1845 le32_to_cpu(ir_header[0]) & 0xffff,
1846 ctx->header_length, ctx->header,
1847 ctx->base.callback_data);
1848 ctx->header_length = 0;
1849 }
1850
1851 return 1;
1852 }
1853
1854 static int handle_ir_packet_per_buffer(struct context *context,
1855 struct descriptor *d,
1856 struct descriptor *last)
1857 {
1858 struct iso_context *ctx =
1859 container_of(context, struct iso_context, context);
1860 struct descriptor *pd;
1861 __le32 *ir_header;
1862 void *p;
1863
1864 for (pd = d; pd <= last; pd++) {
1865 if (pd->transfer_status)
1866 break;
1867 }
1868 if (pd > last)
1869 /* Descriptor(s) not done yet, stop iteration */
1870 return 0;
1871
1872 p = last + 1;
1873 copy_iso_headers(ctx, p);
1874
1875 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1876 ir_header = (__le32 *) p;
1877 ctx->base.callback(&ctx->base,
1878 le32_to_cpu(ir_header[0]) & 0xffff,
1879 ctx->header_length, ctx->header,
1880 ctx->base.callback_data);
1881 ctx->header_length = 0;
1882 }
1883
1884 return 1;
1885 }
1886
1887 static int handle_it_packet(struct context *context,
1888 struct descriptor *d,
1889 struct descriptor *last)
1890 {
1891 struct iso_context *ctx =
1892 container_of(context, struct iso_context, context);
1893
1894 if (last->transfer_status == 0)
1895 /* This descriptor isn't done yet, stop iteration. */
1896 return 0;
1897
1898 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
1899 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1900 0, NULL, ctx->base.callback_data);
1901
1902 return 1;
1903 }
1904
1905 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
1906 int type, int channel, size_t header_size)
1907 {
1908 struct fw_ohci *ohci = fw_ohci(card);
1909 struct iso_context *ctx, *list;
1910 descriptor_callback_t callback;
1911 u64 *channels, dont_care = ~0ULL;
1912 u32 *mask, regs;
1913 unsigned long flags;
1914 int index, ret = -ENOMEM;
1915
1916 if (type == FW_ISO_CONTEXT_TRANSMIT) {
1917 channels = &dont_care;
1918 mask = &ohci->it_context_mask;
1919 list = ohci->it_context_list;
1920 callback = handle_it_packet;
1921 } else {
1922 channels = &ohci->ir_context_channels;
1923 mask = &ohci->ir_context_mask;
1924 list = ohci->ir_context_list;
1925 if (ohci->use_dualbuffer)
1926 callback = handle_ir_dualbuffer_packet;
1927 else
1928 callback = handle_ir_packet_per_buffer;
1929 }
1930
1931 spin_lock_irqsave(&ohci->lock, flags);
1932 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
1933 if (index >= 0) {
1934 *channels &= ~(1ULL << channel);
1935 *mask &= ~(1 << index);
1936 }
1937 spin_unlock_irqrestore(&ohci->lock, flags);
1938
1939 if (index < 0)
1940 return ERR_PTR(-EBUSY);
1941
1942 if (type == FW_ISO_CONTEXT_TRANSMIT)
1943 regs = OHCI1394_IsoXmitContextBase(index);
1944 else
1945 regs = OHCI1394_IsoRcvContextBase(index);
1946
1947 ctx = &list[index];
1948 memset(ctx, 0, sizeof(*ctx));
1949 ctx->header_length = 0;
1950 ctx->header = (void *) __get_free_page(GFP_KERNEL);
1951 if (ctx->header == NULL)
1952 goto out;
1953
1954 ret = context_init(&ctx->context, ohci, regs, callback);
1955 if (ret < 0)
1956 goto out_with_header;
1957
1958 return &ctx->base;
1959
1960 out_with_header:
1961 free_page((unsigned long)ctx->header);
1962 out:
1963 spin_lock_irqsave(&ohci->lock, flags);
1964 *mask |= 1 << index;
1965 spin_unlock_irqrestore(&ohci->lock, flags);
1966
1967 return ERR_PTR(ret);
1968 }
1969
1970 static int ohci_start_iso(struct fw_iso_context *base,
1971 s32 cycle, u32 sync, u32 tags)
1972 {
1973 struct iso_context *ctx = container_of(base, struct iso_context, base);
1974 struct fw_ohci *ohci = ctx->context.ohci;
1975 u32 control, match;
1976 int index;
1977
1978 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1979 index = ctx - ohci->it_context_list;
1980 match = 0;
1981 if (cycle >= 0)
1982 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
1983 (cycle & 0x7fff) << 16;
1984
1985 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
1986 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
1987 context_run(&ctx->context, match);
1988 } else {
1989 index = ctx - ohci->ir_context_list;
1990 control = IR_CONTEXT_ISOCH_HEADER;
1991 if (ohci->use_dualbuffer)
1992 control |= IR_CONTEXT_DUAL_BUFFER_MODE;
1993 match = (tags << 28) | (sync << 8) | ctx->base.channel;
1994 if (cycle >= 0) {
1995 match |= (cycle & 0x07fff) << 12;
1996 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
1997 }
1998
1999 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2000 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2001 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2002 context_run(&ctx->context, control);
2003 }
2004
2005 return 0;
2006 }
2007
2008 static int ohci_stop_iso(struct fw_iso_context *base)
2009 {
2010 struct fw_ohci *ohci = fw_ohci(base->card);
2011 struct iso_context *ctx = container_of(base, struct iso_context, base);
2012 int index;
2013
2014 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2015 index = ctx - ohci->it_context_list;
2016 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2017 } else {
2018 index = ctx - ohci->ir_context_list;
2019 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2020 }
2021 flush_writes(ohci);
2022 context_stop(&ctx->context);
2023
2024 return 0;
2025 }
2026
2027 static void ohci_free_iso_context(struct fw_iso_context *base)
2028 {
2029 struct fw_ohci *ohci = fw_ohci(base->card);
2030 struct iso_context *ctx = container_of(base, struct iso_context, base);
2031 unsigned long flags;
2032 int index;
2033
2034 ohci_stop_iso(base);
2035 context_release(&ctx->context);
2036 free_page((unsigned long)ctx->header);
2037
2038 spin_lock_irqsave(&ohci->lock, flags);
2039
2040 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2041 index = ctx - ohci->it_context_list;
2042 ohci->it_context_mask |= 1 << index;
2043 } else {
2044 index = ctx - ohci->ir_context_list;
2045 ohci->ir_context_mask |= 1 << index;
2046 ohci->ir_context_channels |= 1ULL << base->channel;
2047 }
2048
2049 spin_unlock_irqrestore(&ohci->lock, flags);
2050 }
2051
2052 static int ohci_queue_iso_transmit(struct fw_iso_context *base,
2053 struct fw_iso_packet *packet,
2054 struct fw_iso_buffer *buffer,
2055 unsigned long payload)
2056 {
2057 struct iso_context *ctx = container_of(base, struct iso_context, base);
2058 struct descriptor *d, *last, *pd;
2059 struct fw_iso_packet *p;
2060 __le32 *header;
2061 dma_addr_t d_bus, page_bus;
2062 u32 z, header_z, payload_z, irq;
2063 u32 payload_index, payload_end_index, next_page_index;
2064 int page, end_page, i, length, offset;
2065
2066 /*
2067 * FIXME: Cycle lost behavior should be configurable: lose
2068 * packet, retransmit or terminate..
2069 */
2070
2071 p = packet;
2072 payload_index = payload;
2073
2074 if (p->skip)
2075 z = 1;
2076 else
2077 z = 2;
2078 if (p->header_length > 0)
2079 z++;
2080
2081 /* Determine the first page the payload isn't contained in. */
2082 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2083 if (p->payload_length > 0)
2084 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2085 else
2086 payload_z = 0;
2087
2088 z += payload_z;
2089
2090 /* Get header size in number of descriptors. */
2091 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2092
2093 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2094 if (d == NULL)
2095 return -ENOMEM;
2096
2097 if (!p->skip) {
2098 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2099 d[0].req_count = cpu_to_le16(8);
2100
2101 header = (__le32 *) &d[1];
2102 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2103 IT_HEADER_TAG(p->tag) |
2104 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2105 IT_HEADER_CHANNEL(ctx->base.channel) |
2106 IT_HEADER_SPEED(ctx->base.speed));
2107 header[1] =
2108 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2109 p->payload_length));
2110 }
2111
2112 if (p->header_length > 0) {
2113 d[2].req_count = cpu_to_le16(p->header_length);
2114 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2115 memcpy(&d[z], p->header, p->header_length);
2116 }
2117
2118 pd = d + z - payload_z;
2119 payload_end_index = payload_index + p->payload_length;
2120 for (i = 0; i < payload_z; i++) {
2121 page = payload_index >> PAGE_SHIFT;
2122 offset = payload_index & ~PAGE_MASK;
2123 next_page_index = (page + 1) << PAGE_SHIFT;
2124 length =
2125 min(next_page_index, payload_end_index) - payload_index;
2126 pd[i].req_count = cpu_to_le16(length);
2127
2128 page_bus = page_private(buffer->pages[page]);
2129 pd[i].data_address = cpu_to_le32(page_bus + offset);
2130
2131 payload_index += length;
2132 }
2133
2134 if (p->interrupt)
2135 irq = DESCRIPTOR_IRQ_ALWAYS;
2136 else
2137 irq = DESCRIPTOR_NO_IRQ;
2138
2139 last = z == 2 ? d : d + z - 1;
2140 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2141 DESCRIPTOR_STATUS |
2142 DESCRIPTOR_BRANCH_ALWAYS |
2143 irq);
2144
2145 context_append(&ctx->context, d, z, header_z);
2146
2147 return 0;
2148 }
2149
2150 static int ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
2151 struct fw_iso_packet *packet,
2152 struct fw_iso_buffer *buffer,
2153 unsigned long payload)
2154 {
2155 struct iso_context *ctx = container_of(base, struct iso_context, base);
2156 struct db_descriptor *db = NULL;
2157 struct descriptor *d;
2158 struct fw_iso_packet *p;
2159 dma_addr_t d_bus, page_bus;
2160 u32 z, header_z, length, rest;
2161 int page, offset, packet_count, header_size;
2162
2163 /*
2164 * FIXME: Cycle lost behavior should be configurable: lose
2165 * packet, retransmit or terminate..
2166 */
2167
2168 p = packet;
2169 z = 2;
2170
2171 /*
2172 * The OHCI controller puts the isochronous header and trailer in the
2173 * buffer, so we need at least 8 bytes.
2174 */
2175 packet_count = p->header_length / ctx->base.header_size;
2176 header_size = packet_count * max(ctx->base.header_size, (size_t)8);
2177
2178 /* Get header size in number of descriptors. */
2179 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2180 page = payload >> PAGE_SHIFT;
2181 offset = payload & ~PAGE_MASK;
2182 rest = p->payload_length;
2183
2184 /* FIXME: make packet-per-buffer/dual-buffer a context option */
2185 while (rest > 0) {
2186 d = context_get_descriptors(&ctx->context,
2187 z + header_z, &d_bus);
2188 if (d == NULL)
2189 return -ENOMEM;
2190
2191 db = (struct db_descriptor *) d;
2192 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
2193 DESCRIPTOR_BRANCH_ALWAYS);
2194 db->first_size =
2195 cpu_to_le16(max(ctx->base.header_size, (size_t)8));
2196 if (p->skip && rest == p->payload_length) {
2197 db->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2198 db->first_req_count = db->first_size;
2199 } else {
2200 db->first_req_count = cpu_to_le16(header_size);
2201 }
2202 db->first_res_count = db->first_req_count;
2203 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
2204
2205 if (p->skip && rest == p->payload_length)
2206 length = 4;
2207 else if (offset + rest < PAGE_SIZE)
2208 length = rest;
2209 else
2210 length = PAGE_SIZE - offset;
2211
2212 db->second_req_count = cpu_to_le16(length);
2213 db->second_res_count = db->second_req_count;
2214 page_bus = page_private(buffer->pages[page]);
2215 db->second_buffer = cpu_to_le32(page_bus + offset);
2216
2217 if (p->interrupt && length == rest)
2218 db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2219
2220 context_append(&ctx->context, d, z, header_z);
2221 offset = (offset + length) & ~PAGE_MASK;
2222 rest -= length;
2223 if (offset == 0)
2224 page++;
2225 }
2226
2227 return 0;
2228 }
2229
2230 static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2231 struct fw_iso_packet *packet,
2232 struct fw_iso_buffer *buffer,
2233 unsigned long payload)
2234 {
2235 struct iso_context *ctx = container_of(base, struct iso_context, base);
2236 struct descriptor *d = NULL, *pd = NULL;
2237 struct fw_iso_packet *p = packet;
2238 dma_addr_t d_bus, page_bus;
2239 u32 z, header_z, rest;
2240 int i, j, length;
2241 int page, offset, packet_count, header_size, payload_per_buffer;
2242
2243 /*
2244 * The OHCI controller puts the isochronous header and trailer in the
2245 * buffer, so we need at least 8 bytes.
2246 */
2247 packet_count = p->header_length / ctx->base.header_size;
2248 header_size = max(ctx->base.header_size, (size_t)8);
2249
2250 /* Get header size in number of descriptors. */
2251 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2252 page = payload >> PAGE_SHIFT;
2253 offset = payload & ~PAGE_MASK;
2254 payload_per_buffer = p->payload_length / packet_count;
2255
2256 for (i = 0; i < packet_count; i++) {
2257 /* d points to the header descriptor */
2258 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2259 d = context_get_descriptors(&ctx->context,
2260 z + header_z, &d_bus);
2261 if (d == NULL)
2262 return -ENOMEM;
2263
2264 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2265 DESCRIPTOR_INPUT_MORE);
2266 if (p->skip && i == 0)
2267 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2268 d->req_count = cpu_to_le16(header_size);
2269 d->res_count = d->req_count;
2270 d->transfer_status = 0;
2271 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2272
2273 rest = payload_per_buffer;
2274 for (j = 1; j < z; j++) {
2275 pd = d + j;
2276 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2277 DESCRIPTOR_INPUT_MORE);
2278
2279 if (offset + rest < PAGE_SIZE)
2280 length = rest;
2281 else
2282 length = PAGE_SIZE - offset;
2283 pd->req_count = cpu_to_le16(length);
2284 pd->res_count = pd->req_count;
2285 pd->transfer_status = 0;
2286
2287 page_bus = page_private(buffer->pages[page]);
2288 pd->data_address = cpu_to_le32(page_bus + offset);
2289
2290 offset = (offset + length) & ~PAGE_MASK;
2291 rest -= length;
2292 if (offset == 0)
2293 page++;
2294 }
2295 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2296 DESCRIPTOR_INPUT_LAST |
2297 DESCRIPTOR_BRANCH_ALWAYS);
2298 if (p->interrupt && i == packet_count - 1)
2299 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2300
2301 context_append(&ctx->context, d, z, header_z);
2302 }
2303
2304 return 0;
2305 }
2306
2307 static int ohci_queue_iso(struct fw_iso_context *base,
2308 struct fw_iso_packet *packet,
2309 struct fw_iso_buffer *buffer,
2310 unsigned long payload)
2311 {
2312 struct iso_context *ctx = container_of(base, struct iso_context, base);
2313 unsigned long flags;
2314 int ret;
2315
2316 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2317 if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2318 ret = ohci_queue_iso_transmit(base, packet, buffer, payload);
2319 else if (ctx->context.ohci->use_dualbuffer)
2320 ret = ohci_queue_iso_receive_dualbuffer(base, packet,
2321 buffer, payload);
2322 else
2323 ret = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2324 buffer, payload);
2325 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2326
2327 return ret;
2328 }
2329
2330 static const struct fw_card_driver ohci_driver = {
2331 .enable = ohci_enable,
2332 .update_phy_reg = ohci_update_phy_reg,
2333 .set_config_rom = ohci_set_config_rom,
2334 .send_request = ohci_send_request,
2335 .send_response = ohci_send_response,
2336 .cancel_packet = ohci_cancel_packet,
2337 .enable_phys_dma = ohci_enable_phys_dma,
2338 .get_bus_time = ohci_get_bus_time,
2339
2340 .allocate_iso_context = ohci_allocate_iso_context,
2341 .free_iso_context = ohci_free_iso_context,
2342 .queue_iso = ohci_queue_iso,
2343 .start_iso = ohci_start_iso,
2344 .stop_iso = ohci_stop_iso,
2345 };
2346
2347 #ifdef CONFIG_PPC_PMAC
2348 static void ohci_pmac_on(struct pci_dev *dev)
2349 {
2350 if (machine_is(powermac)) {
2351 struct device_node *ofn = pci_device_to_OF_node(dev);
2352
2353 if (ofn) {
2354 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2355 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2356 }
2357 }
2358 }
2359
2360 static void ohci_pmac_off(struct pci_dev *dev)
2361 {
2362 if (machine_is(powermac)) {
2363 struct device_node *ofn = pci_device_to_OF_node(dev);
2364
2365 if (ofn) {
2366 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2367 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2368 }
2369 }
2370 }
2371 #else
2372 #define ohci_pmac_on(dev)
2373 #define ohci_pmac_off(dev)
2374 #endif /* CONFIG_PPC_PMAC */
2375
2376 #define PCI_VENDOR_ID_AGERE PCI_VENDOR_ID_ATT
2377 #define PCI_DEVICE_ID_AGERE_FW643 0x5901
2378
2379 static int __devinit pci_probe(struct pci_dev *dev,
2380 const struct pci_device_id *ent)
2381 {
2382 struct fw_ohci *ohci;
2383 u32 bus_options, max_receive, link_speed, version;
2384 u64 guid;
2385 int err;
2386 size_t size;
2387
2388 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2389 if (ohci == NULL) {
2390 err = -ENOMEM;
2391 goto fail;
2392 }
2393
2394 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2395
2396 ohci_pmac_on(dev);
2397
2398 err = pci_enable_device(dev);
2399 if (err) {
2400 fw_error("Failed to enable OHCI hardware\n");
2401 goto fail_free;
2402 }
2403
2404 pci_set_master(dev);
2405 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2406 pci_set_drvdata(dev, ohci);
2407
2408 spin_lock_init(&ohci->lock);
2409
2410 tasklet_init(&ohci->bus_reset_tasklet,
2411 bus_reset_tasklet, (unsigned long)ohci);
2412
2413 err = pci_request_region(dev, 0, ohci_driver_name);
2414 if (err) {
2415 fw_error("MMIO resource unavailable\n");
2416 goto fail_disable;
2417 }
2418
2419 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2420 if (ohci->registers == NULL) {
2421 fw_error("Failed to remap registers\n");
2422 err = -ENXIO;
2423 goto fail_iomem;
2424 }
2425
2426 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2427 ohci->use_dualbuffer = version >= OHCI_VERSION_1_1;
2428
2429 /* dual-buffer mode is broken if more than one IR context is active */
2430 if (dev->vendor == PCI_VENDOR_ID_AGERE &&
2431 dev->device == PCI_DEVICE_ID_AGERE_FW643)
2432 ohci->use_dualbuffer = false;
2433
2434 /* x86-32 currently doesn't use highmem for dma_alloc_coherent */
2435 #if !defined(CONFIG_X86_32)
2436 /* dual-buffer mode is broken with descriptor addresses above 2G */
2437 if (dev->vendor == PCI_VENDOR_ID_TI &&
2438 dev->device == PCI_DEVICE_ID_TI_TSB43AB22)
2439 ohci->use_dualbuffer = false;
2440 #endif
2441
2442 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
2443 ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE &&
2444 dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW;
2445 #endif
2446 ohci->bus_reset_packet_quirk = dev->vendor == PCI_VENDOR_ID_TI;
2447
2448 ar_context_init(&ohci->ar_request_ctx, ohci,
2449 OHCI1394_AsReqRcvContextControlSet);
2450
2451 ar_context_init(&ohci->ar_response_ctx, ohci,
2452 OHCI1394_AsRspRcvContextControlSet);
2453
2454 context_init(&ohci->at_request_ctx, ohci,
2455 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2456
2457 context_init(&ohci->at_response_ctx, ohci,
2458 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2459
2460 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2461 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2462 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2463 size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
2464 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2465
2466 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2467 ohci->ir_context_channels = ~0ULL;
2468 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2469 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2470 size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
2471 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2472
2473 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2474 err = -ENOMEM;
2475 goto fail_contexts;
2476 }
2477
2478 /* self-id dma buffer allocation */
2479 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2480 SELF_ID_BUF_SIZE,
2481 &ohci->self_id_bus,
2482 GFP_KERNEL);
2483 if (ohci->self_id_cpu == NULL) {
2484 err = -ENOMEM;
2485 goto fail_contexts;
2486 }
2487
2488 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2489 max_receive = (bus_options >> 12) & 0xf;
2490 link_speed = bus_options & 0x7;
2491 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2492 reg_read(ohci, OHCI1394_GUIDLo);
2493
2494 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2495 if (err)
2496 goto fail_self_id;
2497
2498 fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
2499 dev_name(&dev->dev), version >> 16, version & 0xff);
2500
2501 return 0;
2502
2503 fail_self_id:
2504 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2505 ohci->self_id_cpu, ohci->self_id_bus);
2506 fail_contexts:
2507 kfree(ohci->ir_context_list);
2508 kfree(ohci->it_context_list);
2509 context_release(&ohci->at_response_ctx);
2510 context_release(&ohci->at_request_ctx);
2511 ar_context_release(&ohci->ar_response_ctx);
2512 ar_context_release(&ohci->ar_request_ctx);
2513 pci_iounmap(dev, ohci->registers);
2514 fail_iomem:
2515 pci_release_region(dev, 0);
2516 fail_disable:
2517 pci_disable_device(dev);
2518 fail_free:
2519 kfree(&ohci->card);
2520 ohci_pmac_off(dev);
2521 fail:
2522 if (err == -ENOMEM)
2523 fw_error("Out of memory\n");
2524
2525 return err;
2526 }
2527
2528 static void pci_remove(struct pci_dev *dev)
2529 {
2530 struct fw_ohci *ohci;
2531
2532 ohci = pci_get_drvdata(dev);
2533 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2534 flush_writes(ohci);
2535 fw_core_remove_card(&ohci->card);
2536
2537 /*
2538 * FIXME: Fail all pending packets here, now that the upper
2539 * layers can't queue any more.
2540 */
2541
2542 software_reset(ohci);
2543 free_irq(dev->irq, ohci);
2544
2545 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
2546 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2547 ohci->next_config_rom, ohci->next_config_rom_bus);
2548 if (ohci->config_rom)
2549 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2550 ohci->config_rom, ohci->config_rom_bus);
2551 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2552 ohci->self_id_cpu, ohci->self_id_bus);
2553 ar_context_release(&ohci->ar_request_ctx);
2554 ar_context_release(&ohci->ar_response_ctx);
2555 context_release(&ohci->at_request_ctx);
2556 context_release(&ohci->at_response_ctx);
2557 kfree(ohci->it_context_list);
2558 kfree(ohci->ir_context_list);
2559 pci_iounmap(dev, ohci->registers);
2560 pci_release_region(dev, 0);
2561 pci_disable_device(dev);
2562 kfree(&ohci->card);
2563 ohci_pmac_off(dev);
2564
2565 fw_notify("Removed fw-ohci device.\n");
2566 }
2567
2568 #ifdef CONFIG_PM
2569 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2570 {
2571 struct fw_ohci *ohci = pci_get_drvdata(dev);
2572 int err;
2573
2574 software_reset(ohci);
2575 free_irq(dev->irq, ohci);
2576 err = pci_save_state(dev);
2577 if (err) {
2578 fw_error("pci_save_state failed\n");
2579 return err;
2580 }
2581 err = pci_set_power_state(dev, pci_choose_state(dev, state));
2582 if (err)
2583 fw_error("pci_set_power_state failed with %d\n", err);
2584 ohci_pmac_off(dev);
2585
2586 return 0;
2587 }
2588
2589 static int pci_resume(struct pci_dev *dev)
2590 {
2591 struct fw_ohci *ohci = pci_get_drvdata(dev);
2592 int err;
2593
2594 ohci_pmac_on(dev);
2595 pci_set_power_state(dev, PCI_D0);
2596 pci_restore_state(dev);
2597 err = pci_enable_device(dev);
2598 if (err) {
2599 fw_error("pci_enable_device failed\n");
2600 return err;
2601 }
2602
2603 return ohci_enable(&ohci->card, NULL, 0);
2604 }
2605 #endif
2606
2607 static struct pci_device_id pci_table[] = {
2608 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2609 { }
2610 };
2611
2612 MODULE_DEVICE_TABLE(pci, pci_table);
2613
2614 static struct pci_driver fw_ohci_pci_driver = {
2615 .name = ohci_driver_name,
2616 .id_table = pci_table,
2617 .probe = pci_probe,
2618 .remove = pci_remove,
2619 #ifdef CONFIG_PM
2620 .resume = pci_resume,
2621 .suspend = pci_suspend,
2622 #endif
2623 };
2624
2625 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2626 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2627 MODULE_LICENSE("GPL");
2628
2629 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2630 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2631 MODULE_ALIAS("ohci1394");
2632 #endif
2633
2634 static int __init fw_ohci_init(void)
2635 {
2636 return pci_register_driver(&fw_ohci_pci_driver);
2637 }
2638
2639 static void __exit fw_ohci_cleanup(void)
2640 {
2641 pci_unregister_driver(&fw_ohci_pci_driver);
2642 }
2643
2644 module_init(fw_ohci_init);
2645 module_exit(fw_ohci_cleanup);
Support for the Chinese Samsung S3C2440 based development boards