2 * Firmware replacement code.
4 * Work around broken BIOSes that don't set an aperture or only set the
5 * aperture in the AGP bridge.
6 * If all fails map the aperture over some low memory. This is cheaper than
7 * doing bounce buffering. The memory is lost. This is done at early boot
8 * because only the bootmem allocator can allocate 32+MB.
10 * Copyright 2002 Andi Kleen, SuSE Labs.
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/init.h>
15 #include <linux/bootmem.h>
16 #include <linux/mmzone.h>
17 #include <linux/pci_ids.h>
18 #include <linux/pci.h>
19 #include <linux/bitops.h>
20 #include <linux/ioport.h>
21 #include <linux/suspend.h>
25 #include <asm/pci-direct.h>
29 int gart_iommu_aperture
;
30 int gart_iommu_aperture_disabled __initdata
;
31 int gart_iommu_aperture_allowed __initdata
;
33 int fallback_aper_order __initdata
= 1; /* 64MB */
34 int fallback_aper_force __initdata
;
36 int fix_aperture __initdata
= 1;
38 struct bus_dev_range
{
44 static struct bus_dev_range bus_dev_ranges
[] __initdata
= {
50 static struct resource gart_resource
= {
52 .flags
= IORESOURCE_MEM
,
55 static void __init
insert_aperture_resource(u32 aper_base
, u32 aper_size
)
57 gart_resource
.start
= aper_base
;
58 gart_resource
.end
= aper_base
+ aper_size
- 1;
59 insert_resource(&iomem_resource
, &gart_resource
);
62 /* This code runs before the PCI subsystem is initialized, so just
63 access the northbridge directly. */
65 static u32 __init
allocate_aperture(void)
70 /* aper_size should <= 1G */
71 if (fallback_aper_order
> 5)
72 fallback_aper_order
= 5;
73 aper_size
= (32 * 1024 * 1024) << fallback_aper_order
;
76 * Aperture has to be naturally aligned. This means a 2GB aperture
77 * won't have much chance of finding a place in the lower 4GB of
78 * memory. Unfortunately we cannot move it up because that would
79 * make the IOMMU useless.
82 * using 512M as goal, in case kexec will load kernel_big
83 * that will do the on position decompress, and could overlap with
84 * that positon with gart that is used.
87 * ==> kexec (with kdump trigger path or previous doesn't shutdown gart)
88 * ==> kernel_small(gart area become e820_reserved)
89 * ==> kexec (with kdump trigger path or previous doesn't shutdown gart)
90 * ==> kerne_big (uncompressed size will be big than 64M or 128M)
91 * so don't use 512M below as gart iommu, leave the space for kernel
94 p
= __alloc_bootmem_nopanic(aper_size
, aper_size
, 512ULL<<20);
95 if (!p
|| __pa(p
)+aper_size
> 0xffffffff) {
97 "Cannot allocate aperture memory hole (%p,%uK)\n",
100 free_bootmem(__pa(p
), aper_size
);
103 printk(KERN_INFO
"Mapping aperture over %d KB of RAM @ %lx\n",
104 aper_size
>> 10, __pa(p
));
105 insert_aperture_resource((u32
)__pa(p
), aper_size
);
106 register_nosave_region((u32
)__pa(p
) >> PAGE_SHIFT
,
107 (u32
)__pa(p
+aper_size
) >> PAGE_SHIFT
);
113 /* Find a PCI capability */
114 static u32 __init
find_cap(int bus
, int slot
, int func
, int cap
)
119 if (!(read_pci_config_16(bus
, slot
, func
, PCI_STATUS
) &
120 PCI_STATUS_CAP_LIST
))
123 pos
= read_pci_config_byte(bus
, slot
, func
, PCI_CAPABILITY_LIST
);
124 for (bytes
= 0; bytes
< 48 && pos
>= 0x40; bytes
++) {
128 id
= read_pci_config_byte(bus
, slot
, func
, pos
+PCI_CAP_LIST_ID
);
133 pos
= read_pci_config_byte(bus
, slot
, func
,
134 pos
+PCI_CAP_LIST_NEXT
);
139 /* Read a standard AGPv3 bridge header */
140 static u32 __init
read_agp(int bus
, int slot
, int func
, int cap
, u32
*order
)
145 u32 aper_low
, aper_hi
;
149 printk(KERN_INFO
"AGP bridge at %02x:%02x:%02x\n", bus
, slot
, func
);
150 apsizereg
= read_pci_config_16(bus
, slot
, func
, cap
+ 0x14);
151 if (apsizereg
== 0xffffffff) {
152 printk(KERN_ERR
"APSIZE in AGP bridge unreadable\n");
156 /* old_order could be the value from NB gart setting */
159 apsize
= apsizereg
& 0xfff;
160 /* Some BIOS use weird encodings not in the AGPv3 table. */
163 nbits
= hweight16(apsize
);
165 if ((int)*order
< 0) /* < 32MB */
168 aper_low
= read_pci_config(bus
, slot
, func
, 0x10);
169 aper_hi
= read_pci_config(bus
, slot
, func
, 0x14);
170 aper
= (aper_low
& ~((1<<22)-1)) | ((u64
)aper_hi
<< 32);
173 * On some sick chips, APSIZE is 0. It means it wants 4G
174 * so let double check that order, and lets trust AMD NB settings:
176 printk(KERN_INFO
"Aperture from AGP @ %Lx old size %u MB\n",
177 aper
, 32 << old_order
);
178 if (aper
+ (32ULL<<(20 + *order
)) > 0x100000000ULL
) {
179 printk(KERN_INFO
"Aperture size %u MB (APSIZE %x) is not right, using settings from NB\n",
180 32 << *order
, apsizereg
);
184 printk(KERN_INFO
"Aperture from AGP @ %Lx size %u MB (APSIZE %x)\n",
185 aper
, 32 << *order
, apsizereg
);
187 if (!aperture_valid(aper
, (32*1024*1024) << *order
, 32<<20))
193 * Look for an AGP bridge. Windows only expects the aperture in the
194 * AGP bridge and some BIOS forget to initialize the Northbridge too.
195 * Work around this here.
197 * Do an PCI bus scan by hand because we're running before the PCI
200 * All K8 AGP bridges are AGPv3 compliant, so we can do this scan
201 * generically. It's probably overkill to always scan all slots because
202 * the AGP bridges should be always an own bus on the HT hierarchy,
203 * but do it here for future safety.
205 static u32 __init
search_agp_bridge(u32
*order
, int *valid_agp
)
209 /* Poor man's PCI discovery */
210 for (bus
= 0; bus
< 256; bus
++) {
211 for (slot
= 0; slot
< 32; slot
++) {
212 for (func
= 0; func
< 8; func
++) {
215 class = read_pci_config(bus
, slot
, func
,
217 if (class == 0xffffffff)
220 switch (class >> 16) {
221 case PCI_CLASS_BRIDGE_HOST
:
222 case PCI_CLASS_BRIDGE_OTHER
: /* needed? */
224 cap
= find_cap(bus
, slot
, func
,
229 return read_agp(bus
, slot
, func
, cap
,
233 /* No multi-function device? */
234 type
= read_pci_config_byte(bus
, slot
, func
,
241 printk(KERN_INFO
"No AGP bridge found\n");
246 static int gart_fix_e820 __initdata
= 1;
248 static int __init
parse_gart_mem(char *p
)
253 if (!strncmp(p
, "off", 3))
255 else if (!strncmp(p
, "on", 2))
260 early_param("gart_fix_e820", parse_gart_mem
);
262 void __init
early_gart_iommu_check(void)
265 * in case it is enabled before, esp for kexec/kdump,
266 * previous kernel already enable that. memset called
267 * by allocate_aperture/__alloc_bootmem_nopanic cause restart.
268 * or second kernel have different position for GART hole. and new
269 * kernel could use hole as RAM that is still used by GART set by
271 * or BIOS forget to put that in reserved.
272 * try to update e820 to make that region as reserved.
276 u32 aper_size
= 0, aper_order
= 0, last_aper_order
= 0;
277 u64 aper_base
= 0, last_aper_base
= 0;
278 int aper_enabled
= 0, last_aper_enabled
= 0, last_valid
= 0;
280 if (!early_pci_allowed())
283 /* This is mostly duplicate of iommu_hole_init */
285 for (i
= 0; i
< ARRAY_SIZE(bus_dev_ranges
); i
++) {
287 int dev_base
, dev_limit
;
289 bus
= bus_dev_ranges
[i
].bus
;
290 dev_base
= bus_dev_ranges
[i
].dev_base
;
291 dev_limit
= bus_dev_ranges
[i
].dev_limit
;
293 for (slot
= dev_base
; slot
< dev_limit
; slot
++) {
294 if (!early_is_k8_nb(read_pci_config(bus
, slot
, 3, 0x00)))
297 ctl
= read_pci_config(bus
, slot
, 3, AMD64_GARTAPERTURECTL
);
298 aper_enabled
= ctl
& AMD64_GARTEN
;
299 aper_order
= (ctl
>> 1) & 7;
300 aper_size
= (32 * 1024 * 1024) << aper_order
;
301 aper_base
= read_pci_config(bus
, slot
, 3, AMD64_GARTAPERTUREBASE
) & 0x7fff;
305 if ((aper_order
!= last_aper_order
) ||
306 (aper_base
!= last_aper_base
) ||
307 (aper_enabled
!= last_aper_enabled
)) {
313 last_aper_order
= aper_order
;
314 last_aper_base
= aper_base
;
315 last_aper_enabled
= aper_enabled
;
320 if (!fix
&& !aper_enabled
)
323 if (!aper_base
|| !aper_size
|| aper_base
+ aper_size
> 0x100000000UL
)
326 if (gart_fix_e820
&& !fix
&& aper_enabled
) {
327 if (!e820_all_mapped(aper_base
, aper_base
+ aper_size
,
329 /* reserve it, so we can reuse it in second kernel */
330 printk(KERN_INFO
"update e820 for GART\n");
331 add_memory_region(aper_base
, aper_size
, E820_RESERVED
);
337 /* different nodes have different setting, disable them all at first*/
338 for (i
= 0; i
< ARRAY_SIZE(bus_dev_ranges
); i
++) {
340 int dev_base
, dev_limit
;
342 bus
= bus_dev_ranges
[i
].bus
;
343 dev_base
= bus_dev_ranges
[i
].dev_base
;
344 dev_limit
= bus_dev_ranges
[i
].dev_limit
;
346 for (slot
= dev_base
; slot
< dev_limit
; slot
++) {
347 if (!early_is_k8_nb(read_pci_config(bus
, slot
, 3, 0x00)))
350 ctl
= read_pci_config(bus
, slot
, 3, AMD64_GARTAPERTURECTL
);
351 ctl
&= ~AMD64_GARTEN
;
352 write_pci_config(bus
, slot
, 3, AMD64_GARTAPERTURECTL
, ctl
);
358 static int __initdata printed_gart_size_msg
;
360 void __init
gart_iommu_hole_init(void)
362 u32 agp_aper_base
= 0, agp_aper_order
= 0;
363 u32 aper_size
, aper_alloc
= 0, aper_order
= 0, last_aper_order
= 0;
364 u64 aper_base
, last_aper_base
= 0;
365 int fix
, slot
, valid_agp
= 0;
368 if (gart_iommu_aperture_disabled
|| !fix_aperture
||
369 !early_pci_allowed())
372 printk(KERN_INFO
"Checking aperture...\n");
374 if (!fallback_aper_force
)
375 agp_aper_base
= search_agp_bridge(&agp_aper_order
, &valid_agp
);
379 for (i
= 0; i
< ARRAY_SIZE(bus_dev_ranges
); i
++) {
381 int dev_base
, dev_limit
;
383 bus
= bus_dev_ranges
[i
].bus
;
384 dev_base
= bus_dev_ranges
[i
].dev_base
;
385 dev_limit
= bus_dev_ranges
[i
].dev_limit
;
387 for (slot
= dev_base
; slot
< dev_limit
; slot
++) {
388 if (!early_is_k8_nb(read_pci_config(bus
, slot
, 3, 0x00)))
392 gart_iommu_aperture
= 1;
394 aper_order
= (read_pci_config(bus
, slot
, 3, AMD64_GARTAPERTURECTL
) >> 1) & 7;
395 aper_size
= (32 * 1024 * 1024) << aper_order
;
396 aper_base
= read_pci_config(bus
, slot
, 3, AMD64_GARTAPERTUREBASE
) & 0x7fff;
399 printk(KERN_INFO
"Node %d: aperture @ %Lx size %u MB\n",
400 node
, aper_base
, aper_size
>> 20);
403 if (!aperture_valid(aper_base
, aper_size
, 64<<20)) {
404 if (valid_agp
&& agp_aper_base
&&
405 agp_aper_base
== aper_base
&&
406 agp_aper_order
== aper_order
) {
407 /* the same between two setting from NB and agp */
408 if (!no_iommu
&& end_pfn
> MAX_DMA32_PFN
&& !printed_gart_size_msg
) {
409 printk(KERN_ERR
"you are using iommu with agp, but GART size is less than 64M\n");
410 printk(KERN_ERR
"please increase GART size in your BIOS setup\n");
411 printk(KERN_ERR
"if BIOS doesn't have that option, contact your HW vendor!\n");
412 printed_gart_size_msg
= 1;
420 if ((last_aper_order
&& aper_order
!= last_aper_order
) ||
421 (last_aper_base
&& aper_base
!= last_aper_base
)) {
425 last_aper_order
= aper_order
;
426 last_aper_base
= aper_base
;
431 if (!fix
&& !fallback_aper_force
) {
432 if (last_aper_base
) {
433 unsigned long n
= (32 * 1024 * 1024) << last_aper_order
;
435 insert_aperture_resource((u32
)last_aper_base
, n
);
440 if (!fallback_aper_force
) {
441 aper_alloc
= agp_aper_base
;
442 aper_order
= agp_aper_order
;
446 /* Got the aperture from the AGP bridge */
447 } else if (swiotlb
&& !valid_agp
) {
449 } else if ((!no_iommu
&& end_pfn
> MAX_DMA32_PFN
) ||
452 fallback_aper_force
) {
454 "Your BIOS doesn't leave a aperture memory hole\n");
456 "Please enable the IOMMU option in the BIOS setup\n");
458 "This costs you %d MB of RAM\n",
459 32 << fallback_aper_order
);
461 aper_order
= fallback_aper_order
;
462 aper_alloc
= allocate_aperture();
465 * Could disable AGP and IOMMU here, but it's
466 * probably not worth it. But the later users
467 * cannot deal with bad apertures and turning
468 * on the aperture over memory causes very
469 * strange problems, so it's better to panic
472 panic("Not enough memory for aperture");
478 /* Fix up the north bridges */
479 for (i
= 0; i
< ARRAY_SIZE(bus_dev_ranges
); i
++) {
481 int dev_base
, dev_limit
;
483 bus
= bus_dev_ranges
[i
].bus
;
484 dev_base
= bus_dev_ranges
[i
].dev_base
;
485 dev_limit
= bus_dev_ranges
[i
].dev_limit
;
486 for (slot
= dev_base
; slot
< dev_limit
; slot
++) {
487 if (!early_is_k8_nb(read_pci_config(bus
, slot
, 3, 0x00)))
490 /* Don't enable translation yet. That is done later.
491 Assume this BIOS didn't initialise the GART so
492 just overwrite all previous bits */
493 write_pci_config(bus
, slot
, 3, AMD64_GARTAPERTURECTL
, aper_order
<< 1);
494 write_pci_config(bus
, slot
, 3, AMD64_GARTAPERTUREBASE
, aper_alloc
>> 25);