arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c

   1 /*
   2  * cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
   3  * M (part of the Centrino chipset).
   4  *
   5  * Since the original Pentium M, most new Intel CPUs support Enhanced
   6  * SpeedStep.
   7  *
   8  * Despite the "SpeedStep" in the name, this is almost entirely unlike
   9  * traditional SpeedStep.
  10  *
  11  * Modelled on speedstep.c
  12  *
  13  * Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/init.h>
  19 #include <linux/cpufreq.h>
  20 #include <linux/sched.h>        /* current */
  21 #include <linux/delay.h>
  22 #include <linux/compiler.h>
  23
  24 #include <asm/msr.h>
  25 #include <asm/processor.h>
  26 #include <asm/cpufeature.h>
  27
  28 #define PFX             "speedstep-centrino: "
  29 #define MAINTAINER      "cpufreq@vger.kernel.org"
  30
  31 #define dprintk(msg...) \
  32         cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-centrino", msg)
  33
  34 #define INTEL_MSR_RANGE (0xffff)
  35
  36 struct cpu_id
  37 {
  38         __u8    x86;            /* CPU family */
  39         __u8    x86_model;      /* model */
  40         __u8    x86_mask;       /* stepping */
  41 };
  42
  43 enum {
  44         CPU_BANIAS,
  45         CPU_DOTHAN_A1,
  46         CPU_DOTHAN_A2,
  47         CPU_DOTHAN_B0,
  48         CPU_MP4HT_D0,
  49         CPU_MP4HT_E0,
  50 };
  51
  52 static const struct cpu_id cpu_ids[] = {
  53         [CPU_BANIAS]    = { 6,  9, 5 },
  54         [CPU_DOTHAN_A1] = { 6, 13, 1 },
  55         [CPU_DOTHAN_A2] = { 6, 13, 2 },
  56         [CPU_DOTHAN_B0] = { 6, 13, 6 },
  57         [CPU_MP4HT_D0]  = {15,  3, 4 },
  58         [CPU_MP4HT_E0]  = {15,  4, 1 },
  59 };
  60 #define N_IDS   ARRAY_SIZE(cpu_ids)
  61
  62 struct cpu_model
  63 {
  64         const struct cpu_id *cpu_id;
  65         const char      *model_name;
  66         unsigned        max_freq; /* max clock in kHz */
  67
  68         struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */
  69 };
  70 static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
  71                                   const struct cpu_id *x);
  72
  73 /* Operating points for current CPU */
  74 static DEFINE_PER_CPU(struct cpu_model *, centrino_model);
  75 static DEFINE_PER_CPU(const struct cpu_id *, centrino_cpu);
  76
  77 static struct cpufreq_driver centrino_driver;
  78
  79 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
  80
  81 /* Computes the correct form for IA32_PERF_CTL MSR for a particular
  82    frequency/voltage operating point; frequency in MHz, volts in mV.
  83    This is stored as "index" in the structure. */
  84 #define OP(mhz, mv)                                                     \
  85         {                                                               \
  86                 .frequency = (mhz) * 1000,                              \
  87                 .index = (((mhz)/100) << 8) | ((mv - 700) / 16)         \
  88         }
  89
  90 /*
  91  * These voltage tables were derived from the Intel Pentium M
  92  * datasheet, document 25261202.pdf, Table 5.  I have verified they
  93  * are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
  94  * M.
  95  */
  96
  97 /* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
  98 static struct cpufreq_frequency_table banias_900[] =
  99 {
 100         OP(600,  844),
 101         OP(800,  988),
 102         OP(900, 1004),
 103         { .frequency = CPUFREQ_TABLE_END }
 104 };
 105
 106 /* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
 107 static struct cpufreq_frequency_table banias_1000[] =
 108 {
 109         OP(600,   844),
 110         OP(800,   972),
 111         OP(900,   988),
 112         OP(1000, 1004),
 113         { .frequency = CPUFREQ_TABLE_END }
 114 };
 115
 116 /* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
 117 static struct cpufreq_frequency_table banias_1100[] =
 118 {
 119         OP( 600,  956),
 120         OP( 800, 1020),
 121         OP( 900, 1100),
 122         OP(1000, 1164),
 123         OP(1100, 1180),
 124         { .frequency = CPUFREQ_TABLE_END }
 125 };
 126
 127
 128 /* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
 129 static struct cpufreq_frequency_table banias_1200[] =
 130 {
 131         OP( 600,  956),
 132         OP( 800, 1004),
 133         OP( 900, 1020),
 134         OP(1000, 1100),
 135         OP(1100, 1164),
 136         OP(1200, 1180),
 137         { .frequency = CPUFREQ_TABLE_END }
 138 };
 139
 140 /* Intel Pentium M processor 1.30GHz (Banias) */
 141 static struct cpufreq_frequency_table banias_1300[] =
 142 {
 143         OP( 600,  956),
 144         OP( 800, 1260),
 145         OP(1000, 1292),
 146         OP(1200, 1356),
 147         OP(1300, 1388),
 148         { .frequency = CPUFREQ_TABLE_END }
 149 };
 150
 151 /* Intel Pentium M processor 1.40GHz (Banias) */
 152 static struct cpufreq_frequency_table banias_1400[] =
 153 {
 154         OP( 600,  956),
 155         OP( 800, 1180),
 156         OP(1000, 1308),
 157         OP(1200, 1436),
 158         OP(1400, 1484),
 159         { .frequency = CPUFREQ_TABLE_END }
 160 };
 161
 162 /* Intel Pentium M processor 1.50GHz (Banias) */
 163 static struct cpufreq_frequency_table banias_1500[] =
 164 {
 165         OP( 600,  956),
 166         OP( 800, 1116),
 167         OP(1000, 1228),
 168         OP(1200, 1356),
 169         OP(1400, 1452),
 170         OP(1500, 1484),
 171         { .frequency = CPUFREQ_TABLE_END }
 172 };
 173
 174 /* Intel Pentium M processor 1.60GHz (Banias) */
 175 static struct cpufreq_frequency_table banias_1600[] =
 176 {
 177         OP( 600,  956),
 178         OP( 800, 1036),
 179         OP(1000, 1164),
 180         OP(1200, 1276),
 181         OP(1400, 1420),
 182         OP(1600, 1484),
 183         { .frequency = CPUFREQ_TABLE_END }
 184 };
 185
 186 /* Intel Pentium M processor 1.70GHz (Banias) */
 187 static struct cpufreq_frequency_table banias_1700[] =
 188 {
 189         OP( 600,  956),
 190         OP( 800, 1004),
 191         OP(1000, 1116),
 192         OP(1200, 1228),
 193         OP(1400, 1308),
 194         OP(1700, 1484),
 195         { .frequency = CPUFREQ_TABLE_END }
 196 };
 197 #undef OP
 198
 199 #define _BANIAS(cpuid, max, name)       \
 200 {       .cpu_id         = cpuid,        \
 201         .model_name     = "Intel(R) Pentium(R) M processor " name "MHz", \
 202         .max_freq       = (max)*1000,   \
 203         .op_points      = banias_##max, \
 204 }
 205 #define BANIAS(max)     _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
 206
 207 /* CPU models, their operating frequency range, and freq/voltage
 208    operating points */
 209 static struct cpu_model models[] =
 210 {
 211         _BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
 212         BANIAS(1000),
 213         BANIAS(1100),
 214         BANIAS(1200),
 215         BANIAS(1300),
 216         BANIAS(1400),
 217         BANIAS(1500),
 218         BANIAS(1600),
 219         BANIAS(1700),
 220
 221         /* NULL model_name is a wildcard */
 222         { &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
 223         { &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
 224         { &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
 225         { &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
 226         { &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },
 227
 228         { NULL, }
 229 };
 230 #undef _BANIAS
 231 #undef BANIAS
 232
 233 static int centrino_cpu_init_table(struct cpufreq_policy *policy)
 234 {
 235         struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
 236         struct cpu_model *model;
 237
 238         for(model = models; model->cpu_id != NULL; model++)
 239                 if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
 240                     (model->model_name == NULL ||
 241                      strcmp(cpu->x86_model_id, model->model_name) == 0))
 242                         break;
 243
 244         if (model->cpu_id == NULL) {
 245                 /* No match at all */
 246                 dprintk("no support for CPU model \"%s\": "
 247                        "send /proc/cpuinfo to " MAINTAINER "\n",
 248                        cpu->x86_model_id);
 249                 return -ENOENT;
 250         }
 251
 252         if (model->op_points == NULL) {
 253                 /* Matched a non-match */
 254                 dprintk("no table support for CPU model \"%s\"\n",
 255                        cpu->x86_model_id);
 256                 dprintk("try using the acpi-cpufreq driver\n");
 257                 return -ENOENT;
 258         }
 259
 260         per_cpu(centrino_model, policy->cpu) = model;
 261
 262         dprintk("found \"%s\": max frequency: %dkHz\n",
 263                model->model_name, model->max_freq);
 264
 265         return 0;
 266 }
 267
 268 #else
 269 static inline int centrino_cpu_init_table(struct cpufreq_policy *policy)
 270 {
 271         return -ENODEV;
 272 }
 273 #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
 274
 275 static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
 276                                   const struct cpu_id *x)
 277 {
 278         if ((c->x86 == x->x86) &&
 279             (c->x86_model == x->x86_model) &&
 280             (c->x86_mask == x->x86_mask))
 281                 return 1;
 282         return 0;
 283 }
 284
 285 /* To be called only after centrino_model is initialized */
 286 static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
 287 {
 288         int i;
 289
 290         /*
 291          * Extract clock in kHz from PERF_CTL value
 292          * for centrino, as some DSDTs are buggy.
 293          * Ideally, this can be done using the acpi_data structure.
 294          */
 295         if ((per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_BANIAS]) ||
 296             (per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_A1]) ||
 297             (per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_B0])) {
 298                 msr = (msr >> 8) & 0xff;
 299                 return msr * 100000;
 300         }
 301
 302         if ((!per_cpu(centrino_model, cpu)) ||
 303             (!per_cpu(centrino_model, cpu)->op_points))
 304                 return 0;
 305
 306         msr &= 0xffff;
 307         for (i = 0;
 308                 per_cpu(centrino_model, cpu)->op_points[i].frequency
 309                                                         != CPUFREQ_TABLE_END;
 310              i++) {
 311                 if (msr == per_cpu(centrino_model, cpu)->op_points[i].index)
 312                         return per_cpu(centrino_model, cpu)->
 313                                                         op_points[i].frequency;
 314         }
 315         if (failsafe)
 316                 return per_cpu(centrino_model, cpu)->op_points[i-1].frequency;
 317         else
 318                 return 0;
 319 }
 320
 321 /* Return the current CPU frequency in kHz */
 322 static unsigned int get_cur_freq(unsigned int cpu)
 323 {
 324         unsigned l, h;
 325         unsigned clock_freq;
 326         cpumask_t saved_mask;
 327
 328         saved_mask = current->cpus_allowed;
 329         set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
 330         if (smp_processor_id() != cpu)
 331                 return 0;
 332
 333         rdmsr(MSR_IA32_PERF_STATUS, l, h);
 334         clock_freq = extract_clock(l, cpu, 0);
 335
 336         if (unlikely(clock_freq == 0)) {
 337                 /*
 338                  * On some CPUs, we can see transient MSR values (which are
 339                  * not present in _PSS), while CPU is doing some automatic
 340                  * P-state transition (like TM2). Get the last freq set
 341                  * in PERF_CTL.
 342                  */
 343                 rdmsr(MSR_IA32_PERF_CTL, l, h);
 344                 clock_freq = extract_clock(l, cpu, 1);
 345         }
 346
 347         set_cpus_allowed_ptr(current, &saved_mask);
 348         return clock_freq;
 349 }
 350
 351
 352 static int centrino_cpu_init(struct cpufreq_policy *policy)
 353 {
 354         struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
 355         unsigned freq;
 356         unsigned l, h;
 357         int ret;
 358         int i;
 359
 360         /* Only Intel makes Enhanced Speedstep-capable CPUs */
 361         if (cpu->x86_vendor != X86_VENDOR_INTEL ||
 362             !cpu_has(cpu, X86_FEATURE_EST))
 363                 return -ENODEV;
 364
 365         if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC))
 366                 centrino_driver.flags |= CPUFREQ_CONST_LOOPS;
 367
 368         if (policy->cpu != 0)
 369                 return -ENODEV;
 370
 371         for (i = 0; i < N_IDS; i++)
 372                 if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
 373                         break;
 374
 375         if (i != N_IDS)
 376                 per_cpu(centrino_cpu, policy->cpu) = &cpu_ids[i];
 377
 378         if (!per_cpu(centrino_cpu, policy->cpu)) {
 379                 dprintk("found unsupported CPU with "
 380                 "Enhanced SpeedStep: send /proc/cpuinfo to "
 381                 MAINTAINER "\n");
 382                 return -ENODEV;
 383         }
 384
 385         if (centrino_cpu_init_table(policy)) {
 386                 return -ENODEV;
 387         }
 388
 389         /* Check to see if Enhanced SpeedStep is enabled, and try to
 390            enable it if not. */
 391         rdmsr(MSR_IA32_MISC_ENABLE, l, h);
 392
 393         if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
 394                 l |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;
 395                 dprintk("trying to enable Enhanced SpeedStep (%x)\n", l);
 396                 wrmsr(MSR_IA32_MISC_ENABLE, l, h);
 397
 398                 /* check to see if it stuck */
 399                 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
 400                 if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
 401                         printk(KERN_INFO PFX
 402                                 "couldn't enable Enhanced SpeedStep\n");
 403                         return -ENODEV;
 404                 }
 405         }
 406
 407         freq = get_cur_freq(policy->cpu);
 408         policy->cpuinfo.transition_latency = 10000;
 409                                                 /* 10uS transition latency */
 410         policy->cur = freq;
 411
 412         dprintk("centrino_cpu_init: cur=%dkHz\n", policy->cur);
 413
 414         ret = cpufreq_frequency_table_cpuinfo(policy,
 415                 per_cpu(centrino_model, policy->cpu)->op_points);
 416         if (ret)
 417                 return (ret);
 418
 419         cpufreq_frequency_table_get_attr(
 420                 per_cpu(centrino_model, policy->cpu)->op_points, policy->cpu);
 421
 422         return 0;
 423 }
 424
 425 static int centrino_cpu_exit(struct cpufreq_policy *policy)
 426 {
 427         unsigned int cpu = policy->cpu;
 428
 429         if (!per_cpu(centrino_model, cpu))
 430                 return -ENODEV;
 431
 432         cpufreq_frequency_table_put_attr(cpu);
 433
 434         per_cpu(centrino_model, cpu) = NULL;
 435
 436         return 0;
 437 }
 438
 439 /**
 440  * centrino_verify - verifies a new CPUFreq policy
 441  * @policy: new policy
 442  *
 443  * Limit must be within this model's frequency range at least one
 444  * border included.
 445  */
 446 static int centrino_verify (struct cpufreq_policy *policy)
 447 {
 448         return cpufreq_frequency_table_verify(policy,
 449                         per_cpu(centrino_model, policy->cpu)->op_points);
 450 }
 451
 452 /**
 453  * centrino_setpolicy - set a new CPUFreq policy
 454  * @policy: new policy
 455  * @target_freq: the target frequency
 456  * @relation: how that frequency relates to achieved frequency
 457  *      (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
 458  *
 459  * Sets a new CPUFreq policy.
 460  */
 461 static int centrino_target (struct cpufreq_policy *policy,
 462                             unsigned int target_freq,
 463                             unsigned int relation)
 464 {
 465         unsigned int    newstate = 0;
 466         unsigned int    msr, oldmsr = 0, h = 0, cpu = policy->cpu;
 467         struct cpufreq_freqs    freqs;
 468         int                     retval = 0;
 469         unsigned int            j, k, first_cpu, tmp;
 470         cpumask_var_t saved_mask, covered_cpus;
 471
 472         if (unlikely(!alloc_cpumask_var(&saved_mask, GFP_KERNEL)))
 473                 return -ENOMEM;
 474         if (unlikely(!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL))) {
 475                 free_cpumask_var(saved_mask);
 476                 return -ENOMEM;
 477         }
 478         cpumask_copy(saved_mask, &current->cpus_allowed);
 479
 480         if (unlikely(per_cpu(centrino_model, cpu) == NULL)) {
 481                 retval = -ENODEV;
 482                 goto out;
 483         }
 484
 485         if (unlikely(cpufreq_frequency_table_target(policy,
 486                         per_cpu(centrino_model, cpu)->op_points,
 487                         target_freq,
 488                         relation,
 489                         &newstate))) {
 490                 retval = -EINVAL;
 491                 goto out;
 492         }
 493
 494         first_cpu = 1;
 495         for_each_cpu(j, policy->cpus) {
 496                 const struct cpumask *mask;
 497
 498                 /* cpufreq holds the hotplug lock, so we are safe here */
 499                 if (!cpu_online(j))
 500                         continue;
 501
 502                 /*
 503                  * Support for SMP systems.
 504                  * Make sure we are running on CPU that wants to change freq
 505                  */
 506                 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
 507                         mask = policy->cpus;
 508                 else
 509                         mask = cpumask_of(j);
 510
 511                 set_cpus_allowed_ptr(current, mask);
 512                 preempt_disable();
 513                 if (unlikely(!cpu_isset(smp_processor_id(), *mask))) {
 514                         dprintk("couldn't limit to CPUs in this domain\n");
 515                         retval = -EAGAIN;
 516                         if (first_cpu) {
 517                                 /* We haven't started the transition yet. */
 518                                 goto migrate_end;
 519                         }
 520                         preempt_enable();
 521                         break;
 522                 }
 523
 524                 msr = per_cpu(centrino_model, cpu)->op_points[newstate].index;
 525
 526                 if (first_cpu) {
 527                         rdmsr(MSR_IA32_PERF_CTL, oldmsr, h);
 528                         if (msr == (oldmsr & 0xffff)) {
 529                                 dprintk("no change needed - msr was and needs "
 530                                         "to be %x\n", oldmsr);
 531                                 retval = 0;
 532                                 goto migrate_end;
 533                         }
 534
 535                         freqs.old = extract_clock(oldmsr, cpu, 0);
 536                         freqs.new = extract_clock(msr, cpu, 0);
 537
 538                         dprintk("target=%dkHz old=%d new=%d msr=%04x\n",
 539                                 target_freq, freqs.old, freqs.new, msr);
 540
 541                         for_each_cpu(k, policy->cpus) {
 542                                 if (!cpu_online(k))
 543                                         continue;
 544                                 freqs.cpu = k;
 545                                 cpufreq_notify_transition(&freqs,
 546                                         CPUFREQ_PRECHANGE);
 547                         }
 548
 549                         first_cpu = 0;
 550                         /* all but 16 LSB are reserved, treat them with care */
 551                         oldmsr &= ~0xffff;
 552                         msr &= 0xffff;
 553                         oldmsr |= msr;
 554                 }
 555
 556                 wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
 557                 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) {
 558                         preempt_enable();
 559                         break;
 560                 }
 561
 562                 cpu_set(j, *covered_cpus);
 563                 preempt_enable();
 564         }
 565
 566         for_each_cpu(k, policy->cpus) {
 567                 if (!cpu_online(k))
 568                         continue;
 569                 freqs.cpu = k;
 570                 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 571         }
 572
 573         if (unlikely(retval)) {
 574                 /*
 575                  * We have failed halfway through the frequency change.
 576                  * We have sent callbacks to policy->cpus and
 577                  * MSRs have already been written on coverd_cpus.
 578                  * Best effort undo..
 579                  */
 580
 581                 for_each_cpu_mask_nr(j, *covered_cpus) {
 582                         set_cpus_allowed_ptr(current, &cpumask_of_cpu(j));
 583                         wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
 584                 }
 585
 586                 tmp = freqs.new;
 587                 freqs.new = freqs.old;
 588                 freqs.old = tmp;
 589                 for_each_cpu(j, policy->cpus) {
 590                         if (!cpu_online(j))
 591                                 continue;
 592                         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 593                         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 594                 }
 595         }
 596         set_cpus_allowed_ptr(current, saved_mask);
 597         retval = 0;
 598         goto out;
 599
 600 migrate_end:
 601         preempt_enable();
 602         set_cpus_allowed_ptr(current, saved_mask);
 603 out:
 604         free_cpumask_var(saved_mask);
 605         free_cpumask_var(covered_cpus);
 606         return retval;
 607 }
 608
 609 static struct freq_attr* centrino_attr[] = {
 610         &cpufreq_freq_attr_scaling_available_freqs,
 611         NULL,
 612 };
 613
 614 static struct cpufreq_driver centrino_driver = {
 615         .name           = "centrino", /* should be speedstep-centrino,
 616                                          but there's a 16 char limit */
 617         .init           = centrino_cpu_init,
 618         .exit           = centrino_cpu_exit,
 619         .verify         = centrino_verify,
 620         .target         = centrino_target,
 621         .get            = get_cur_freq,
 622         .attr           = centrino_attr,
 623         .owner          = THIS_MODULE,
 624 };
 625
 626
 627 /**
 628  * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
 629  *
 630  * Initializes the Enhanced SpeedStep support. Returns -ENODEV on
 631  * unsupported devices, -ENOENT if there's no voltage table for this
 632  * particular CPU model, -EINVAL on problems during initiatization,
 633  * and zero on success.
 634  *
 635  * This is quite picky.  Not only does the CPU have to advertise the
 636  * "est" flag in the cpuid capability flags, we look for a specific
 637  * CPU model and stepping, and we need to have the exact model name in
 638  * our voltage tables.  That is, be paranoid about not releasing
 639  * someone's valuable magic smoke.
 640  */
 641 static int __init centrino_init(void)
 642 {
 643         struct cpuinfo_x86 *cpu = &cpu_data(0);
 644
 645         if (!cpu_has(cpu, X86_FEATURE_EST))
 646                 return -ENODEV;
 647
 648         return cpufreq_register_driver(&centrino_driver);
 649 }
 650
 651 static void __exit centrino_exit(void)
 652 {
 653         cpufreq_unregister_driver(&centrino_driver);
 654 }
 655
 656 MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
 657 MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
 658 MODULE_LICENSE ("GPL");
 659
 660 late_initcall(centrino_init);
 661 module_exit(centrino_exit);