2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/ratelimit.h>
14 #include <linux/kallsyms.h>
15 #include <linux/rcupdate.h>
16 #include <linux/smp_lock.h>
17 #include <linux/kobject.h>
18 #include <linux/kdebug.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/string.h>
22 #include <linux/sysdev.h>
23 #include <linux/ctype.h>
24 #include <linux/sched.h>
25 #include <linux/sysfs.h>
26 #include <linux/types.h>
27 #include <linux/init.h>
28 #include <linux/kmod.h>
29 #include <linux/poll.h>
30 #include <linux/cpu.h>
33 #include <asm/processor.h>
34 #include <asm/uaccess.h>
42 /* Handle unconfigured int18 (should never happen) */
43 static void unexpected_machine_check(struct pt_regs
*regs
, long error_code
)
45 printk(KERN_ERR
"CPU#%d: Unexpected int18 (Machine Check).\n",
49 /* Call the installed machine check handler for this CPU setup. */
50 void (*machine_check_vector
)(struct pt_regs
*, long error_code
) =
51 unexpected_machine_check
;
55 #ifdef CONFIG_X86_NEW_MCE
57 #define MISC_MCELOG_MINOR 227
63 * 0: always panic on uncorrected errors, log corrected errors
64 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
65 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
66 * 3: never panic or SIGBUS, log all errors (for testing only)
68 static int tolerant
= 1;
71 static unsigned long notify_user
;
73 static int mce_bootlog
= -1;
74 static atomic_t mce_events
;
76 static char trigger
[128];
77 static char *trigger_argv
[2] = { trigger
, NULL
};
79 static unsigned long dont_init_banks
;
81 static DECLARE_WAIT_QUEUE_HEAD(mce_wait
);
83 /* MCA banks polled by the period polling timer for corrected events */
84 DEFINE_PER_CPU(mce_banks_t
, mce_poll_banks
) = {
85 [0 ... BITS_TO_LONGS(MAX_NR_BANKS
)-1] = ~0UL
88 static inline int skip_bank_init(int i
)
90 return i
< BITS_PER_LONG
&& test_bit(i
, &dont_init_banks
);
93 /* Do initial initialization of a struct mce */
94 void mce_setup(struct mce
*m
)
96 memset(m
, 0, sizeof(struct mce
));
97 m
->cpu
= smp_processor_id();
101 DEFINE_PER_CPU(struct mce
, injectm
);
102 EXPORT_PER_CPU_SYMBOL_GPL(injectm
);
105 * Lockless MCE logging infrastructure.
106 * This avoids deadlocks on printk locks without having to break locks. Also
107 * separate MCEs from kernel messages to avoid bogus bug reports.
110 static struct mce_log mcelog
= {
115 void mce_log(struct mce
*mce
)
117 unsigned next
, entry
;
119 atomic_inc(&mce_events
);
123 entry
= rcu_dereference(mcelog
.next
);
126 * When the buffer fills up discard new entries.
127 * Assume that the earlier errors are the more
130 if (entry
>= MCE_LOG_LEN
) {
131 set_bit(MCE_OVERFLOW
, (unsigned long *)&mcelog
.flags
);
134 /* Old left over entry. Skip: */
135 if (mcelog
.entry
[entry
].finished
) {
143 if (cmpxchg(&mcelog
.next
, entry
, next
) == entry
)
146 memcpy(mcelog
.entry
+ entry
, mce
, sizeof(struct mce
));
148 mcelog
.entry
[entry
].finished
= 1;
151 set_bit(0, ¬ify_user
);
154 static void print_mce(struct mce
*m
)
156 printk(KERN_EMERG
"\n"
157 KERN_EMERG
"HARDWARE ERROR\n"
159 "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
160 m
->cpu
, m
->mcgstatus
, m
->bank
, m
->status
);
162 printk(KERN_EMERG
"RIP%s %02x:<%016Lx> ",
163 !(m
->mcgstatus
& MCG_STATUS_EIPV
) ? " !INEXACT!" : "",
165 if (m
->cs
== __KERNEL_CS
)
166 print_symbol("{%s}", m
->ip
);
169 printk(KERN_EMERG
"TSC %llx ", m
->tsc
);
171 printk("ADDR %llx ", m
->addr
);
173 printk("MISC %llx ", m
->misc
);
175 printk(KERN_EMERG
"This is not a software problem!\n");
176 printk(KERN_EMERG
"Run through mcelog --ascii to decode "
177 "and contact your hardware vendor\n");
180 static void mce_panic(char *msg
, struct mce
*backup
, u64 start
)
186 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
187 u64 tsc
= mcelog
.entry
[i
].tsc
;
189 if ((s64
)(tsc
- start
) < 0)
191 print_mce(&mcelog
.entry
[i
]);
192 if (backup
&& mcelog
.entry
[i
].tsc
== backup
->tsc
)
200 /* Support code for software error injection */
202 static int msr_to_offset(u32 msr
)
204 unsigned bank
= __get_cpu_var(injectm
.bank
);
206 return offsetof(struct mce
, ip
);
207 if (msr
== MSR_IA32_MC0_STATUS
+ bank
*4)
208 return offsetof(struct mce
, status
);
209 if (msr
== MSR_IA32_MC0_ADDR
+ bank
*4)
210 return offsetof(struct mce
, addr
);
211 if (msr
== MSR_IA32_MC0_MISC
+ bank
*4)
212 return offsetof(struct mce
, misc
);
213 if (msr
== MSR_IA32_MCG_STATUS
)
214 return offsetof(struct mce
, mcgstatus
);
218 /* MSR access wrappers used for error injection */
219 static u64
mce_rdmsrl(u32 msr
)
222 if (__get_cpu_var(injectm
).finished
) {
223 int offset
= msr_to_offset(msr
);
226 return *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
);
232 static void mce_wrmsrl(u32 msr
, u64 v
)
234 if (__get_cpu_var(injectm
).finished
) {
235 int offset
= msr_to_offset(msr
);
237 *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
) = v
;
243 int mce_available(struct cpuinfo_x86
*c
)
247 return cpu_has(c
, X86_FEATURE_MCE
) && cpu_has(c
, X86_FEATURE_MCA
);
250 static inline void mce_get_rip(struct mce
*m
, struct pt_regs
*regs
)
252 if (regs
&& (m
->mcgstatus
& MCG_STATUS_RIPV
)) {
260 /* Assume the RIP in the MSR is exact. Is this true? */
261 m
->mcgstatus
|= MCG_STATUS_EIPV
;
262 m
->ip
= mce_rdmsrl(rip_msr
);
268 * Poll for corrected events or events that happened before reset.
269 * Those are just logged through /dev/mcelog.
271 * This is executed in standard interrupt context.
273 void machine_check_poll(enum mcp_flags flags
, mce_banks_t
*b
)
280 m
.mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
281 for (i
= 0; i
< banks
; i
++) {
282 if (!bank
[i
] || !test_bit(i
, *b
))
291 m
.status
= mce_rdmsrl(MSR_IA32_MC0_STATUS
+ i
*4);
292 if (!(m
.status
& MCI_STATUS_VAL
))
296 * Uncorrected events are handled by the exception handler
297 * when it is enabled. But when the exception is disabled log
300 * TBD do the same check for MCI_STATUS_EN here?
302 if ((m
.status
& MCI_STATUS_UC
) && !(flags
& MCP_UC
))
305 if (m
.status
& MCI_STATUS_MISCV
)
306 m
.misc
= mce_rdmsrl(MSR_IA32_MC0_MISC
+ i
*4);
307 if (m
.status
& MCI_STATUS_ADDRV
)
308 m
.addr
= mce_rdmsrl(MSR_IA32_MC0_ADDR
+ i
*4);
310 if (!(flags
& MCP_TIMESTAMP
))
313 * Don't get the IP here because it's unlikely to
314 * have anything to do with the actual error location.
316 if (!(flags
& MCP_DONTLOG
)) {
318 add_taint(TAINT_MACHINE_CHECK
);
322 * Clear state for this bank.
324 mce_wrmsrl(MSR_IA32_MC0_STATUS
+4*i
, 0);
328 * Don't clear MCG_STATUS here because it's only defined for
332 EXPORT_SYMBOL_GPL(machine_check_poll
);
335 * The actual machine check handler. This only handles real
336 * exceptions when something got corrupted coming in through int 18.
338 * This is executed in NMI context not subject to normal locking rules. This
339 * implies that most kernel services cannot be safely used. Don't even
340 * think about putting a printk in there!
342 void do_machine_check(struct pt_regs
*regs
, long error_code
)
344 struct mce m
, panicm
;
345 int panicm_found
= 0;
349 * If no_way_out gets set, there is no safe way to recover from this
350 * MCE. If tolerant is cranked up, we'll try anyway.
354 * If kill_it gets set, there might be a way to recover from this
358 DECLARE_BITMAP(toclear
, MAX_NR_BANKS
);
360 atomic_inc(&mce_entry
);
362 if (notify_die(DIE_NMI
, "machine check", regs
, error_code
,
363 18, SIGKILL
) == NOTIFY_STOP
)
370 m
.mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
372 /* if the restart IP is not valid, we're done for */
373 if (!(m
.mcgstatus
& MCG_STATUS_RIPV
))
379 for (i
= 0; i
< banks
; i
++) {
380 __clear_bit(i
, toclear
);
388 m
.status
= mce_rdmsrl(MSR_IA32_MC0_STATUS
+ i
*4);
389 if ((m
.status
& MCI_STATUS_VAL
) == 0)
393 * Non uncorrected errors are handled by machine_check_poll
396 if ((m
.status
& MCI_STATUS_UC
) == 0)
400 * Set taint even when machine check was not enabled.
402 add_taint(TAINT_MACHINE_CHECK
);
404 __set_bit(i
, toclear
);
406 if (m
.status
& MCI_STATUS_EN
) {
407 /* if PCC was set, there's no way out */
408 no_way_out
|= !!(m
.status
& MCI_STATUS_PCC
);
410 * If this error was uncorrectable and there was
411 * an overflow, we're in trouble. If no overflow,
412 * we might get away with just killing a task.
414 if (m
.status
& MCI_STATUS_UC
) {
415 if (tolerant
< 1 || m
.status
& MCI_STATUS_OVER
)
421 * Machine check event was not enabled. Clear, but
427 if (m
.status
& MCI_STATUS_MISCV
)
428 m
.misc
= mce_rdmsrl(MSR_IA32_MC0_MISC
+ i
*4);
429 if (m
.status
& MCI_STATUS_ADDRV
)
430 m
.addr
= mce_rdmsrl(MSR_IA32_MC0_ADDR
+ i
*4);
432 mce_get_rip(&m
, regs
);
436 * Did this bank cause the exception?
438 * Assume that the bank with uncorrectable errors did it,
439 * and that there is only a single one:
441 if ((m
.status
& MCI_STATUS_UC
) &&
442 (m
.status
& MCI_STATUS_EN
)) {
449 * If we didn't find an uncorrectable error, pick
450 * the last one (shouldn't happen, just being safe).
456 * If we have decided that we just CAN'T continue, and the user
457 * has not set tolerant to an insane level, give up and die.
459 if (no_way_out
&& tolerant
< 3)
460 mce_panic("Machine check", &panicm
, mcestart
);
463 * If the error seems to be unrecoverable, something should be
464 * done. Try to kill as little as possible. If we can kill just
465 * one task, do that. If the user has set the tolerance very
466 * high, don't try to do anything at all.
468 if (kill_it
&& tolerant
< 3) {
472 * If the EIPV bit is set, it means the saved IP is the
473 * instruction which caused the MCE.
475 if (m
.mcgstatus
& MCG_STATUS_EIPV
)
476 user_space
= panicm
.ip
&& (panicm
.cs
& 3);
479 * If we know that the error was in user space, send a
480 * SIGBUS. Otherwise, panic if tolerance is low.
482 * force_sig() takes an awful lot of locks and has a slight
483 * risk of deadlocking.
486 force_sig(SIGBUS
, current
);
487 } else if (panic_on_oops
|| tolerant
< 2) {
488 mce_panic("Uncorrected machine check",
493 /* notify userspace ASAP */
494 set_thread_flag(TIF_MCE_NOTIFY
);
496 /* the last thing we do is clear state */
497 for (i
= 0; i
< banks
; i
++) {
498 if (test_bit(i
, toclear
))
499 mce_wrmsrl(MSR_IA32_MC0_STATUS
+4*i
, 0);
501 mce_wrmsrl(MSR_IA32_MCG_STATUS
, 0);
503 atomic_dec(&mce_entry
);
505 EXPORT_SYMBOL_GPL(do_machine_check
);
507 #ifdef CONFIG_X86_MCE_INTEL
509 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
510 * @cpu: The CPU on which the event occurred.
511 * @status: Event status information
513 * This function should be called by the thermal interrupt after the
514 * event has been processed and the decision was made to log the event
517 * The status parameter will be saved to the 'status' field of 'struct mce'
518 * and historically has been the register value of the
519 * MSR_IA32_THERMAL_STATUS (Intel) msr.
521 void mce_log_therm_throt_event(__u64 status
)
526 m
.bank
= MCE_THERMAL_BANK
;
530 #endif /* CONFIG_X86_MCE_INTEL */
533 * Periodic polling timer for "silent" machine check errors. If the
534 * poller finds an MCE, poll 2x faster. When the poller finds no more
535 * errors, poll 2x slower (up to check_interval seconds).
537 static int check_interval
= 5 * 60; /* 5 minutes */
539 static DEFINE_PER_CPU(int, next_interval
); /* in jiffies */
540 static DEFINE_PER_CPU(struct timer_list
, mce_timer
);
542 static void mcheck_timer(unsigned long data
)
544 struct timer_list
*t
= &per_cpu(mce_timer
, data
);
547 WARN_ON(smp_processor_id() != data
);
549 if (mce_available(¤t_cpu_data
)) {
550 machine_check_poll(MCP_TIMESTAMP
,
551 &__get_cpu_var(mce_poll_banks
));
555 * Alert userspace if needed. If we logged an MCE, reduce the
556 * polling interval, otherwise increase the polling interval.
558 n
= &__get_cpu_var(next_interval
);
559 if (mce_notify_user()) {
560 *n
= max(*n
/2, HZ
/100);
562 *n
= min(*n
*2, (int)round_jiffies_relative(check_interval
*HZ
));
565 t
->expires
= jiffies
+ *n
;
569 static void mce_do_trigger(struct work_struct
*work
)
571 call_usermodehelper(trigger
, trigger_argv
, NULL
, UMH_NO_WAIT
);
574 static DECLARE_WORK(mce_trigger_work
, mce_do_trigger
);
577 * Notify the user(s) about new machine check events.
578 * Can be called from interrupt context, but not from machine check/NMI
581 int mce_notify_user(void)
583 /* Not more than two messages every minute */
584 static DEFINE_RATELIMIT_STATE(ratelimit
, 60*HZ
, 2);
586 clear_thread_flag(TIF_MCE_NOTIFY
);
588 if (test_and_clear_bit(0, ¬ify_user
)) {
589 wake_up_interruptible(&mce_wait
);
592 * There is no risk of missing notifications because
593 * work_pending is always cleared before the function is
596 if (trigger
[0] && !work_pending(&mce_trigger_work
))
597 schedule_work(&mce_trigger_work
);
599 if (__ratelimit(&ratelimit
))
600 printk(KERN_INFO
"Machine check events logged\n");
606 EXPORT_SYMBOL_GPL(mce_notify_user
);
609 * Initialize Machine Checks for a CPU.
611 static int mce_cap_init(void)
616 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
618 b
= cap
& MCG_BANKCNT_MASK
;
619 printk(KERN_INFO
"mce: CPU supports %d MCE banks\n", b
);
621 if (b
> MAX_NR_BANKS
) {
623 "MCE: Using only %u machine check banks out of %u\n",
628 /* Don't support asymmetric configurations today */
629 WARN_ON(banks
!= 0 && b
!= banks
);
632 bank
= kmalloc(banks
* sizeof(u64
), GFP_KERNEL
);
635 memset(bank
, 0xff, banks
* sizeof(u64
));
638 /* Use accurate RIP reporting if available. */
639 if ((cap
& MCG_EXT_P
) && MCG_EXT_CNT(cap
) >= 9)
640 rip_msr
= MSR_IA32_MCG_EIP
;
645 static void mce_init(void *dummy
)
647 mce_banks_t all_banks
;
652 * Log the machine checks left over from the previous reset.
654 bitmap_fill(all_banks
, MAX_NR_BANKS
);
655 machine_check_poll(MCP_UC
|(!mce_bootlog
? MCP_DONTLOG
: 0), &all_banks
);
657 set_in_cr4(X86_CR4_MCE
);
659 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
661 wrmsr(MSR_IA32_MCG_CTL
, 0xffffffff, 0xffffffff);
663 for (i
= 0; i
< banks
; i
++) {
664 if (skip_bank_init(i
))
666 wrmsrl(MSR_IA32_MC0_CTL
+4*i
, bank
[i
]);
667 wrmsrl(MSR_IA32_MC0_STATUS
+4*i
, 0);
671 /* Add per CPU specific workarounds here */
672 static void mce_cpu_quirks(struct cpuinfo_x86
*c
)
674 /* This should be disabled by the BIOS, but isn't always */
675 if (c
->x86_vendor
== X86_VENDOR_AMD
) {
676 if (c
->x86
== 15 && banks
> 4) {
678 * disable GART TBL walk error reporting, which
679 * trips off incorrectly with the IOMMU & 3ware
682 clear_bit(10, (unsigned long *)&bank
[4]);
684 if (c
->x86
<= 17 && mce_bootlog
< 0) {
686 * Lots of broken BIOS around that don't clear them
687 * by default and leave crap in there. Don't log:
692 * Various K7s with broken bank 0 around. Always disable
699 if (c
->x86_vendor
== X86_VENDOR_INTEL
) {
701 * SDM documents that on family 6 bank 0 should not be written
702 * because it aliases to another special BIOS controlled
704 * But it's not aliased anymore on model 0x1a+
705 * Don't ignore bank 0 completely because there could be a
706 * valid event later, merely don't write CTL0.
709 if (c
->x86
== 6 && c
->x86_model
< 0x1A)
710 __set_bit(0, &dont_init_banks
);
714 static void __cpuinit
mce_ancient_init(struct cpuinfo_x86
*c
)
718 switch (c
->x86_vendor
) {
719 case X86_VENDOR_INTEL
:
720 if (mce_p5_enabled())
721 intel_p5_mcheck_init(c
);
723 case X86_VENDOR_CENTAUR
:
724 winchip_mcheck_init(c
);
729 static void mce_cpu_features(struct cpuinfo_x86
*c
)
731 switch (c
->x86_vendor
) {
732 case X86_VENDOR_INTEL
:
733 mce_intel_feature_init(c
);
736 mce_amd_feature_init(c
);
743 static void mce_init_timer(void)
745 struct timer_list
*t
= &__get_cpu_var(mce_timer
);
746 int *n
= &__get_cpu_var(next_interval
);
748 *n
= check_interval
* HZ
;
751 setup_timer(t
, mcheck_timer
, smp_processor_id());
752 t
->expires
= round_jiffies(jiffies
+ *n
);
757 * Called for each booted CPU to set up machine checks.
758 * Must be called with preempt off:
760 void __cpuinit
mcheck_init(struct cpuinfo_x86
*c
)
767 if (!mce_available(c
))
770 if (mce_cap_init() < 0) {
776 machine_check_vector
= do_machine_check
;
784 * Character device to read and clear the MCE log.
787 static DEFINE_SPINLOCK(mce_state_lock
);
788 static int open_count
; /* #times opened */
789 static int open_exclu
; /* already open exclusive? */
791 static int mce_open(struct inode
*inode
, struct file
*file
)
794 spin_lock(&mce_state_lock
);
796 if (open_exclu
|| (open_count
&& (file
->f_flags
& O_EXCL
))) {
797 spin_unlock(&mce_state_lock
);
803 if (file
->f_flags
& O_EXCL
)
807 spin_unlock(&mce_state_lock
);
810 return nonseekable_open(inode
, file
);
813 static int mce_release(struct inode
*inode
, struct file
*file
)
815 spin_lock(&mce_state_lock
);
820 spin_unlock(&mce_state_lock
);
825 static void collect_tscs(void *data
)
827 unsigned long *cpu_tsc
= (unsigned long *)data
;
829 rdtscll(cpu_tsc
[smp_processor_id()]);
832 static DEFINE_MUTEX(mce_read_mutex
);
834 static ssize_t
mce_read(struct file
*filp
, char __user
*ubuf
, size_t usize
,
837 char __user
*buf
= ubuf
;
838 unsigned long *cpu_tsc
;
842 cpu_tsc
= kmalloc(nr_cpu_ids
* sizeof(long), GFP_KERNEL
);
846 mutex_lock(&mce_read_mutex
);
847 next
= rcu_dereference(mcelog
.next
);
849 /* Only supports full reads right now */
850 if (*off
!= 0 || usize
< MCE_LOG_LEN
*sizeof(struct mce
)) {
851 mutex_unlock(&mce_read_mutex
);
860 for (i
= prev
; i
< next
; i
++) {
861 unsigned long start
= jiffies
;
863 while (!mcelog
.entry
[i
].finished
) {
864 if (time_after_eq(jiffies
, start
+ 2)) {
865 memset(mcelog
.entry
+ i
, 0,
872 err
|= copy_to_user(buf
, mcelog
.entry
+ i
,
874 buf
+= sizeof(struct mce
);
879 memset(mcelog
.entry
+ prev
, 0,
880 (next
- prev
) * sizeof(struct mce
));
882 next
= cmpxchg(&mcelog
.next
, prev
, 0);
883 } while (next
!= prev
);
888 * Collect entries that were still getting written before the
891 on_each_cpu(collect_tscs
, cpu_tsc
, 1);
893 for (i
= next
; i
< MCE_LOG_LEN
; i
++) {
894 if (mcelog
.entry
[i
].finished
&&
895 mcelog
.entry
[i
].tsc
< cpu_tsc
[mcelog
.entry
[i
].cpu
]) {
896 err
|= copy_to_user(buf
, mcelog
.entry
+i
,
899 buf
+= sizeof(struct mce
);
900 memset(&mcelog
.entry
[i
], 0, sizeof(struct mce
));
903 mutex_unlock(&mce_read_mutex
);
906 return err
? -EFAULT
: buf
- ubuf
;
909 static unsigned int mce_poll(struct file
*file
, poll_table
*wait
)
911 poll_wait(file
, &mce_wait
, wait
);
912 if (rcu_dereference(mcelog
.next
))
913 return POLLIN
| POLLRDNORM
;
917 static long mce_ioctl(struct file
*f
, unsigned int cmd
, unsigned long arg
)
919 int __user
*p
= (int __user
*)arg
;
921 if (!capable(CAP_SYS_ADMIN
))
925 case MCE_GET_RECORD_LEN
:
926 return put_user(sizeof(struct mce
), p
);
927 case MCE_GET_LOG_LEN
:
928 return put_user(MCE_LOG_LEN
, p
);
929 case MCE_GETCLEAR_FLAGS
: {
933 flags
= mcelog
.flags
;
934 } while (cmpxchg(&mcelog
.flags
, flags
, 0) != flags
);
936 return put_user(flags
, p
);
943 struct file_operations mce_chrdev_ops
= {
945 .release
= mce_release
,
948 .unlocked_ioctl
= mce_ioctl
,
950 EXPORT_SYMBOL_GPL(mce_chrdev_ops
);
952 static struct miscdevice mce_log_device
= {
959 * mce=off disables machine check
960 * mce=TOLERANCELEVEL (number, see above)
961 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
962 * mce=nobootlog Don't log MCEs from before booting.
964 static int __init
mcheck_enable(char *str
)
970 if (!strcmp(str
, "off"))
972 else if (!strcmp(str
, "bootlog") || !strcmp(str
, "nobootlog"))
973 mce_bootlog
= (str
[0] == 'b');
974 else if (isdigit(str
[0]))
975 get_option(&str
, &tolerant
);
977 printk(KERN_INFO
"mce argument %s ignored. Please use /sys\n",
983 __setup("mce", mcheck_enable
);
990 * Disable machine checks on suspend and shutdown. We can't really handle
993 static int mce_disable(void)
997 for (i
= 0; i
< banks
; i
++) {
998 if (!skip_bank_init(i
))
999 wrmsrl(MSR_IA32_MC0_CTL
+ i
*4, 0);
1004 static int mce_suspend(struct sys_device
*dev
, pm_message_t state
)
1006 return mce_disable();
1009 static int mce_shutdown(struct sys_device
*dev
)
1011 return mce_disable();
1015 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1016 * Only one CPU is active at this time, the others get re-added later using
1019 static int mce_resume(struct sys_device
*dev
)
1022 mce_cpu_features(¤t_cpu_data
);
1027 static void mce_cpu_restart(void *data
)
1029 del_timer_sync(&__get_cpu_var(mce_timer
));
1030 if (mce_available(¤t_cpu_data
))
1035 /* Reinit MCEs after user configuration changes */
1036 static void mce_restart(void)
1038 on_each_cpu(mce_cpu_restart
, NULL
, 1);
1041 static struct sysdev_class mce_sysclass
= {
1042 .suspend
= mce_suspend
,
1043 .shutdown
= mce_shutdown
,
1044 .resume
= mce_resume
,
1045 .name
= "machinecheck",
1048 DEFINE_PER_CPU(struct sys_device
, mce_dev
);
1051 void (*threshold_cpu_callback
)(unsigned long action
, unsigned int cpu
);
1053 /* Why are there no generic functions for this? */
1054 #define ACCESSOR(name, var, start) \
1055 static ssize_t show_ ## name(struct sys_device *s, \
1056 struct sysdev_attribute *attr, \
1058 return sprintf(buf, "%Lx\n", (u64)var); \
1060 static ssize_t set_ ## name(struct sys_device *s, \
1061 struct sysdev_attribute *attr, \
1062 const char *buf, size_t siz) { \
1064 u64 new = simple_strtoull(buf, &end, 0); \
1073 static SYSDEV_ATTR(name, 0644, show_ ## name, set_ ## name);
1075 static struct sysdev_attribute
*bank_attrs
;
1077 static ssize_t
show_bank(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1080 u64 b
= bank
[attr
- bank_attrs
];
1082 return sprintf(buf
, "%llx\n", b
);
1085 static ssize_t
set_bank(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1086 const char *buf
, size_t siz
)
1089 u64
new = simple_strtoull(buf
, &end
, 0);
1094 bank
[attr
- bank_attrs
] = new;
1101 show_trigger(struct sys_device
*s
, struct sysdev_attribute
*attr
, char *buf
)
1103 strcpy(buf
, trigger
);
1105 return strlen(trigger
) + 1;
1108 static ssize_t
set_trigger(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1109 const char *buf
, size_t siz
)
1114 strncpy(trigger
, buf
, sizeof(trigger
));
1115 trigger
[sizeof(trigger
)-1] = 0;
1116 len
= strlen(trigger
);
1117 p
= strchr(trigger
, '\n');
1125 static SYSDEV_ATTR(trigger
, 0644, show_trigger
, set_trigger
);
1126 static SYSDEV_INT_ATTR(tolerant
, 0644, tolerant
);
1128 ACCESSOR(check_interval
, check_interval
, mce_restart())
1130 static struct sysdev_attribute
*mce_attrs
[] = {
1131 &attr_tolerant
.attr
, &attr_check_interval
, &attr_trigger
,
1135 static cpumask_var_t mce_dev_initialized
;
1137 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1138 static __cpuinit
int mce_create_device(unsigned int cpu
)
1143 if (!mce_available(&boot_cpu_data
))
1146 memset(&per_cpu(mce_dev
, cpu
).kobj
, 0, sizeof(struct kobject
));
1147 per_cpu(mce_dev
, cpu
).id
= cpu
;
1148 per_cpu(mce_dev
, cpu
).cls
= &mce_sysclass
;
1150 err
= sysdev_register(&per_cpu(mce_dev
, cpu
));
1154 for (i
= 0; mce_attrs
[i
]; i
++) {
1155 err
= sysdev_create_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
1159 for (i
= 0; i
< banks
; i
++) {
1160 err
= sysdev_create_file(&per_cpu(mce_dev
, cpu
),
1165 cpumask_set_cpu(cpu
, mce_dev_initialized
);
1170 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), &bank_attrs
[i
]);
1173 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
1175 sysdev_unregister(&per_cpu(mce_dev
, cpu
));
1180 static __cpuinit
void mce_remove_device(unsigned int cpu
)
1184 if (!cpumask_test_cpu(cpu
, mce_dev_initialized
))
1187 for (i
= 0; mce_attrs
[i
]; i
++)
1188 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
1190 for (i
= 0; i
< banks
; i
++)
1191 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), &bank_attrs
[i
]);
1193 sysdev_unregister(&per_cpu(mce_dev
, cpu
));
1194 cpumask_clear_cpu(cpu
, mce_dev_initialized
);
1197 /* Make sure there are no machine checks on offlined CPUs. */
1198 static void mce_disable_cpu(void *h
)
1200 unsigned long action
= *(unsigned long *)h
;
1203 if (!mce_available(¤t_cpu_data
))
1205 if (!(action
& CPU_TASKS_FROZEN
))
1207 for (i
= 0; i
< banks
; i
++) {
1208 if (!skip_bank_init(i
))
1209 wrmsrl(MSR_IA32_MC0_CTL
+ i
*4, 0);
1213 static void mce_reenable_cpu(void *h
)
1215 unsigned long action
= *(unsigned long *)h
;
1218 if (!mce_available(¤t_cpu_data
))
1221 if (!(action
& CPU_TASKS_FROZEN
))
1223 for (i
= 0; i
< banks
; i
++) {
1224 if (!skip_bank_init(i
))
1225 wrmsrl(MSR_IA32_MC0_CTL
+ i
*4, bank
[i
]);
1229 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
1230 static int __cpuinit
1231 mce_cpu_callback(struct notifier_block
*nfb
, unsigned long action
, void *hcpu
)
1233 unsigned int cpu
= (unsigned long)hcpu
;
1234 struct timer_list
*t
= &per_cpu(mce_timer
, cpu
);
1238 case CPU_ONLINE_FROZEN
:
1239 mce_create_device(cpu
);
1240 if (threshold_cpu_callback
)
1241 threshold_cpu_callback(action
, cpu
);
1244 case CPU_DEAD_FROZEN
:
1245 if (threshold_cpu_callback
)
1246 threshold_cpu_callback(action
, cpu
);
1247 mce_remove_device(cpu
);
1249 case CPU_DOWN_PREPARE
:
1250 case CPU_DOWN_PREPARE_FROZEN
:
1252 smp_call_function_single(cpu
, mce_disable_cpu
, &action
, 1);
1254 case CPU_DOWN_FAILED
:
1255 case CPU_DOWN_FAILED_FROZEN
:
1256 t
->expires
= round_jiffies(jiffies
+
1257 __get_cpu_var(next_interval
));
1258 add_timer_on(t
, cpu
);
1259 smp_call_function_single(cpu
, mce_reenable_cpu
, &action
, 1);
1262 /* intentionally ignoring frozen here */
1263 cmci_rediscover(cpu
);
1269 static struct notifier_block mce_cpu_notifier __cpuinitdata
= {
1270 .notifier_call
= mce_cpu_callback
,
1273 static __init
int mce_init_banks(void)
1277 bank_attrs
= kzalloc(sizeof(struct sysdev_attribute
) * banks
,
1282 for (i
= 0; i
< banks
; i
++) {
1283 struct sysdev_attribute
*a
= &bank_attrs
[i
];
1285 a
->attr
.name
= kasprintf(GFP_KERNEL
, "bank%d", i
);
1289 a
->attr
.mode
= 0644;
1290 a
->show
= show_bank
;
1291 a
->store
= set_bank
;
1297 kfree(bank_attrs
[i
].attr
.name
);
1304 static __init
int mce_init_device(void)
1309 if (!mce_available(&boot_cpu_data
))
1312 alloc_cpumask_var(&mce_dev_initialized
, GFP_KERNEL
);
1314 err
= mce_init_banks();
1318 err
= sysdev_class_register(&mce_sysclass
);
1322 for_each_online_cpu(i
) {
1323 err
= mce_create_device(i
);
1328 register_hotcpu_notifier(&mce_cpu_notifier
);
1329 misc_register(&mce_log_device
);
1334 device_initcall(mce_init_device
);
1336 #else /* CONFIG_X86_OLD_MCE: */
1339 EXPORT_SYMBOL_GPL(nr_mce_banks
); /* non-fatal.o */
1341 /* This has to be run for each processor */
1342 void mcheck_init(struct cpuinfo_x86
*c
)
1344 if (mce_disabled
== 1)
1347 switch (c
->x86_vendor
) {
1348 case X86_VENDOR_AMD
:
1352 case X86_VENDOR_INTEL
:
1354 intel_p5_mcheck_init(c
);
1356 intel_p6_mcheck_init(c
);
1358 intel_p4_mcheck_init(c
);
1361 case X86_VENDOR_CENTAUR
:
1363 winchip_mcheck_init(c
);
1369 printk(KERN_INFO
"mce: CPU supports %d MCE banks\n", nr_mce_banks
);
1372 static int __init
mcheck_enable(char *str
)
1378 __setup("mce", mcheck_enable
);
1380 #endif /* CONFIG_X86_OLD_MCE */
1383 * Old style boot options parsing. Only for compatibility.
1385 static int __init
mcheck_disable(char *str
)
1390 __setup("nomce", mcheck_disable
);