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b43: Workaround circular locking in hw-tkip key update callback
[linux-2.6/mini2440.git] / drivers / net / wireless / b43 / main.c
bloba8a00d28a1a81f4f99f9635cb7a78300e7ac44e3
1 /*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005-2009 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 SDIO support
12 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
13
14 Some parts of the code in this file are derived from the ipw2200
15 driver Copyright(c) 2003 - 2004 Intel Corporation.
16
17 This program is free software; you can redistribute it and/or modify
18 it under the terms of the GNU General Public License as published by
19 the Free Software Foundation; either version 2 of the License, or
20 (at your option) any later version.
21
22 This program is distributed in the hope that it will be useful,
23 but WITHOUT ANY WARRANTY; without even the implied warranty of
24 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 GNU General Public License for more details.
26
27 You should have received a copy of the GNU General Public License
28 along with this program; see the file COPYING. If not, write to
29 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
30 Boston, MA 02110-1301, USA.
31
32 */
33
34 #include <linux/delay.h>
35 #include <linux/init.h>
36 #include <linux/moduleparam.h>
37 #include <linux/if_arp.h>
38 #include <linux/etherdevice.h>
39 #include <linux/firmware.h>
40 #include <linux/wireless.h>
41 #include <linux/workqueue.h>
42 #include <linux/skbuff.h>
43 #include <linux/io.h>
44 #include <linux/dma-mapping.h>
45 #include <asm/unaligned.h>
46
47 #include "b43.h"
48 #include "main.h"
49 #include "debugfs.h"
50 #include "phy_common.h"
51 #include "phy_g.h"
52 #include "phy_n.h"
53 #include "dma.h"
54 #include "pio.h"
55 #include "sysfs.h"
56 #include "xmit.h"
57 #include "lo.h"
58 #include "pcmcia.h"
59 #include "sdio.h"
60 #include <linux/mmc/sdio_func.h>
61
62 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
63 MODULE_AUTHOR("Martin Langer");
64 MODULE_AUTHOR("Stefano Brivio");
65 MODULE_AUTHOR("Michael Buesch");
66 MODULE_AUTHOR("Gábor Stefanik");
67 MODULE_LICENSE("GPL");
68
69 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
70
71
72 static int modparam_bad_frames_preempt;
73 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
74 MODULE_PARM_DESC(bad_frames_preempt,
75 "enable(1) / disable(0) Bad Frames Preemption");
76
77 static char modparam_fwpostfix[16];
78 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
79 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
80
81 static int modparam_hwpctl;
82 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
83 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
84
85 static int modparam_nohwcrypt;
86 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
87 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
88
89 static int modparam_hwtkip;
90 module_param_named(hwtkip, modparam_hwtkip, int, 0444);
91 MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
92
93 static int modparam_qos = 1;
94 module_param_named(qos, modparam_qos, int, 0444);
95 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
96
97 static int modparam_btcoex = 1;
98 module_param_named(btcoex, modparam_btcoex, int, 0444);
99 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
100
101 int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
102 module_param_named(verbose, b43_modparam_verbose, int, 0644);
103 MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
104
105
106 static const struct ssb_device_id b43_ssb_tbl[] = {
107 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
108 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
109 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
110 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
111 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
112 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
113 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
114 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
115 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
116 SSB_DEVTABLE_END
117 };
118
119 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
120
121 /* Channel and ratetables are shared for all devices.
122 * They can't be const, because ieee80211 puts some precalculated
123 * data in there. This data is the same for all devices, so we don't
124 * get concurrency issues */
125 #define RATETAB_ENT(_rateid, _flags) \
126 { \
127 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
128 .hw_value = (_rateid), \
129 .flags = (_flags), \
130 }
131
132 /*
133 * NOTE: When changing this, sync with xmit.c's
134 * b43_plcp_get_bitrate_idx_* functions!
135 */
136 static struct ieee80211_rate __b43_ratetable[] = {
137 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
138 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
139 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
140 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
141 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
142 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
143 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
144 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
145 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
146 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
147 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
148 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
149 };
150
151 #define b43_a_ratetable (__b43_ratetable + 4)
152 #define b43_a_ratetable_size 8
153 #define b43_b_ratetable (__b43_ratetable + 0)
154 #define b43_b_ratetable_size 4
155 #define b43_g_ratetable (__b43_ratetable + 0)
156 #define b43_g_ratetable_size 12
157
158 #define CHAN4G(_channel, _freq, _flags) { \
159 .band = IEEE80211_BAND_2GHZ, \
160 .center_freq = (_freq), \
161 .hw_value = (_channel), \
162 .flags = (_flags), \
163 .max_antenna_gain = 0, \
164 .max_power = 30, \
165 }
166 static struct ieee80211_channel b43_2ghz_chantable[] = {
167 CHAN4G(1, 2412, 0),
168 CHAN4G(2, 2417, 0),
169 CHAN4G(3, 2422, 0),
170 CHAN4G(4, 2427, 0),
171 CHAN4G(5, 2432, 0),
172 CHAN4G(6, 2437, 0),
173 CHAN4G(7, 2442, 0),
174 CHAN4G(8, 2447, 0),
175 CHAN4G(9, 2452, 0),
176 CHAN4G(10, 2457, 0),
177 CHAN4G(11, 2462, 0),
178 CHAN4G(12, 2467, 0),
179 CHAN4G(13, 2472, 0),
180 CHAN4G(14, 2484, 0),
181 };
182 #undef CHAN4G
183
184 #define CHAN5G(_channel, _flags) { \
185 .band = IEEE80211_BAND_5GHZ, \
186 .center_freq = 5000 + (5 * (_channel)), \
187 .hw_value = (_channel), \
188 .flags = (_flags), \
189 .max_antenna_gain = 0, \
190 .max_power = 30, \
191 }
192 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
193 CHAN5G(32, 0), CHAN5G(34, 0),
194 CHAN5G(36, 0), CHAN5G(38, 0),
195 CHAN5G(40, 0), CHAN5G(42, 0),
196 CHAN5G(44, 0), CHAN5G(46, 0),
197 CHAN5G(48, 0), CHAN5G(50, 0),
198 CHAN5G(52, 0), CHAN5G(54, 0),
199 CHAN5G(56, 0), CHAN5G(58, 0),
200 CHAN5G(60, 0), CHAN5G(62, 0),
201 CHAN5G(64, 0), CHAN5G(66, 0),
202 CHAN5G(68, 0), CHAN5G(70, 0),
203 CHAN5G(72, 0), CHAN5G(74, 0),
204 CHAN5G(76, 0), CHAN5G(78, 0),
205 CHAN5G(80, 0), CHAN5G(82, 0),
206 CHAN5G(84, 0), CHAN5G(86, 0),
207 CHAN5G(88, 0), CHAN5G(90, 0),
208 CHAN5G(92, 0), CHAN5G(94, 0),
209 CHAN5G(96, 0), CHAN5G(98, 0),
210 CHAN5G(100, 0), CHAN5G(102, 0),
211 CHAN5G(104, 0), CHAN5G(106, 0),
212 CHAN5G(108, 0), CHAN5G(110, 0),
213 CHAN5G(112, 0), CHAN5G(114, 0),
214 CHAN5G(116, 0), CHAN5G(118, 0),
215 CHAN5G(120, 0), CHAN5G(122, 0),
216 CHAN5G(124, 0), CHAN5G(126, 0),
217 CHAN5G(128, 0), CHAN5G(130, 0),
218 CHAN5G(132, 0), CHAN5G(134, 0),
219 CHAN5G(136, 0), CHAN5G(138, 0),
220 CHAN5G(140, 0), CHAN5G(142, 0),
221 CHAN5G(144, 0), CHAN5G(145, 0),
222 CHAN5G(146, 0), CHAN5G(147, 0),
223 CHAN5G(148, 0), CHAN5G(149, 0),
224 CHAN5G(150, 0), CHAN5G(151, 0),
225 CHAN5G(152, 0), CHAN5G(153, 0),
226 CHAN5G(154, 0), CHAN5G(155, 0),
227 CHAN5G(156, 0), CHAN5G(157, 0),
228 CHAN5G(158, 0), CHAN5G(159, 0),
229 CHAN5G(160, 0), CHAN5G(161, 0),
230 CHAN5G(162, 0), CHAN5G(163, 0),
231 CHAN5G(164, 0), CHAN5G(165, 0),
232 CHAN5G(166, 0), CHAN5G(168, 0),
233 CHAN5G(170, 0), CHAN5G(172, 0),
234 CHAN5G(174, 0), CHAN5G(176, 0),
235 CHAN5G(178, 0), CHAN5G(180, 0),
236 CHAN5G(182, 0), CHAN5G(184, 0),
237 CHAN5G(186, 0), CHAN5G(188, 0),
238 CHAN5G(190, 0), CHAN5G(192, 0),
239 CHAN5G(194, 0), CHAN5G(196, 0),
240 CHAN5G(198, 0), CHAN5G(200, 0),
241 CHAN5G(202, 0), CHAN5G(204, 0),
242 CHAN5G(206, 0), CHAN5G(208, 0),
243 CHAN5G(210, 0), CHAN5G(212, 0),
244 CHAN5G(214, 0), CHAN5G(216, 0),
245 CHAN5G(218, 0), CHAN5G(220, 0),
246 CHAN5G(222, 0), CHAN5G(224, 0),
247 CHAN5G(226, 0), CHAN5G(228, 0),
248 };
249
250 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
251 CHAN5G(34, 0), CHAN5G(36, 0),
252 CHAN5G(38, 0), CHAN5G(40, 0),
253 CHAN5G(42, 0), CHAN5G(44, 0),
254 CHAN5G(46, 0), CHAN5G(48, 0),
255 CHAN5G(52, 0), CHAN5G(56, 0),
256 CHAN5G(60, 0), CHAN5G(64, 0),
257 CHAN5G(100, 0), CHAN5G(104, 0),
258 CHAN5G(108, 0), CHAN5G(112, 0),
259 CHAN5G(116, 0), CHAN5G(120, 0),
260 CHAN5G(124, 0), CHAN5G(128, 0),
261 CHAN5G(132, 0), CHAN5G(136, 0),
262 CHAN5G(140, 0), CHAN5G(149, 0),
263 CHAN5G(153, 0), CHAN5G(157, 0),
264 CHAN5G(161, 0), CHAN5G(165, 0),
265 CHAN5G(184, 0), CHAN5G(188, 0),
266 CHAN5G(192, 0), CHAN5G(196, 0),
267 CHAN5G(200, 0), CHAN5G(204, 0),
268 CHAN5G(208, 0), CHAN5G(212, 0),
269 CHAN5G(216, 0),
270 };
271 #undef CHAN5G
272
273 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
274 .band = IEEE80211_BAND_5GHZ,
275 .channels = b43_5ghz_nphy_chantable,
276 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
277 .bitrates = b43_a_ratetable,
278 .n_bitrates = b43_a_ratetable_size,
279 };
280
281 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
282 .band = IEEE80211_BAND_5GHZ,
283 .channels = b43_5ghz_aphy_chantable,
284 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
285 .bitrates = b43_a_ratetable,
286 .n_bitrates = b43_a_ratetable_size,
287 };
288
289 static struct ieee80211_supported_band b43_band_2GHz = {
290 .band = IEEE80211_BAND_2GHZ,
291 .channels = b43_2ghz_chantable,
292 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
293 .bitrates = b43_g_ratetable,
294 .n_bitrates = b43_g_ratetable_size,
295 };
296
297 static void b43_wireless_core_exit(struct b43_wldev *dev);
298 static int b43_wireless_core_init(struct b43_wldev *dev);
299 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
300 static int b43_wireless_core_start(struct b43_wldev *dev);
301
302 static int b43_ratelimit(struct b43_wl *wl)
303 {
304 if (!wl || !wl->current_dev)
305 return 1;
306 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
307 return 1;
308 /* We are up and running.
309 * Ratelimit the messages to avoid DoS over the net. */
310 return net_ratelimit();
311 }
312
313 void b43info(struct b43_wl *wl, const char *fmt, ...)
314 {
315 va_list args;
316
317 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
318 return;
319 if (!b43_ratelimit(wl))
320 return;
321 va_start(args, fmt);
322 printk(KERN_INFO "b43-%s: ",
323 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
324 vprintk(fmt, args);
325 va_end(args);
326 }
327
328 void b43err(struct b43_wl *wl, const char *fmt, ...)
329 {
330 va_list args;
331
332 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
333 return;
334 if (!b43_ratelimit(wl))
335 return;
336 va_start(args, fmt);
337 printk(KERN_ERR "b43-%s ERROR: ",
338 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
339 vprintk(fmt, args);
340 va_end(args);
341 }
342
343 void b43warn(struct b43_wl *wl, const char *fmt, ...)
344 {
345 va_list args;
346
347 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
348 return;
349 if (!b43_ratelimit(wl))
350 return;
351 va_start(args, fmt);
352 printk(KERN_WARNING "b43-%s warning: ",
353 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
354 vprintk(fmt, args);
355 va_end(args);
356 }
357
358 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
359 {
360 va_list args;
361
362 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
363 return;
364 va_start(args, fmt);
365 printk(KERN_DEBUG "b43-%s debug: ",
366 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
367 vprintk(fmt, args);
368 va_end(args);
369 }
370
371 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
372 {
373 u32 macctl;
374
375 B43_WARN_ON(offset % 4 != 0);
376
377 macctl = b43_read32(dev, B43_MMIO_MACCTL);
378 if (macctl & B43_MACCTL_BE)
379 val = swab32(val);
380
381 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
382 mmiowb();
383 b43_write32(dev, B43_MMIO_RAM_DATA, val);
384 }
385
386 static inline void b43_shm_control_word(struct b43_wldev *dev,
387 u16 routing, u16 offset)
388 {
389 u32 control;
390
391 /* "offset" is the WORD offset. */
392 control = routing;
393 control <<= 16;
394 control |= offset;
395 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
396 }
397
398 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
399 {
400 u32 ret;
401
402 if (routing == B43_SHM_SHARED) {
403 B43_WARN_ON(offset & 0x0001);
404 if (offset & 0x0003) {
405 /* Unaligned access */
406 b43_shm_control_word(dev, routing, offset >> 2);
407 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
408 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
409 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
410
411 goto out;
412 }
413 offset >>= 2;
414 }
415 b43_shm_control_word(dev, routing, offset);
416 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
417 out:
418 return ret;
419 }
420
421 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
422 {
423 u16 ret;
424
425 if (routing == B43_SHM_SHARED) {
426 B43_WARN_ON(offset & 0x0001);
427 if (offset & 0x0003) {
428 /* Unaligned access */
429 b43_shm_control_word(dev, routing, offset >> 2);
430 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
431
432 goto out;
433 }
434 offset >>= 2;
435 }
436 b43_shm_control_word(dev, routing, offset);
437 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
438 out:
439 return ret;
440 }
441
442 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
443 {
444 if (routing == B43_SHM_SHARED) {
445 B43_WARN_ON(offset & 0x0001);
446 if (offset & 0x0003) {
447 /* Unaligned access */
448 b43_shm_control_word(dev, routing, offset >> 2);
449 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
450 value & 0xFFFF);
451 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
452 b43_write16(dev, B43_MMIO_SHM_DATA,
453 (value >> 16) & 0xFFFF);
454 return;
455 }
456 offset >>= 2;
457 }
458 b43_shm_control_word(dev, routing, offset);
459 b43_write32(dev, B43_MMIO_SHM_DATA, value);
460 }
461
462 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
463 {
464 if (routing == B43_SHM_SHARED) {
465 B43_WARN_ON(offset & 0x0001);
466 if (offset & 0x0003) {
467 /* Unaligned access */
468 b43_shm_control_word(dev, routing, offset >> 2);
469 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
470 return;
471 }
472 offset >>= 2;
473 }
474 b43_shm_control_word(dev, routing, offset);
475 b43_write16(dev, B43_MMIO_SHM_DATA, value);
476 }
477
478 /* Read HostFlags */
479 u64 b43_hf_read(struct b43_wldev *dev)
480 {
481 u64 ret;
482
483 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
484 ret <<= 16;
485 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
486 ret <<= 16;
487 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
488
489 return ret;
490 }
491
492 /* Write HostFlags */
493 void b43_hf_write(struct b43_wldev *dev, u64 value)
494 {
495 u16 lo, mi, hi;
496
497 lo = (value & 0x00000000FFFFULL);
498 mi = (value & 0x0000FFFF0000ULL) >> 16;
499 hi = (value & 0xFFFF00000000ULL) >> 32;
500 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
501 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
502 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
503 }
504
505 /* Read the firmware capabilities bitmask (Opensource firmware only) */
506 static u16 b43_fwcapa_read(struct b43_wldev *dev)
507 {
508 B43_WARN_ON(!dev->fw.opensource);
509 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
510 }
511
512 void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
513 {
514 u32 low, high;
515
516 B43_WARN_ON(dev->dev->id.revision < 3);
517
518 /* The hardware guarantees us an atomic read, if we
519 * read the low register first. */
520 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
521 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
522
523 *tsf = high;
524 *tsf <<= 32;
525 *tsf |= low;
526 }
527
528 static void b43_time_lock(struct b43_wldev *dev)
529 {
530 u32 macctl;
531
532 macctl = b43_read32(dev, B43_MMIO_MACCTL);
533 macctl |= B43_MACCTL_TBTTHOLD;
534 b43_write32(dev, B43_MMIO_MACCTL, macctl);
535 /* Commit the write */
536 b43_read32(dev, B43_MMIO_MACCTL);
537 }
538
539 static void b43_time_unlock(struct b43_wldev *dev)
540 {
541 u32 macctl;
542
543 macctl = b43_read32(dev, B43_MMIO_MACCTL);
544 macctl &= ~B43_MACCTL_TBTTHOLD;
545 b43_write32(dev, B43_MMIO_MACCTL, macctl);
546 /* Commit the write */
547 b43_read32(dev, B43_MMIO_MACCTL);
548 }
549
550 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
551 {
552 u32 low, high;
553
554 B43_WARN_ON(dev->dev->id.revision < 3);
555
556 low = tsf;
557 high = (tsf >> 32);
558 /* The hardware guarantees us an atomic write, if we
559 * write the low register first. */
560 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
561 mmiowb();
562 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
563 mmiowb();
564 }
565
566 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
567 {
568 b43_time_lock(dev);
569 b43_tsf_write_locked(dev, tsf);
570 b43_time_unlock(dev);
571 }
572
573 static
574 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
575 {
576 static const u8 zero_addr[ETH_ALEN] = { 0 };
577 u16 data;
578
579 if (!mac)
580 mac = zero_addr;
581
582 offset |= 0x0020;
583 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
584
585 data = mac[0];
586 data |= mac[1] << 8;
587 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
588 data = mac[2];
589 data |= mac[3] << 8;
590 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
591 data = mac[4];
592 data |= mac[5] << 8;
593 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
594 }
595
596 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
597 {
598 const u8 *mac;
599 const u8 *bssid;
600 u8 mac_bssid[ETH_ALEN * 2];
601 int i;
602 u32 tmp;
603
604 bssid = dev->wl->bssid;
605 mac = dev->wl->mac_addr;
606
607 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
608
609 memcpy(mac_bssid, mac, ETH_ALEN);
610 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
611
612 /* Write our MAC address and BSSID to template ram */
613 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
614 tmp = (u32) (mac_bssid[i + 0]);
615 tmp |= (u32) (mac_bssid[i + 1]) << 8;
616 tmp |= (u32) (mac_bssid[i + 2]) << 16;
617 tmp |= (u32) (mac_bssid[i + 3]) << 24;
618 b43_ram_write(dev, 0x20 + i, tmp);
619 }
620 }
621
622 static void b43_upload_card_macaddress(struct b43_wldev *dev)
623 {
624 b43_write_mac_bssid_templates(dev);
625 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
626 }
627
628 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
629 {
630 /* slot_time is in usec. */
631 /* This test used to exit for all but a G PHY. */
632 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
633 return;
634 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
635 /* Shared memory location 0x0010 is the slot time and should be
636 * set to slot_time; however, this register is initially 0 and changing
637 * the value adversely affects the transmit rate for BCM4311
638 * devices. Until this behavior is unterstood, delete this step
639 *
640 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
641 */
642 }
643
644 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
645 {
646 b43_set_slot_time(dev, 9);
647 }
648
649 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
650 {
651 b43_set_slot_time(dev, 20);
652 }
653
654 /* DummyTransmission function, as documented on
655 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
656 */
657 void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
658 {
659 struct b43_phy *phy = &dev->phy;
660 unsigned int i, max_loop;
661 u16 value;
662 u32 buffer[5] = {
663 0x00000000,
664 0x00D40000,
665 0x00000000,
666 0x01000000,
667 0x00000000,
668 };
669
670 if (ofdm) {
671 max_loop = 0x1E;
672 buffer[0] = 0x000201CC;
673 } else {
674 max_loop = 0xFA;
675 buffer[0] = 0x000B846E;
676 }
677
678 for (i = 0; i < 5; i++)
679 b43_ram_write(dev, i * 4, buffer[i]);
680
681 b43_write16(dev, 0x0568, 0x0000);
682 if (dev->dev->id.revision < 11)
683 b43_write16(dev, 0x07C0, 0x0000);
684 else
685 b43_write16(dev, 0x07C0, 0x0100);
686 value = (ofdm ? 0x41 : 0x40);
687 b43_write16(dev, 0x050C, value);
688 if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP))
689 b43_write16(dev, 0x0514, 0x1A02);
690 b43_write16(dev, 0x0508, 0x0000);
691 b43_write16(dev, 0x050A, 0x0000);
692 b43_write16(dev, 0x054C, 0x0000);
693 b43_write16(dev, 0x056A, 0x0014);
694 b43_write16(dev, 0x0568, 0x0826);
695 b43_write16(dev, 0x0500, 0x0000);
696 if (!pa_on && (phy->type == B43_PHYTYPE_N)) {
697 //SPEC TODO
698 }
699
700 switch (phy->type) {
701 case B43_PHYTYPE_N:
702 b43_write16(dev, 0x0502, 0x00D0);
703 break;
704 case B43_PHYTYPE_LP:
705 b43_write16(dev, 0x0502, 0x0050);
706 break;
707 default:
708 b43_write16(dev, 0x0502, 0x0030);
709 }
710
711 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
712 b43_radio_write16(dev, 0x0051, 0x0017);
713 for (i = 0x00; i < max_loop; i++) {
714 value = b43_read16(dev, 0x050E);
715 if (value & 0x0080)
716 break;
717 udelay(10);
718 }
719 for (i = 0x00; i < 0x0A; i++) {
720 value = b43_read16(dev, 0x050E);
721 if (value & 0x0400)
722 break;
723 udelay(10);
724 }
725 for (i = 0x00; i < 0x19; i++) {
726 value = b43_read16(dev, 0x0690);
727 if (!(value & 0x0100))
728 break;
729 udelay(10);
730 }
731 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
732 b43_radio_write16(dev, 0x0051, 0x0037);
733 }
734
735 static void key_write(struct b43_wldev *dev,
736 u8 index, u8 algorithm, const u8 *key)
737 {
738 unsigned int i;
739 u32 offset;
740 u16 value;
741 u16 kidx;
742
743 /* Key index/algo block */
744 kidx = b43_kidx_to_fw(dev, index);
745 value = ((kidx << 4) | algorithm);
746 b43_shm_write16(dev, B43_SHM_SHARED,
747 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
748
749 /* Write the key to the Key Table Pointer offset */
750 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
751 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
752 value = key[i];
753 value |= (u16) (key[i + 1]) << 8;
754 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
755 }
756 }
757
758 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
759 {
760 u32 addrtmp[2] = { 0, 0, };
761 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
762
763 if (b43_new_kidx_api(dev))
764 pairwise_keys_start = B43_NR_GROUP_KEYS;
765
766 B43_WARN_ON(index < pairwise_keys_start);
767 /* We have four default TX keys and possibly four default RX keys.
768 * Physical mac 0 is mapped to physical key 4 or 8, depending
769 * on the firmware version.
770 * So we must adjust the index here.
771 */
772 index -= pairwise_keys_start;
773 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
774
775 if (addr) {
776 addrtmp[0] = addr[0];
777 addrtmp[0] |= ((u32) (addr[1]) << 8);
778 addrtmp[0] |= ((u32) (addr[2]) << 16);
779 addrtmp[0] |= ((u32) (addr[3]) << 24);
780 addrtmp[1] = addr[4];
781 addrtmp[1] |= ((u32) (addr[5]) << 8);
782 }
783
784 /* Receive match transmitter address (RCMTA) mechanism */
785 b43_shm_write32(dev, B43_SHM_RCMTA,
786 (index * 2) + 0, addrtmp[0]);
787 b43_shm_write16(dev, B43_SHM_RCMTA,
788 (index * 2) + 1, addrtmp[1]);
789 }
790
791 /* The ucode will use phase1 key with TEK key to decrypt rx packets.
792 * When a packet is received, the iv32 is checked.
793 * - if it doesn't the packet is returned without modification (and software
794 * decryption can be done). That's what happen when iv16 wrap.
795 * - if it does, the rc4 key is computed, and decryption is tried.
796 * Either it will success and B43_RX_MAC_DEC is returned,
797 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
798 * and the packet is not usable (it got modified by the ucode).
799 * So in order to never have B43_RX_MAC_DECERR, we should provide
800 * a iv32 and phase1key that match. Because we drop packets in case of
801 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
802 * packets will be lost without higher layer knowing (ie no resync possible
803 * until next wrap).
804 *
805 * NOTE : this should support 50 key like RCMTA because
806 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
807 */
808 static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
809 u16 *phase1key)
810 {
811 unsigned int i;
812 u32 offset;
813 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
814
815 if (!modparam_hwtkip)
816 return;
817
818 if (b43_new_kidx_api(dev))
819 pairwise_keys_start = B43_NR_GROUP_KEYS;
820
821 B43_WARN_ON(index < pairwise_keys_start);
822 /* We have four default TX keys and possibly four default RX keys.
823 * Physical mac 0 is mapped to physical key 4 or 8, depending
824 * on the firmware version.
825 * So we must adjust the index here.
826 */
827 index -= pairwise_keys_start;
828 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
829
830 if (b43_debug(dev, B43_DBG_KEYS)) {
831 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
832 index, iv32);
833 }
834 /* Write the key to the RX tkip shared mem */
835 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
836 for (i = 0; i < 10; i += 2) {
837 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
838 phase1key ? phase1key[i / 2] : 0);
839 }
840 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
841 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
842 }
843
844 static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
845 struct ieee80211_key_conf *keyconf, const u8 *addr,
846 u32 iv32, u16 *phase1key)
847 {
848 struct b43_wl *wl = hw_to_b43_wl(hw);
849 struct b43_wldev *dev;
850 int index = keyconf->hw_key_idx;
851
852 if (B43_WARN_ON(!modparam_hwtkip))
853 return;
854
855 /* This is only called from the RX path through mac80211, where
856 * our mutex is already locked. */
857 B43_WARN_ON(!mutex_is_locked(&wl->mutex));
858 dev = wl->current_dev;
859 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
860
861 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
862
863 rx_tkip_phase1_write(dev, index, iv32, phase1key);
864 keymac_write(dev, index, addr);
865 }
866
867 static void do_key_write(struct b43_wldev *dev,
868 u8 index, u8 algorithm,
869 const u8 *key, size_t key_len, const u8 *mac_addr)
870 {
871 u8 buf[B43_SEC_KEYSIZE] = { 0, };
872 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
873
874 if (b43_new_kidx_api(dev))
875 pairwise_keys_start = B43_NR_GROUP_KEYS;
876
877 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
878 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
879
880 if (index >= pairwise_keys_start)
881 keymac_write(dev, index, NULL); /* First zero out mac. */
882 if (algorithm == B43_SEC_ALGO_TKIP) {
883 /*
884 * We should provide an initial iv32, phase1key pair.
885 * We could start with iv32=0 and compute the corresponding
886 * phase1key, but this means calling ieee80211_get_tkip_key
887 * with a fake skb (or export other tkip function).
888 * Because we are lazy we hope iv32 won't start with
889 * 0xffffffff and let's b43_op_update_tkip_key provide a
890 * correct pair.
891 */
892 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
893 } else if (index >= pairwise_keys_start) /* clear it */
894 rx_tkip_phase1_write(dev, index, 0, NULL);
895 if (key)
896 memcpy(buf, key, key_len);
897 key_write(dev, index, algorithm, buf);
898 if (index >= pairwise_keys_start)
899 keymac_write(dev, index, mac_addr);
900
901 dev->key[index].algorithm = algorithm;
902 }
903
904 static int b43_key_write(struct b43_wldev *dev,
905 int index, u8 algorithm,
906 const u8 *key, size_t key_len,
907 const u8 *mac_addr,
908 struct ieee80211_key_conf *keyconf)
909 {
910 int i;
911 int pairwise_keys_start;
912
913 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
914 * - Temporal Encryption Key (128 bits)
915 * - Temporal Authenticator Tx MIC Key (64 bits)
916 * - Temporal Authenticator Rx MIC Key (64 bits)
917 *
918 * Hardware only store TEK
919 */
920 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
921 key_len = 16;
922 if (key_len > B43_SEC_KEYSIZE)
923 return -EINVAL;
924 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
925 /* Check that we don't already have this key. */
926 B43_WARN_ON(dev->key[i].keyconf == keyconf);
927 }
928 if (index < 0) {
929 /* Pairwise key. Get an empty slot for the key. */
930 if (b43_new_kidx_api(dev))
931 pairwise_keys_start = B43_NR_GROUP_KEYS;
932 else
933 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
934 for (i = pairwise_keys_start;
935 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
936 i++) {
937 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
938 if (!dev->key[i].keyconf) {
939 /* found empty */
940 index = i;
941 break;
942 }
943 }
944 if (index < 0) {
945 b43warn(dev->wl, "Out of hardware key memory\n");
946 return -ENOSPC;
947 }
948 } else
949 B43_WARN_ON(index > 3);
950
951 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
952 if ((index <= 3) && !b43_new_kidx_api(dev)) {
953 /* Default RX key */
954 B43_WARN_ON(mac_addr);
955 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
956 }
957 keyconf->hw_key_idx = index;
958 dev->key[index].keyconf = keyconf;
959
960 return 0;
961 }
962
963 static int b43_key_clear(struct b43_wldev *dev, int index)
964 {
965 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
966 return -EINVAL;
967 do_key_write(dev, index, B43_SEC_ALGO_NONE,
968 NULL, B43_SEC_KEYSIZE, NULL);
969 if ((index <= 3) && !b43_new_kidx_api(dev)) {
970 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
971 NULL, B43_SEC_KEYSIZE, NULL);
972 }
973 dev->key[index].keyconf = NULL;
974
975 return 0;
976 }
977
978 static void b43_clear_keys(struct b43_wldev *dev)
979 {
980 int i, count;
981
982 if (b43_new_kidx_api(dev))
983 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
984 else
985 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
986 for (i = 0; i < count; i++)
987 b43_key_clear(dev, i);
988 }
989
990 static void b43_dump_keymemory(struct b43_wldev *dev)
991 {
992 unsigned int i, index, count, offset, pairwise_keys_start;
993 u8 mac[ETH_ALEN];
994 u16 algo;
995 u32 rcmta0;
996 u16 rcmta1;
997 u64 hf;
998 struct b43_key *key;
999
1000 if (!b43_debug(dev, B43_DBG_KEYS))
1001 return;
1002
1003 hf = b43_hf_read(dev);
1004 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1005 !!(hf & B43_HF_USEDEFKEYS));
1006 if (b43_new_kidx_api(dev)) {
1007 pairwise_keys_start = B43_NR_GROUP_KEYS;
1008 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1009 } else {
1010 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1011 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1012 }
1013 for (index = 0; index < count; index++) {
1014 key = &(dev->key[index]);
1015 printk(KERN_DEBUG "Key slot %02u: %s",
1016 index, (key->keyconf == NULL) ? " " : "*");
1017 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1018 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1019 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1020 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1021 }
1022
1023 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1024 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1025 printk(" Algo: %04X/%02X", algo, key->algorithm);
1026
1027 if (index >= pairwise_keys_start) {
1028 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1029 printk(" TKIP: ");
1030 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1031 for (i = 0; i < 14; i += 2) {
1032 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1033 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1034 }
1035 }
1036 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
1037 ((index - pairwise_keys_start) * 2) + 0);
1038 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
1039 ((index - pairwise_keys_start) * 2) + 1);
1040 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1041 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
1042 printk(" MAC: %pM", mac);
1043 } else
1044 printk(" DEFAULT KEY");
1045 printk("\n");
1046 }
1047 }
1048
1049 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1050 {
1051 u32 macctl;
1052 u16 ucstat;
1053 bool hwps;
1054 bool awake;
1055 int i;
1056
1057 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1058 (ps_flags & B43_PS_DISABLED));
1059 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1060
1061 if (ps_flags & B43_PS_ENABLED) {
1062 hwps = 1;
1063 } else if (ps_flags & B43_PS_DISABLED) {
1064 hwps = 0;
1065 } else {
1066 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1067 // and thus is not an AP and we are associated, set bit 25
1068 }
1069 if (ps_flags & B43_PS_AWAKE) {
1070 awake = 1;
1071 } else if (ps_flags & B43_PS_ASLEEP) {
1072 awake = 0;
1073 } else {
1074 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1075 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1076 // successful, set bit26
1077 }
1078
1079 /* FIXME: For now we force awake-on and hwps-off */
1080 hwps = 0;
1081 awake = 1;
1082
1083 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1084 if (hwps)
1085 macctl |= B43_MACCTL_HWPS;
1086 else
1087 macctl &= ~B43_MACCTL_HWPS;
1088 if (awake)
1089 macctl |= B43_MACCTL_AWAKE;
1090 else
1091 macctl &= ~B43_MACCTL_AWAKE;
1092 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1093 /* Commit write */
1094 b43_read32(dev, B43_MMIO_MACCTL);
1095 if (awake && dev->dev->id.revision >= 5) {
1096 /* Wait for the microcode to wake up. */
1097 for (i = 0; i < 100; i++) {
1098 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1099 B43_SHM_SH_UCODESTAT);
1100 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1101 break;
1102 udelay(10);
1103 }
1104 }
1105 }
1106
1107 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1108 {
1109 u32 tmslow;
1110 u32 macctl;
1111
1112 flags |= B43_TMSLOW_PHYCLKEN;
1113 flags |= B43_TMSLOW_PHYRESET;
1114 ssb_device_enable(dev->dev, flags);
1115 msleep(2); /* Wait for the PLL to turn on. */
1116
1117 /* Now take the PHY out of Reset again */
1118 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1119 tmslow |= SSB_TMSLOW_FGC;
1120 tmslow &= ~B43_TMSLOW_PHYRESET;
1121 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1122 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1123 msleep(1);
1124 tmslow &= ~SSB_TMSLOW_FGC;
1125 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1126 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1127 msleep(1);
1128
1129 /* Turn Analog ON, but only if we already know the PHY-type.
1130 * This protects against very early setup where we don't know the
1131 * PHY-type, yet. wireless_core_reset will be called once again later,
1132 * when we know the PHY-type. */
1133 if (dev->phy.ops)
1134 dev->phy.ops->switch_analog(dev, 1);
1135
1136 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1137 macctl &= ~B43_MACCTL_GMODE;
1138 if (flags & B43_TMSLOW_GMODE)
1139 macctl |= B43_MACCTL_GMODE;
1140 macctl |= B43_MACCTL_IHR_ENABLED;
1141 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1142 }
1143
1144 static void handle_irq_transmit_status(struct b43_wldev *dev)
1145 {
1146 u32 v0, v1;
1147 u16 tmp;
1148 struct b43_txstatus stat;
1149
1150 while (1) {
1151 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1152 if (!(v0 & 0x00000001))
1153 break;
1154 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1155
1156 stat.cookie = (v0 >> 16);
1157 stat.seq = (v1 & 0x0000FFFF);
1158 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1159 tmp = (v0 & 0x0000FFFF);
1160 stat.frame_count = ((tmp & 0xF000) >> 12);
1161 stat.rts_count = ((tmp & 0x0F00) >> 8);
1162 stat.supp_reason = ((tmp & 0x001C) >> 2);
1163 stat.pm_indicated = !!(tmp & 0x0080);
1164 stat.intermediate = !!(tmp & 0x0040);
1165 stat.for_ampdu = !!(tmp & 0x0020);
1166 stat.acked = !!(tmp & 0x0002);
1167
1168 b43_handle_txstatus(dev, &stat);
1169 }
1170 }
1171
1172 static void drain_txstatus_queue(struct b43_wldev *dev)
1173 {
1174 u32 dummy;
1175
1176 if (dev->dev->id.revision < 5)
1177 return;
1178 /* Read all entries from the microcode TXstatus FIFO
1179 * and throw them away.
1180 */
1181 while (1) {
1182 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1183 if (!(dummy & 0x00000001))
1184 break;
1185 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1186 }
1187 }
1188
1189 static u32 b43_jssi_read(struct b43_wldev *dev)
1190 {
1191 u32 val = 0;
1192
1193 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1194 val <<= 16;
1195 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1196
1197 return val;
1198 }
1199
1200 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1201 {
1202 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1203 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1204 }
1205
1206 static void b43_generate_noise_sample(struct b43_wldev *dev)
1207 {
1208 b43_jssi_write(dev, 0x7F7F7F7F);
1209 b43_write32(dev, B43_MMIO_MACCMD,
1210 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1211 }
1212
1213 static void b43_calculate_link_quality(struct b43_wldev *dev)
1214 {
1215 /* Top half of Link Quality calculation. */
1216
1217 if (dev->phy.type != B43_PHYTYPE_G)
1218 return;
1219 if (dev->noisecalc.calculation_running)
1220 return;
1221 dev->noisecalc.calculation_running = 1;
1222 dev->noisecalc.nr_samples = 0;
1223
1224 b43_generate_noise_sample(dev);
1225 }
1226
1227 static void handle_irq_noise(struct b43_wldev *dev)
1228 {
1229 struct b43_phy_g *phy = dev->phy.g;
1230 u16 tmp;
1231 u8 noise[4];
1232 u8 i, j;
1233 s32 average;
1234
1235 /* Bottom half of Link Quality calculation. */
1236
1237 if (dev->phy.type != B43_PHYTYPE_G)
1238 return;
1239
1240 /* Possible race condition: It might be possible that the user
1241 * changed to a different channel in the meantime since we
1242 * started the calculation. We ignore that fact, since it's
1243 * not really that much of a problem. The background noise is
1244 * an estimation only anyway. Slightly wrong results will get damped
1245 * by the averaging of the 8 sample rounds. Additionally the
1246 * value is shortlived. So it will be replaced by the next noise
1247 * calculation round soon. */
1248
1249 B43_WARN_ON(!dev->noisecalc.calculation_running);
1250 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1251 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1252 noise[2] == 0x7F || noise[3] == 0x7F)
1253 goto generate_new;
1254
1255 /* Get the noise samples. */
1256 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1257 i = dev->noisecalc.nr_samples;
1258 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1259 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1260 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1261 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1262 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1263 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1264 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1265 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1266 dev->noisecalc.nr_samples++;
1267 if (dev->noisecalc.nr_samples == 8) {
1268 /* Calculate the Link Quality by the noise samples. */
1269 average = 0;
1270 for (i = 0; i < 8; i++) {
1271 for (j = 0; j < 4; j++)
1272 average += dev->noisecalc.samples[i][j];
1273 }
1274 average /= (8 * 4);
1275 average *= 125;
1276 average += 64;
1277 average /= 128;
1278 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1279 tmp = (tmp / 128) & 0x1F;
1280 if (tmp >= 8)
1281 average += 2;
1282 else
1283 average -= 25;
1284 if (tmp == 8)
1285 average -= 72;
1286 else
1287 average -= 48;
1288
1289 dev->stats.link_noise = average;
1290 dev->noisecalc.calculation_running = 0;
1291 return;
1292 }
1293 generate_new:
1294 b43_generate_noise_sample(dev);
1295 }
1296
1297 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1298 {
1299 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1300 ///TODO: PS TBTT
1301 } else {
1302 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1303 b43_power_saving_ctl_bits(dev, 0);
1304 }
1305 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1306 dev->dfq_valid = 1;
1307 }
1308
1309 static void handle_irq_atim_end(struct b43_wldev *dev)
1310 {
1311 if (dev->dfq_valid) {
1312 b43_write32(dev, B43_MMIO_MACCMD,
1313 b43_read32(dev, B43_MMIO_MACCMD)
1314 | B43_MACCMD_DFQ_VALID);
1315 dev->dfq_valid = 0;
1316 }
1317 }
1318
1319 static void handle_irq_pmq(struct b43_wldev *dev)
1320 {
1321 u32 tmp;
1322
1323 //TODO: AP mode.
1324
1325 while (1) {
1326 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1327 if (!(tmp & 0x00000008))
1328 break;
1329 }
1330 /* 16bit write is odd, but correct. */
1331 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1332 }
1333
1334 static void b43_write_template_common(struct b43_wldev *dev,
1335 const u8 *data, u16 size,
1336 u16 ram_offset,
1337 u16 shm_size_offset, u8 rate)
1338 {
1339 u32 i, tmp;
1340 struct b43_plcp_hdr4 plcp;
1341
1342 plcp.data = 0;
1343 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1344 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1345 ram_offset += sizeof(u32);
1346 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1347 * So leave the first two bytes of the next write blank.
1348 */
1349 tmp = (u32) (data[0]) << 16;
1350 tmp |= (u32) (data[1]) << 24;
1351 b43_ram_write(dev, ram_offset, tmp);
1352 ram_offset += sizeof(u32);
1353 for (i = 2; i < size; i += sizeof(u32)) {
1354 tmp = (u32) (data[i + 0]);
1355 if (i + 1 < size)
1356 tmp |= (u32) (data[i + 1]) << 8;
1357 if (i + 2 < size)
1358 tmp |= (u32) (data[i + 2]) << 16;
1359 if (i + 3 < size)
1360 tmp |= (u32) (data[i + 3]) << 24;
1361 b43_ram_write(dev, ram_offset + i - 2, tmp);
1362 }
1363 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1364 size + sizeof(struct b43_plcp_hdr6));
1365 }
1366
1367 /* Check if the use of the antenna that ieee80211 told us to
1368 * use is possible. This will fall back to DEFAULT.
1369 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1370 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1371 u8 antenna_nr)
1372 {
1373 u8 antenna_mask;
1374
1375 if (antenna_nr == 0) {
1376 /* Zero means "use default antenna". That's always OK. */
1377 return 0;
1378 }
1379
1380 /* Get the mask of available antennas. */
1381 if (dev->phy.gmode)
1382 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1383 else
1384 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1385
1386 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1387 /* This antenna is not available. Fall back to default. */
1388 return 0;
1389 }
1390
1391 return antenna_nr;
1392 }
1393
1394 /* Convert a b43 antenna number value to the PHY TX control value. */
1395 static u16 b43_antenna_to_phyctl(int antenna)
1396 {
1397 switch (antenna) {
1398 case B43_ANTENNA0:
1399 return B43_TXH_PHY_ANT0;
1400 case B43_ANTENNA1:
1401 return B43_TXH_PHY_ANT1;
1402 case B43_ANTENNA2:
1403 return B43_TXH_PHY_ANT2;
1404 case B43_ANTENNA3:
1405 return B43_TXH_PHY_ANT3;
1406 case B43_ANTENNA_AUTO0:
1407 case B43_ANTENNA_AUTO1:
1408 return B43_TXH_PHY_ANT01AUTO;
1409 }
1410 B43_WARN_ON(1);
1411 return 0;
1412 }
1413
1414 static void b43_write_beacon_template(struct b43_wldev *dev,
1415 u16 ram_offset,
1416 u16 shm_size_offset)
1417 {
1418 unsigned int i, len, variable_len;
1419 const struct ieee80211_mgmt *bcn;
1420 const u8 *ie;
1421 bool tim_found = 0;
1422 unsigned int rate;
1423 u16 ctl;
1424 int antenna;
1425 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1426
1427 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1428 len = min((size_t) dev->wl->current_beacon->len,
1429 0x200 - sizeof(struct b43_plcp_hdr6));
1430 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1431
1432 b43_write_template_common(dev, (const u8 *)bcn,
1433 len, ram_offset, shm_size_offset, rate);
1434
1435 /* Write the PHY TX control parameters. */
1436 antenna = B43_ANTENNA_DEFAULT;
1437 antenna = b43_antenna_to_phyctl(antenna);
1438 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1439 /* We can't send beacons with short preamble. Would get PHY errors. */
1440 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1441 ctl &= ~B43_TXH_PHY_ANT;
1442 ctl &= ~B43_TXH_PHY_ENC;
1443 ctl |= antenna;
1444 if (b43_is_cck_rate(rate))
1445 ctl |= B43_TXH_PHY_ENC_CCK;
1446 else
1447 ctl |= B43_TXH_PHY_ENC_OFDM;
1448 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1449
1450 /* Find the position of the TIM and the DTIM_period value
1451 * and write them to SHM. */
1452 ie = bcn->u.beacon.variable;
1453 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1454 for (i = 0; i < variable_len - 2; ) {
1455 uint8_t ie_id, ie_len;
1456
1457 ie_id = ie[i];
1458 ie_len = ie[i + 1];
1459 if (ie_id == 5) {
1460 u16 tim_position;
1461 u16 dtim_period;
1462 /* This is the TIM Information Element */
1463
1464 /* Check whether the ie_len is in the beacon data range. */
1465 if (variable_len < ie_len + 2 + i)
1466 break;
1467 /* A valid TIM is at least 4 bytes long. */
1468 if (ie_len < 4)
1469 break;
1470 tim_found = 1;
1471
1472 tim_position = sizeof(struct b43_plcp_hdr6);
1473 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1474 tim_position += i;
1475
1476 dtim_period = ie[i + 3];
1477
1478 b43_shm_write16(dev, B43_SHM_SHARED,
1479 B43_SHM_SH_TIMBPOS, tim_position);
1480 b43_shm_write16(dev, B43_SHM_SHARED,
1481 B43_SHM_SH_DTIMPER, dtim_period);
1482 break;
1483 }
1484 i += ie_len + 2;
1485 }
1486 if (!tim_found) {
1487 /*
1488 * If ucode wants to modify TIM do it behind the beacon, this
1489 * will happen, for example, when doing mesh networking.
1490 */
1491 b43_shm_write16(dev, B43_SHM_SHARED,
1492 B43_SHM_SH_TIMBPOS,
1493 len + sizeof(struct b43_plcp_hdr6));
1494 b43_shm_write16(dev, B43_SHM_SHARED,
1495 B43_SHM_SH_DTIMPER, 0);
1496 }
1497 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1498 }
1499
1500 static void b43_upload_beacon0(struct b43_wldev *dev)
1501 {
1502 struct b43_wl *wl = dev->wl;
1503
1504 if (wl->beacon0_uploaded)
1505 return;
1506 b43_write_beacon_template(dev, 0x68, 0x18);
1507 wl->beacon0_uploaded = 1;
1508 }
1509
1510 static void b43_upload_beacon1(struct b43_wldev *dev)
1511 {
1512 struct b43_wl *wl = dev->wl;
1513
1514 if (wl->beacon1_uploaded)
1515 return;
1516 b43_write_beacon_template(dev, 0x468, 0x1A);
1517 wl->beacon1_uploaded = 1;
1518 }
1519
1520 static void handle_irq_beacon(struct b43_wldev *dev)
1521 {
1522 struct b43_wl *wl = dev->wl;
1523 u32 cmd, beacon0_valid, beacon1_valid;
1524
1525 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1526 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
1527 return;
1528
1529 /* This is the bottom half of the asynchronous beacon update. */
1530
1531 /* Ignore interrupt in the future. */
1532 dev->irq_mask &= ~B43_IRQ_BEACON;
1533
1534 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1535 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1536 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1537
1538 /* Schedule interrupt manually, if busy. */
1539 if (beacon0_valid && beacon1_valid) {
1540 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1541 dev->irq_mask |= B43_IRQ_BEACON;
1542 return;
1543 }
1544
1545 if (unlikely(wl->beacon_templates_virgin)) {
1546 /* We never uploaded a beacon before.
1547 * Upload both templates now, but only mark one valid. */
1548 wl->beacon_templates_virgin = 0;
1549 b43_upload_beacon0(dev);
1550 b43_upload_beacon1(dev);
1551 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1552 cmd |= B43_MACCMD_BEACON0_VALID;
1553 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1554 } else {
1555 if (!beacon0_valid) {
1556 b43_upload_beacon0(dev);
1557 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1558 cmd |= B43_MACCMD_BEACON0_VALID;
1559 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1560 } else if (!beacon1_valid) {
1561 b43_upload_beacon1(dev);
1562 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1563 cmd |= B43_MACCMD_BEACON1_VALID;
1564 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1565 }
1566 }
1567 }
1568
1569 static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1570 {
1571 u32 old_irq_mask = dev->irq_mask;
1572
1573 /* update beacon right away or defer to irq */
1574 handle_irq_beacon(dev);
1575 if (old_irq_mask != dev->irq_mask) {
1576 /* The handler updated the IRQ mask. */
1577 B43_WARN_ON(!dev->irq_mask);
1578 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1579 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1580 } else {
1581 /* Device interrupts are currently disabled. That means
1582 * we just ran the hardirq handler and scheduled the
1583 * IRQ thread. The thread will write the IRQ mask when
1584 * it finished, so there's nothing to do here. Writing
1585 * the mask _here_ would incorrectly re-enable IRQs. */
1586 }
1587 }
1588 }
1589
1590 static void b43_beacon_update_trigger_work(struct work_struct *work)
1591 {
1592 struct b43_wl *wl = container_of(work, struct b43_wl,
1593 beacon_update_trigger);
1594 struct b43_wldev *dev;
1595
1596 mutex_lock(&wl->mutex);
1597 dev = wl->current_dev;
1598 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1599 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
1600 /* wl->mutex is enough. */
1601 b43_do_beacon_update_trigger_work(dev);
1602 mmiowb();
1603 } else {
1604 spin_lock_irq(&wl->hardirq_lock);
1605 b43_do_beacon_update_trigger_work(dev);
1606 mmiowb();
1607 spin_unlock_irq(&wl->hardirq_lock);
1608 }
1609 }
1610 mutex_unlock(&wl->mutex);
1611 }
1612
1613 /* Asynchronously update the packet templates in template RAM.
1614 * Locking: Requires wl->mutex to be locked. */
1615 static void b43_update_templates(struct b43_wl *wl)
1616 {
1617 struct sk_buff *beacon;
1618
1619 /* This is the top half of the ansynchronous beacon update.
1620 * The bottom half is the beacon IRQ.
1621 * Beacon update must be asynchronous to avoid sending an
1622 * invalid beacon. This can happen for example, if the firmware
1623 * transmits a beacon while we are updating it. */
1624
1625 /* We could modify the existing beacon and set the aid bit in
1626 * the TIM field, but that would probably require resizing and
1627 * moving of data within the beacon template.
1628 * Simply request a new beacon and let mac80211 do the hard work. */
1629 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1630 if (unlikely(!beacon))
1631 return;
1632
1633 if (wl->current_beacon)
1634 dev_kfree_skb_any(wl->current_beacon);
1635 wl->current_beacon = beacon;
1636 wl->beacon0_uploaded = 0;
1637 wl->beacon1_uploaded = 0;
1638 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1639 }
1640
1641 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1642 {
1643 b43_time_lock(dev);
1644 if (dev->dev->id.revision >= 3) {
1645 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1646 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1647 } else {
1648 b43_write16(dev, 0x606, (beacon_int >> 6));
1649 b43_write16(dev, 0x610, beacon_int);
1650 }
1651 b43_time_unlock(dev);
1652 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1653 }
1654
1655 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1656 {
1657 u16 reason;
1658
1659 /* Read the register that contains the reason code for the panic. */
1660 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1661 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1662
1663 switch (reason) {
1664 default:
1665 b43dbg(dev->wl, "The panic reason is unknown.\n");
1666 /* fallthrough */
1667 case B43_FWPANIC_DIE:
1668 /* Do not restart the controller or firmware.
1669 * The device is nonfunctional from now on.
1670 * Restarting would result in this panic to trigger again,
1671 * so we avoid that recursion. */
1672 break;
1673 case B43_FWPANIC_RESTART:
1674 b43_controller_restart(dev, "Microcode panic");
1675 break;
1676 }
1677 }
1678
1679 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1680 {
1681 unsigned int i, cnt;
1682 u16 reason, marker_id, marker_line;
1683 __le16 *buf;
1684
1685 /* The proprietary firmware doesn't have this IRQ. */
1686 if (!dev->fw.opensource)
1687 return;
1688
1689 /* Read the register that contains the reason code for this IRQ. */
1690 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1691
1692 switch (reason) {
1693 case B43_DEBUGIRQ_PANIC:
1694 b43_handle_firmware_panic(dev);
1695 break;
1696 case B43_DEBUGIRQ_DUMP_SHM:
1697 if (!B43_DEBUG)
1698 break; /* Only with driver debugging enabled. */
1699 buf = kmalloc(4096, GFP_ATOMIC);
1700 if (!buf) {
1701 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1702 goto out;
1703 }
1704 for (i = 0; i < 4096; i += 2) {
1705 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1706 buf[i / 2] = cpu_to_le16(tmp);
1707 }
1708 b43info(dev->wl, "Shared memory dump:\n");
1709 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1710 16, 2, buf, 4096, 1);
1711 kfree(buf);
1712 break;
1713 case B43_DEBUGIRQ_DUMP_REGS:
1714 if (!B43_DEBUG)
1715 break; /* Only with driver debugging enabled. */
1716 b43info(dev->wl, "Microcode register dump:\n");
1717 for (i = 0, cnt = 0; i < 64; i++) {
1718 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1719 if (cnt == 0)
1720 printk(KERN_INFO);
1721 printk("r%02u: 0x%04X ", i, tmp);
1722 cnt++;
1723 if (cnt == 6) {
1724 printk("\n");
1725 cnt = 0;
1726 }
1727 }
1728 printk("\n");
1729 break;
1730 case B43_DEBUGIRQ_MARKER:
1731 if (!B43_DEBUG)
1732 break; /* Only with driver debugging enabled. */
1733 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1734 B43_MARKER_ID_REG);
1735 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1736 B43_MARKER_LINE_REG);
1737 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1738 "at line number %u\n",
1739 marker_id, marker_line);
1740 break;
1741 default:
1742 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1743 reason);
1744 }
1745 out:
1746 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1747 b43_shm_write16(dev, B43_SHM_SCRATCH,
1748 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1749 }
1750
1751 static void b43_do_interrupt_thread(struct b43_wldev *dev)
1752 {
1753 u32 reason;
1754 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1755 u32 merged_dma_reason = 0;
1756 int i;
1757
1758 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1759 return;
1760
1761 reason = dev->irq_reason;
1762 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1763 dma_reason[i] = dev->dma_reason[i];
1764 merged_dma_reason |= dma_reason[i];
1765 }
1766
1767 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1768 b43err(dev->wl, "MAC transmission error\n");
1769
1770 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1771 b43err(dev->wl, "PHY transmission error\n");
1772 rmb();
1773 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1774 atomic_set(&dev->phy.txerr_cnt,
1775 B43_PHY_TX_BADNESS_LIMIT);
1776 b43err(dev->wl, "Too many PHY TX errors, "
1777 "restarting the controller\n");
1778 b43_controller_restart(dev, "PHY TX errors");
1779 }
1780 }
1781
1782 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1783 B43_DMAIRQ_NONFATALMASK))) {
1784 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1785 b43err(dev->wl, "Fatal DMA error: "
1786 "0x%08X, 0x%08X, 0x%08X, "
1787 "0x%08X, 0x%08X, 0x%08X\n",
1788 dma_reason[0], dma_reason[1],
1789 dma_reason[2], dma_reason[3],
1790 dma_reason[4], dma_reason[5]);
1791 b43_controller_restart(dev, "DMA error");
1792 return;
1793 }
1794 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1795 b43err(dev->wl, "DMA error: "
1796 "0x%08X, 0x%08X, 0x%08X, "
1797 "0x%08X, 0x%08X, 0x%08X\n",
1798 dma_reason[0], dma_reason[1],
1799 dma_reason[2], dma_reason[3],
1800 dma_reason[4], dma_reason[5]);
1801 }
1802 }
1803
1804 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1805 handle_irq_ucode_debug(dev);
1806 if (reason & B43_IRQ_TBTT_INDI)
1807 handle_irq_tbtt_indication(dev);
1808 if (reason & B43_IRQ_ATIM_END)
1809 handle_irq_atim_end(dev);
1810 if (reason & B43_IRQ_BEACON)
1811 handle_irq_beacon(dev);
1812 if (reason & B43_IRQ_PMQ)
1813 handle_irq_pmq(dev);
1814 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1815 ;/* TODO */
1816 if (reason & B43_IRQ_NOISESAMPLE_OK)
1817 handle_irq_noise(dev);
1818
1819 /* Check the DMA reason registers for received data. */
1820 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1821 if (b43_using_pio_transfers(dev))
1822 b43_pio_rx(dev->pio.rx_queue);
1823 else
1824 b43_dma_rx(dev->dma.rx_ring);
1825 }
1826 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1827 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1828 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1829 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1830 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1831
1832 if (reason & B43_IRQ_TX_OK)
1833 handle_irq_transmit_status(dev);
1834
1835 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
1836 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1837
1838 #if B43_DEBUG
1839 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
1840 dev->irq_count++;
1841 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
1842 if (reason & (1 << i))
1843 dev->irq_bit_count[i]++;
1844 }
1845 }
1846 #endif
1847 }
1848
1849 /* Interrupt thread handler. Handles device interrupts in thread context. */
1850 static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
1851 {
1852 struct b43_wldev *dev = dev_id;
1853
1854 mutex_lock(&dev->wl->mutex);
1855 b43_do_interrupt_thread(dev);
1856 mmiowb();
1857 mutex_unlock(&dev->wl->mutex);
1858
1859 return IRQ_HANDLED;
1860 }
1861
1862 static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
1863 {
1864 u32 reason;
1865
1866 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1867 * On SDIO, this runs under wl->mutex. */
1868
1869 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1870 if (reason == 0xffffffff) /* shared IRQ */
1871 return IRQ_NONE;
1872 reason &= dev->irq_mask;
1873 if (!reason)
1874 return IRQ_HANDLED;
1875
1876 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1877 & 0x0001DC00;
1878 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1879 & 0x0000DC00;
1880 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1881 & 0x0000DC00;
1882 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1883 & 0x0001DC00;
1884 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1885 & 0x0000DC00;
1886 /* Unused ring
1887 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1888 & 0x0000DC00;
1889 */
1890
1891 /* ACK the interrupt. */
1892 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1893 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1894 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1895 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1896 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1897 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1898 /* Unused ring
1899 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1900 */
1901
1902 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
1903 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
1904 /* Save the reason bitmasks for the IRQ thread handler. */
1905 dev->irq_reason = reason;
1906
1907 return IRQ_WAKE_THREAD;
1908 }
1909
1910 /* Interrupt handler top-half. This runs with interrupts disabled. */
1911 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1912 {
1913 struct b43_wldev *dev = dev_id;
1914 irqreturn_t ret;
1915
1916 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
1917 return IRQ_NONE;
1918
1919 spin_lock(&dev->wl->hardirq_lock);
1920 ret = b43_do_interrupt(dev);
1921 mmiowb();
1922 spin_unlock(&dev->wl->hardirq_lock);
1923
1924 return ret;
1925 }
1926
1927 /* SDIO interrupt handler. This runs in process context. */
1928 static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
1929 {
1930 struct b43_wl *wl = dev->wl;
1931 irqreturn_t ret;
1932
1933 mutex_lock(&wl->mutex);
1934
1935 ret = b43_do_interrupt(dev);
1936 if (ret == IRQ_WAKE_THREAD)
1937 b43_do_interrupt_thread(dev);
1938
1939 mutex_unlock(&wl->mutex);
1940 }
1941
1942 void b43_do_release_fw(struct b43_firmware_file *fw)
1943 {
1944 release_firmware(fw->data);
1945 fw->data = NULL;
1946 fw->filename = NULL;
1947 }
1948
1949 static void b43_release_firmware(struct b43_wldev *dev)
1950 {
1951 b43_do_release_fw(&dev->fw.ucode);
1952 b43_do_release_fw(&dev->fw.pcm);
1953 b43_do_release_fw(&dev->fw.initvals);
1954 b43_do_release_fw(&dev->fw.initvals_band);
1955 }
1956
1957 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
1958 {
1959 const char text[] =
1960 "You must go to " \
1961 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
1962 "and download the correct firmware for this driver version. " \
1963 "Please carefully read all instructions on this website.\n";
1964
1965 if (error)
1966 b43err(wl, text);
1967 else
1968 b43warn(wl, text);
1969 }
1970
1971 int b43_do_request_fw(struct b43_request_fw_context *ctx,
1972 const char *name,
1973 struct b43_firmware_file *fw)
1974 {
1975 const struct firmware *blob;
1976 struct b43_fw_header *hdr;
1977 u32 size;
1978 int err;
1979
1980 if (!name) {
1981 /* Don't fetch anything. Free possibly cached firmware. */
1982 /* FIXME: We should probably keep it anyway, to save some headache
1983 * on suspend/resume with multiband devices. */
1984 b43_do_release_fw(fw);
1985 return 0;
1986 }
1987 if (fw->filename) {
1988 if ((fw->type == ctx->req_type) &&
1989 (strcmp(fw->filename, name) == 0))
1990 return 0; /* Already have this fw. */
1991 /* Free the cached firmware first. */
1992 /* FIXME: We should probably do this later after we successfully
1993 * got the new fw. This could reduce headache with multiband devices.
1994 * We could also redesign this to cache the firmware for all possible
1995 * bands all the time. */
1996 b43_do_release_fw(fw);
1997 }
1998
1999 switch (ctx->req_type) {
2000 case B43_FWTYPE_PROPRIETARY:
2001 snprintf(ctx->fwname, sizeof(ctx->fwname),
2002 "b43%s/%s.fw",
2003 modparam_fwpostfix, name);
2004 break;
2005 case B43_FWTYPE_OPENSOURCE:
2006 snprintf(ctx->fwname, sizeof(ctx->fwname),
2007 "b43-open%s/%s.fw",
2008 modparam_fwpostfix, name);
2009 break;
2010 default:
2011 B43_WARN_ON(1);
2012 return -ENOSYS;
2013 }
2014 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
2015 if (err == -ENOENT) {
2016 snprintf(ctx->errors[ctx->req_type],
2017 sizeof(ctx->errors[ctx->req_type]),
2018 "Firmware file \"%s\" not found\n", ctx->fwname);
2019 return err;
2020 } else if (err) {
2021 snprintf(ctx->errors[ctx->req_type],
2022 sizeof(ctx->errors[ctx->req_type]),
2023 "Firmware file \"%s\" request failed (err=%d)\n",
2024 ctx->fwname, err);
2025 return err;
2026 }
2027 if (blob->size < sizeof(struct b43_fw_header))
2028 goto err_format;
2029 hdr = (struct b43_fw_header *)(blob->data);
2030 switch (hdr->type) {
2031 case B43_FW_TYPE_UCODE:
2032 case B43_FW_TYPE_PCM:
2033 size = be32_to_cpu(hdr->size);
2034 if (size != blob->size - sizeof(struct b43_fw_header))
2035 goto err_format;
2036 /* fallthrough */
2037 case B43_FW_TYPE_IV:
2038 if (hdr->ver != 1)
2039 goto err_format;
2040 break;
2041 default:
2042 goto err_format;
2043 }
2044
2045 fw->data = blob;
2046 fw->filename = name;
2047 fw->type = ctx->req_type;
2048
2049 return 0;
2050
2051 err_format:
2052 snprintf(ctx->errors[ctx->req_type],
2053 sizeof(ctx->errors[ctx->req_type]),
2054 "Firmware file \"%s\" format error.\n", ctx->fwname);
2055 release_firmware(blob);
2056
2057 return -EPROTO;
2058 }
2059
2060 static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2061 {
2062 struct b43_wldev *dev = ctx->dev;
2063 struct b43_firmware *fw = &ctx->dev->fw;
2064 const u8 rev = ctx->dev->dev->id.revision;
2065 const char *filename;
2066 u32 tmshigh;
2067 int err;
2068
2069 /* Get microcode */
2070 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
2071 if ((rev >= 5) && (rev <= 10))
2072 filename = "ucode5";
2073 else if ((rev >= 11) && (rev <= 12))
2074 filename = "ucode11";
2075 else if (rev == 13)
2076 filename = "ucode13";
2077 else if (rev == 14)
2078 filename = "ucode14";
2079 else if (rev >= 15)
2080 filename = "ucode15";
2081 else
2082 goto err_no_ucode;
2083 err = b43_do_request_fw(ctx, filename, &fw->ucode);
2084 if (err)
2085 goto err_load;
2086
2087 /* Get PCM code */
2088 if ((rev >= 5) && (rev <= 10))
2089 filename = "pcm5";
2090 else if (rev >= 11)
2091 filename = NULL;
2092 else
2093 goto err_no_pcm;
2094 fw->pcm_request_failed = 0;
2095 err = b43_do_request_fw(ctx, filename, &fw->pcm);
2096 if (err == -ENOENT) {
2097 /* We did not find a PCM file? Not fatal, but
2098 * core rev <= 10 must do without hwcrypto then. */
2099 fw->pcm_request_failed = 1;
2100 } else if (err)
2101 goto err_load;
2102
2103 /* Get initvals */
2104 switch (dev->phy.type) {
2105 case B43_PHYTYPE_A:
2106 if ((rev >= 5) && (rev <= 10)) {
2107 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2108 filename = "a0g1initvals5";
2109 else
2110 filename = "a0g0initvals5";
2111 } else
2112 goto err_no_initvals;
2113 break;
2114 case B43_PHYTYPE_G:
2115 if ((rev >= 5) && (rev <= 10))
2116 filename = "b0g0initvals5";
2117 else if (rev >= 13)
2118 filename = "b0g0initvals13";
2119 else
2120 goto err_no_initvals;
2121 break;
2122 case B43_PHYTYPE_N:
2123 if ((rev >= 11) && (rev <= 12))
2124 filename = "n0initvals11";
2125 else
2126 goto err_no_initvals;
2127 break;
2128 case B43_PHYTYPE_LP:
2129 if (rev == 13)
2130 filename = "lp0initvals13";
2131 else if (rev == 14)
2132 filename = "lp0initvals14";
2133 else if (rev >= 15)
2134 filename = "lp0initvals15";
2135 else
2136 goto err_no_initvals;
2137 break;
2138 default:
2139 goto err_no_initvals;
2140 }
2141 err = b43_do_request_fw(ctx, filename, &fw->initvals);
2142 if (err)
2143 goto err_load;
2144
2145 /* Get bandswitch initvals */
2146 switch (dev->phy.type) {
2147 case B43_PHYTYPE_A:
2148 if ((rev >= 5) && (rev <= 10)) {
2149 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2150 filename = "a0g1bsinitvals5";
2151 else
2152 filename = "a0g0bsinitvals5";
2153 } else if (rev >= 11)
2154 filename = NULL;
2155 else
2156 goto err_no_initvals;
2157 break;
2158 case B43_PHYTYPE_G:
2159 if ((rev >= 5) && (rev <= 10))
2160 filename = "b0g0bsinitvals5";
2161 else if (rev >= 11)
2162 filename = NULL;
2163 else
2164 goto err_no_initvals;
2165 break;
2166 case B43_PHYTYPE_N:
2167 if ((rev >= 11) && (rev <= 12))
2168 filename = "n0bsinitvals11";
2169 else
2170 goto err_no_initvals;
2171 break;
2172 case B43_PHYTYPE_LP:
2173 if (rev == 13)
2174 filename = "lp0bsinitvals13";
2175 else if (rev == 14)
2176 filename = "lp0bsinitvals14";
2177 else if (rev >= 15)
2178 filename = "lp0bsinitvals15";
2179 else
2180 goto err_no_initvals;
2181 break;
2182 default:
2183 goto err_no_initvals;
2184 }
2185 err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
2186 if (err)
2187 goto err_load;
2188
2189 return 0;
2190
2191 err_no_ucode:
2192 err = ctx->fatal_failure = -EOPNOTSUPP;
2193 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2194 "is required for your device (wl-core rev %u)\n", rev);
2195 goto error;
2196
2197 err_no_pcm:
2198 err = ctx->fatal_failure = -EOPNOTSUPP;
2199 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2200 "is required for your device (wl-core rev %u)\n", rev);
2201 goto error;
2202
2203 err_no_initvals:
2204 err = ctx->fatal_failure = -EOPNOTSUPP;
2205 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2206 "is required for your device (wl-core rev %u)\n", rev);
2207 goto error;
2208
2209 err_load:
2210 /* We failed to load this firmware image. The error message
2211 * already is in ctx->errors. Return and let our caller decide
2212 * what to do. */
2213 goto error;
2214
2215 error:
2216 b43_release_firmware(dev);
2217 return err;
2218 }
2219
2220 static int b43_request_firmware(struct b43_wldev *dev)
2221 {
2222 struct b43_request_fw_context *ctx;
2223 unsigned int i;
2224 int err;
2225 const char *errmsg;
2226
2227 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2228 if (!ctx)
2229 return -ENOMEM;
2230 ctx->dev = dev;
2231
2232 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2233 err = b43_try_request_fw(ctx);
2234 if (!err)
2235 goto out; /* Successfully loaded it. */
2236 err = ctx->fatal_failure;
2237 if (err)
2238 goto out;
2239
2240 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2241 err = b43_try_request_fw(ctx);
2242 if (!err)
2243 goto out; /* Successfully loaded it. */
2244 err = ctx->fatal_failure;
2245 if (err)
2246 goto out;
2247
2248 /* Could not find a usable firmware. Print the errors. */
2249 for (i = 0; i < B43_NR_FWTYPES; i++) {
2250 errmsg = ctx->errors[i];
2251 if (strlen(errmsg))
2252 b43err(dev->wl, errmsg);
2253 }
2254 b43_print_fw_helptext(dev->wl, 1);
2255 err = -ENOENT;
2256
2257 out:
2258 kfree(ctx);
2259 return err;
2260 }
2261
2262 static int b43_upload_microcode(struct b43_wldev *dev)
2263 {
2264 const size_t hdr_len = sizeof(struct b43_fw_header);
2265 const __be32 *data;
2266 unsigned int i, len;
2267 u16 fwrev, fwpatch, fwdate, fwtime;
2268 u32 tmp, macctl;
2269 int err = 0;
2270
2271 /* Jump the microcode PSM to offset 0 */
2272 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2273 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2274 macctl |= B43_MACCTL_PSM_JMP0;
2275 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2276 /* Zero out all microcode PSM registers and shared memory. */
2277 for (i = 0; i < 64; i++)
2278 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2279 for (i = 0; i < 4096; i += 2)
2280 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2281
2282 /* Upload Microcode. */
2283 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2284 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2285 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2286 for (i = 0; i < len; i++) {
2287 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2288 udelay(10);
2289 }
2290
2291 if (dev->fw.pcm.data) {
2292 /* Upload PCM data. */
2293 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2294 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2295 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2296 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2297 /* No need for autoinc bit in SHM_HW */
2298 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2299 for (i = 0; i < len; i++) {
2300 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2301 udelay(10);
2302 }
2303 }
2304
2305 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2306
2307 /* Start the microcode PSM */
2308 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2309 macctl &= ~B43_MACCTL_PSM_JMP0;
2310 macctl |= B43_MACCTL_PSM_RUN;
2311 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2312
2313 /* Wait for the microcode to load and respond */
2314 i = 0;
2315 while (1) {
2316 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2317 if (tmp == B43_IRQ_MAC_SUSPENDED)
2318 break;
2319 i++;
2320 if (i >= 20) {
2321 b43err(dev->wl, "Microcode not responding\n");
2322 b43_print_fw_helptext(dev->wl, 1);
2323 err = -ENODEV;
2324 goto error;
2325 }
2326 msleep(50);
2327 }
2328 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2329
2330 /* Get and check the revisions. */
2331 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2332 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2333 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2334 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2335
2336 if (fwrev <= 0x128) {
2337 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2338 "binary drivers older than version 4.x is unsupported. "
2339 "You must upgrade your firmware files.\n");
2340 b43_print_fw_helptext(dev->wl, 1);
2341 err = -EOPNOTSUPP;
2342 goto error;
2343 }
2344 dev->fw.rev = fwrev;
2345 dev->fw.patch = fwpatch;
2346 dev->fw.opensource = (fwdate == 0xFFFF);
2347
2348 /* Default to use-all-queues. */
2349 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2350 dev->qos_enabled = !!modparam_qos;
2351 /* Default to firmware/hardware crypto acceleration. */
2352 dev->hwcrypto_enabled = 1;
2353
2354 if (dev->fw.opensource) {
2355 u16 fwcapa;
2356
2357 /* Patchlevel info is encoded in the "time" field. */
2358 dev->fw.patch = fwtime;
2359 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2360 dev->fw.rev, dev->fw.patch);
2361
2362 fwcapa = b43_fwcapa_read(dev);
2363 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2364 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2365 /* Disable hardware crypto and fall back to software crypto. */
2366 dev->hwcrypto_enabled = 0;
2367 }
2368 if (!(fwcapa & B43_FWCAPA_QOS)) {
2369 b43info(dev->wl, "QoS not supported by firmware\n");
2370 /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2371 * ieee80211_unregister to make sure the networking core can
2372 * properly free possible resources. */
2373 dev->wl->hw->queues = 1;
2374 dev->qos_enabled = 0;
2375 }
2376 } else {
2377 b43info(dev->wl, "Loading firmware version %u.%u "
2378 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2379 fwrev, fwpatch,
2380 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2381 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2382 if (dev->fw.pcm_request_failed) {
2383 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2384 "Hardware accelerated cryptography is disabled.\n");
2385 b43_print_fw_helptext(dev->wl, 0);
2386 }
2387 }
2388
2389 if (b43_is_old_txhdr_format(dev)) {
2390 /* We're over the deadline, but we keep support for old fw
2391 * until it turns out to be in major conflict with something new. */
2392 b43warn(dev->wl, "You are using an old firmware image. "
2393 "Support for old firmware will be removed soon "
2394 "(official deadline was July 2008).\n");
2395 b43_print_fw_helptext(dev->wl, 0);
2396 }
2397
2398 return 0;
2399
2400 error:
2401 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2402 macctl &= ~B43_MACCTL_PSM_RUN;
2403 macctl |= B43_MACCTL_PSM_JMP0;
2404 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2405
2406 return err;
2407 }
2408
2409 static int b43_write_initvals(struct b43_wldev *dev,
2410 const struct b43_iv *ivals,
2411 size_t count,
2412 size_t array_size)
2413 {
2414 const struct b43_iv *iv;
2415 u16 offset;
2416 size_t i;
2417 bool bit32;
2418
2419 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2420 iv = ivals;
2421 for (i = 0; i < count; i++) {
2422 if (array_size < sizeof(iv->offset_size))
2423 goto err_format;
2424 array_size -= sizeof(iv->offset_size);
2425 offset = be16_to_cpu(iv->offset_size);
2426 bit32 = !!(offset & B43_IV_32BIT);
2427 offset &= B43_IV_OFFSET_MASK;
2428 if (offset >= 0x1000)
2429 goto err_format;
2430 if (bit32) {
2431 u32 value;
2432
2433 if (array_size < sizeof(iv->data.d32))
2434 goto err_format;
2435 array_size -= sizeof(iv->data.d32);
2436
2437 value = get_unaligned_be32(&iv->data.d32);
2438 b43_write32(dev, offset, value);
2439
2440 iv = (const struct b43_iv *)((const uint8_t *)iv +
2441 sizeof(__be16) +
2442 sizeof(__be32));
2443 } else {
2444 u16 value;
2445
2446 if (array_size < sizeof(iv->data.d16))
2447 goto err_format;
2448 array_size -= sizeof(iv->data.d16);
2449
2450 value = be16_to_cpu(iv->data.d16);
2451 b43_write16(dev, offset, value);
2452
2453 iv = (const struct b43_iv *)((const uint8_t *)iv +
2454 sizeof(__be16) +
2455 sizeof(__be16));
2456 }
2457 }
2458 if (array_size)
2459 goto err_format;
2460
2461 return 0;
2462
2463 err_format:
2464 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2465 b43_print_fw_helptext(dev->wl, 1);
2466
2467 return -EPROTO;
2468 }
2469
2470 static int b43_upload_initvals(struct b43_wldev *dev)
2471 {
2472 const size_t hdr_len = sizeof(struct b43_fw_header);
2473 const struct b43_fw_header *hdr;
2474 struct b43_firmware *fw = &dev->fw;
2475 const struct b43_iv *ivals;
2476 size_t count;
2477 int err;
2478
2479 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2480 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2481 count = be32_to_cpu(hdr->size);
2482 err = b43_write_initvals(dev, ivals, count,
2483 fw->initvals.data->size - hdr_len);
2484 if (err)
2485 goto out;
2486 if (fw->initvals_band.data) {
2487 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2488 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2489 count = be32_to_cpu(hdr->size);
2490 err = b43_write_initvals(dev, ivals, count,
2491 fw->initvals_band.data->size - hdr_len);
2492 if (err)
2493 goto out;
2494 }
2495 out:
2496
2497 return err;
2498 }
2499
2500 /* Initialize the GPIOs
2501 * http://bcm-specs.sipsolutions.net/GPIO
2502 */
2503 static int b43_gpio_init(struct b43_wldev *dev)
2504 {
2505 struct ssb_bus *bus = dev->dev->bus;
2506 struct ssb_device *gpiodev, *pcidev = NULL;
2507 u32 mask, set;
2508
2509 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2510 & ~B43_MACCTL_GPOUTSMSK);
2511
2512 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2513 | 0x000F);
2514
2515 mask = 0x0000001F;
2516 set = 0x0000000F;
2517 if (dev->dev->bus->chip_id == 0x4301) {
2518 mask |= 0x0060;
2519 set |= 0x0060;
2520 }
2521 if (0 /* FIXME: conditional unknown */ ) {
2522 b43_write16(dev, B43_MMIO_GPIO_MASK,
2523 b43_read16(dev, B43_MMIO_GPIO_MASK)
2524 | 0x0100);
2525 mask |= 0x0180;
2526 set |= 0x0180;
2527 }
2528 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
2529 b43_write16(dev, B43_MMIO_GPIO_MASK,
2530 b43_read16(dev, B43_MMIO_GPIO_MASK)
2531 | 0x0200);
2532 mask |= 0x0200;
2533 set |= 0x0200;
2534 }
2535 if (dev->dev->id.revision >= 2)
2536 mask |= 0x0010; /* FIXME: This is redundant. */
2537
2538 #ifdef CONFIG_SSB_DRIVER_PCICORE
2539 pcidev = bus->pcicore.dev;
2540 #endif
2541 gpiodev = bus->chipco.dev ? : pcidev;
2542 if (!gpiodev)
2543 return 0;
2544 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2545 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2546 & mask) | set);
2547
2548 return 0;
2549 }
2550
2551 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2552 static void b43_gpio_cleanup(struct b43_wldev *dev)
2553 {
2554 struct ssb_bus *bus = dev->dev->bus;
2555 struct ssb_device *gpiodev, *pcidev = NULL;
2556
2557 #ifdef CONFIG_SSB_DRIVER_PCICORE
2558 pcidev = bus->pcicore.dev;
2559 #endif
2560 gpiodev = bus->chipco.dev ? : pcidev;
2561 if (!gpiodev)
2562 return;
2563 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2564 }
2565
2566 /* http://bcm-specs.sipsolutions.net/EnableMac */
2567 void b43_mac_enable(struct b43_wldev *dev)
2568 {
2569 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2570 u16 fwstate;
2571
2572 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2573 B43_SHM_SH_UCODESTAT);
2574 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2575 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2576 b43err(dev->wl, "b43_mac_enable(): The firmware "
2577 "should be suspended, but current state is %u\n",
2578 fwstate);
2579 }
2580 }
2581
2582 dev->mac_suspended--;
2583 B43_WARN_ON(dev->mac_suspended < 0);
2584 if (dev->mac_suspended == 0) {
2585 b43_write32(dev, B43_MMIO_MACCTL,
2586 b43_read32(dev, B43_MMIO_MACCTL)
2587 | B43_MACCTL_ENABLED);
2588 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2589 B43_IRQ_MAC_SUSPENDED);
2590 /* Commit writes */
2591 b43_read32(dev, B43_MMIO_MACCTL);
2592 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2593 b43_power_saving_ctl_bits(dev, 0);
2594 }
2595 }
2596
2597 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2598 void b43_mac_suspend(struct b43_wldev *dev)
2599 {
2600 int i;
2601 u32 tmp;
2602
2603 might_sleep();
2604 B43_WARN_ON(dev->mac_suspended < 0);
2605
2606 if (dev->mac_suspended == 0) {
2607 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2608 b43_write32(dev, B43_MMIO_MACCTL,
2609 b43_read32(dev, B43_MMIO_MACCTL)
2610 & ~B43_MACCTL_ENABLED);
2611 /* force pci to flush the write */
2612 b43_read32(dev, B43_MMIO_MACCTL);
2613 for (i = 35; i; i--) {
2614 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2615 if (tmp & B43_IRQ_MAC_SUSPENDED)
2616 goto out;
2617 udelay(10);
2618 }
2619 /* Hm, it seems this will take some time. Use msleep(). */
2620 for (i = 40; i; i--) {
2621 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2622 if (tmp & B43_IRQ_MAC_SUSPENDED)
2623 goto out;
2624 msleep(1);
2625 }
2626 b43err(dev->wl, "MAC suspend failed\n");
2627 }
2628 out:
2629 dev->mac_suspended++;
2630 }
2631
2632 static void b43_adjust_opmode(struct b43_wldev *dev)
2633 {
2634 struct b43_wl *wl = dev->wl;
2635 u32 ctl;
2636 u16 cfp_pretbtt;
2637
2638 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2639 /* Reset status to STA infrastructure mode. */
2640 ctl &= ~B43_MACCTL_AP;
2641 ctl &= ~B43_MACCTL_KEEP_CTL;
2642 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2643 ctl &= ~B43_MACCTL_KEEP_BAD;
2644 ctl &= ~B43_MACCTL_PROMISC;
2645 ctl &= ~B43_MACCTL_BEACPROMISC;
2646 ctl |= B43_MACCTL_INFRA;
2647
2648 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2649 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
2650 ctl |= B43_MACCTL_AP;
2651 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
2652 ctl &= ~B43_MACCTL_INFRA;
2653
2654 if (wl->filter_flags & FIF_CONTROL)
2655 ctl |= B43_MACCTL_KEEP_CTL;
2656 if (wl->filter_flags & FIF_FCSFAIL)
2657 ctl |= B43_MACCTL_KEEP_BAD;
2658 if (wl->filter_flags & FIF_PLCPFAIL)
2659 ctl |= B43_MACCTL_KEEP_BADPLCP;
2660 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2661 ctl |= B43_MACCTL_PROMISC;
2662 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2663 ctl |= B43_MACCTL_BEACPROMISC;
2664
2665 /* Workaround: On old hardware the HW-MAC-address-filter
2666 * doesn't work properly, so always run promisc in filter
2667 * it in software. */
2668 if (dev->dev->id.revision <= 4)
2669 ctl |= B43_MACCTL_PROMISC;
2670
2671 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2672
2673 cfp_pretbtt = 2;
2674 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2675 if (dev->dev->bus->chip_id == 0x4306 &&
2676 dev->dev->bus->chip_rev == 3)
2677 cfp_pretbtt = 100;
2678 else
2679 cfp_pretbtt = 50;
2680 }
2681 b43_write16(dev, 0x612, cfp_pretbtt);
2682
2683 /* FIXME: We don't currently implement the PMQ mechanism,
2684 * so always disable it. If we want to implement PMQ,
2685 * we need to enable it here (clear DISCPMQ) in AP mode.
2686 */
2687 if (0 /* ctl & B43_MACCTL_AP */) {
2688 b43_write32(dev, B43_MMIO_MACCTL,
2689 b43_read32(dev, B43_MMIO_MACCTL)
2690 & ~B43_MACCTL_DISCPMQ);
2691 } else {
2692 b43_write32(dev, B43_MMIO_MACCTL,
2693 b43_read32(dev, B43_MMIO_MACCTL)
2694 | B43_MACCTL_DISCPMQ);
2695 }
2696 }
2697
2698 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2699 {
2700 u16 offset;
2701
2702 if (is_ofdm) {
2703 offset = 0x480;
2704 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2705 } else {
2706 offset = 0x4C0;
2707 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2708 }
2709 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2710 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2711 }
2712
2713 static void b43_rate_memory_init(struct b43_wldev *dev)
2714 {
2715 switch (dev->phy.type) {
2716 case B43_PHYTYPE_A:
2717 case B43_PHYTYPE_G:
2718 case B43_PHYTYPE_N:
2719 case B43_PHYTYPE_LP:
2720 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2721 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2722 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2723 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2724 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2725 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2726 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2727 if (dev->phy.type == B43_PHYTYPE_A)
2728 break;
2729 /* fallthrough */
2730 case B43_PHYTYPE_B:
2731 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2732 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2733 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2734 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2735 break;
2736 default:
2737 B43_WARN_ON(1);
2738 }
2739 }
2740
2741 /* Set the default values for the PHY TX Control Words. */
2742 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2743 {
2744 u16 ctl = 0;
2745
2746 ctl |= B43_TXH_PHY_ENC_CCK;
2747 ctl |= B43_TXH_PHY_ANT01AUTO;
2748 ctl |= B43_TXH_PHY_TXPWR;
2749
2750 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2751 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2752 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2753 }
2754
2755 /* Set the TX-Antenna for management frames sent by firmware. */
2756 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2757 {
2758 u16 ant;
2759 u16 tmp;
2760
2761 ant = b43_antenna_to_phyctl(antenna);
2762
2763 /* For ACK/CTS */
2764 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2765 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2766 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2767 /* For Probe Resposes */
2768 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2769 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2770 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2771 }
2772
2773 /* This is the opposite of b43_chip_init() */
2774 static void b43_chip_exit(struct b43_wldev *dev)
2775 {
2776 b43_phy_exit(dev);
2777 b43_gpio_cleanup(dev);
2778 /* firmware is released later */
2779 }
2780
2781 /* Initialize the chip
2782 * http://bcm-specs.sipsolutions.net/ChipInit
2783 */
2784 static int b43_chip_init(struct b43_wldev *dev)
2785 {
2786 struct b43_phy *phy = &dev->phy;
2787 int err;
2788 u32 value32, macctl;
2789 u16 value16;
2790
2791 /* Initialize the MAC control */
2792 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2793 if (dev->phy.gmode)
2794 macctl |= B43_MACCTL_GMODE;
2795 macctl |= B43_MACCTL_INFRA;
2796 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2797
2798 err = b43_request_firmware(dev);
2799 if (err)
2800 goto out;
2801 err = b43_upload_microcode(dev);
2802 if (err)
2803 goto out; /* firmware is released later */
2804
2805 err = b43_gpio_init(dev);
2806 if (err)
2807 goto out; /* firmware is released later */
2808
2809 err = b43_upload_initvals(dev);
2810 if (err)
2811 goto err_gpio_clean;
2812
2813 /* Turn the Analog on and initialize the PHY. */
2814 phy->ops->switch_analog(dev, 1);
2815 err = b43_phy_init(dev);
2816 if (err)
2817 goto err_gpio_clean;
2818
2819 /* Disable Interference Mitigation. */
2820 if (phy->ops->interf_mitigation)
2821 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
2822
2823 /* Select the antennae */
2824 if (phy->ops->set_rx_antenna)
2825 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2826 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2827
2828 if (phy->type == B43_PHYTYPE_B) {
2829 value16 = b43_read16(dev, 0x005E);
2830 value16 |= 0x0004;
2831 b43_write16(dev, 0x005E, value16);
2832 }
2833 b43_write32(dev, 0x0100, 0x01000000);
2834 if (dev->dev->id.revision < 5)
2835 b43_write32(dev, 0x010C, 0x01000000);
2836
2837 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2838 & ~B43_MACCTL_INFRA);
2839 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2840 | B43_MACCTL_INFRA);
2841
2842 /* Probe Response Timeout value */
2843 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2844 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2845
2846 /* Initially set the wireless operation mode. */
2847 b43_adjust_opmode(dev);
2848
2849 if (dev->dev->id.revision < 3) {
2850 b43_write16(dev, 0x060E, 0x0000);
2851 b43_write16(dev, 0x0610, 0x8000);
2852 b43_write16(dev, 0x0604, 0x0000);
2853 b43_write16(dev, 0x0606, 0x0200);
2854 } else {
2855 b43_write32(dev, 0x0188, 0x80000000);
2856 b43_write32(dev, 0x018C, 0x02000000);
2857 }
2858 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2859 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2860 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2861 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2862 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2863 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2864 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2865
2866 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2867 value32 |= 0x00100000;
2868 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2869
2870 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2871 dev->dev->bus->chipco.fast_pwrup_delay);
2872
2873 err = 0;
2874 b43dbg(dev->wl, "Chip initialized\n");
2875 out:
2876 return err;
2877
2878 err_gpio_clean:
2879 b43_gpio_cleanup(dev);
2880 return err;
2881 }
2882
2883 static void b43_periodic_every60sec(struct b43_wldev *dev)
2884 {
2885 const struct b43_phy_operations *ops = dev->phy.ops;
2886
2887 if (ops->pwork_60sec)
2888 ops->pwork_60sec(dev);
2889
2890 /* Force check the TX power emission now. */
2891 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
2892 }
2893
2894 static void b43_periodic_every30sec(struct b43_wldev *dev)
2895 {
2896 /* Update device statistics. */
2897 b43_calculate_link_quality(dev);
2898 }
2899
2900 static void b43_periodic_every15sec(struct b43_wldev *dev)
2901 {
2902 struct b43_phy *phy = &dev->phy;
2903 u16 wdr;
2904
2905 if (dev->fw.opensource) {
2906 /* Check if the firmware is still alive.
2907 * It will reset the watchdog counter to 0 in its idle loop. */
2908 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2909 if (unlikely(wdr)) {
2910 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2911 b43_controller_restart(dev, "Firmware watchdog");
2912 return;
2913 } else {
2914 b43_shm_write16(dev, B43_SHM_SCRATCH,
2915 B43_WATCHDOG_REG, 1);
2916 }
2917 }
2918
2919 if (phy->ops->pwork_15sec)
2920 phy->ops->pwork_15sec(dev);
2921
2922 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2923 wmb();
2924
2925 #if B43_DEBUG
2926 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
2927 unsigned int i;
2928
2929 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
2930 dev->irq_count / 15,
2931 dev->tx_count / 15,
2932 dev->rx_count / 15);
2933 dev->irq_count = 0;
2934 dev->tx_count = 0;
2935 dev->rx_count = 0;
2936 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
2937 if (dev->irq_bit_count[i]) {
2938 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
2939 dev->irq_bit_count[i] / 15, i, (1 << i));
2940 dev->irq_bit_count[i] = 0;
2941 }
2942 }
2943 }
2944 #endif
2945 }
2946
2947 static void do_periodic_work(struct b43_wldev *dev)
2948 {
2949 unsigned int state;
2950
2951 state = dev->periodic_state;
2952 if (state % 4 == 0)
2953 b43_periodic_every60sec(dev);
2954 if (state % 2 == 0)
2955 b43_periodic_every30sec(dev);
2956 b43_periodic_every15sec(dev);
2957 }
2958
2959 /* Periodic work locking policy:
2960 * The whole periodic work handler is protected by
2961 * wl->mutex. If another lock is needed somewhere in the
2962 * pwork callchain, it's aquired in-place, where it's needed.
2963 */
2964 static void b43_periodic_work_handler(struct work_struct *work)
2965 {
2966 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2967 periodic_work.work);
2968 struct b43_wl *wl = dev->wl;
2969 unsigned long delay;
2970
2971 mutex_lock(&wl->mutex);
2972
2973 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2974 goto out;
2975 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2976 goto out_requeue;
2977
2978 do_periodic_work(dev);
2979
2980 dev->periodic_state++;
2981 out_requeue:
2982 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2983 delay = msecs_to_jiffies(50);
2984 else
2985 delay = round_jiffies_relative(HZ * 15);
2986 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
2987 out:
2988 mutex_unlock(&wl->mutex);
2989 }
2990
2991 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2992 {
2993 struct delayed_work *work = &dev->periodic_work;
2994
2995 dev->periodic_state = 0;
2996 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2997 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
2998 }
2999
3000 /* Check if communication with the device works correctly. */
3001 static int b43_validate_chipaccess(struct b43_wldev *dev)
3002 {
3003 u32 v, backup0, backup4;
3004
3005 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3006 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
3007
3008 /* Check for read/write and endianness problems. */
3009 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3010 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3011 goto error;
3012 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3013 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
3014 goto error;
3015
3016 /* Check if unaligned 32bit SHM_SHARED access works properly.
3017 * However, don't bail out on failure, because it's noncritical. */
3018 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3019 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3020 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3021 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3022 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3023 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3024 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3025 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3026 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3027 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3028 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3029 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3030
3031 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3032 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
3033
3034 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
3035 /* The 32bit register shadows the two 16bit registers
3036 * with update sideeffects. Validate this. */
3037 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3038 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3039 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3040 goto error;
3041 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3042 goto error;
3043 }
3044 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3045
3046 v = b43_read32(dev, B43_MMIO_MACCTL);
3047 v |= B43_MACCTL_GMODE;
3048 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
3049 goto error;
3050
3051 return 0;
3052 error:
3053 b43err(dev->wl, "Failed to validate the chipaccess\n");
3054 return -ENODEV;
3055 }
3056
3057 static void b43_security_init(struct b43_wldev *dev)
3058 {
3059 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3060 /* KTP is a word address, but we address SHM bytewise.
3061 * So multiply by two.
3062 */
3063 dev->ktp *= 2;
3064 /* Number of RCMTA address slots */
3065 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3066 /* Clear the key memory. */
3067 b43_clear_keys(dev);
3068 }
3069
3070 #ifdef CONFIG_B43_HWRNG
3071 static int b43_rng_read(struct hwrng *rng, u32 *data)
3072 {
3073 struct b43_wl *wl = (struct b43_wl *)rng->priv;
3074 struct b43_wldev *dev;
3075 int count = -ENODEV;
3076
3077 mutex_lock(&wl->mutex);
3078 dev = wl->current_dev;
3079 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3080 *data = b43_read16(dev, B43_MMIO_RNG);
3081 count = sizeof(u16);
3082 }
3083 mutex_unlock(&wl->mutex);
3084
3085 return count;
3086 }
3087 #endif /* CONFIG_B43_HWRNG */
3088
3089 static void b43_rng_exit(struct b43_wl *wl)
3090 {
3091 #ifdef CONFIG_B43_HWRNG
3092 if (wl->rng_initialized)
3093 hwrng_unregister(&wl->rng);
3094 #endif /* CONFIG_B43_HWRNG */
3095 }
3096
3097 static int b43_rng_init(struct b43_wl *wl)
3098 {
3099 int err = 0;
3100
3101 #ifdef CONFIG_B43_HWRNG
3102 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3103 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3104 wl->rng.name = wl->rng_name;
3105 wl->rng.data_read = b43_rng_read;
3106 wl->rng.priv = (unsigned long)wl;
3107 wl->rng_initialized = 1;
3108 err = hwrng_register(&wl->rng);
3109 if (err) {
3110 wl->rng_initialized = 0;
3111 b43err(wl, "Failed to register the random "
3112 "number generator (%d)\n", err);
3113 }
3114 #endif /* CONFIG_B43_HWRNG */
3115
3116 return err;
3117 }
3118
3119 static void b43_tx_work(struct work_struct *work)
3120 {
3121 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3122 struct b43_wldev *dev;
3123 struct sk_buff *skb;
3124 int err = 0;
3125
3126 mutex_lock(&wl->mutex);
3127 dev = wl->current_dev;
3128 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3129 mutex_unlock(&wl->mutex);
3130 return;
3131 }
3132
3133 while (skb_queue_len(&wl->tx_queue)) {
3134 skb = skb_dequeue(&wl->tx_queue);
3135
3136 if (b43_using_pio_transfers(dev))
3137 err = b43_pio_tx(dev, skb);
3138 else
3139 err = b43_dma_tx(dev, skb);
3140 if (unlikely(err))
3141 dev_kfree_skb(skb); /* Drop it */
3142 }
3143
3144 #if B43_DEBUG
3145 dev->tx_count++;
3146 #endif
3147 mutex_unlock(&wl->mutex);
3148 }
3149
3150 static int b43_op_tx(struct ieee80211_hw *hw,
3151 struct sk_buff *skb)
3152 {
3153 struct b43_wl *wl = hw_to_b43_wl(hw);
3154
3155 if (unlikely(skb->len < 2 + 2 + 6)) {
3156 /* Too short, this can't be a valid frame. */
3157 dev_kfree_skb_any(skb);
3158 return NETDEV_TX_OK;
3159 }
3160 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3161
3162 skb_queue_tail(&wl->tx_queue, skb);
3163 ieee80211_queue_work(wl->hw, &wl->tx_work);
3164
3165 return NETDEV_TX_OK;
3166 }
3167
3168 static void b43_qos_params_upload(struct b43_wldev *dev,
3169 const struct ieee80211_tx_queue_params *p,
3170 u16 shm_offset)
3171 {
3172 u16 params[B43_NR_QOSPARAMS];
3173 int bslots, tmp;
3174 unsigned int i;
3175
3176 if (!dev->qos_enabled)
3177 return;
3178
3179 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3180
3181 memset(&params, 0, sizeof(params));
3182
3183 params[B43_QOSPARAM_TXOP] = p->txop * 32;
3184 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3185 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3186 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3187 params[B43_QOSPARAM_AIFS] = p->aifs;
3188 params[B43_QOSPARAM_BSLOTS] = bslots;
3189 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3190
3191 for (i = 0; i < ARRAY_SIZE(params); i++) {
3192 if (i == B43_QOSPARAM_STATUS) {
3193 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3194 shm_offset + (i * 2));
3195 /* Mark the parameters as updated. */
3196 tmp |= 0x100;
3197 b43_shm_write16(dev, B43_SHM_SHARED,
3198 shm_offset + (i * 2),
3199 tmp);
3200 } else {
3201 b43_shm_write16(dev, B43_SHM_SHARED,
3202 shm_offset + (i * 2),
3203 params[i]);
3204 }
3205 }
3206 }
3207
3208 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3209 static const u16 b43_qos_shm_offsets[] = {
3210 /* [mac80211-queue-nr] = SHM_OFFSET, */
3211 [0] = B43_QOS_VOICE,
3212 [1] = B43_QOS_VIDEO,
3213 [2] = B43_QOS_BESTEFFORT,
3214 [3] = B43_QOS_BACKGROUND,
3215 };
3216
3217 /* Update all QOS parameters in hardware. */
3218 static void b43_qos_upload_all(struct b43_wldev *dev)
3219 {
3220 struct b43_wl *wl = dev->wl;
3221 struct b43_qos_params *params;
3222 unsigned int i;
3223
3224 if (!dev->qos_enabled)
3225 return;
3226
3227 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3228 ARRAY_SIZE(wl->qos_params));
3229
3230 b43_mac_suspend(dev);
3231 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3232 params = &(wl->qos_params[i]);
3233 b43_qos_params_upload(dev, &(params->p),
3234 b43_qos_shm_offsets[i]);
3235 }
3236 b43_mac_enable(dev);
3237 }
3238
3239 static void b43_qos_clear(struct b43_wl *wl)
3240 {
3241 struct b43_qos_params *params;
3242 unsigned int i;
3243
3244 /* Initialize QoS parameters to sane defaults. */
3245
3246 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3247 ARRAY_SIZE(wl->qos_params));
3248
3249 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3250 params = &(wl->qos_params[i]);
3251
3252 switch (b43_qos_shm_offsets[i]) {
3253 case B43_QOS_VOICE:
3254 params->p.txop = 0;
3255 params->p.aifs = 2;
3256 params->p.cw_min = 0x0001;
3257 params->p.cw_max = 0x0001;
3258 break;
3259 case B43_QOS_VIDEO:
3260 params->p.txop = 0;
3261 params->p.aifs = 2;
3262 params->p.cw_min = 0x0001;
3263 params->p.cw_max = 0x0001;
3264 break;
3265 case B43_QOS_BESTEFFORT:
3266 params->p.txop = 0;
3267 params->p.aifs = 3;
3268 params->p.cw_min = 0x0001;
3269 params->p.cw_max = 0x03FF;
3270 break;
3271 case B43_QOS_BACKGROUND:
3272 params->p.txop = 0;
3273 params->p.aifs = 7;
3274 params->p.cw_min = 0x0001;
3275 params->p.cw_max = 0x03FF;
3276 break;
3277 default:
3278 B43_WARN_ON(1);
3279 }
3280 }
3281 }
3282
3283 /* Initialize the core's QOS capabilities */
3284 static void b43_qos_init(struct b43_wldev *dev)
3285 {
3286 if (!dev->qos_enabled) {
3287 /* Disable QOS support. */
3288 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3289 b43_write16(dev, B43_MMIO_IFSCTL,
3290 b43_read16(dev, B43_MMIO_IFSCTL)
3291 & ~B43_MMIO_IFSCTL_USE_EDCF);
3292 b43dbg(dev->wl, "QoS disabled\n");
3293 return;
3294 }
3295
3296 /* Upload the current QOS parameters. */
3297 b43_qos_upload_all(dev);
3298
3299 /* Enable QOS support. */
3300 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3301 b43_write16(dev, B43_MMIO_IFSCTL,
3302 b43_read16(dev, B43_MMIO_IFSCTL)
3303 | B43_MMIO_IFSCTL_USE_EDCF);
3304 b43dbg(dev->wl, "QoS enabled\n");
3305 }
3306
3307 static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
3308 const struct ieee80211_tx_queue_params *params)
3309 {
3310 struct b43_wl *wl = hw_to_b43_wl(hw);
3311 struct b43_wldev *dev;
3312 unsigned int queue = (unsigned int)_queue;
3313 int err = -ENODEV;
3314
3315 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3316 /* Queue not available or don't support setting
3317 * params on this queue. Return success to not
3318 * confuse mac80211. */
3319 return 0;
3320 }
3321 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3322 ARRAY_SIZE(wl->qos_params));
3323
3324 mutex_lock(&wl->mutex);
3325 dev = wl->current_dev;
3326 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3327 goto out_unlock;
3328
3329 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3330 b43_mac_suspend(dev);
3331 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3332 b43_qos_shm_offsets[queue]);
3333 b43_mac_enable(dev);
3334 err = 0;
3335
3336 out_unlock:
3337 mutex_unlock(&wl->mutex);
3338
3339 return err;
3340 }
3341
3342 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
3343 struct ieee80211_tx_queue_stats *stats)
3344 {
3345 struct b43_wl *wl = hw_to_b43_wl(hw);
3346 struct b43_wldev *dev;
3347 int err = -ENODEV;
3348
3349 mutex_lock(&wl->mutex);
3350 dev = wl->current_dev;
3351 if (dev && b43_status(dev) >= B43_STAT_STARTED) {
3352 if (b43_using_pio_transfers(dev))
3353 b43_pio_get_tx_stats(dev, stats);
3354 else
3355 b43_dma_get_tx_stats(dev, stats);
3356 err = 0;
3357 }
3358 mutex_unlock(&wl->mutex);
3359
3360 return err;
3361 }
3362
3363 static int b43_op_get_stats(struct ieee80211_hw *hw,
3364 struct ieee80211_low_level_stats *stats)
3365 {
3366 struct b43_wl *wl = hw_to_b43_wl(hw);
3367
3368 mutex_lock(&wl->mutex);
3369 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3370 mutex_unlock(&wl->mutex);
3371
3372 return 0;
3373 }
3374
3375 static u64 b43_op_get_tsf(struct ieee80211_hw *hw)
3376 {
3377 struct b43_wl *wl = hw_to_b43_wl(hw);
3378 struct b43_wldev *dev;
3379 u64 tsf;
3380
3381 mutex_lock(&wl->mutex);
3382 dev = wl->current_dev;
3383
3384 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3385 b43_tsf_read(dev, &tsf);
3386 else
3387 tsf = 0;
3388
3389 mutex_unlock(&wl->mutex);
3390
3391 return tsf;
3392 }
3393
3394 static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3395 {
3396 struct b43_wl *wl = hw_to_b43_wl(hw);
3397 struct b43_wldev *dev;
3398
3399 mutex_lock(&wl->mutex);
3400 dev = wl->current_dev;
3401
3402 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3403 b43_tsf_write(dev, tsf);
3404
3405 mutex_unlock(&wl->mutex);
3406 }
3407
3408 static void b43_put_phy_into_reset(struct b43_wldev *dev)
3409 {
3410 struct ssb_device *sdev = dev->dev;
3411 u32 tmslow;
3412
3413 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3414 tmslow &= ~B43_TMSLOW_GMODE;
3415 tmslow |= B43_TMSLOW_PHYRESET;
3416 tmslow |= SSB_TMSLOW_FGC;
3417 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3418 msleep(1);
3419
3420 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3421 tmslow &= ~SSB_TMSLOW_FGC;
3422 tmslow |= B43_TMSLOW_PHYRESET;
3423 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3424 msleep(1);
3425 }
3426
3427 static const char *band_to_string(enum ieee80211_band band)
3428 {
3429 switch (band) {
3430 case IEEE80211_BAND_5GHZ:
3431 return "5";
3432 case IEEE80211_BAND_2GHZ:
3433 return "2.4";
3434 default:
3435 break;
3436 }
3437 B43_WARN_ON(1);
3438 return "";
3439 }
3440
3441 /* Expects wl->mutex locked */
3442 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3443 {
3444 struct b43_wldev *up_dev = NULL;
3445 struct b43_wldev *down_dev;
3446 struct b43_wldev *d;
3447 int err;
3448 bool uninitialized_var(gmode);
3449 int prev_status;
3450
3451 /* Find a device and PHY which supports the band. */
3452 list_for_each_entry(d, &wl->devlist, list) {
3453 switch (chan->band) {
3454 case IEEE80211_BAND_5GHZ:
3455 if (d->phy.supports_5ghz) {
3456 up_dev = d;
3457 gmode = 0;
3458 }
3459 break;
3460 case IEEE80211_BAND_2GHZ:
3461 if (d->phy.supports_2ghz) {
3462 up_dev = d;
3463 gmode = 1;
3464 }
3465 break;
3466 default:
3467 B43_WARN_ON(1);
3468 return -EINVAL;
3469 }
3470 if (up_dev)
3471 break;
3472 }
3473 if (!up_dev) {
3474 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3475 band_to_string(chan->band));
3476 return -ENODEV;
3477 }
3478 if ((up_dev == wl->current_dev) &&
3479 (!!wl->current_dev->phy.gmode == !!gmode)) {
3480 /* This device is already running. */
3481 return 0;
3482 }
3483 b43dbg(wl, "Switching to %s-GHz band\n",
3484 band_to_string(chan->band));
3485 down_dev = wl->current_dev;
3486
3487 prev_status = b43_status(down_dev);
3488 /* Shutdown the currently running core. */
3489 if (prev_status >= B43_STAT_STARTED)
3490 down_dev = b43_wireless_core_stop(down_dev);
3491 if (prev_status >= B43_STAT_INITIALIZED)
3492 b43_wireless_core_exit(down_dev);
3493
3494 if (down_dev != up_dev) {
3495 /* We switch to a different core, so we put PHY into
3496 * RESET on the old core. */
3497 b43_put_phy_into_reset(down_dev);
3498 }
3499
3500 /* Now start the new core. */
3501 up_dev->phy.gmode = gmode;
3502 if (prev_status >= B43_STAT_INITIALIZED) {
3503 err = b43_wireless_core_init(up_dev);
3504 if (err) {
3505 b43err(wl, "Fatal: Could not initialize device for "
3506 "selected %s-GHz band\n",
3507 band_to_string(chan->band));
3508 goto init_failure;
3509 }
3510 }
3511 if (prev_status >= B43_STAT_STARTED) {
3512 err = b43_wireless_core_start(up_dev);
3513 if (err) {
3514 b43err(wl, "Fatal: Coult not start device for "
3515 "selected %s-GHz band\n",
3516 band_to_string(chan->band));
3517 b43_wireless_core_exit(up_dev);
3518 goto init_failure;
3519 }
3520 }
3521 B43_WARN_ON(b43_status(up_dev) != prev_status);
3522
3523 wl->current_dev = up_dev;
3524
3525 return 0;
3526 init_failure:
3527 /* Whoops, failed to init the new core. No core is operating now. */
3528 wl->current_dev = NULL;
3529 return err;
3530 }
3531
3532 /* Write the short and long frame retry limit values. */
3533 static void b43_set_retry_limits(struct b43_wldev *dev,
3534 unsigned int short_retry,
3535 unsigned int long_retry)
3536 {
3537 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3538 * the chip-internal counter. */
3539 short_retry = min(short_retry, (unsigned int)0xF);
3540 long_retry = min(long_retry, (unsigned int)0xF);
3541
3542 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3543 short_retry);
3544 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3545 long_retry);
3546 }
3547
3548 static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3549 {
3550 struct b43_wl *wl = hw_to_b43_wl(hw);
3551 struct b43_wldev *dev;
3552 struct b43_phy *phy;
3553 struct ieee80211_conf *conf = &hw->conf;
3554 int antenna;
3555 int err = 0;
3556
3557 mutex_lock(&wl->mutex);
3558
3559 /* Switch the band (if necessary). This might change the active core. */
3560 err = b43_switch_band(wl, conf->channel);
3561 if (err)
3562 goto out_unlock_mutex;
3563 dev = wl->current_dev;
3564 phy = &dev->phy;
3565
3566 b43_mac_suspend(dev);
3567
3568 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3569 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3570 conf->long_frame_max_tx_count);
3571 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3572 if (!changed)
3573 goto out_mac_enable;
3574
3575 /* Switch to the requested channel.
3576 * The firmware takes care of races with the TX handler. */
3577 if (conf->channel->hw_value != phy->channel)
3578 b43_switch_channel(dev, conf->channel->hw_value);
3579
3580 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3581
3582 /* Adjust the desired TX power level. */
3583 if (conf->power_level != 0) {
3584 if (conf->power_level != phy->desired_txpower) {
3585 phy->desired_txpower = conf->power_level;
3586 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3587 B43_TXPWR_IGNORE_TSSI);
3588 }
3589 }
3590
3591 /* Antennas for RX and management frame TX. */
3592 antenna = B43_ANTENNA_DEFAULT;
3593 b43_mgmtframe_txantenna(dev, antenna);
3594 antenna = B43_ANTENNA_DEFAULT;
3595 if (phy->ops->set_rx_antenna)
3596 phy->ops->set_rx_antenna(dev, antenna);
3597
3598 if (wl->radio_enabled != phy->radio_on) {
3599 if (wl->radio_enabled) {
3600 b43_software_rfkill(dev, false);
3601 b43info(dev->wl, "Radio turned on by software\n");
3602 if (!dev->radio_hw_enable) {
3603 b43info(dev->wl, "The hardware RF-kill button "
3604 "still turns the radio physically off. "
3605 "Press the button to turn it on.\n");
3606 }
3607 } else {
3608 b43_software_rfkill(dev, true);
3609 b43info(dev->wl, "Radio turned off by software\n");
3610 }
3611 }
3612
3613 out_mac_enable:
3614 b43_mac_enable(dev);
3615 out_unlock_mutex:
3616 mutex_unlock(&wl->mutex);
3617
3618 return err;
3619 }
3620
3621 static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
3622 {
3623 struct ieee80211_supported_band *sband =
3624 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3625 struct ieee80211_rate *rate;
3626 int i;
3627 u16 basic, direct, offset, basic_offset, rateptr;
3628
3629 for (i = 0; i < sband->n_bitrates; i++) {
3630 rate = &sband->bitrates[i];
3631
3632 if (b43_is_cck_rate(rate->hw_value)) {
3633 direct = B43_SHM_SH_CCKDIRECT;
3634 basic = B43_SHM_SH_CCKBASIC;
3635 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3636 offset &= 0xF;
3637 } else {
3638 direct = B43_SHM_SH_OFDMDIRECT;
3639 basic = B43_SHM_SH_OFDMBASIC;
3640 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3641 offset &= 0xF;
3642 }
3643
3644 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3645
3646 if (b43_is_cck_rate(rate->hw_value)) {
3647 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3648 basic_offset &= 0xF;
3649 } else {
3650 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3651 basic_offset &= 0xF;
3652 }
3653
3654 /*
3655 * Get the pointer that we need to point to
3656 * from the direct map
3657 */
3658 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3659 direct + 2 * basic_offset);
3660 /* and write it to the basic map */
3661 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3662 rateptr);
3663 }
3664 }
3665
3666 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3667 struct ieee80211_vif *vif,
3668 struct ieee80211_bss_conf *conf,
3669 u32 changed)
3670 {
3671 struct b43_wl *wl = hw_to_b43_wl(hw);
3672 struct b43_wldev *dev;
3673
3674 mutex_lock(&wl->mutex);
3675
3676 dev = wl->current_dev;
3677 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3678 goto out_unlock_mutex;
3679
3680 B43_WARN_ON(wl->vif != vif);
3681
3682 if (changed & BSS_CHANGED_BSSID) {
3683 if (conf->bssid)
3684 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3685 else
3686 memset(wl->bssid, 0, ETH_ALEN);
3687 }
3688
3689 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3690 if (changed & BSS_CHANGED_BEACON &&
3691 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3692 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3693 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3694 b43_update_templates(wl);
3695
3696 if (changed & BSS_CHANGED_BSSID)
3697 b43_write_mac_bssid_templates(dev);
3698 }
3699
3700 b43_mac_suspend(dev);
3701
3702 /* Update templates for AP/mesh mode. */
3703 if (changed & BSS_CHANGED_BEACON_INT &&
3704 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3705 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3706 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3707 b43_set_beacon_int(dev, conf->beacon_int);
3708
3709 if (changed & BSS_CHANGED_BASIC_RATES)
3710 b43_update_basic_rates(dev, conf->basic_rates);
3711
3712 if (changed & BSS_CHANGED_ERP_SLOT) {
3713 if (conf->use_short_slot)
3714 b43_short_slot_timing_enable(dev);
3715 else
3716 b43_short_slot_timing_disable(dev);
3717 }
3718
3719 b43_mac_enable(dev);
3720 out_unlock_mutex:
3721 mutex_unlock(&wl->mutex);
3722 }
3723
3724 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3725 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3726 struct ieee80211_key_conf *key)
3727 {
3728 struct b43_wl *wl = hw_to_b43_wl(hw);
3729 struct b43_wldev *dev;
3730 u8 algorithm;
3731 u8 index;
3732 int err;
3733 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3734
3735 if (modparam_nohwcrypt)
3736 return -ENOSPC; /* User disabled HW-crypto */
3737
3738 mutex_lock(&wl->mutex);
3739
3740 dev = wl->current_dev;
3741 err = -ENODEV;
3742 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3743 goto out_unlock;
3744
3745 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
3746 /* We don't have firmware for the crypto engine.
3747 * Must use software-crypto. */
3748 err = -EOPNOTSUPP;
3749 goto out_unlock;
3750 }
3751
3752 err = -EINVAL;
3753 switch (key->alg) {
3754 case ALG_WEP:
3755 if (key->keylen == WLAN_KEY_LEN_WEP40)
3756 algorithm = B43_SEC_ALGO_WEP40;
3757 else
3758 algorithm = B43_SEC_ALGO_WEP104;
3759 break;
3760 case ALG_TKIP:
3761 algorithm = B43_SEC_ALGO_TKIP;
3762 break;
3763 case ALG_CCMP:
3764 algorithm = B43_SEC_ALGO_AES;
3765 break;
3766 default:
3767 B43_WARN_ON(1);
3768 goto out_unlock;
3769 }
3770 index = (u8) (key->keyidx);
3771 if (index > 3)
3772 goto out_unlock;
3773
3774 switch (cmd) {
3775 case SET_KEY:
3776 if (algorithm == B43_SEC_ALGO_TKIP &&
3777 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
3778 !modparam_hwtkip)) {
3779 /* We support only pairwise key */
3780 err = -EOPNOTSUPP;
3781 goto out_unlock;
3782 }
3783
3784 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
3785 if (WARN_ON(!sta)) {
3786 err = -EOPNOTSUPP;
3787 goto out_unlock;
3788 }
3789 /* Pairwise key with an assigned MAC address. */
3790 err = b43_key_write(dev, -1, algorithm,
3791 key->key, key->keylen,
3792 sta->addr, key);
3793 } else {
3794 /* Group key */
3795 err = b43_key_write(dev, index, algorithm,
3796 key->key, key->keylen, NULL, key);
3797 }
3798 if (err)
3799 goto out_unlock;
3800
3801 if (algorithm == B43_SEC_ALGO_WEP40 ||
3802 algorithm == B43_SEC_ALGO_WEP104) {
3803 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3804 } else {
3805 b43_hf_write(dev,
3806 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3807 }
3808 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3809 if (algorithm == B43_SEC_ALGO_TKIP)
3810 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3811 break;
3812 case DISABLE_KEY: {
3813 err = b43_key_clear(dev, key->hw_key_idx);
3814 if (err)
3815 goto out_unlock;
3816 break;
3817 }
3818 default:
3819 B43_WARN_ON(1);
3820 }
3821
3822 out_unlock:
3823 if (!err) {
3824 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
3825 "mac: %pM\n",
3826 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
3827 sta ? sta->addr : bcast_addr);
3828 b43_dump_keymemory(dev);
3829 }
3830 mutex_unlock(&wl->mutex);
3831
3832 return err;
3833 }
3834
3835 static void b43_op_configure_filter(struct ieee80211_hw *hw,
3836 unsigned int changed, unsigned int *fflags,
3837 u64 multicast)
3838 {
3839 struct b43_wl *wl = hw_to_b43_wl(hw);
3840 struct b43_wldev *dev;
3841
3842 mutex_lock(&wl->mutex);
3843 dev = wl->current_dev;
3844 if (!dev) {
3845 *fflags = 0;
3846 goto out_unlock;
3847 }
3848
3849 *fflags &= FIF_PROMISC_IN_BSS |
3850 FIF_ALLMULTI |
3851 FIF_FCSFAIL |
3852 FIF_PLCPFAIL |
3853 FIF_CONTROL |
3854 FIF_OTHER_BSS |
3855 FIF_BCN_PRBRESP_PROMISC;
3856
3857 changed &= FIF_PROMISC_IN_BSS |
3858 FIF_ALLMULTI |
3859 FIF_FCSFAIL |
3860 FIF_PLCPFAIL |
3861 FIF_CONTROL |
3862 FIF_OTHER_BSS |
3863 FIF_BCN_PRBRESP_PROMISC;
3864
3865 wl->filter_flags = *fflags;
3866
3867 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3868 b43_adjust_opmode(dev);
3869
3870 out_unlock:
3871 mutex_unlock(&wl->mutex);
3872 }
3873
3874 /* Locking: wl->mutex
3875 * Returns the current dev. This might be different from the passed in dev,
3876 * because the core might be gone away while we unlocked the mutex. */
3877 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
3878 {
3879 struct b43_wl *wl = dev->wl;
3880 struct b43_wldev *orig_dev;
3881 u32 mask;
3882
3883 redo:
3884 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3885 return dev;
3886
3887 /* Cancel work. Unlock to avoid deadlocks. */
3888 mutex_unlock(&wl->mutex);
3889 cancel_delayed_work_sync(&dev->periodic_work);
3890 cancel_work_sync(&wl->tx_work);
3891 mutex_lock(&wl->mutex);
3892 dev = wl->current_dev;
3893 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
3894 /* Whoops, aliens ate up the device while we were unlocked. */
3895 return dev;
3896 }
3897
3898 /* Disable interrupts on the device. */
3899 b43_set_status(dev, B43_STAT_INITIALIZED);
3900 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
3901 /* wl->mutex is locked. That is enough. */
3902 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
3903 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
3904 } else {
3905 spin_lock_irq(&wl->hardirq_lock);
3906 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
3907 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
3908 spin_unlock_irq(&wl->hardirq_lock);
3909 }
3910 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
3911 orig_dev = dev;
3912 mutex_unlock(&wl->mutex);
3913 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
3914 b43_sdio_free_irq(dev);
3915 } else {
3916 synchronize_irq(dev->dev->irq);
3917 free_irq(dev->dev->irq, dev);
3918 }
3919 mutex_lock(&wl->mutex);
3920 dev = wl->current_dev;
3921 if (!dev)
3922 return dev;
3923 if (dev != orig_dev) {
3924 if (b43_status(dev) >= B43_STAT_STARTED)
3925 goto redo;
3926 return dev;
3927 }
3928 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
3929 B43_WARN_ON(mask != 0xFFFFFFFF && mask);
3930
3931 /* Drain the TX queue */
3932 while (skb_queue_len(&wl->tx_queue))
3933 dev_kfree_skb(skb_dequeue(&wl->tx_queue));
3934
3935 b43_mac_suspend(dev);
3936 b43_leds_exit(dev);
3937 b43dbg(wl, "Wireless interface stopped\n");
3938
3939 return dev;
3940 }
3941
3942 /* Locking: wl->mutex */
3943 static int b43_wireless_core_start(struct b43_wldev *dev)
3944 {
3945 int err;
3946
3947 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3948
3949 drain_txstatus_queue(dev);
3950 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
3951 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
3952 if (err) {
3953 b43err(dev->wl, "Cannot request SDIO IRQ\n");
3954 goto out;
3955 }
3956 } else {
3957 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
3958 b43_interrupt_thread_handler,
3959 IRQF_SHARED, KBUILD_MODNAME, dev);
3960 if (err) {
3961 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3962 goto out;
3963 }
3964 }
3965
3966 /* We are ready to run. */
3967 ieee80211_wake_queues(dev->wl->hw);
3968 b43_set_status(dev, B43_STAT_STARTED);
3969
3970 /* Start data flow (TX/RX). */
3971 b43_mac_enable(dev);
3972 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
3973
3974 /* Start maintainance work */
3975 b43_periodic_tasks_setup(dev);
3976
3977 b43_leds_init(dev);
3978
3979 b43dbg(dev->wl, "Wireless interface started\n");
3980 out:
3981 return err;
3982 }
3983
3984 /* Get PHY and RADIO versioning numbers */
3985 static int b43_phy_versioning(struct b43_wldev *dev)
3986 {
3987 struct b43_phy *phy = &dev->phy;
3988 u32 tmp;
3989 u8 analog_type;
3990 u8 phy_type;
3991 u8 phy_rev;
3992 u16 radio_manuf;
3993 u16 radio_ver;
3994 u16 radio_rev;
3995 int unsupported = 0;
3996
3997 /* Get PHY versioning */
3998 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3999 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4000 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4001 phy_rev = (tmp & B43_PHYVER_VERSION);
4002 switch (phy_type) {
4003 case B43_PHYTYPE_A:
4004 if (phy_rev >= 4)
4005 unsupported = 1;
4006 break;
4007 case B43_PHYTYPE_B:
4008 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
4009 && phy_rev != 7)
4010 unsupported = 1;
4011 break;
4012 case B43_PHYTYPE_G:
4013 if (phy_rev > 9)
4014 unsupported = 1;
4015 break;
4016 #ifdef CONFIG_B43_NPHY
4017 case B43_PHYTYPE_N:
4018 if (phy_rev > 4)
4019 unsupported = 1;
4020 break;
4021 #endif
4022 #ifdef CONFIG_B43_PHY_LP
4023 case B43_PHYTYPE_LP:
4024 if (phy_rev > 2)
4025 unsupported = 1;
4026 break;
4027 #endif
4028 default:
4029 unsupported = 1;
4030 };
4031 if (unsupported) {
4032 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
4033 "(Analog %u, Type %u, Revision %u)\n",
4034 analog_type, phy_type, phy_rev);
4035 return -EOPNOTSUPP;
4036 }
4037 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
4038 analog_type, phy_type, phy_rev);
4039
4040 /* Get RADIO versioning */
4041 if (dev->dev->bus->chip_id == 0x4317) {
4042 if (dev->dev->bus->chip_rev == 0)
4043 tmp = 0x3205017F;
4044 else if (dev->dev->bus->chip_rev == 1)
4045 tmp = 0x4205017F;
4046 else
4047 tmp = 0x5205017F;
4048 } else {
4049 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
4050 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4051 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
4052 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
4053 }
4054 radio_manuf = (tmp & 0x00000FFF);
4055 radio_ver = (tmp & 0x0FFFF000) >> 12;
4056 radio_rev = (tmp & 0xF0000000) >> 28;
4057 if (radio_manuf != 0x17F /* Broadcom */)
4058 unsupported = 1;
4059 switch (phy_type) {
4060 case B43_PHYTYPE_A:
4061 if (radio_ver != 0x2060)
4062 unsupported = 1;
4063 if (radio_rev != 1)
4064 unsupported = 1;
4065 if (radio_manuf != 0x17F)
4066 unsupported = 1;
4067 break;
4068 case B43_PHYTYPE_B:
4069 if ((radio_ver & 0xFFF0) != 0x2050)
4070 unsupported = 1;
4071 break;
4072 case B43_PHYTYPE_G:
4073 if (radio_ver != 0x2050)
4074 unsupported = 1;
4075 break;
4076 case B43_PHYTYPE_N:
4077 if (radio_ver != 0x2055 && radio_ver != 0x2056)
4078 unsupported = 1;
4079 break;
4080 case B43_PHYTYPE_LP:
4081 if (radio_ver != 0x2062 && radio_ver != 0x2063)
4082 unsupported = 1;
4083 break;
4084 default:
4085 B43_WARN_ON(1);
4086 }
4087 if (unsupported) {
4088 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4089 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4090 radio_manuf, radio_ver, radio_rev);
4091 return -EOPNOTSUPP;
4092 }
4093 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4094 radio_manuf, radio_ver, radio_rev);
4095
4096 phy->radio_manuf = radio_manuf;
4097 phy->radio_ver = radio_ver;
4098 phy->radio_rev = radio_rev;
4099
4100 phy->analog = analog_type;
4101 phy->type = phy_type;
4102 phy->rev = phy_rev;
4103
4104 return 0;
4105 }
4106
4107 static void setup_struct_phy_for_init(struct b43_wldev *dev,
4108 struct b43_phy *phy)
4109 {
4110 phy->hardware_power_control = !!modparam_hwpctl;
4111 phy->next_txpwr_check_time = jiffies;
4112 /* PHY TX errors counter. */
4113 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
4114
4115 #if B43_DEBUG
4116 phy->phy_locked = 0;
4117 phy->radio_locked = 0;
4118 #endif
4119 }
4120
4121 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4122 {
4123 dev->dfq_valid = 0;
4124
4125 /* Assume the radio is enabled. If it's not enabled, the state will
4126 * immediately get fixed on the first periodic work run. */
4127 dev->radio_hw_enable = 1;
4128
4129 /* Stats */
4130 memset(&dev->stats, 0, sizeof(dev->stats));
4131
4132 setup_struct_phy_for_init(dev, &dev->phy);
4133
4134 /* IRQ related flags */
4135 dev->irq_reason = 0;
4136 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
4137 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
4138 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
4139 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
4140
4141 dev->mac_suspended = 1;
4142
4143 /* Noise calculation context */
4144 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4145 }
4146
4147 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4148 {
4149 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
4150 u64 hf;
4151
4152 if (!modparam_btcoex)
4153 return;
4154 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
4155 return;
4156 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4157 return;
4158
4159 hf = b43_hf_read(dev);
4160 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
4161 hf |= B43_HF_BTCOEXALT;
4162 else
4163 hf |= B43_HF_BTCOEX;
4164 b43_hf_write(dev, hf);
4165 }
4166
4167 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
4168 {
4169 if (!modparam_btcoex)
4170 return;
4171 //TODO
4172 }
4173
4174 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4175 {
4176 #ifdef CONFIG_SSB_DRIVER_PCICORE
4177 struct ssb_bus *bus = dev->dev->bus;
4178 u32 tmp;
4179
4180 if (bus->pcicore.dev &&
4181 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
4182 bus->pcicore.dev->id.revision <= 5) {
4183 /* IMCFGLO timeouts workaround. */
4184 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
4185 switch (bus->bustype) {
4186 case SSB_BUSTYPE_PCI:
4187 case SSB_BUSTYPE_PCMCIA:
4188 tmp &= ~SSB_IMCFGLO_REQTO;
4189 tmp &= ~SSB_IMCFGLO_SERTO;
4190 tmp |= 0x32;
4191 break;
4192 case SSB_BUSTYPE_SSB:
4193 tmp &= ~SSB_IMCFGLO_REQTO;
4194 tmp &= ~SSB_IMCFGLO_SERTO;
4195 tmp |= 0x53;
4196 break;
4197 default:
4198 break;
4199 }
4200 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
4201 }
4202 #endif /* CONFIG_SSB_DRIVER_PCICORE */
4203 }
4204
4205 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4206 {
4207 u16 pu_delay;
4208
4209 /* The time value is in microseconds. */
4210 if (dev->phy.type == B43_PHYTYPE_A)
4211 pu_delay = 3700;
4212 else
4213 pu_delay = 1050;
4214 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
4215 pu_delay = 500;
4216 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4217 pu_delay = max(pu_delay, (u16)2400);
4218
4219 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4220 }
4221
4222 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4223 static void b43_set_pretbtt(struct b43_wldev *dev)
4224 {
4225 u16 pretbtt;
4226
4227 /* The time value is in microseconds. */
4228 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
4229 pretbtt = 2;
4230 } else {
4231 if (dev->phy.type == B43_PHYTYPE_A)
4232 pretbtt = 120;
4233 else
4234 pretbtt = 250;
4235 }
4236 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4237 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4238 }
4239
4240 /* Shutdown a wireless core */
4241 /* Locking: wl->mutex */
4242 static void b43_wireless_core_exit(struct b43_wldev *dev)
4243 {
4244 u32 macctl;
4245
4246 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4247 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
4248 return;
4249 b43_set_status(dev, B43_STAT_UNINIT);
4250
4251 /* Stop the microcode PSM. */
4252 macctl = b43_read32(dev, B43_MMIO_MACCTL);
4253 macctl &= ~B43_MACCTL_PSM_RUN;
4254 macctl |= B43_MACCTL_PSM_JMP0;
4255 b43_write32(dev, B43_MMIO_MACCTL, macctl);
4256
4257 b43_dma_free(dev);
4258 b43_pio_free(dev);
4259 b43_chip_exit(dev);
4260 dev->phy.ops->switch_analog(dev, 0);
4261 if (dev->wl->current_beacon) {
4262 dev_kfree_skb_any(dev->wl->current_beacon);
4263 dev->wl->current_beacon = NULL;
4264 }
4265
4266 ssb_device_disable(dev->dev, 0);
4267 ssb_bus_may_powerdown(dev->dev->bus);
4268 }
4269
4270 /* Initialize a wireless core */
4271 static int b43_wireless_core_init(struct b43_wldev *dev)
4272 {
4273 struct ssb_bus *bus = dev->dev->bus;
4274 struct ssb_sprom *sprom = &bus->sprom;
4275 struct b43_phy *phy = &dev->phy;
4276 int err;
4277 u64 hf;
4278 u32 tmp;
4279
4280 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4281
4282 err = ssb_bus_powerup(bus, 0);
4283 if (err)
4284 goto out;
4285 if (!ssb_device_is_enabled(dev->dev)) {
4286 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
4287 b43_wireless_core_reset(dev, tmp);
4288 }
4289
4290 /* Reset all data structures. */
4291 setup_struct_wldev_for_init(dev);
4292 phy->ops->prepare_structs(dev);
4293
4294 /* Enable IRQ routing to this device. */
4295 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
4296
4297 b43_imcfglo_timeouts_workaround(dev);
4298 b43_bluetooth_coext_disable(dev);
4299 if (phy->ops->prepare_hardware) {
4300 err = phy->ops->prepare_hardware(dev);
4301 if (err)
4302 goto err_busdown;
4303 }
4304 err = b43_chip_init(dev);
4305 if (err)
4306 goto err_busdown;
4307 b43_shm_write16(dev, B43_SHM_SHARED,
4308 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
4309 hf = b43_hf_read(dev);
4310 if (phy->type == B43_PHYTYPE_G) {
4311 hf |= B43_HF_SYMW;
4312 if (phy->rev == 1)
4313 hf |= B43_HF_GDCW;
4314 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4315 hf |= B43_HF_OFDMPABOOST;
4316 }
4317 if (phy->radio_ver == 0x2050) {
4318 if (phy->radio_rev == 6)
4319 hf |= B43_HF_4318TSSI;
4320 if (phy->radio_rev < 6)
4321 hf |= B43_HF_VCORECALC;
4322 }
4323 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4324 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
4325 #ifdef CONFIG_SSB_DRIVER_PCICORE
4326 if ((bus->bustype == SSB_BUSTYPE_PCI) &&
4327 (bus->pcicore.dev->id.revision <= 10))
4328 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
4329 #endif
4330 hf &= ~B43_HF_SKCFPUP;
4331 b43_hf_write(dev, hf);
4332
4333 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4334 B43_DEFAULT_LONG_RETRY_LIMIT);
4335 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4336 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4337
4338 /* Disable sending probe responses from firmware.
4339 * Setting the MaxTime to one usec will always trigger
4340 * a timeout, so we never send any probe resp.
4341 * A timeout of zero is infinite. */
4342 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4343
4344 b43_rate_memory_init(dev);
4345 b43_set_phytxctl_defaults(dev);
4346
4347 /* Minimum Contention Window */
4348 if (phy->type == B43_PHYTYPE_B) {
4349 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4350 } else {
4351 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4352 }
4353 /* Maximum Contention Window */
4354 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4355
4356 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) ||
4357 (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) ||
4358 B43_FORCE_PIO) {
4359 dev->__using_pio_transfers = 1;
4360 err = b43_pio_init(dev);
4361 } else {
4362 dev->__using_pio_transfers = 0;
4363 err = b43_dma_init(dev);
4364 }
4365 if (err)
4366 goto err_chip_exit;
4367 b43_qos_init(dev);
4368 b43_set_synth_pu_delay(dev, 1);
4369 b43_bluetooth_coext_enable(dev);
4370
4371 ssb_bus_powerup(bus, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4372 b43_upload_card_macaddress(dev);
4373 b43_security_init(dev);
4374
4375 ieee80211_wake_queues(dev->wl->hw);
4376
4377 b43_set_status(dev, B43_STAT_INITIALIZED);
4378
4379 out:
4380 return err;
4381
4382 err_chip_exit:
4383 b43_chip_exit(dev);
4384 err_busdown:
4385 ssb_bus_may_powerdown(bus);
4386 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4387 return err;
4388 }
4389
4390 static int b43_op_add_interface(struct ieee80211_hw *hw,
4391 struct ieee80211_if_init_conf *conf)
4392 {
4393 struct b43_wl *wl = hw_to_b43_wl(hw);
4394 struct b43_wldev *dev;
4395 int err = -EOPNOTSUPP;
4396
4397 /* TODO: allow WDS/AP devices to coexist */
4398
4399 if (conf->type != NL80211_IFTYPE_AP &&
4400 conf->type != NL80211_IFTYPE_MESH_POINT &&
4401 conf->type != NL80211_IFTYPE_STATION &&
4402 conf->type != NL80211_IFTYPE_WDS &&
4403 conf->type != NL80211_IFTYPE_ADHOC)
4404 return -EOPNOTSUPP;
4405
4406 mutex_lock(&wl->mutex);
4407 if (wl->operating)
4408 goto out_mutex_unlock;
4409
4410 b43dbg(wl, "Adding Interface type %d\n", conf->type);
4411
4412 dev = wl->current_dev;
4413 wl->operating = 1;
4414 wl->vif = conf->vif;
4415 wl->if_type = conf->type;
4416 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
4417
4418 b43_adjust_opmode(dev);
4419 b43_set_pretbtt(dev);
4420 b43_set_synth_pu_delay(dev, 0);
4421 b43_upload_card_macaddress(dev);
4422
4423 err = 0;
4424 out_mutex_unlock:
4425 mutex_unlock(&wl->mutex);
4426
4427 return err;
4428 }
4429
4430 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4431 struct ieee80211_if_init_conf *conf)
4432 {
4433 struct b43_wl *wl = hw_to_b43_wl(hw);
4434 struct b43_wldev *dev = wl->current_dev;
4435
4436 b43dbg(wl, "Removing Interface type %d\n", conf->type);
4437
4438 mutex_lock(&wl->mutex);
4439
4440 B43_WARN_ON(!wl->operating);
4441 B43_WARN_ON(wl->vif != conf->vif);
4442 wl->vif = NULL;
4443
4444 wl->operating = 0;
4445
4446 b43_adjust_opmode(dev);
4447 memset(wl->mac_addr, 0, ETH_ALEN);
4448 b43_upload_card_macaddress(dev);
4449
4450 mutex_unlock(&wl->mutex);
4451 }
4452
4453 static int b43_op_start(struct ieee80211_hw *hw)
4454 {
4455 struct b43_wl *wl = hw_to_b43_wl(hw);
4456 struct b43_wldev *dev = wl->current_dev;
4457 int did_init = 0;
4458 int err = 0;
4459
4460 /* Kill all old instance specific information to make sure
4461 * the card won't use it in the short timeframe between start
4462 * and mac80211 reconfiguring it. */
4463 memset(wl->bssid, 0, ETH_ALEN);
4464 memset(wl->mac_addr, 0, ETH_ALEN);
4465 wl->filter_flags = 0;
4466 wl->radiotap_enabled = 0;
4467 b43_qos_clear(wl);
4468 wl->beacon0_uploaded = 0;
4469 wl->beacon1_uploaded = 0;
4470 wl->beacon_templates_virgin = 1;
4471 wl->radio_enabled = 1;
4472
4473 mutex_lock(&wl->mutex);
4474
4475 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4476 err = b43_wireless_core_init(dev);
4477 if (err)
4478 goto out_mutex_unlock;
4479 did_init = 1;
4480 }
4481
4482 if (b43_status(dev) < B43_STAT_STARTED) {
4483 err = b43_wireless_core_start(dev);
4484 if (err) {
4485 if (did_init)
4486 b43_wireless_core_exit(dev);
4487 goto out_mutex_unlock;
4488 }
4489 }
4490
4491 /* XXX: only do if device doesn't support rfkill irq */
4492 wiphy_rfkill_start_polling(hw->wiphy);
4493
4494 out_mutex_unlock:
4495 mutex_unlock(&wl->mutex);
4496
4497 return err;
4498 }
4499
4500 static void b43_op_stop(struct ieee80211_hw *hw)
4501 {
4502 struct b43_wl *wl = hw_to_b43_wl(hw);
4503 struct b43_wldev *dev = wl->current_dev;
4504
4505 cancel_work_sync(&(wl->beacon_update_trigger));
4506
4507 mutex_lock(&wl->mutex);
4508 if (b43_status(dev) >= B43_STAT_STARTED) {
4509 dev = b43_wireless_core_stop(dev);
4510 if (!dev)
4511 goto out_unlock;
4512 }
4513 b43_wireless_core_exit(dev);
4514 wl->radio_enabled = 0;
4515
4516 out_unlock:
4517 mutex_unlock(&wl->mutex);
4518
4519 cancel_work_sync(&(wl->txpower_adjust_work));
4520 }
4521
4522 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4523 struct ieee80211_sta *sta, bool set)
4524 {
4525 struct b43_wl *wl = hw_to_b43_wl(hw);
4526
4527 /* FIXME: add locking */
4528 b43_update_templates(wl);
4529
4530 return 0;
4531 }
4532
4533 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4534 struct ieee80211_vif *vif,
4535 enum sta_notify_cmd notify_cmd,
4536 struct ieee80211_sta *sta)
4537 {
4538 struct b43_wl *wl = hw_to_b43_wl(hw);
4539
4540 B43_WARN_ON(!vif || wl->vif != vif);
4541 }
4542
4543 static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4544 {
4545 struct b43_wl *wl = hw_to_b43_wl(hw);
4546 struct b43_wldev *dev;
4547
4548 mutex_lock(&wl->mutex);
4549 dev = wl->current_dev;
4550 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4551 /* Disable CFP update during scan on other channels. */
4552 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4553 }
4554 mutex_unlock(&wl->mutex);
4555 }
4556
4557 static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4558 {
4559 struct b43_wl *wl = hw_to_b43_wl(hw);
4560 struct b43_wldev *dev;
4561
4562 mutex_lock(&wl->mutex);
4563 dev = wl->current_dev;
4564 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4565 /* Re-enable CFP update. */
4566 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4567 }
4568 mutex_unlock(&wl->mutex);
4569 }
4570
4571 static const struct ieee80211_ops b43_hw_ops = {
4572 .tx = b43_op_tx,
4573 .conf_tx = b43_op_conf_tx,
4574 .add_interface = b43_op_add_interface,
4575 .remove_interface = b43_op_remove_interface,
4576 .config = b43_op_config,
4577 .bss_info_changed = b43_op_bss_info_changed,
4578 .configure_filter = b43_op_configure_filter,
4579 .set_key = b43_op_set_key,
4580 .update_tkip_key = b43_op_update_tkip_key,
4581 .get_stats = b43_op_get_stats,
4582 .get_tx_stats = b43_op_get_tx_stats,
4583 .get_tsf = b43_op_get_tsf,
4584 .set_tsf = b43_op_set_tsf,
4585 .start = b43_op_start,
4586 .stop = b43_op_stop,
4587 .set_tim = b43_op_beacon_set_tim,
4588 .sta_notify = b43_op_sta_notify,
4589 .sw_scan_start = b43_op_sw_scan_start_notifier,
4590 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
4591 .rfkill_poll = b43_rfkill_poll,
4592 };
4593
4594 /* Hard-reset the chip. Do not call this directly.
4595 * Use b43_controller_restart()
4596 */
4597 static void b43_chip_reset(struct work_struct *work)
4598 {
4599 struct b43_wldev *dev =
4600 container_of(work, struct b43_wldev, restart_work);
4601 struct b43_wl *wl = dev->wl;
4602 int err = 0;
4603 int prev_status;
4604
4605 mutex_lock(&wl->mutex);
4606
4607 prev_status = b43_status(dev);
4608 /* Bring the device down... */
4609 if (prev_status >= B43_STAT_STARTED) {
4610 dev = b43_wireless_core_stop(dev);
4611 if (!dev) {
4612 err = -ENODEV;
4613 goto out;
4614 }
4615 }
4616 if (prev_status >= B43_STAT_INITIALIZED)
4617 b43_wireless_core_exit(dev);
4618
4619 /* ...and up again. */
4620 if (prev_status >= B43_STAT_INITIALIZED) {
4621 err = b43_wireless_core_init(dev);
4622 if (err)
4623 goto out;
4624 }
4625 if (prev_status >= B43_STAT_STARTED) {
4626 err = b43_wireless_core_start(dev);
4627 if (err) {
4628 b43_wireless_core_exit(dev);
4629 goto out;
4630 }
4631 }
4632 out:
4633 if (err)
4634 wl->current_dev = NULL; /* Failed to init the dev. */
4635 mutex_unlock(&wl->mutex);
4636 if (err)
4637 b43err(wl, "Controller restart FAILED\n");
4638 else
4639 b43info(wl, "Controller restarted\n");
4640 }
4641
4642 static int b43_setup_bands(struct b43_wldev *dev,
4643 bool have_2ghz_phy, bool have_5ghz_phy)
4644 {
4645 struct ieee80211_hw *hw = dev->wl->hw;
4646
4647 if (have_2ghz_phy)
4648 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4649 if (dev->phy.type == B43_PHYTYPE_N) {
4650 if (have_5ghz_phy)
4651 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4652 } else {
4653 if (have_5ghz_phy)
4654 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4655 }
4656
4657 dev->phy.supports_2ghz = have_2ghz_phy;
4658 dev->phy.supports_5ghz = have_5ghz_phy;
4659
4660 return 0;
4661 }
4662
4663 static void b43_wireless_core_detach(struct b43_wldev *dev)
4664 {
4665 /* We release firmware that late to not be required to re-request
4666 * is all the time when we reinit the core. */
4667 b43_release_firmware(dev);
4668 b43_phy_free(dev);
4669 }
4670
4671 static int b43_wireless_core_attach(struct b43_wldev *dev)
4672 {
4673 struct b43_wl *wl = dev->wl;
4674 struct ssb_bus *bus = dev->dev->bus;
4675 struct pci_dev *pdev = bus->host_pci;
4676 int err;
4677 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
4678 u32 tmp;
4679
4680 /* Do NOT do any device initialization here.
4681 * Do it in wireless_core_init() instead.
4682 * This function is for gathering basic information about the HW, only.
4683 * Also some structs may be set up here. But most likely you want to have
4684 * that in core_init(), too.
4685 */
4686
4687 err = ssb_bus_powerup(bus, 0);
4688 if (err) {
4689 b43err(wl, "Bus powerup failed\n");
4690 goto out;
4691 }
4692 /* Get the PHY type. */
4693 if (dev->dev->id.revision >= 5) {
4694 u32 tmshigh;
4695
4696 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
4697 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4698 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
4699 } else
4700 B43_WARN_ON(1);
4701
4702 dev->phy.gmode = have_2ghz_phy;
4703 dev->phy.radio_on = 1;
4704 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4705 b43_wireless_core_reset(dev, tmp);
4706
4707 err = b43_phy_versioning(dev);
4708 if (err)
4709 goto err_powerdown;
4710 /* Check if this device supports multiband. */
4711 if (!pdev ||
4712 (pdev->device != 0x4312 &&
4713 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4714 /* No multiband support. */
4715 have_2ghz_phy = 0;
4716 have_5ghz_phy = 0;
4717 switch (dev->phy.type) {
4718 case B43_PHYTYPE_A:
4719 have_5ghz_phy = 1;
4720 break;
4721 case B43_PHYTYPE_LP: //FIXME not always!
4722 #if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
4723 have_5ghz_phy = 1;
4724 #endif
4725 case B43_PHYTYPE_G:
4726 case B43_PHYTYPE_N:
4727 have_2ghz_phy = 1;
4728 break;
4729 default:
4730 B43_WARN_ON(1);
4731 }
4732 }
4733 if (dev->phy.type == B43_PHYTYPE_A) {
4734 /* FIXME */
4735 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4736 err = -EOPNOTSUPP;
4737 goto err_powerdown;
4738 }
4739 if (1 /* disable A-PHY */) {
4740 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
4741 if (dev->phy.type != B43_PHYTYPE_N &&
4742 dev->phy.type != B43_PHYTYPE_LP) {
4743 have_2ghz_phy = 1;
4744 have_5ghz_phy = 0;
4745 }
4746 }
4747
4748 err = b43_phy_allocate(dev);
4749 if (err)
4750 goto err_powerdown;
4751
4752 dev->phy.gmode = have_2ghz_phy;
4753 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4754 b43_wireless_core_reset(dev, tmp);
4755
4756 err = b43_validate_chipaccess(dev);
4757 if (err)
4758 goto err_phy_free;
4759 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
4760 if (err)
4761 goto err_phy_free;
4762
4763 /* Now set some default "current_dev" */
4764 if (!wl->current_dev)
4765 wl->current_dev = dev;
4766 INIT_WORK(&dev->restart_work, b43_chip_reset);
4767
4768 dev->phy.ops->switch_analog(dev, 0);
4769 ssb_device_disable(dev->dev, 0);
4770 ssb_bus_may_powerdown(bus);
4771
4772 out:
4773 return err;
4774
4775 err_phy_free:
4776 b43_phy_free(dev);
4777 err_powerdown:
4778 ssb_bus_may_powerdown(bus);
4779 return err;
4780 }
4781
4782 static void b43_one_core_detach(struct ssb_device *dev)
4783 {
4784 struct b43_wldev *wldev;
4785 struct b43_wl *wl;
4786
4787 /* Do not cancel ieee80211-workqueue based work here.
4788 * See comment in b43_remove(). */
4789
4790 wldev = ssb_get_drvdata(dev);
4791 wl = wldev->wl;
4792 b43_debugfs_remove_device(wldev);
4793 b43_wireless_core_detach(wldev);
4794 list_del(&wldev->list);
4795 wl->nr_devs--;
4796 ssb_set_drvdata(dev, NULL);
4797 kfree(wldev);
4798 }
4799
4800 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4801 {
4802 struct b43_wldev *wldev;
4803 struct pci_dev *pdev;
4804 int err = -ENOMEM;
4805
4806 if (!list_empty(&wl->devlist)) {
4807 /* We are not the first core on this chip. */
4808 pdev = dev->bus->host_pci;
4809 /* Only special chips support more than one wireless
4810 * core, although some of the other chips have more than
4811 * one wireless core as well. Check for this and
4812 * bail out early.
4813 */
4814 if (!pdev ||
4815 ((pdev->device != 0x4321) &&
4816 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4817 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4818 return -ENODEV;
4819 }
4820 }
4821
4822 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4823 if (!wldev)
4824 goto out;
4825
4826 wldev->dev = dev;
4827 wldev->wl = wl;
4828 b43_set_status(wldev, B43_STAT_UNINIT);
4829 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4830 INIT_LIST_HEAD(&wldev->list);
4831
4832 err = b43_wireless_core_attach(wldev);
4833 if (err)
4834 goto err_kfree_wldev;
4835
4836 list_add(&wldev->list, &wl->devlist);
4837 wl->nr_devs++;
4838 ssb_set_drvdata(dev, wldev);
4839 b43_debugfs_add_device(wldev);
4840
4841 out:
4842 return err;
4843
4844 err_kfree_wldev:
4845 kfree(wldev);
4846 return err;
4847 }
4848
4849 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4850 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4851 (pdev->device == _device) && \
4852 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4853 (pdev->subsystem_device == _subdevice) )
4854
4855 static void b43_sprom_fixup(struct ssb_bus *bus)
4856 {
4857 struct pci_dev *pdev;
4858
4859 /* boardflags workarounds */
4860 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4861 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
4862 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
4863 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4864 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
4865 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
4866 if (bus->bustype == SSB_BUSTYPE_PCI) {
4867 pdev = bus->host_pci;
4868 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
4869 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
4870 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
4871 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
4872 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
4873 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
4874 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
4875 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4876 }
4877 }
4878
4879 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4880 {
4881 struct ieee80211_hw *hw = wl->hw;
4882
4883 ssb_set_devtypedata(dev, NULL);
4884 ieee80211_free_hw(hw);
4885 }
4886
4887 static int b43_wireless_init(struct ssb_device *dev)
4888 {
4889 struct ssb_sprom *sprom = &dev->bus->sprom;
4890 struct ieee80211_hw *hw;
4891 struct b43_wl *wl;
4892 int err = -ENOMEM;
4893
4894 b43_sprom_fixup(dev->bus);
4895
4896 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4897 if (!hw) {
4898 b43err(NULL, "Could not allocate ieee80211 device\n");
4899 goto out;
4900 }
4901 wl = hw_to_b43_wl(hw);
4902
4903 /* fill hw info */
4904 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
4905 IEEE80211_HW_SIGNAL_DBM |
4906 IEEE80211_HW_NOISE_DBM;
4907
4908 hw->wiphy->interface_modes =
4909 BIT(NL80211_IFTYPE_AP) |
4910 BIT(NL80211_IFTYPE_MESH_POINT) |
4911 BIT(NL80211_IFTYPE_STATION) |
4912 BIT(NL80211_IFTYPE_WDS) |
4913 BIT(NL80211_IFTYPE_ADHOC);
4914
4915 hw->queues = modparam_qos ? 4 : 1;
4916 wl->mac80211_initially_registered_queues = hw->queues;
4917 hw->max_rates = 2;
4918 SET_IEEE80211_DEV(hw, dev->dev);
4919 if (is_valid_ether_addr(sprom->et1mac))
4920 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
4921 else
4922 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
4923
4924 /* Initialize struct b43_wl */
4925 wl->hw = hw;
4926 mutex_init(&wl->mutex);
4927 spin_lock_init(&wl->hardirq_lock);
4928 INIT_LIST_HEAD(&wl->devlist);
4929 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
4930 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
4931 INIT_WORK(&wl->tx_work, b43_tx_work);
4932 skb_queue_head_init(&wl->tx_queue);
4933
4934 ssb_set_devtypedata(dev, wl);
4935 b43info(wl, "Broadcom %04X WLAN found (core revision %u)\n",
4936 dev->bus->chip_id, dev->id.revision);
4937 err = 0;
4938 out:
4939 return err;
4940 }
4941
4942 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4943 {
4944 struct b43_wl *wl;
4945 int err;
4946 int first = 0;
4947
4948 wl = ssb_get_devtypedata(dev);
4949 if (!wl) {
4950 /* Probing the first core. Must setup common struct b43_wl */
4951 first = 1;
4952 err = b43_wireless_init(dev);
4953 if (err)
4954 goto out;
4955 wl = ssb_get_devtypedata(dev);
4956 B43_WARN_ON(!wl);
4957 }
4958 err = b43_one_core_attach(dev, wl);
4959 if (err)
4960 goto err_wireless_exit;
4961
4962 if (first) {
4963 err = ieee80211_register_hw(wl->hw);
4964 if (err)
4965 goto err_one_core_detach;
4966 b43_leds_register(wl->current_dev);
4967 b43_rng_init(wl);
4968 }
4969
4970 out:
4971 return err;
4972
4973 err_one_core_detach:
4974 b43_one_core_detach(dev);
4975 err_wireless_exit:
4976 if (first)
4977 b43_wireless_exit(dev, wl);
4978 return err;
4979 }
4980
4981 static void b43_remove(struct ssb_device *dev)
4982 {
4983 struct b43_wl *wl = ssb_get_devtypedata(dev);
4984 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4985
4986 /* We must cancel any work here before unregistering from ieee80211,
4987 * as the ieee80211 unreg will destroy the workqueue. */
4988 cancel_work_sync(&wldev->restart_work);
4989
4990 B43_WARN_ON(!wl);
4991 if (wl->current_dev == wldev) {
4992 /* Restore the queues count before unregistering, because firmware detect
4993 * might have modified it. Restoring is important, so the networking
4994 * stack can properly free resources. */
4995 wl->hw->queues = wl->mac80211_initially_registered_queues;
4996 b43_leds_stop(wldev);
4997 ieee80211_unregister_hw(wl->hw);
4998 }
4999
5000 b43_one_core_detach(dev);
5001
5002 if (list_empty(&wl->devlist)) {
5003 b43_rng_exit(wl);
5004 b43_leds_unregister(wl);
5005 /* Last core on the chip unregistered.
5006 * We can destroy common struct b43_wl.
5007 */
5008 b43_wireless_exit(dev, wl);
5009 }
5010 }
5011
5012 /* Perform a hardware reset. This can be called from any context. */
5013 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5014 {
5015 /* Must avoid requeueing, if we are in shutdown. */
5016 if (b43_status(dev) < B43_STAT_INITIALIZED)
5017 return;
5018 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
5019 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
5020 }
5021
5022 static struct ssb_driver b43_ssb_driver = {
5023 .name = KBUILD_MODNAME,
5024 .id_table = b43_ssb_tbl,
5025 .probe = b43_probe,
5026 .remove = b43_remove,
5027 };
5028
5029 static void b43_print_driverinfo(void)
5030 {
5031 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
5032 *feat_leds = "", *feat_sdio = "";
5033
5034 #ifdef CONFIG_B43_PCI_AUTOSELECT
5035 feat_pci = "P";
5036 #endif
5037 #ifdef CONFIG_B43_PCMCIA
5038 feat_pcmcia = "M";
5039 #endif
5040 #ifdef CONFIG_B43_NPHY
5041 feat_nphy = "N";
5042 #endif
5043 #ifdef CONFIG_B43_LEDS
5044 feat_leds = "L";
5045 #endif
5046 #ifdef CONFIG_B43_SDIO
5047 feat_sdio = "S";
5048 #endif
5049 printk(KERN_INFO "Broadcom 43xx driver loaded "
5050 "[ Features: %s%s%s%s%s, Firmware-ID: "
5051 B43_SUPPORTED_FIRMWARE_ID " ]\n",
5052 feat_pci, feat_pcmcia, feat_nphy,
5053 feat_leds, feat_sdio);
5054 }
5055
5056 static int __init b43_init(void)
5057 {
5058 int err;
5059
5060 b43_debugfs_init();
5061 err = b43_pcmcia_init();
5062 if (err)
5063 goto err_dfs_exit;
5064 err = b43_sdio_init();
5065 if (err)
5066 goto err_pcmcia_exit;
5067 err = ssb_driver_register(&b43_ssb_driver);
5068 if (err)
5069 goto err_sdio_exit;
5070 b43_print_driverinfo();
5071
5072 return err;
5073
5074 err_sdio_exit:
5075 b43_sdio_exit();
5076 err_pcmcia_exit:
5077 b43_pcmcia_exit();
5078 err_dfs_exit:
5079 b43_debugfs_exit();
5080 return err;
5081 }
5082
5083 static void __exit b43_exit(void)
5084 {
5085 ssb_driver_unregister(&b43_ssb_driver);
5086 b43_sdio_exit();
5087 b43_pcmcia_exit();
5088 b43_debugfs_exit();
5089 }
5090
5091 module_init(b43_init)
5092 module_exit(b43_exit)
Support for the Chinese Samsung S3C2440 based development boards