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KVM: VMX: Fix cr8 exiting control clobbering by EPT
[linux-2.6/mini2440.git] / arch / x86 / kvm / vmx.c
blob691f8e0ff91bfd0cee17f453dcff280aa38d2c0b
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "irq.h"
19 #include "mmu.h"
20
21 #include <linux/kvm_host.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/mm.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27 #include <linux/moduleparam.h>
28 #include "kvm_cache_regs.h"
29 #include "x86.h"
30
31 #include <asm/io.h>
32 #include <asm/desc.h>
33 #include <asm/vmx.h>
34 #include <asm/virtext.h>
35 #include <asm/mce.h>
36
37 #define __ex(x) __kvm_handle_fault_on_reboot(x)
38
39 MODULE_AUTHOR("Qumranet");
40 MODULE_LICENSE("GPL");
41
42 static int bypass_guest_pf = 1;
43 module_param(bypass_guest_pf, bool, 0);
44
45 static int enable_vpid = 1;
46 module_param(enable_vpid, bool, 0);
47
48 static int flexpriority_enabled = 1;
49 module_param(flexpriority_enabled, bool, 0);
50
51 static int enable_ept = 1;
52 module_param(enable_ept, bool, 0);
53
54 static int emulate_invalid_guest_state = 0;
55 module_param(emulate_invalid_guest_state, bool, 0);
56
57 struct vmcs {
58 u32 revision_id;
59 u32 abort;
60 char data[0];
61 };
62
63 struct vcpu_vmx {
64 struct kvm_vcpu vcpu;
65 struct list_head local_vcpus_link;
66 unsigned long host_rsp;
67 int launched;
68 u8 fail;
69 u32 idt_vectoring_info;
70 struct kvm_msr_entry *guest_msrs;
71 struct kvm_msr_entry *host_msrs;
72 int nmsrs;
73 int save_nmsrs;
74 int msr_offset_efer;
75 #ifdef CONFIG_X86_64
76 int msr_offset_kernel_gs_base;
77 #endif
78 struct vmcs *vmcs;
79 struct {
80 int loaded;
81 u16 fs_sel, gs_sel, ldt_sel;
82 int gs_ldt_reload_needed;
83 int fs_reload_needed;
84 int guest_efer_loaded;
85 } host_state;
86 struct {
87 struct {
88 bool pending;
89 u8 vector;
90 unsigned rip;
91 } irq;
92 } rmode;
93 int vpid;
94 bool emulation_required;
95 enum emulation_result invalid_state_emulation_result;
96
97 /* Support for vnmi-less CPUs */
98 int soft_vnmi_blocked;
99 ktime_t entry_time;
100 s64 vnmi_blocked_time;
101
102 u32 exit_reason;
103 };
104
105 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
106 {
107 return container_of(vcpu, struct vcpu_vmx, vcpu);
108 }
109
110 static int init_rmode(struct kvm *kvm);
111 static u64 construct_eptp(unsigned long root_hpa);
112
113 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
114 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
115 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
116
117 static struct page *vmx_io_bitmap_a;
118 static struct page *vmx_io_bitmap_b;
119 static struct page *vmx_msr_bitmap;
120
121 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
122 static DEFINE_SPINLOCK(vmx_vpid_lock);
123
124 static struct vmcs_config {
125 int size;
126 int order;
127 u32 revision_id;
128 u32 pin_based_exec_ctrl;
129 u32 cpu_based_exec_ctrl;
130 u32 cpu_based_2nd_exec_ctrl;
131 u32 vmexit_ctrl;
132 u32 vmentry_ctrl;
133 } vmcs_config;
134
135 static struct vmx_capability {
136 u32 ept;
137 u32 vpid;
138 } vmx_capability;
139
140 #define VMX_SEGMENT_FIELD(seg) \
141 [VCPU_SREG_##seg] = { \
142 .selector = GUEST_##seg##_SELECTOR, \
143 .base = GUEST_##seg##_BASE, \
144 .limit = GUEST_##seg##_LIMIT, \
145 .ar_bytes = GUEST_##seg##_AR_BYTES, \
146 }
147
148 static struct kvm_vmx_segment_field {
149 unsigned selector;
150 unsigned base;
151 unsigned limit;
152 unsigned ar_bytes;
153 } kvm_vmx_segment_fields[] = {
154 VMX_SEGMENT_FIELD(CS),
155 VMX_SEGMENT_FIELD(DS),
156 VMX_SEGMENT_FIELD(ES),
157 VMX_SEGMENT_FIELD(FS),
158 VMX_SEGMENT_FIELD(GS),
159 VMX_SEGMENT_FIELD(SS),
160 VMX_SEGMENT_FIELD(TR),
161 VMX_SEGMENT_FIELD(LDTR),
162 };
163
164 /*
165 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
166 * away by decrementing the array size.
167 */
168 static const u32 vmx_msr_index[] = {
169 #ifdef CONFIG_X86_64
170 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
171 #endif
172 MSR_EFER, MSR_K6_STAR,
173 };
174 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
175
176 static void load_msrs(struct kvm_msr_entry *e, int n)
177 {
178 int i;
179
180 for (i = 0; i < n; ++i)
181 wrmsrl(e[i].index, e[i].data);
182 }
183
184 static void save_msrs(struct kvm_msr_entry *e, int n)
185 {
186 int i;
187
188 for (i = 0; i < n; ++i)
189 rdmsrl(e[i].index, e[i].data);
190 }
191
192 static inline int is_page_fault(u32 intr_info)
193 {
194 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
195 INTR_INFO_VALID_MASK)) ==
196 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
197 }
198
199 static inline int is_no_device(u32 intr_info)
200 {
201 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
202 INTR_INFO_VALID_MASK)) ==
203 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
204 }
205
206 static inline int is_invalid_opcode(u32 intr_info)
207 {
208 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
209 INTR_INFO_VALID_MASK)) ==
210 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
211 }
212
213 static inline int is_external_interrupt(u32 intr_info)
214 {
215 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
216 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
217 }
218
219 static inline int cpu_has_vmx_msr_bitmap(void)
220 {
221 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
222 }
223
224 static inline int cpu_has_vmx_tpr_shadow(void)
225 {
226 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
227 }
228
229 static inline int vm_need_tpr_shadow(struct kvm *kvm)
230 {
231 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
232 }
233
234 static inline int cpu_has_secondary_exec_ctrls(void)
235 {
236 return (vmcs_config.cpu_based_exec_ctrl &
237 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
238 }
239
240 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
241 {
242 return flexpriority_enabled
243 && (vmcs_config.cpu_based_2nd_exec_ctrl &
244 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
245 }
246
247 static inline int cpu_has_vmx_invept_individual_addr(void)
248 {
249 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
250 }
251
252 static inline int cpu_has_vmx_invept_context(void)
253 {
254 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
255 }
256
257 static inline int cpu_has_vmx_invept_global(void)
258 {
259 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
260 }
261
262 static inline int cpu_has_vmx_ept(void)
263 {
264 return (vmcs_config.cpu_based_2nd_exec_ctrl &
265 SECONDARY_EXEC_ENABLE_EPT);
266 }
267
268 static inline int vm_need_ept(void)
269 {
270 return (cpu_has_vmx_ept() && enable_ept);
271 }
272
273 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
274 {
275 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
276 (irqchip_in_kernel(kvm)));
277 }
278
279 static inline int cpu_has_vmx_vpid(void)
280 {
281 return (vmcs_config.cpu_based_2nd_exec_ctrl &
282 SECONDARY_EXEC_ENABLE_VPID);
283 }
284
285 static inline int cpu_has_virtual_nmis(void)
286 {
287 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
288 }
289
290 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
291 {
292 int i;
293
294 for (i = 0; i < vmx->nmsrs; ++i)
295 if (vmx->guest_msrs[i].index == msr)
296 return i;
297 return -1;
298 }
299
300 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
301 {
302 struct {
303 u64 vpid : 16;
304 u64 rsvd : 48;
305 u64 gva;
306 } operand = { vpid, 0, gva };
307
308 asm volatile (__ex(ASM_VMX_INVVPID)
309 /* CF==1 or ZF==1 --> rc = -1 */
310 "; ja 1f ; ud2 ; 1:"
311 : : "a"(&operand), "c"(ext) : "cc", "memory");
312 }
313
314 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
315 {
316 struct {
317 u64 eptp, gpa;
318 } operand = {eptp, gpa};
319
320 asm volatile (__ex(ASM_VMX_INVEPT)
321 /* CF==1 or ZF==1 --> rc = -1 */
322 "; ja 1f ; ud2 ; 1:\n"
323 : : "a" (&operand), "c" (ext) : "cc", "memory");
324 }
325
326 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
327 {
328 int i;
329
330 i = __find_msr_index(vmx, msr);
331 if (i >= 0)
332 return &vmx->guest_msrs[i];
333 return NULL;
334 }
335
336 static void vmcs_clear(struct vmcs *vmcs)
337 {
338 u64 phys_addr = __pa(vmcs);
339 u8 error;
340
341 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
342 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
343 : "cc", "memory");
344 if (error)
345 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
346 vmcs, phys_addr);
347 }
348
349 static void __vcpu_clear(void *arg)
350 {
351 struct vcpu_vmx *vmx = arg;
352 int cpu = raw_smp_processor_id();
353
354 if (vmx->vcpu.cpu == cpu)
355 vmcs_clear(vmx->vmcs);
356 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
357 per_cpu(current_vmcs, cpu) = NULL;
358 rdtscll(vmx->vcpu.arch.host_tsc);
359 list_del(&vmx->local_vcpus_link);
360 vmx->vcpu.cpu = -1;
361 vmx->launched = 0;
362 }
363
364 static void vcpu_clear(struct vcpu_vmx *vmx)
365 {
366 if (vmx->vcpu.cpu == -1)
367 return;
368 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
369 }
370
371 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
372 {
373 if (vmx->vpid == 0)
374 return;
375
376 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
377 }
378
379 static inline void ept_sync_global(void)
380 {
381 if (cpu_has_vmx_invept_global())
382 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
383 }
384
385 static inline void ept_sync_context(u64 eptp)
386 {
387 if (vm_need_ept()) {
388 if (cpu_has_vmx_invept_context())
389 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
390 else
391 ept_sync_global();
392 }
393 }
394
395 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
396 {
397 if (vm_need_ept()) {
398 if (cpu_has_vmx_invept_individual_addr())
399 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
400 eptp, gpa);
401 else
402 ept_sync_context(eptp);
403 }
404 }
405
406 static unsigned long vmcs_readl(unsigned long field)
407 {
408 unsigned long value;
409
410 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
411 : "=a"(value) : "d"(field) : "cc");
412 return value;
413 }
414
415 static u16 vmcs_read16(unsigned long field)
416 {
417 return vmcs_readl(field);
418 }
419
420 static u32 vmcs_read32(unsigned long field)
421 {
422 return vmcs_readl(field);
423 }
424
425 static u64 vmcs_read64(unsigned long field)
426 {
427 #ifdef CONFIG_X86_64
428 return vmcs_readl(field);
429 #else
430 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
431 #endif
432 }
433
434 static noinline void vmwrite_error(unsigned long field, unsigned long value)
435 {
436 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
437 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
438 dump_stack();
439 }
440
441 static void vmcs_writel(unsigned long field, unsigned long value)
442 {
443 u8 error;
444
445 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
446 : "=q"(error) : "a"(value), "d"(field) : "cc");
447 if (unlikely(error))
448 vmwrite_error(field, value);
449 }
450
451 static void vmcs_write16(unsigned long field, u16 value)
452 {
453 vmcs_writel(field, value);
454 }
455
456 static void vmcs_write32(unsigned long field, u32 value)
457 {
458 vmcs_writel(field, value);
459 }
460
461 static void vmcs_write64(unsigned long field, u64 value)
462 {
463 vmcs_writel(field, value);
464 #ifndef CONFIG_X86_64
465 asm volatile ("");
466 vmcs_writel(field+1, value >> 32);
467 #endif
468 }
469
470 static void vmcs_clear_bits(unsigned long field, u32 mask)
471 {
472 vmcs_writel(field, vmcs_readl(field) & ~mask);
473 }
474
475 static void vmcs_set_bits(unsigned long field, u32 mask)
476 {
477 vmcs_writel(field, vmcs_readl(field) | mask);
478 }
479
480 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
481 {
482 u32 eb;
483
484 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
485 if (!vcpu->fpu_active)
486 eb |= 1u << NM_VECTOR;
487 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
488 if (vcpu->guest_debug &
489 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
490 eb |= 1u << DB_VECTOR;
491 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
492 eb |= 1u << BP_VECTOR;
493 }
494 if (vcpu->arch.rmode.active)
495 eb = ~0;
496 if (vm_need_ept())
497 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
498 vmcs_write32(EXCEPTION_BITMAP, eb);
499 }
500
501 static void reload_tss(void)
502 {
503 /*
504 * VT restores TR but not its size. Useless.
505 */
506 struct descriptor_table gdt;
507 struct desc_struct *descs;
508
509 kvm_get_gdt(&gdt);
510 descs = (void *)gdt.base;
511 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
512 load_TR_desc();
513 }
514
515 static void load_transition_efer(struct vcpu_vmx *vmx)
516 {
517 int efer_offset = vmx->msr_offset_efer;
518 u64 host_efer = vmx->host_msrs[efer_offset].data;
519 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
520 u64 ignore_bits;
521
522 if (efer_offset < 0)
523 return;
524 /*
525 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
526 * outside long mode
527 */
528 ignore_bits = EFER_NX | EFER_SCE;
529 #ifdef CONFIG_X86_64
530 ignore_bits |= EFER_LMA | EFER_LME;
531 /* SCE is meaningful only in long mode on Intel */
532 if (guest_efer & EFER_LMA)
533 ignore_bits &= ~(u64)EFER_SCE;
534 #endif
535 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
536 return;
537
538 vmx->host_state.guest_efer_loaded = 1;
539 guest_efer &= ~ignore_bits;
540 guest_efer |= host_efer & ignore_bits;
541 wrmsrl(MSR_EFER, guest_efer);
542 vmx->vcpu.stat.efer_reload++;
543 }
544
545 static void reload_host_efer(struct vcpu_vmx *vmx)
546 {
547 if (vmx->host_state.guest_efer_loaded) {
548 vmx->host_state.guest_efer_loaded = 0;
549 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
550 }
551 }
552
553 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
554 {
555 struct vcpu_vmx *vmx = to_vmx(vcpu);
556
557 if (vmx->host_state.loaded)
558 return;
559
560 vmx->host_state.loaded = 1;
561 /*
562 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
563 * allow segment selectors with cpl > 0 or ti == 1.
564 */
565 vmx->host_state.ldt_sel = kvm_read_ldt();
566 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
567 vmx->host_state.fs_sel = kvm_read_fs();
568 if (!(vmx->host_state.fs_sel & 7)) {
569 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
570 vmx->host_state.fs_reload_needed = 0;
571 } else {
572 vmcs_write16(HOST_FS_SELECTOR, 0);
573 vmx->host_state.fs_reload_needed = 1;
574 }
575 vmx->host_state.gs_sel = kvm_read_gs();
576 if (!(vmx->host_state.gs_sel & 7))
577 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
578 else {
579 vmcs_write16(HOST_GS_SELECTOR, 0);
580 vmx->host_state.gs_ldt_reload_needed = 1;
581 }
582
583 #ifdef CONFIG_X86_64
584 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
585 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
586 #else
587 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
588 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
589 #endif
590
591 #ifdef CONFIG_X86_64
592 if (is_long_mode(&vmx->vcpu))
593 save_msrs(vmx->host_msrs +
594 vmx->msr_offset_kernel_gs_base, 1);
595
596 #endif
597 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
598 load_transition_efer(vmx);
599 }
600
601 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
602 {
603 unsigned long flags;
604
605 if (!vmx->host_state.loaded)
606 return;
607
608 ++vmx->vcpu.stat.host_state_reload;
609 vmx->host_state.loaded = 0;
610 if (vmx->host_state.fs_reload_needed)
611 kvm_load_fs(vmx->host_state.fs_sel);
612 if (vmx->host_state.gs_ldt_reload_needed) {
613 kvm_load_ldt(vmx->host_state.ldt_sel);
614 /*
615 * If we have to reload gs, we must take care to
616 * preserve our gs base.
617 */
618 local_irq_save(flags);
619 kvm_load_gs(vmx->host_state.gs_sel);
620 #ifdef CONFIG_X86_64
621 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
622 #endif
623 local_irq_restore(flags);
624 }
625 reload_tss();
626 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
627 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
628 reload_host_efer(vmx);
629 }
630
631 static void vmx_load_host_state(struct vcpu_vmx *vmx)
632 {
633 preempt_disable();
634 __vmx_load_host_state(vmx);
635 preempt_enable();
636 }
637
638 /*
639 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
640 * vcpu mutex is already taken.
641 */
642 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
643 {
644 struct vcpu_vmx *vmx = to_vmx(vcpu);
645 u64 phys_addr = __pa(vmx->vmcs);
646 u64 tsc_this, delta, new_offset;
647
648 if (vcpu->cpu != cpu) {
649 vcpu_clear(vmx);
650 kvm_migrate_timers(vcpu);
651 vpid_sync_vcpu_all(vmx);
652 local_irq_disable();
653 list_add(&vmx->local_vcpus_link,
654 &per_cpu(vcpus_on_cpu, cpu));
655 local_irq_enable();
656 }
657
658 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
659 u8 error;
660
661 per_cpu(current_vmcs, cpu) = vmx->vmcs;
662 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
663 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
664 : "cc");
665 if (error)
666 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
667 vmx->vmcs, phys_addr);
668 }
669
670 if (vcpu->cpu != cpu) {
671 struct descriptor_table dt;
672 unsigned long sysenter_esp;
673
674 vcpu->cpu = cpu;
675 /*
676 * Linux uses per-cpu TSS and GDT, so set these when switching
677 * processors.
678 */
679 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
680 kvm_get_gdt(&dt);
681 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
682
683 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
684 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
685
686 /*
687 * Make sure the time stamp counter is monotonous.
688 */
689 rdtscll(tsc_this);
690 if (tsc_this < vcpu->arch.host_tsc) {
691 delta = vcpu->arch.host_tsc - tsc_this;
692 new_offset = vmcs_read64(TSC_OFFSET) + delta;
693 vmcs_write64(TSC_OFFSET, new_offset);
694 }
695 }
696 }
697
698 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
699 {
700 __vmx_load_host_state(to_vmx(vcpu));
701 }
702
703 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
704 {
705 if (vcpu->fpu_active)
706 return;
707 vcpu->fpu_active = 1;
708 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
709 if (vcpu->arch.cr0 & X86_CR0_TS)
710 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
711 update_exception_bitmap(vcpu);
712 }
713
714 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
715 {
716 if (!vcpu->fpu_active)
717 return;
718 vcpu->fpu_active = 0;
719 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
720 update_exception_bitmap(vcpu);
721 }
722
723 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
724 {
725 return vmcs_readl(GUEST_RFLAGS);
726 }
727
728 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
729 {
730 if (vcpu->arch.rmode.active)
731 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
732 vmcs_writel(GUEST_RFLAGS, rflags);
733 }
734
735 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
736 {
737 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
738 int ret = 0;
739
740 if (interruptibility & GUEST_INTR_STATE_STI)
741 ret |= X86_SHADOW_INT_STI;
742 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
743 ret |= X86_SHADOW_INT_MOV_SS;
744
745 return ret & mask;
746 }
747
748 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
749 {
750 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
751 u32 interruptibility = interruptibility_old;
752
753 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
754
755 if (mask & X86_SHADOW_INT_MOV_SS)
756 interruptibility |= GUEST_INTR_STATE_MOV_SS;
757 if (mask & X86_SHADOW_INT_STI)
758 interruptibility |= GUEST_INTR_STATE_STI;
759
760 if ((interruptibility != interruptibility_old))
761 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
762 }
763
764 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
765 {
766 unsigned long rip;
767
768 rip = kvm_rip_read(vcpu);
769 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
770 kvm_rip_write(vcpu, rip);
771
772 /* skipping an emulated instruction also counts */
773 vmx_set_interrupt_shadow(vcpu, 0);
774 vcpu->arch.interrupt_window_open = 1;
775 }
776
777 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
778 bool has_error_code, u32 error_code)
779 {
780 struct vcpu_vmx *vmx = to_vmx(vcpu);
781 u32 intr_info = nr | INTR_INFO_VALID_MASK;
782
783 if (has_error_code) {
784 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
785 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
786 }
787
788 if (vcpu->arch.rmode.active) {
789 vmx->rmode.irq.pending = true;
790 vmx->rmode.irq.vector = nr;
791 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
792 if (nr == BP_VECTOR || nr == OF_VECTOR)
793 vmx->rmode.irq.rip++;
794 intr_info |= INTR_TYPE_SOFT_INTR;
795 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
796 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
797 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
798 return;
799 }
800
801 if (nr == BP_VECTOR || nr == OF_VECTOR) {
802 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
803 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
804 } else
805 intr_info |= INTR_TYPE_HARD_EXCEPTION;
806
807 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
808 }
809
810 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
811 {
812 return false;
813 }
814
815 /*
816 * Swap MSR entry in host/guest MSR entry array.
817 */
818 #ifdef CONFIG_X86_64
819 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
820 {
821 struct kvm_msr_entry tmp;
822
823 tmp = vmx->guest_msrs[to];
824 vmx->guest_msrs[to] = vmx->guest_msrs[from];
825 vmx->guest_msrs[from] = tmp;
826 tmp = vmx->host_msrs[to];
827 vmx->host_msrs[to] = vmx->host_msrs[from];
828 vmx->host_msrs[from] = tmp;
829 }
830 #endif
831
832 /*
833 * Set up the vmcs to automatically save and restore system
834 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
835 * mode, as fiddling with msrs is very expensive.
836 */
837 static void setup_msrs(struct vcpu_vmx *vmx)
838 {
839 int save_nmsrs;
840
841 vmx_load_host_state(vmx);
842 save_nmsrs = 0;
843 #ifdef CONFIG_X86_64
844 if (is_long_mode(&vmx->vcpu)) {
845 int index;
846
847 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
848 if (index >= 0)
849 move_msr_up(vmx, index, save_nmsrs++);
850 index = __find_msr_index(vmx, MSR_LSTAR);
851 if (index >= 0)
852 move_msr_up(vmx, index, save_nmsrs++);
853 index = __find_msr_index(vmx, MSR_CSTAR);
854 if (index >= 0)
855 move_msr_up(vmx, index, save_nmsrs++);
856 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
857 if (index >= 0)
858 move_msr_up(vmx, index, save_nmsrs++);
859 /*
860 * MSR_K6_STAR is only needed on long mode guests, and only
861 * if efer.sce is enabled.
862 */
863 index = __find_msr_index(vmx, MSR_K6_STAR);
864 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
865 move_msr_up(vmx, index, save_nmsrs++);
866 }
867 #endif
868 vmx->save_nmsrs = save_nmsrs;
869
870 #ifdef CONFIG_X86_64
871 vmx->msr_offset_kernel_gs_base =
872 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
873 #endif
874 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
875 }
876
877 /*
878 * reads and returns guest's timestamp counter "register"
879 * guest_tsc = host_tsc + tsc_offset -- 21.3
880 */
881 static u64 guest_read_tsc(void)
882 {
883 u64 host_tsc, tsc_offset;
884
885 rdtscll(host_tsc);
886 tsc_offset = vmcs_read64(TSC_OFFSET);
887 return host_tsc + tsc_offset;
888 }
889
890 /*
891 * writes 'guest_tsc' into guest's timestamp counter "register"
892 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
893 */
894 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
895 {
896 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
897 }
898
899 /*
900 * Reads an msr value (of 'msr_index') into 'pdata'.
901 * Returns 0 on success, non-0 otherwise.
902 * Assumes vcpu_load() was already called.
903 */
904 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
905 {
906 u64 data;
907 struct kvm_msr_entry *msr;
908
909 if (!pdata) {
910 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
911 return -EINVAL;
912 }
913
914 switch (msr_index) {
915 #ifdef CONFIG_X86_64
916 case MSR_FS_BASE:
917 data = vmcs_readl(GUEST_FS_BASE);
918 break;
919 case MSR_GS_BASE:
920 data = vmcs_readl(GUEST_GS_BASE);
921 break;
922 case MSR_EFER:
923 return kvm_get_msr_common(vcpu, msr_index, pdata);
924 #endif
925 case MSR_IA32_TIME_STAMP_COUNTER:
926 data = guest_read_tsc();
927 break;
928 case MSR_IA32_SYSENTER_CS:
929 data = vmcs_read32(GUEST_SYSENTER_CS);
930 break;
931 case MSR_IA32_SYSENTER_EIP:
932 data = vmcs_readl(GUEST_SYSENTER_EIP);
933 break;
934 case MSR_IA32_SYSENTER_ESP:
935 data = vmcs_readl(GUEST_SYSENTER_ESP);
936 break;
937 default:
938 vmx_load_host_state(to_vmx(vcpu));
939 msr = find_msr_entry(to_vmx(vcpu), msr_index);
940 if (msr) {
941 data = msr->data;
942 break;
943 }
944 return kvm_get_msr_common(vcpu, msr_index, pdata);
945 }
946
947 *pdata = data;
948 return 0;
949 }
950
951 /*
952 * Writes msr value into into the appropriate "register".
953 * Returns 0 on success, non-0 otherwise.
954 * Assumes vcpu_load() was already called.
955 */
956 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
957 {
958 struct vcpu_vmx *vmx = to_vmx(vcpu);
959 struct kvm_msr_entry *msr;
960 u64 host_tsc;
961 int ret = 0;
962
963 switch (msr_index) {
964 case MSR_EFER:
965 vmx_load_host_state(vmx);
966 ret = kvm_set_msr_common(vcpu, msr_index, data);
967 break;
968 #ifdef CONFIG_X86_64
969 case MSR_FS_BASE:
970 vmcs_writel(GUEST_FS_BASE, data);
971 break;
972 case MSR_GS_BASE:
973 vmcs_writel(GUEST_GS_BASE, data);
974 break;
975 #endif
976 case MSR_IA32_SYSENTER_CS:
977 vmcs_write32(GUEST_SYSENTER_CS, data);
978 break;
979 case MSR_IA32_SYSENTER_EIP:
980 vmcs_writel(GUEST_SYSENTER_EIP, data);
981 break;
982 case MSR_IA32_SYSENTER_ESP:
983 vmcs_writel(GUEST_SYSENTER_ESP, data);
984 break;
985 case MSR_IA32_TIME_STAMP_COUNTER:
986 rdtscll(host_tsc);
987 guest_write_tsc(data, host_tsc);
988 break;
989 case MSR_P6_PERFCTR0:
990 case MSR_P6_PERFCTR1:
991 case MSR_P6_EVNTSEL0:
992 case MSR_P6_EVNTSEL1:
993 /*
994 * Just discard all writes to the performance counters; this
995 * should keep both older linux and windows 64-bit guests
996 * happy
997 */
998 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
999
1000 break;
1001 case MSR_IA32_CR_PAT:
1002 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1003 vmcs_write64(GUEST_IA32_PAT, data);
1004 vcpu->arch.pat = data;
1005 break;
1006 }
1007 /* Otherwise falls through to kvm_set_msr_common */
1008 default:
1009 vmx_load_host_state(vmx);
1010 msr = find_msr_entry(vmx, msr_index);
1011 if (msr) {
1012 msr->data = data;
1013 break;
1014 }
1015 ret = kvm_set_msr_common(vcpu, msr_index, data);
1016 }
1017
1018 return ret;
1019 }
1020
1021 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1022 {
1023 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1024 switch (reg) {
1025 case VCPU_REGS_RSP:
1026 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1027 break;
1028 case VCPU_REGS_RIP:
1029 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1030 break;
1031 default:
1032 break;
1033 }
1034 }
1035
1036 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1037 {
1038 int old_debug = vcpu->guest_debug;
1039 unsigned long flags;
1040
1041 vcpu->guest_debug = dbg->control;
1042 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1043 vcpu->guest_debug = 0;
1044
1045 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1046 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1047 else
1048 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1049
1050 flags = vmcs_readl(GUEST_RFLAGS);
1051 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1052 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1053 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1054 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1055 vmcs_writel(GUEST_RFLAGS, flags);
1056
1057 update_exception_bitmap(vcpu);
1058
1059 return 0;
1060 }
1061
1062 static int vmx_get_irq(struct kvm_vcpu *vcpu)
1063 {
1064 if (!vcpu->arch.interrupt.pending)
1065 return -1;
1066 return vcpu->arch.interrupt.nr;
1067 }
1068
1069 static __init int cpu_has_kvm_support(void)
1070 {
1071 return cpu_has_vmx();
1072 }
1073
1074 static __init int vmx_disabled_by_bios(void)
1075 {
1076 u64 msr;
1077
1078 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1079 return (msr & (FEATURE_CONTROL_LOCKED |
1080 FEATURE_CONTROL_VMXON_ENABLED))
1081 == FEATURE_CONTROL_LOCKED;
1082 /* locked but not enabled */
1083 }
1084
1085 static void hardware_enable(void *garbage)
1086 {
1087 int cpu = raw_smp_processor_id();
1088 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1089 u64 old;
1090
1091 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1092 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1093 if ((old & (FEATURE_CONTROL_LOCKED |
1094 FEATURE_CONTROL_VMXON_ENABLED))
1095 != (FEATURE_CONTROL_LOCKED |
1096 FEATURE_CONTROL_VMXON_ENABLED))
1097 /* enable and lock */
1098 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1099 FEATURE_CONTROL_LOCKED |
1100 FEATURE_CONTROL_VMXON_ENABLED);
1101 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1102 asm volatile (ASM_VMX_VMXON_RAX
1103 : : "a"(&phys_addr), "m"(phys_addr)
1104 : "memory", "cc");
1105 }
1106
1107 static void vmclear_local_vcpus(void)
1108 {
1109 int cpu = raw_smp_processor_id();
1110 struct vcpu_vmx *vmx, *n;
1111
1112 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1113 local_vcpus_link)
1114 __vcpu_clear(vmx);
1115 }
1116
1117
1118 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1119 * tricks.
1120 */
1121 static void kvm_cpu_vmxoff(void)
1122 {
1123 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1124 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1125 }
1126
1127 static void hardware_disable(void *garbage)
1128 {
1129 vmclear_local_vcpus();
1130 kvm_cpu_vmxoff();
1131 }
1132
1133 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1134 u32 msr, u32 *result)
1135 {
1136 u32 vmx_msr_low, vmx_msr_high;
1137 u32 ctl = ctl_min | ctl_opt;
1138
1139 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1140
1141 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1142 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1143
1144 /* Ensure minimum (required) set of control bits are supported. */
1145 if (ctl_min & ~ctl)
1146 return -EIO;
1147
1148 *result = ctl;
1149 return 0;
1150 }
1151
1152 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1153 {
1154 u32 vmx_msr_low, vmx_msr_high;
1155 u32 min, opt, min2, opt2;
1156 u32 _pin_based_exec_control = 0;
1157 u32 _cpu_based_exec_control = 0;
1158 u32 _cpu_based_2nd_exec_control = 0;
1159 u32 _vmexit_control = 0;
1160 u32 _vmentry_control = 0;
1161
1162 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1163 opt = PIN_BASED_VIRTUAL_NMIS;
1164 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1165 &_pin_based_exec_control) < 0)
1166 return -EIO;
1167
1168 min = CPU_BASED_HLT_EXITING |
1169 #ifdef CONFIG_X86_64
1170 CPU_BASED_CR8_LOAD_EXITING |
1171 CPU_BASED_CR8_STORE_EXITING |
1172 #endif
1173 CPU_BASED_CR3_LOAD_EXITING |
1174 CPU_BASED_CR3_STORE_EXITING |
1175 CPU_BASED_USE_IO_BITMAPS |
1176 CPU_BASED_MOV_DR_EXITING |
1177 CPU_BASED_USE_TSC_OFFSETING |
1178 CPU_BASED_INVLPG_EXITING;
1179 opt = CPU_BASED_TPR_SHADOW |
1180 CPU_BASED_USE_MSR_BITMAPS |
1181 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1182 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1183 &_cpu_based_exec_control) < 0)
1184 return -EIO;
1185 #ifdef CONFIG_X86_64
1186 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1187 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1188 ~CPU_BASED_CR8_STORE_EXITING;
1189 #endif
1190 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1191 min2 = 0;
1192 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1193 SECONDARY_EXEC_WBINVD_EXITING |
1194 SECONDARY_EXEC_ENABLE_VPID |
1195 SECONDARY_EXEC_ENABLE_EPT;
1196 if (adjust_vmx_controls(min2, opt2,
1197 MSR_IA32_VMX_PROCBASED_CTLS2,
1198 &_cpu_based_2nd_exec_control) < 0)
1199 return -EIO;
1200 }
1201 #ifndef CONFIG_X86_64
1202 if (!(_cpu_based_2nd_exec_control &
1203 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1204 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1205 #endif
1206 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1207 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1208 enabled */
1209 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1210 CPU_BASED_CR3_STORE_EXITING |
1211 CPU_BASED_INVLPG_EXITING);
1212 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1213 vmx_capability.ept, vmx_capability.vpid);
1214 }
1215
1216 min = 0;
1217 #ifdef CONFIG_X86_64
1218 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1219 #endif
1220 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1221 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1222 &_vmexit_control) < 0)
1223 return -EIO;
1224
1225 min = 0;
1226 opt = VM_ENTRY_LOAD_IA32_PAT;
1227 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1228 &_vmentry_control) < 0)
1229 return -EIO;
1230
1231 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1232
1233 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1234 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1235 return -EIO;
1236
1237 #ifdef CONFIG_X86_64
1238 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1239 if (vmx_msr_high & (1u<<16))
1240 return -EIO;
1241 #endif
1242
1243 /* Require Write-Back (WB) memory type for VMCS accesses. */
1244 if (((vmx_msr_high >> 18) & 15) != 6)
1245 return -EIO;
1246
1247 vmcs_conf->size = vmx_msr_high & 0x1fff;
1248 vmcs_conf->order = get_order(vmcs_config.size);
1249 vmcs_conf->revision_id = vmx_msr_low;
1250
1251 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1252 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1253 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1254 vmcs_conf->vmexit_ctrl = _vmexit_control;
1255 vmcs_conf->vmentry_ctrl = _vmentry_control;
1256
1257 return 0;
1258 }
1259
1260 static struct vmcs *alloc_vmcs_cpu(int cpu)
1261 {
1262 int node = cpu_to_node(cpu);
1263 struct page *pages;
1264 struct vmcs *vmcs;
1265
1266 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1267 if (!pages)
1268 return NULL;
1269 vmcs = page_address(pages);
1270 memset(vmcs, 0, vmcs_config.size);
1271 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1272 return vmcs;
1273 }
1274
1275 static struct vmcs *alloc_vmcs(void)
1276 {
1277 return alloc_vmcs_cpu(raw_smp_processor_id());
1278 }
1279
1280 static void free_vmcs(struct vmcs *vmcs)
1281 {
1282 free_pages((unsigned long)vmcs, vmcs_config.order);
1283 }
1284
1285 static void free_kvm_area(void)
1286 {
1287 int cpu;
1288
1289 for_each_online_cpu(cpu)
1290 free_vmcs(per_cpu(vmxarea, cpu));
1291 }
1292
1293 static __init int alloc_kvm_area(void)
1294 {
1295 int cpu;
1296
1297 for_each_online_cpu(cpu) {
1298 struct vmcs *vmcs;
1299
1300 vmcs = alloc_vmcs_cpu(cpu);
1301 if (!vmcs) {
1302 free_kvm_area();
1303 return -ENOMEM;
1304 }
1305
1306 per_cpu(vmxarea, cpu) = vmcs;
1307 }
1308 return 0;
1309 }
1310
1311 static __init int hardware_setup(void)
1312 {
1313 if (setup_vmcs_config(&vmcs_config) < 0)
1314 return -EIO;
1315
1316 if (boot_cpu_has(X86_FEATURE_NX))
1317 kvm_enable_efer_bits(EFER_NX);
1318
1319 return alloc_kvm_area();
1320 }
1321
1322 static __exit void hardware_unsetup(void)
1323 {
1324 free_kvm_area();
1325 }
1326
1327 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1328 {
1329 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1330
1331 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1332 vmcs_write16(sf->selector, save->selector);
1333 vmcs_writel(sf->base, save->base);
1334 vmcs_write32(sf->limit, save->limit);
1335 vmcs_write32(sf->ar_bytes, save->ar);
1336 } else {
1337 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1338 << AR_DPL_SHIFT;
1339 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1340 }
1341 }
1342
1343 static void enter_pmode(struct kvm_vcpu *vcpu)
1344 {
1345 unsigned long flags;
1346 struct vcpu_vmx *vmx = to_vmx(vcpu);
1347
1348 vmx->emulation_required = 1;
1349 vcpu->arch.rmode.active = 0;
1350
1351 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1352 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1353 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1354
1355 flags = vmcs_readl(GUEST_RFLAGS);
1356 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1357 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1358 vmcs_writel(GUEST_RFLAGS, flags);
1359
1360 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1361 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1362
1363 update_exception_bitmap(vcpu);
1364
1365 if (emulate_invalid_guest_state)
1366 return;
1367
1368 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1369 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1370 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1371 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1372
1373 vmcs_write16(GUEST_SS_SELECTOR, 0);
1374 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1375
1376 vmcs_write16(GUEST_CS_SELECTOR,
1377 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1378 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1379 }
1380
1381 static gva_t rmode_tss_base(struct kvm *kvm)
1382 {
1383 if (!kvm->arch.tss_addr) {
1384 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1385 kvm->memslots[0].npages - 3;
1386 return base_gfn << PAGE_SHIFT;
1387 }
1388 return kvm->arch.tss_addr;
1389 }
1390
1391 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1392 {
1393 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1394
1395 save->selector = vmcs_read16(sf->selector);
1396 save->base = vmcs_readl(sf->base);
1397 save->limit = vmcs_read32(sf->limit);
1398 save->ar = vmcs_read32(sf->ar_bytes);
1399 vmcs_write16(sf->selector, save->base >> 4);
1400 vmcs_write32(sf->base, save->base & 0xfffff);
1401 vmcs_write32(sf->limit, 0xffff);
1402 vmcs_write32(sf->ar_bytes, 0xf3);
1403 }
1404
1405 static void enter_rmode(struct kvm_vcpu *vcpu)
1406 {
1407 unsigned long flags;
1408 struct vcpu_vmx *vmx = to_vmx(vcpu);
1409
1410 vmx->emulation_required = 1;
1411 vcpu->arch.rmode.active = 1;
1412
1413 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1414 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1415
1416 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1417 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1418
1419 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1420 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1421
1422 flags = vmcs_readl(GUEST_RFLAGS);
1423 vcpu->arch.rmode.save_iopl
1424 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1425
1426 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1427
1428 vmcs_writel(GUEST_RFLAGS, flags);
1429 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1430 update_exception_bitmap(vcpu);
1431
1432 if (emulate_invalid_guest_state)
1433 goto continue_rmode;
1434
1435 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1436 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1437 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1438
1439 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1440 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1441 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1442 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1443 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1444
1445 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1446 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1447 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1448 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1449
1450 continue_rmode:
1451 kvm_mmu_reset_context(vcpu);
1452 init_rmode(vcpu->kvm);
1453 }
1454
1455 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1456 {
1457 struct vcpu_vmx *vmx = to_vmx(vcpu);
1458 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1459
1460 vcpu->arch.shadow_efer = efer;
1461 if (!msr)
1462 return;
1463 if (efer & EFER_LMA) {
1464 vmcs_write32(VM_ENTRY_CONTROLS,
1465 vmcs_read32(VM_ENTRY_CONTROLS) |
1466 VM_ENTRY_IA32E_MODE);
1467 msr->data = efer;
1468 } else {
1469 vmcs_write32(VM_ENTRY_CONTROLS,
1470 vmcs_read32(VM_ENTRY_CONTROLS) &
1471 ~VM_ENTRY_IA32E_MODE);
1472
1473 msr->data = efer & ~EFER_LME;
1474 }
1475 setup_msrs(vmx);
1476 }
1477
1478 #ifdef CONFIG_X86_64
1479
1480 static void enter_lmode(struct kvm_vcpu *vcpu)
1481 {
1482 u32 guest_tr_ar;
1483
1484 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1485 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1486 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1487 __func__);
1488 vmcs_write32(GUEST_TR_AR_BYTES,
1489 (guest_tr_ar & ~AR_TYPE_MASK)
1490 | AR_TYPE_BUSY_64_TSS);
1491 }
1492 vcpu->arch.shadow_efer |= EFER_LMA;
1493 vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
1494 }
1495
1496 static void exit_lmode(struct kvm_vcpu *vcpu)
1497 {
1498 vcpu->arch.shadow_efer &= ~EFER_LMA;
1499
1500 vmcs_write32(VM_ENTRY_CONTROLS,
1501 vmcs_read32(VM_ENTRY_CONTROLS)
1502 & ~VM_ENTRY_IA32E_MODE);
1503 }
1504
1505 #endif
1506
1507 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1508 {
1509 vpid_sync_vcpu_all(to_vmx(vcpu));
1510 if (vm_need_ept())
1511 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1512 }
1513
1514 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1515 {
1516 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1517 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1518 }
1519
1520 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1521 {
1522 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1523 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1524 printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1525 return;
1526 }
1527 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1528 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1529 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1530 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1531 }
1532 }
1533
1534 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1535
1536 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1537 unsigned long cr0,
1538 struct kvm_vcpu *vcpu)
1539 {
1540 if (!(cr0 & X86_CR0_PG)) {
1541 /* From paging/starting to nonpaging */
1542 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1543 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1544 (CPU_BASED_CR3_LOAD_EXITING |
1545 CPU_BASED_CR3_STORE_EXITING));
1546 vcpu->arch.cr0 = cr0;
1547 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1548 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1549 *hw_cr0 &= ~X86_CR0_WP;
1550 } else if (!is_paging(vcpu)) {
1551 /* From nonpaging to paging */
1552 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1553 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1554 ~(CPU_BASED_CR3_LOAD_EXITING |
1555 CPU_BASED_CR3_STORE_EXITING));
1556 vcpu->arch.cr0 = cr0;
1557 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1558 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1559 *hw_cr0 &= ~X86_CR0_WP;
1560 }
1561 }
1562
1563 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1564 struct kvm_vcpu *vcpu)
1565 {
1566 if (!is_paging(vcpu)) {
1567 *hw_cr4 &= ~X86_CR4_PAE;
1568 *hw_cr4 |= X86_CR4_PSE;
1569 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1570 *hw_cr4 &= ~X86_CR4_PAE;
1571 }
1572
1573 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1574 {
1575 unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1576 KVM_VM_CR0_ALWAYS_ON;
1577
1578 vmx_fpu_deactivate(vcpu);
1579
1580 if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1581 enter_pmode(vcpu);
1582
1583 if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1584 enter_rmode(vcpu);
1585
1586 #ifdef CONFIG_X86_64
1587 if (vcpu->arch.shadow_efer & EFER_LME) {
1588 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1589 enter_lmode(vcpu);
1590 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1591 exit_lmode(vcpu);
1592 }
1593 #endif
1594
1595 if (vm_need_ept())
1596 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1597
1598 vmcs_writel(CR0_READ_SHADOW, cr0);
1599 vmcs_writel(GUEST_CR0, hw_cr0);
1600 vcpu->arch.cr0 = cr0;
1601
1602 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1603 vmx_fpu_activate(vcpu);
1604 }
1605
1606 static u64 construct_eptp(unsigned long root_hpa)
1607 {
1608 u64 eptp;
1609
1610 /* TODO write the value reading from MSR */
1611 eptp = VMX_EPT_DEFAULT_MT |
1612 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1613 eptp |= (root_hpa & PAGE_MASK);
1614
1615 return eptp;
1616 }
1617
1618 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1619 {
1620 unsigned long guest_cr3;
1621 u64 eptp;
1622
1623 guest_cr3 = cr3;
1624 if (vm_need_ept()) {
1625 eptp = construct_eptp(cr3);
1626 vmcs_write64(EPT_POINTER, eptp);
1627 ept_sync_context(eptp);
1628 ept_load_pdptrs(vcpu);
1629 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1630 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1631 }
1632
1633 vmx_flush_tlb(vcpu);
1634 vmcs_writel(GUEST_CR3, guest_cr3);
1635 if (vcpu->arch.cr0 & X86_CR0_PE)
1636 vmx_fpu_deactivate(vcpu);
1637 }
1638
1639 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1640 {
1641 unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1642 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1643
1644 vcpu->arch.cr4 = cr4;
1645 if (vm_need_ept())
1646 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1647
1648 vmcs_writel(CR4_READ_SHADOW, cr4);
1649 vmcs_writel(GUEST_CR4, hw_cr4);
1650 }
1651
1652 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1653 {
1654 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1655
1656 return vmcs_readl(sf->base);
1657 }
1658
1659 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1660 struct kvm_segment *var, int seg)
1661 {
1662 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1663 u32 ar;
1664
1665 var->base = vmcs_readl(sf->base);
1666 var->limit = vmcs_read32(sf->limit);
1667 var->selector = vmcs_read16(sf->selector);
1668 ar = vmcs_read32(sf->ar_bytes);
1669 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1670 ar = 0;
1671 var->type = ar & 15;
1672 var->s = (ar >> 4) & 1;
1673 var->dpl = (ar >> 5) & 3;
1674 var->present = (ar >> 7) & 1;
1675 var->avl = (ar >> 12) & 1;
1676 var->l = (ar >> 13) & 1;
1677 var->db = (ar >> 14) & 1;
1678 var->g = (ar >> 15) & 1;
1679 var->unusable = (ar >> 16) & 1;
1680 }
1681
1682 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1683 {
1684 struct kvm_segment kvm_seg;
1685
1686 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1687 return 0;
1688
1689 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1690 return 3;
1691
1692 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1693 return kvm_seg.selector & 3;
1694 }
1695
1696 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1697 {
1698 u32 ar;
1699
1700 if (var->unusable)
1701 ar = 1 << 16;
1702 else {
1703 ar = var->type & 15;
1704 ar |= (var->s & 1) << 4;
1705 ar |= (var->dpl & 3) << 5;
1706 ar |= (var->present & 1) << 7;
1707 ar |= (var->avl & 1) << 12;
1708 ar |= (var->l & 1) << 13;
1709 ar |= (var->db & 1) << 14;
1710 ar |= (var->g & 1) << 15;
1711 }
1712 if (ar == 0) /* a 0 value means unusable */
1713 ar = AR_UNUSABLE_MASK;
1714
1715 return ar;
1716 }
1717
1718 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1719 struct kvm_segment *var, int seg)
1720 {
1721 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1722 u32 ar;
1723
1724 if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1725 vcpu->arch.rmode.tr.selector = var->selector;
1726 vcpu->arch.rmode.tr.base = var->base;
1727 vcpu->arch.rmode.tr.limit = var->limit;
1728 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1729 return;
1730 }
1731 vmcs_writel(sf->base, var->base);
1732 vmcs_write32(sf->limit, var->limit);
1733 vmcs_write16(sf->selector, var->selector);
1734 if (vcpu->arch.rmode.active && var->s) {
1735 /*
1736 * Hack real-mode segments into vm86 compatibility.
1737 */
1738 if (var->base == 0xffff0000 && var->selector == 0xf000)
1739 vmcs_writel(sf->base, 0xf0000);
1740 ar = 0xf3;
1741 } else
1742 ar = vmx_segment_access_rights(var);
1743 vmcs_write32(sf->ar_bytes, ar);
1744 }
1745
1746 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1747 {
1748 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1749
1750 *db = (ar >> 14) & 1;
1751 *l = (ar >> 13) & 1;
1752 }
1753
1754 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1755 {
1756 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1757 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1758 }
1759
1760 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1761 {
1762 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1763 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1764 }
1765
1766 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1767 {
1768 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1769 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1770 }
1771
1772 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1773 {
1774 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1775 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1776 }
1777
1778 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1779 {
1780 struct kvm_segment var;
1781 u32 ar;
1782
1783 vmx_get_segment(vcpu, &var, seg);
1784 ar = vmx_segment_access_rights(&var);
1785
1786 if (var.base != (var.selector << 4))
1787 return false;
1788 if (var.limit != 0xffff)
1789 return false;
1790 if (ar != 0xf3)
1791 return false;
1792
1793 return true;
1794 }
1795
1796 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1797 {
1798 struct kvm_segment cs;
1799 unsigned int cs_rpl;
1800
1801 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1802 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1803
1804 if (cs.unusable)
1805 return false;
1806 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1807 return false;
1808 if (!cs.s)
1809 return false;
1810 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1811 if (cs.dpl > cs_rpl)
1812 return false;
1813 } else {
1814 if (cs.dpl != cs_rpl)
1815 return false;
1816 }
1817 if (!cs.present)
1818 return false;
1819
1820 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1821 return true;
1822 }
1823
1824 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1825 {
1826 struct kvm_segment ss;
1827 unsigned int ss_rpl;
1828
1829 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1830 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1831
1832 if (ss.unusable)
1833 return true;
1834 if (ss.type != 3 && ss.type != 7)
1835 return false;
1836 if (!ss.s)
1837 return false;
1838 if (ss.dpl != ss_rpl) /* DPL != RPL */
1839 return false;
1840 if (!ss.present)
1841 return false;
1842
1843 return true;
1844 }
1845
1846 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1847 {
1848 struct kvm_segment var;
1849 unsigned int rpl;
1850
1851 vmx_get_segment(vcpu, &var, seg);
1852 rpl = var.selector & SELECTOR_RPL_MASK;
1853
1854 if (var.unusable)
1855 return true;
1856 if (!var.s)
1857 return false;
1858 if (!var.present)
1859 return false;
1860 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1861 if (var.dpl < rpl) /* DPL < RPL */
1862 return false;
1863 }
1864
1865 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1866 * rights flags
1867 */
1868 return true;
1869 }
1870
1871 static bool tr_valid(struct kvm_vcpu *vcpu)
1872 {
1873 struct kvm_segment tr;
1874
1875 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1876
1877 if (tr.unusable)
1878 return false;
1879 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1880 return false;
1881 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
1882 return false;
1883 if (!tr.present)
1884 return false;
1885
1886 return true;
1887 }
1888
1889 static bool ldtr_valid(struct kvm_vcpu *vcpu)
1890 {
1891 struct kvm_segment ldtr;
1892
1893 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1894
1895 if (ldtr.unusable)
1896 return true;
1897 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1898 return false;
1899 if (ldtr.type != 2)
1900 return false;
1901 if (!ldtr.present)
1902 return false;
1903
1904 return true;
1905 }
1906
1907 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
1908 {
1909 struct kvm_segment cs, ss;
1910
1911 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1912 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1913
1914 return ((cs.selector & SELECTOR_RPL_MASK) ==
1915 (ss.selector & SELECTOR_RPL_MASK));
1916 }
1917
1918 /*
1919 * Check if guest state is valid. Returns true if valid, false if
1920 * not.
1921 * We assume that registers are always usable
1922 */
1923 static bool guest_state_valid(struct kvm_vcpu *vcpu)
1924 {
1925 /* real mode guest state checks */
1926 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
1927 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
1928 return false;
1929 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
1930 return false;
1931 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
1932 return false;
1933 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
1934 return false;
1935 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
1936 return false;
1937 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
1938 return false;
1939 } else {
1940 /* protected mode guest state checks */
1941 if (!cs_ss_rpl_check(vcpu))
1942 return false;
1943 if (!code_segment_valid(vcpu))
1944 return false;
1945 if (!stack_segment_valid(vcpu))
1946 return false;
1947 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
1948 return false;
1949 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
1950 return false;
1951 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
1952 return false;
1953 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
1954 return false;
1955 if (!tr_valid(vcpu))
1956 return false;
1957 if (!ldtr_valid(vcpu))
1958 return false;
1959 }
1960 /* TODO:
1961 * - Add checks on RIP
1962 * - Add checks on RFLAGS
1963 */
1964
1965 return true;
1966 }
1967
1968 static int init_rmode_tss(struct kvm *kvm)
1969 {
1970 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1971 u16 data = 0;
1972 int ret = 0;
1973 int r;
1974
1975 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1976 if (r < 0)
1977 goto out;
1978 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1979 r = kvm_write_guest_page(kvm, fn++, &data,
1980 TSS_IOPB_BASE_OFFSET, sizeof(u16));
1981 if (r < 0)
1982 goto out;
1983 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1984 if (r < 0)
1985 goto out;
1986 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1987 if (r < 0)
1988 goto out;
1989 data = ~0;
1990 r = kvm_write_guest_page(kvm, fn, &data,
1991 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1992 sizeof(u8));
1993 if (r < 0)
1994 goto out;
1995
1996 ret = 1;
1997 out:
1998 return ret;
1999 }
2000
2001 static int init_rmode_identity_map(struct kvm *kvm)
2002 {
2003 int i, r, ret;
2004 pfn_t identity_map_pfn;
2005 u32 tmp;
2006
2007 if (!vm_need_ept())
2008 return 1;
2009 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2010 printk(KERN_ERR "EPT: identity-mapping pagetable "
2011 "haven't been allocated!\n");
2012 return 0;
2013 }
2014 if (likely(kvm->arch.ept_identity_pagetable_done))
2015 return 1;
2016 ret = 0;
2017 identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
2018 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2019 if (r < 0)
2020 goto out;
2021 /* Set up identity-mapping pagetable for EPT in real mode */
2022 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2023 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2024 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2025 r = kvm_write_guest_page(kvm, identity_map_pfn,
2026 &tmp, i * sizeof(tmp), sizeof(tmp));
2027 if (r < 0)
2028 goto out;
2029 }
2030 kvm->arch.ept_identity_pagetable_done = true;
2031 ret = 1;
2032 out:
2033 return ret;
2034 }
2035
2036 static void seg_setup(int seg)
2037 {
2038 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2039
2040 vmcs_write16(sf->selector, 0);
2041 vmcs_writel(sf->base, 0);
2042 vmcs_write32(sf->limit, 0xffff);
2043 vmcs_write32(sf->ar_bytes, 0xf3);
2044 }
2045
2046 static int alloc_apic_access_page(struct kvm *kvm)
2047 {
2048 struct kvm_userspace_memory_region kvm_userspace_mem;
2049 int r = 0;
2050
2051 down_write(&kvm->slots_lock);
2052 if (kvm->arch.apic_access_page)
2053 goto out;
2054 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2055 kvm_userspace_mem.flags = 0;
2056 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2057 kvm_userspace_mem.memory_size = PAGE_SIZE;
2058 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2059 if (r)
2060 goto out;
2061
2062 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2063 out:
2064 up_write(&kvm->slots_lock);
2065 return r;
2066 }
2067
2068 static int alloc_identity_pagetable(struct kvm *kvm)
2069 {
2070 struct kvm_userspace_memory_region kvm_userspace_mem;
2071 int r = 0;
2072
2073 down_write(&kvm->slots_lock);
2074 if (kvm->arch.ept_identity_pagetable)
2075 goto out;
2076 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2077 kvm_userspace_mem.flags = 0;
2078 kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2079 kvm_userspace_mem.memory_size = PAGE_SIZE;
2080 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2081 if (r)
2082 goto out;
2083
2084 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2085 VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
2086 out:
2087 up_write(&kvm->slots_lock);
2088 return r;
2089 }
2090
2091 static void allocate_vpid(struct vcpu_vmx *vmx)
2092 {
2093 int vpid;
2094
2095 vmx->vpid = 0;
2096 if (!enable_vpid || !cpu_has_vmx_vpid())
2097 return;
2098 spin_lock(&vmx_vpid_lock);
2099 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2100 if (vpid < VMX_NR_VPIDS) {
2101 vmx->vpid = vpid;
2102 __set_bit(vpid, vmx_vpid_bitmap);
2103 }
2104 spin_unlock(&vmx_vpid_lock);
2105 }
2106
2107 static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
2108 {
2109 void *va;
2110
2111 if (!cpu_has_vmx_msr_bitmap())
2112 return;
2113
2114 /*
2115 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2116 * have the write-low and read-high bitmap offsets the wrong way round.
2117 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2118 */
2119 va = kmap(msr_bitmap);
2120 if (msr <= 0x1fff) {
2121 __clear_bit(msr, va + 0x000); /* read-low */
2122 __clear_bit(msr, va + 0x800); /* write-low */
2123 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2124 msr &= 0x1fff;
2125 __clear_bit(msr, va + 0x400); /* read-high */
2126 __clear_bit(msr, va + 0xc00); /* write-high */
2127 }
2128 kunmap(msr_bitmap);
2129 }
2130
2131 /*
2132 * Sets up the vmcs for emulated real mode.
2133 */
2134 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2135 {
2136 u32 host_sysenter_cs, msr_low, msr_high;
2137 u32 junk;
2138 u64 host_pat, tsc_this, tsc_base;
2139 unsigned long a;
2140 struct descriptor_table dt;
2141 int i;
2142 unsigned long kvm_vmx_return;
2143 u32 exec_control;
2144
2145 /* I/O */
2146 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
2147 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
2148
2149 if (cpu_has_vmx_msr_bitmap())
2150 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
2151
2152 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2153
2154 /* Control */
2155 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2156 vmcs_config.pin_based_exec_ctrl);
2157
2158 exec_control = vmcs_config.cpu_based_exec_ctrl;
2159 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2160 exec_control &= ~CPU_BASED_TPR_SHADOW;
2161 #ifdef CONFIG_X86_64
2162 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2163 CPU_BASED_CR8_LOAD_EXITING;
2164 #endif
2165 }
2166 if (!vm_need_ept())
2167 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2168 CPU_BASED_CR3_LOAD_EXITING |
2169 CPU_BASED_INVLPG_EXITING;
2170 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2171
2172 if (cpu_has_secondary_exec_ctrls()) {
2173 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2174 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2175 exec_control &=
2176 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2177 if (vmx->vpid == 0)
2178 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2179 if (!vm_need_ept())
2180 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2181 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2182 }
2183
2184 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2185 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2186 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2187
2188 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2189 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2190 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2191
2192 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2193 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2194 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2195 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2196 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
2197 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2198 #ifdef CONFIG_X86_64
2199 rdmsrl(MSR_FS_BASE, a);
2200 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2201 rdmsrl(MSR_GS_BASE, a);
2202 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2203 #else
2204 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2205 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2206 #endif
2207
2208 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2209
2210 kvm_get_idt(&dt);
2211 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2212
2213 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2214 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2215 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2216 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2217 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2218
2219 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2220 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2221 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2222 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2223 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2224 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2225
2226 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2227 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2228 host_pat = msr_low | ((u64) msr_high << 32);
2229 vmcs_write64(HOST_IA32_PAT, host_pat);
2230 }
2231 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2232 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2233 host_pat = msr_low | ((u64) msr_high << 32);
2234 /* Write the default value follow host pat */
2235 vmcs_write64(GUEST_IA32_PAT, host_pat);
2236 /* Keep arch.pat sync with GUEST_IA32_PAT */
2237 vmx->vcpu.arch.pat = host_pat;
2238 }
2239
2240 for (i = 0; i < NR_VMX_MSR; ++i) {
2241 u32 index = vmx_msr_index[i];
2242 u32 data_low, data_high;
2243 u64 data;
2244 int j = vmx->nmsrs;
2245
2246 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2247 continue;
2248 if (wrmsr_safe(index, data_low, data_high) < 0)
2249 continue;
2250 data = data_low | ((u64)data_high << 32);
2251 vmx->host_msrs[j].index = index;
2252 vmx->host_msrs[j].reserved = 0;
2253 vmx->host_msrs[j].data = data;
2254 vmx->guest_msrs[j] = vmx->host_msrs[j];
2255 ++vmx->nmsrs;
2256 }
2257
2258 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2259
2260 /* 22.2.1, 20.8.1 */
2261 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2262
2263 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2264 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2265
2266 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2267 rdtscll(tsc_this);
2268 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2269 tsc_base = tsc_this;
2270
2271 guest_write_tsc(0, tsc_base);
2272
2273 return 0;
2274 }
2275
2276 static int init_rmode(struct kvm *kvm)
2277 {
2278 if (!init_rmode_tss(kvm))
2279 return 0;
2280 if (!init_rmode_identity_map(kvm))
2281 return 0;
2282 return 1;
2283 }
2284
2285 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2286 {
2287 struct vcpu_vmx *vmx = to_vmx(vcpu);
2288 u64 msr;
2289 int ret;
2290
2291 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2292 down_read(&vcpu->kvm->slots_lock);
2293 if (!init_rmode(vmx->vcpu.kvm)) {
2294 ret = -ENOMEM;
2295 goto out;
2296 }
2297
2298 vmx->vcpu.arch.rmode.active = 0;
2299
2300 vmx->soft_vnmi_blocked = 0;
2301
2302 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2303 kvm_set_cr8(&vmx->vcpu, 0);
2304 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2305 if (vmx->vcpu.vcpu_id == 0)
2306 msr |= MSR_IA32_APICBASE_BSP;
2307 kvm_set_apic_base(&vmx->vcpu, msr);
2308
2309 fx_init(&vmx->vcpu);
2310
2311 seg_setup(VCPU_SREG_CS);
2312 /*
2313 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2314 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2315 */
2316 if (vmx->vcpu.vcpu_id == 0) {
2317 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2318 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2319 } else {
2320 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2321 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2322 }
2323
2324 seg_setup(VCPU_SREG_DS);
2325 seg_setup(VCPU_SREG_ES);
2326 seg_setup(VCPU_SREG_FS);
2327 seg_setup(VCPU_SREG_GS);
2328 seg_setup(VCPU_SREG_SS);
2329
2330 vmcs_write16(GUEST_TR_SELECTOR, 0);
2331 vmcs_writel(GUEST_TR_BASE, 0);
2332 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2333 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2334
2335 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2336 vmcs_writel(GUEST_LDTR_BASE, 0);
2337 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2338 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2339
2340 vmcs_write32(GUEST_SYSENTER_CS, 0);
2341 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2342 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2343
2344 vmcs_writel(GUEST_RFLAGS, 0x02);
2345 if (vmx->vcpu.vcpu_id == 0)
2346 kvm_rip_write(vcpu, 0xfff0);
2347 else
2348 kvm_rip_write(vcpu, 0);
2349 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2350
2351 vmcs_writel(GUEST_DR7, 0x400);
2352
2353 vmcs_writel(GUEST_GDTR_BASE, 0);
2354 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2355
2356 vmcs_writel(GUEST_IDTR_BASE, 0);
2357 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2358
2359 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2360 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2361 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2362
2363 /* Special registers */
2364 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2365
2366 setup_msrs(vmx);
2367
2368 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2369
2370 if (cpu_has_vmx_tpr_shadow()) {
2371 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2372 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2373 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2374 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2375 vmcs_write32(TPR_THRESHOLD, 0);
2376 }
2377
2378 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2379 vmcs_write64(APIC_ACCESS_ADDR,
2380 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2381
2382 if (vmx->vpid != 0)
2383 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2384
2385 vmx->vcpu.arch.cr0 = 0x60000010;
2386 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2387 vmx_set_cr4(&vmx->vcpu, 0);
2388 vmx_set_efer(&vmx->vcpu, 0);
2389 vmx_fpu_activate(&vmx->vcpu);
2390 update_exception_bitmap(&vmx->vcpu);
2391
2392 vpid_sync_vcpu_all(vmx);
2393
2394 ret = 0;
2395
2396 /* HACK: Don't enable emulation on guest boot/reset */
2397 vmx->emulation_required = 0;
2398
2399 out:
2400 up_read(&vcpu->kvm->slots_lock);
2401 return ret;
2402 }
2403
2404 static void enable_irq_window(struct kvm_vcpu *vcpu)
2405 {
2406 u32 cpu_based_vm_exec_control;
2407
2408 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2409 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2410 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2411 }
2412
2413 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2414 {
2415 u32 cpu_based_vm_exec_control;
2416
2417 if (!cpu_has_virtual_nmis()) {
2418 enable_irq_window(vcpu);
2419 return;
2420 }
2421
2422 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2423 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2424 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2425 }
2426
2427 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2428 {
2429 struct vcpu_vmx *vmx = to_vmx(vcpu);
2430
2431 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2432
2433 ++vcpu->stat.irq_injections;
2434 if (vcpu->arch.rmode.active) {
2435 vmx->rmode.irq.pending = true;
2436 vmx->rmode.irq.vector = irq;
2437 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2438 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2439 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2440 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2441 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2442 return;
2443 }
2444 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2445 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2446 }
2447
2448 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2449 {
2450 struct vcpu_vmx *vmx = to_vmx(vcpu);
2451
2452 if (!cpu_has_virtual_nmis()) {
2453 /*
2454 * Tracking the NMI-blocked state in software is built upon
2455 * finding the next open IRQ window. This, in turn, depends on
2456 * well-behaving guests: They have to keep IRQs disabled at
2457 * least as long as the NMI handler runs. Otherwise we may
2458 * cause NMI nesting, maybe breaking the guest. But as this is
2459 * highly unlikely, we can live with the residual risk.
2460 */
2461 vmx->soft_vnmi_blocked = 1;
2462 vmx->vnmi_blocked_time = 0;
2463 }
2464
2465 ++vcpu->stat.nmi_injections;
2466 if (vcpu->arch.rmode.active) {
2467 vmx->rmode.irq.pending = true;
2468 vmx->rmode.irq.vector = NMI_VECTOR;
2469 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2470 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2471 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2472 INTR_INFO_VALID_MASK);
2473 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2474 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2475 return;
2476 }
2477 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2478 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2479 }
2480
2481 static void vmx_update_window_states(struct kvm_vcpu *vcpu)
2482 {
2483 u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2484
2485 vcpu->arch.nmi_window_open =
2486 !(guest_intr & (GUEST_INTR_STATE_STI |
2487 GUEST_INTR_STATE_MOV_SS |
2488 GUEST_INTR_STATE_NMI));
2489 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2490 vcpu->arch.nmi_window_open = 0;
2491
2492 vcpu->arch.interrupt_window_open =
2493 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2494 !(guest_intr & (GUEST_INTR_STATE_STI |
2495 GUEST_INTR_STATE_MOV_SS)));
2496 }
2497
2498 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
2499 {
2500 int word_index = __ffs(vcpu->arch.irq_summary);
2501 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
2502 int irq = word_index * BITS_PER_LONG + bit_index;
2503
2504 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2505 if (!vcpu->arch.irq_pending[word_index])
2506 clear_bit(word_index, &vcpu->arch.irq_summary);
2507 kvm_queue_interrupt(vcpu, irq);
2508 }
2509
2510 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2511 struct kvm_run *kvm_run)
2512 {
2513 vmx_update_window_states(vcpu);
2514
2515 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
2516 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2517 GUEST_INTR_STATE_STI |
2518 GUEST_INTR_STATE_MOV_SS);
2519
2520 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
2521 if (vcpu->arch.interrupt.pending) {
2522 enable_nmi_window(vcpu);
2523 } else if (vcpu->arch.nmi_window_open) {
2524 vcpu->arch.nmi_pending = false;
2525 vcpu->arch.nmi_injected = true;
2526 } else {
2527 enable_nmi_window(vcpu);
2528 return;
2529 }
2530 }
2531 if (vcpu->arch.nmi_injected) {
2532 vmx_inject_nmi(vcpu);
2533 if (vcpu->arch.nmi_pending)
2534 enable_nmi_window(vcpu);
2535 else if (vcpu->arch.irq_summary
2536 || kvm_run->request_interrupt_window)
2537 enable_irq_window(vcpu);
2538 return;
2539 }
2540
2541 if (vcpu->arch.interrupt_window_open) {
2542 if (vcpu->arch.irq_summary && !vcpu->arch.interrupt.pending)
2543 kvm_do_inject_irq(vcpu);
2544
2545 if (vcpu->arch.interrupt.pending)
2546 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
2547 }
2548 if (!vcpu->arch.interrupt_window_open &&
2549 (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
2550 enable_irq_window(vcpu);
2551 }
2552
2553 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2554 {
2555 int ret;
2556 struct kvm_userspace_memory_region tss_mem = {
2557 .slot = TSS_PRIVATE_MEMSLOT,
2558 .guest_phys_addr = addr,
2559 .memory_size = PAGE_SIZE * 3,
2560 .flags = 0,
2561 };
2562
2563 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2564 if (ret)
2565 return ret;
2566 kvm->arch.tss_addr = addr;
2567 return 0;
2568 }
2569
2570 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2571 int vec, u32 err_code)
2572 {
2573 /*
2574 * Instruction with address size override prefix opcode 0x67
2575 * Cause the #SS fault with 0 error code in VM86 mode.
2576 */
2577 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2578 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2579 return 1;
2580 /*
2581 * Forward all other exceptions that are valid in real mode.
2582 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2583 * the required debugging infrastructure rework.
2584 */
2585 switch (vec) {
2586 case DB_VECTOR:
2587 if (vcpu->guest_debug &
2588 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2589 return 0;
2590 kvm_queue_exception(vcpu, vec);
2591 return 1;
2592 case BP_VECTOR:
2593 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2594 return 0;
2595 /* fall through */
2596 case DE_VECTOR:
2597 case OF_VECTOR:
2598 case BR_VECTOR:
2599 case UD_VECTOR:
2600 case DF_VECTOR:
2601 case SS_VECTOR:
2602 case GP_VECTOR:
2603 case MF_VECTOR:
2604 kvm_queue_exception(vcpu, vec);
2605 return 1;
2606 }
2607 return 0;
2608 }
2609
2610 /*
2611 * Trigger machine check on the host. We assume all the MSRs are already set up
2612 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2613 * We pass a fake environment to the machine check handler because we want
2614 * the guest to be always treated like user space, no matter what context
2615 * it used internally.
2616 */
2617 static void kvm_machine_check(void)
2618 {
2619 #ifdef CONFIG_X86_MCE
2620 struct pt_regs regs = {
2621 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2622 .flags = X86_EFLAGS_IF,
2623 };
2624
2625 #ifdef CONFIG_X86_64
2626 do_machine_check(&regs, 0);
2627 #else
2628 machine_check_vector(&regs, 0);
2629 #endif
2630 #endif
2631 }
2632
2633 static int handle_machine_check(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2634 {
2635 /* already handled by vcpu_run */
2636 return 1;
2637 }
2638
2639 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2640 {
2641 struct vcpu_vmx *vmx = to_vmx(vcpu);
2642 u32 intr_info, ex_no, error_code;
2643 unsigned long cr2, rip, dr6;
2644 u32 vect_info;
2645 enum emulation_result er;
2646
2647 vect_info = vmx->idt_vectoring_info;
2648 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2649
2650 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2651 if (ex_no == MC_VECTOR)
2652 return handle_machine_check(vcpu, kvm_run);
2653
2654 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2655 !is_page_fault(intr_info))
2656 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2657 "intr info 0x%x\n", __func__, vect_info, intr_info);
2658
2659 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
2660 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
2661 set_bit(irq, vcpu->arch.irq_pending);
2662 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
2663 }
2664
2665 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2666 return 1; /* already handled by vmx_vcpu_run() */
2667
2668 if (is_no_device(intr_info)) {
2669 vmx_fpu_activate(vcpu);
2670 return 1;
2671 }
2672
2673 if (is_invalid_opcode(intr_info)) {
2674 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2675 if (er != EMULATE_DONE)
2676 kvm_queue_exception(vcpu, UD_VECTOR);
2677 return 1;
2678 }
2679
2680 error_code = 0;
2681 rip = kvm_rip_read(vcpu);
2682 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2683 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2684 if (is_page_fault(intr_info)) {
2685 /* EPT won't cause page fault directly */
2686 if (vm_need_ept())
2687 BUG();
2688 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2689 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2690 (u32)((u64)cr2 >> 32), handler);
2691 if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending)
2692 kvm_mmu_unprotect_page_virt(vcpu, cr2);
2693 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2694 }
2695
2696 if (vcpu->arch.rmode.active &&
2697 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2698 error_code)) {
2699 if (vcpu->arch.halt_request) {
2700 vcpu->arch.halt_request = 0;
2701 return kvm_emulate_halt(vcpu);
2702 }
2703 return 1;
2704 }
2705
2706 switch (ex_no) {
2707 case DB_VECTOR:
2708 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2709 if (!(vcpu->guest_debug &
2710 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2711 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2712 kvm_queue_exception(vcpu, DB_VECTOR);
2713 return 1;
2714 }
2715 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2716 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2717 /* fall through */
2718 case BP_VECTOR:
2719 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2720 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2721 kvm_run->debug.arch.exception = ex_no;
2722 break;
2723 default:
2724 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2725 kvm_run->ex.exception = ex_no;
2726 kvm_run->ex.error_code = error_code;
2727 break;
2728 }
2729 return 0;
2730 }
2731
2732 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2733 struct kvm_run *kvm_run)
2734 {
2735 ++vcpu->stat.irq_exits;
2736 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2737 return 1;
2738 }
2739
2740 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2741 {
2742 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2743 return 0;
2744 }
2745
2746 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2747 {
2748 unsigned long exit_qualification;
2749 int size, in, string;
2750 unsigned port;
2751
2752 ++vcpu->stat.io_exits;
2753 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2754 string = (exit_qualification & 16) != 0;
2755
2756 if (string) {
2757 if (emulate_instruction(vcpu,
2758 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2759 return 0;
2760 return 1;
2761 }
2762
2763 size = (exit_qualification & 7) + 1;
2764 in = (exit_qualification & 8) != 0;
2765 port = exit_qualification >> 16;
2766
2767 skip_emulated_instruction(vcpu);
2768 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2769 }
2770
2771 static void
2772 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2773 {
2774 /*
2775 * Patch in the VMCALL instruction:
2776 */
2777 hypercall[0] = 0x0f;
2778 hypercall[1] = 0x01;
2779 hypercall[2] = 0xc1;
2780 }
2781
2782 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2783 {
2784 unsigned long exit_qualification;
2785 int cr;
2786 int reg;
2787
2788 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2789 cr = exit_qualification & 15;
2790 reg = (exit_qualification >> 8) & 15;
2791 switch ((exit_qualification >> 4) & 3) {
2792 case 0: /* mov to cr */
2793 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2794 (u32)kvm_register_read(vcpu, reg),
2795 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2796 handler);
2797 switch (cr) {
2798 case 0:
2799 kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
2800 skip_emulated_instruction(vcpu);
2801 return 1;
2802 case 3:
2803 kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
2804 skip_emulated_instruction(vcpu);
2805 return 1;
2806 case 4:
2807 kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
2808 skip_emulated_instruction(vcpu);
2809 return 1;
2810 case 8:
2811 kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg));
2812 skip_emulated_instruction(vcpu);
2813 if (irqchip_in_kernel(vcpu->kvm))
2814 return 1;
2815 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2816 return 0;
2817 };
2818 break;
2819 case 2: /* clts */
2820 vmx_fpu_deactivate(vcpu);
2821 vcpu->arch.cr0 &= ~X86_CR0_TS;
2822 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2823 vmx_fpu_activate(vcpu);
2824 KVMTRACE_0D(CLTS, vcpu, handler);
2825 skip_emulated_instruction(vcpu);
2826 return 1;
2827 case 1: /*mov from cr*/
2828 switch (cr) {
2829 case 3:
2830 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2831 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2832 (u32)kvm_register_read(vcpu, reg),
2833 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2834 handler);
2835 skip_emulated_instruction(vcpu);
2836 return 1;
2837 case 8:
2838 kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2839 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2840 (u32)kvm_register_read(vcpu, reg), handler);
2841 skip_emulated_instruction(vcpu);
2842 return 1;
2843 }
2844 break;
2845 case 3: /* lmsw */
2846 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2847
2848 skip_emulated_instruction(vcpu);
2849 return 1;
2850 default:
2851 break;
2852 }
2853 kvm_run->exit_reason = 0;
2854 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2855 (int)(exit_qualification >> 4) & 3, cr);
2856 return 0;
2857 }
2858
2859 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2860 {
2861 unsigned long exit_qualification;
2862 unsigned long val;
2863 int dr, reg;
2864
2865 if (!kvm_require_cpl(vcpu, 0))
2866 return 1;
2867 dr = vmcs_readl(GUEST_DR7);
2868 if (dr & DR7_GD) {
2869 /*
2870 * As the vm-exit takes precedence over the debug trap, we
2871 * need to emulate the latter, either for the host or the
2872 * guest debugging itself.
2873 */
2874 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2875 kvm_run->debug.arch.dr6 = vcpu->arch.dr6;
2876 kvm_run->debug.arch.dr7 = dr;
2877 kvm_run->debug.arch.pc =
2878 vmcs_readl(GUEST_CS_BASE) +
2879 vmcs_readl(GUEST_RIP);
2880 kvm_run->debug.arch.exception = DB_VECTOR;
2881 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2882 return 0;
2883 } else {
2884 vcpu->arch.dr7 &= ~DR7_GD;
2885 vcpu->arch.dr6 |= DR6_BD;
2886 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2887 kvm_queue_exception(vcpu, DB_VECTOR);
2888 return 1;
2889 }
2890 }
2891
2892 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2893 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2894 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2895 if (exit_qualification & TYPE_MOV_FROM_DR) {
2896 switch (dr) {
2897 case 0 ... 3:
2898 val = vcpu->arch.db[dr];
2899 break;
2900 case 6:
2901 val = vcpu->arch.dr6;
2902 break;
2903 case 7:
2904 val = vcpu->arch.dr7;
2905 break;
2906 default:
2907 val = 0;
2908 }
2909 kvm_register_write(vcpu, reg, val);
2910 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2911 } else {
2912 val = vcpu->arch.regs[reg];
2913 switch (dr) {
2914 case 0 ... 3:
2915 vcpu->arch.db[dr] = val;
2916 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2917 vcpu->arch.eff_db[dr] = val;
2918 break;
2919 case 4 ... 5:
2920 if (vcpu->arch.cr4 & X86_CR4_DE)
2921 kvm_queue_exception(vcpu, UD_VECTOR);
2922 break;
2923 case 6:
2924 if (val & 0xffffffff00000000ULL) {
2925 kvm_queue_exception(vcpu, GP_VECTOR);
2926 break;
2927 }
2928 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
2929 break;
2930 case 7:
2931 if (val & 0xffffffff00000000ULL) {
2932 kvm_queue_exception(vcpu, GP_VECTOR);
2933 break;
2934 }
2935 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
2936 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
2937 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2938 vcpu->arch.switch_db_regs =
2939 (val & DR7_BP_EN_MASK);
2940 }
2941 break;
2942 }
2943 KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)val, handler);
2944 }
2945 skip_emulated_instruction(vcpu);
2946 return 1;
2947 }
2948
2949 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2950 {
2951 kvm_emulate_cpuid(vcpu);
2952 return 1;
2953 }
2954
2955 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2956 {
2957 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2958 u64 data;
2959
2960 if (vmx_get_msr(vcpu, ecx, &data)) {
2961 kvm_inject_gp(vcpu, 0);
2962 return 1;
2963 }
2964
2965 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2966 handler);
2967
2968 /* FIXME: handling of bits 32:63 of rax, rdx */
2969 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2970 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2971 skip_emulated_instruction(vcpu);
2972 return 1;
2973 }
2974
2975 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2976 {
2977 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2978 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2979 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2980
2981 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2982 handler);
2983
2984 if (vmx_set_msr(vcpu, ecx, data) != 0) {
2985 kvm_inject_gp(vcpu, 0);
2986 return 1;
2987 }
2988
2989 skip_emulated_instruction(vcpu);
2990 return 1;
2991 }
2992
2993 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2994 struct kvm_run *kvm_run)
2995 {
2996 return 1;
2997 }
2998
2999 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
3000 struct kvm_run *kvm_run)
3001 {
3002 u32 cpu_based_vm_exec_control;
3003
3004 /* clear pending irq */
3005 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3006 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3007 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3008
3009 KVMTRACE_0D(PEND_INTR, vcpu, handler);
3010 ++vcpu->stat.irq_window_exits;
3011
3012 /*
3013 * If the user space waits to inject interrupts, exit as soon as
3014 * possible
3015 */
3016 if (kvm_run->request_interrupt_window &&
3017 !vcpu->arch.irq_summary) {
3018 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3019 return 0;
3020 }
3021 return 1;
3022 }
3023
3024 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3025 {
3026 skip_emulated_instruction(vcpu);
3027 return kvm_emulate_halt(vcpu);
3028 }
3029
3030 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3031 {
3032 skip_emulated_instruction(vcpu);
3033 kvm_emulate_hypercall(vcpu);
3034 return 1;
3035 }
3036
3037 static int handle_vmx_insn(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3038 {
3039 kvm_queue_exception(vcpu, UD_VECTOR);
3040 return 1;
3041 }
3042
3043 static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3044 {
3045 u64 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
3046
3047 kvm_mmu_invlpg(vcpu, exit_qualification);
3048 skip_emulated_instruction(vcpu);
3049 return 1;
3050 }
3051
3052 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3053 {
3054 skip_emulated_instruction(vcpu);
3055 /* TODO: Add support for VT-d/pass-through device */
3056 return 1;
3057 }
3058
3059 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3060 {
3061 u64 exit_qualification;
3062 enum emulation_result er;
3063 unsigned long offset;
3064
3065 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
3066 offset = exit_qualification & 0xffful;
3067
3068 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3069
3070 if (er != EMULATE_DONE) {
3071 printk(KERN_ERR
3072 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3073 offset);
3074 return -ENOTSUPP;
3075 }
3076 return 1;
3077 }
3078
3079 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3080 {
3081 struct vcpu_vmx *vmx = to_vmx(vcpu);
3082 unsigned long exit_qualification;
3083 u16 tss_selector;
3084 int reason;
3085
3086 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3087
3088 reason = (u32)exit_qualification >> 30;
3089 if (reason == TASK_SWITCH_GATE && vmx->vcpu.arch.nmi_injected &&
3090 (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
3091 (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK)
3092 == INTR_TYPE_NMI_INTR) {
3093 vcpu->arch.nmi_injected = false;
3094 if (cpu_has_virtual_nmis())
3095 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3096 GUEST_INTR_STATE_NMI);
3097 }
3098 tss_selector = exit_qualification;
3099
3100 if (!kvm_task_switch(vcpu, tss_selector, reason))
3101 return 0;
3102
3103 /* clear all local breakpoint enable flags */
3104 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3105
3106 /*
3107 * TODO: What about debug traps on tss switch?
3108 * Are we supposed to inject them and update dr6?
3109 */
3110
3111 return 1;
3112 }
3113
3114 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3115 {
3116 u64 exit_qualification;
3117 gpa_t gpa;
3118 int gla_validity;
3119
3120 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
3121
3122 if (exit_qualification & (1 << 6)) {
3123 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3124 return -ENOTSUPP;
3125 }
3126
3127 gla_validity = (exit_qualification >> 7) & 0x3;
3128 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3129 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3130 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3131 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3132 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
3133 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3134 (long unsigned int)exit_qualification);
3135 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3136 kvm_run->hw.hardware_exit_reason = 0;
3137 return -ENOTSUPP;
3138 }
3139
3140 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3141 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3142 }
3143
3144 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3145 {
3146 u32 cpu_based_vm_exec_control;
3147
3148 /* clear pending NMI */
3149 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3150 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3151 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3152 ++vcpu->stat.nmi_window_exits;
3153
3154 return 1;
3155 }
3156
3157 static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3158 struct kvm_run *kvm_run)
3159 {
3160 struct vcpu_vmx *vmx = to_vmx(vcpu);
3161 enum emulation_result err = EMULATE_DONE;
3162
3163 preempt_enable();
3164 local_irq_enable();
3165
3166 while (!guest_state_valid(vcpu)) {
3167 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3168
3169 if (err == EMULATE_DO_MMIO)
3170 break;
3171
3172 if (err != EMULATE_DONE) {
3173 kvm_report_emulation_failure(vcpu, "emulation failure");
3174 return;
3175 }
3176
3177 if (signal_pending(current))
3178 break;
3179 if (need_resched())
3180 schedule();
3181 }
3182
3183 local_irq_disable();
3184 preempt_disable();
3185
3186 vmx->invalid_state_emulation_result = err;
3187 }
3188
3189 /*
3190 * The exit handlers return 1 if the exit was handled fully and guest execution
3191 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3192 * to be done to userspace and return 0.
3193 */
3194 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3195 struct kvm_run *kvm_run) = {
3196 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3197 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3198 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3199 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3200 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3201 [EXIT_REASON_CR_ACCESS] = handle_cr,
3202 [EXIT_REASON_DR_ACCESS] = handle_dr,
3203 [EXIT_REASON_CPUID] = handle_cpuid,
3204 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3205 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3206 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3207 [EXIT_REASON_HLT] = handle_halt,
3208 [EXIT_REASON_INVLPG] = handle_invlpg,
3209 [EXIT_REASON_VMCALL] = handle_vmcall,
3210 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3211 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3212 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3213 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3214 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3215 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3216 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3217 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3218 [EXIT_REASON_VMON] = handle_vmx_insn,
3219 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3220 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3221 [EXIT_REASON_WBINVD] = handle_wbinvd,
3222 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3223 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3224 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
3225 };
3226
3227 static const int kvm_vmx_max_exit_handlers =
3228 ARRAY_SIZE(kvm_vmx_exit_handlers);
3229
3230 /*
3231 * The guest has exited. See if we can fix it or if we need userspace
3232 * assistance.
3233 */
3234 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
3235 {
3236 struct vcpu_vmx *vmx = to_vmx(vcpu);
3237 u32 exit_reason = vmx->exit_reason;
3238 u32 vectoring_info = vmx->idt_vectoring_info;
3239
3240 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
3241 (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
3242
3243 /* If we need to emulate an MMIO from handle_invalid_guest_state
3244 * we just return 0 */
3245 if (vmx->emulation_required && emulate_invalid_guest_state) {
3246 if (guest_state_valid(vcpu))
3247 vmx->emulation_required = 0;
3248 return vmx->invalid_state_emulation_result != EMULATE_DO_MMIO;
3249 }
3250
3251 /* Access CR3 don't cause VMExit in paging mode, so we need
3252 * to sync with guest real CR3. */
3253 if (vm_need_ept() && is_paging(vcpu)) {
3254 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3255 ept_load_pdptrs(vcpu);
3256 }
3257
3258 if (unlikely(vmx->fail)) {
3259 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3260 kvm_run->fail_entry.hardware_entry_failure_reason
3261 = vmcs_read32(VM_INSTRUCTION_ERROR);
3262 return 0;
3263 }
3264
3265 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3266 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3267 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3268 exit_reason != EXIT_REASON_TASK_SWITCH))
3269 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3270 "(0x%x) and exit reason is 0x%x\n",
3271 __func__, vectoring_info, exit_reason);
3272
3273 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3274 if (vcpu->arch.interrupt_window_open) {
3275 vmx->soft_vnmi_blocked = 0;
3276 vcpu->arch.nmi_window_open = 1;
3277 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3278 vcpu->arch.nmi_pending) {
3279 /*
3280 * This CPU don't support us in finding the end of an
3281 * NMI-blocked window if the guest runs with IRQs
3282 * disabled. So we pull the trigger after 1 s of
3283 * futile waiting, but inform the user about this.
3284 */
3285 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3286 "state on VCPU %d after 1 s timeout\n",
3287 __func__, vcpu->vcpu_id);
3288 vmx->soft_vnmi_blocked = 0;
3289 vmx->vcpu.arch.nmi_window_open = 1;
3290 }
3291 }
3292
3293 if (exit_reason < kvm_vmx_max_exit_handlers
3294 && kvm_vmx_exit_handlers[exit_reason])
3295 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3296 else {
3297 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3298 kvm_run->hw.hardware_exit_reason = exit_reason;
3299 }
3300 return 0;
3301 }
3302
3303 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
3304 {
3305 int max_irr, tpr;
3306
3307 if (!vm_need_tpr_shadow(vcpu->kvm))
3308 return;
3309
3310 if (!kvm_lapic_enabled(vcpu) ||
3311 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
3312 vmcs_write32(TPR_THRESHOLD, 0);
3313 return;
3314 }
3315
3316 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
3317 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
3318 }
3319
3320 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3321 {
3322 u32 exit_intr_info;
3323 u32 idt_vectoring_info;
3324 bool unblock_nmi;
3325 u8 vector;
3326 int type;
3327 bool idtv_info_valid;
3328 u32 error;
3329
3330 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3331 if (cpu_has_virtual_nmis()) {
3332 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3333 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3334 /*
3335 * SDM 3: 25.7.1.2
3336 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3337 * a guest IRET fault.
3338 */
3339 if (unblock_nmi && vector != DF_VECTOR)
3340 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3341 GUEST_INTR_STATE_NMI);
3342 } else if (unlikely(vmx->soft_vnmi_blocked))
3343 vmx->vnmi_blocked_time +=
3344 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3345
3346 idt_vectoring_info = vmx->idt_vectoring_info;
3347 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3348 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3349 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3350 if (vmx->vcpu.arch.nmi_injected) {
3351 /*
3352 * SDM 3: 25.7.1.2
3353 * Clear bit "block by NMI" before VM entry if a NMI delivery
3354 * faulted.
3355 */
3356 if (idtv_info_valid && type == INTR_TYPE_NMI_INTR)
3357 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3358 GUEST_INTR_STATE_NMI);
3359 else
3360 vmx->vcpu.arch.nmi_injected = false;
3361 }
3362 kvm_clear_exception_queue(&vmx->vcpu);
3363 if (idtv_info_valid && (type == INTR_TYPE_HARD_EXCEPTION ||
3364 type == INTR_TYPE_SOFT_EXCEPTION)) {
3365 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3366 error = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3367 kvm_queue_exception_e(&vmx->vcpu, vector, error);
3368 } else
3369 kvm_queue_exception(&vmx->vcpu, vector);
3370 vmx->idt_vectoring_info = 0;
3371 }
3372 kvm_clear_interrupt_queue(&vmx->vcpu);
3373 if (idtv_info_valid && type == INTR_TYPE_EXT_INTR) {
3374 kvm_queue_interrupt(&vmx->vcpu, vector);
3375 vmx->idt_vectoring_info = 0;
3376 }
3377 }
3378
3379 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
3380 {
3381 update_tpr_threshold(vcpu);
3382
3383 vmx_update_window_states(vcpu);
3384
3385 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3386 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3387 GUEST_INTR_STATE_STI |
3388 GUEST_INTR_STATE_MOV_SS);
3389
3390 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
3391 if (vcpu->arch.interrupt.pending) {
3392 enable_nmi_window(vcpu);
3393 } else if (vcpu->arch.nmi_window_open) {
3394 vcpu->arch.nmi_pending = false;
3395 vcpu->arch.nmi_injected = true;
3396 } else {
3397 enable_nmi_window(vcpu);
3398 return;
3399 }
3400 }
3401 if (vcpu->arch.nmi_injected) {
3402 vmx_inject_nmi(vcpu);
3403 if (vcpu->arch.nmi_pending)
3404 enable_nmi_window(vcpu);
3405 else if (kvm_cpu_has_interrupt(vcpu))
3406 enable_irq_window(vcpu);
3407 return;
3408 }
3409 if (!vcpu->arch.interrupt.pending && kvm_cpu_has_interrupt(vcpu)) {
3410 if (vcpu->arch.interrupt_window_open)
3411 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu));
3412 else
3413 enable_irq_window(vcpu);
3414 }
3415 if (vcpu->arch.interrupt.pending) {
3416 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
3417 if (kvm_cpu_has_interrupt(vcpu))
3418 enable_irq_window(vcpu);
3419 }
3420 }
3421
3422 /*
3423 * Failure to inject an interrupt should give us the information
3424 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3425 * when fetching the interrupt redirection bitmap in the real-mode
3426 * tss, this doesn't happen. So we do it ourselves.
3427 */
3428 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3429 {
3430 vmx->rmode.irq.pending = 0;
3431 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3432 return;
3433 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3434 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3435 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3436 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3437 return;
3438 }
3439 vmx->idt_vectoring_info =
3440 VECTORING_INFO_VALID_MASK
3441 | INTR_TYPE_EXT_INTR
3442 | vmx->rmode.irq.vector;
3443 }
3444
3445 #ifdef CONFIG_X86_64
3446 #define R "r"
3447 #define Q "q"
3448 #else
3449 #define R "e"
3450 #define Q "l"
3451 #endif
3452
3453 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3454 {
3455 struct vcpu_vmx *vmx = to_vmx(vcpu);
3456 u32 intr_info;
3457
3458 /* Record the guest's net vcpu time for enforced NMI injections. */
3459 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3460 vmx->entry_time = ktime_get();
3461
3462 /* Handle invalid guest state instead of entering VMX */
3463 if (vmx->emulation_required && emulate_invalid_guest_state) {
3464 handle_invalid_guest_state(vcpu, kvm_run);
3465 return;
3466 }
3467
3468 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3469 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3470 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3471 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3472
3473 /*
3474 * Loading guest fpu may have cleared host cr0.ts
3475 */
3476 vmcs_writel(HOST_CR0, read_cr0());
3477
3478 set_debugreg(vcpu->arch.dr6, 6);
3479
3480 asm(
3481 /* Store host registers */
3482 "push %%"R"dx; push %%"R"bp;"
3483 "push %%"R"cx \n\t"
3484 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3485 "je 1f \n\t"
3486 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3487 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3488 "1: \n\t"
3489 /* Check if vmlaunch of vmresume is needed */
3490 "cmpl $0, %c[launched](%0) \n\t"
3491 /* Load guest registers. Don't clobber flags. */
3492 "mov %c[cr2](%0), %%"R"ax \n\t"
3493 "mov %%"R"ax, %%cr2 \n\t"
3494 "mov %c[rax](%0), %%"R"ax \n\t"
3495 "mov %c[rbx](%0), %%"R"bx \n\t"
3496 "mov %c[rdx](%0), %%"R"dx \n\t"
3497 "mov %c[rsi](%0), %%"R"si \n\t"
3498 "mov %c[rdi](%0), %%"R"di \n\t"
3499 "mov %c[rbp](%0), %%"R"bp \n\t"
3500 #ifdef CONFIG_X86_64
3501 "mov %c[r8](%0), %%r8 \n\t"
3502 "mov %c[r9](%0), %%r9 \n\t"
3503 "mov %c[r10](%0), %%r10 \n\t"
3504 "mov %c[r11](%0), %%r11 \n\t"
3505 "mov %c[r12](%0), %%r12 \n\t"
3506 "mov %c[r13](%0), %%r13 \n\t"
3507 "mov %c[r14](%0), %%r14 \n\t"
3508 "mov %c[r15](%0), %%r15 \n\t"
3509 #endif
3510 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3511
3512 /* Enter guest mode */
3513 "jne .Llaunched \n\t"
3514 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3515 "jmp .Lkvm_vmx_return \n\t"
3516 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3517 ".Lkvm_vmx_return: "
3518 /* Save guest registers, load host registers, keep flags */
3519 "xchg %0, (%%"R"sp) \n\t"
3520 "mov %%"R"ax, %c[rax](%0) \n\t"
3521 "mov %%"R"bx, %c[rbx](%0) \n\t"
3522 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3523 "mov %%"R"dx, %c[rdx](%0) \n\t"
3524 "mov %%"R"si, %c[rsi](%0) \n\t"
3525 "mov %%"R"di, %c[rdi](%0) \n\t"
3526 "mov %%"R"bp, %c[rbp](%0) \n\t"
3527 #ifdef CONFIG_X86_64
3528 "mov %%r8, %c[r8](%0) \n\t"
3529 "mov %%r9, %c[r9](%0) \n\t"
3530 "mov %%r10, %c[r10](%0) \n\t"
3531 "mov %%r11, %c[r11](%0) \n\t"
3532 "mov %%r12, %c[r12](%0) \n\t"
3533 "mov %%r13, %c[r13](%0) \n\t"
3534 "mov %%r14, %c[r14](%0) \n\t"
3535 "mov %%r15, %c[r15](%0) \n\t"
3536 #endif
3537 "mov %%cr2, %%"R"ax \n\t"
3538 "mov %%"R"ax, %c[cr2](%0) \n\t"
3539
3540 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
3541 "setbe %c[fail](%0) \n\t"
3542 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3543 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3544 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3545 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3546 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3547 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3548 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3549 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3550 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3551 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3552 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3553 #ifdef CONFIG_X86_64
3554 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3555 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3556 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3557 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3558 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3559 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3560 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3561 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3562 #endif
3563 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3564 : "cc", "memory"
3565 , R"bx", R"di", R"si"
3566 #ifdef CONFIG_X86_64
3567 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3568 #endif
3569 );
3570
3571 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3572 vcpu->arch.regs_dirty = 0;
3573
3574 get_debugreg(vcpu->arch.dr6, 6);
3575
3576 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3577 if (vmx->rmode.irq.pending)
3578 fixup_rmode_irq(vmx);
3579
3580 vmx_update_window_states(vcpu);
3581
3582 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3583 vmx->launched = 1;
3584
3585 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3586
3587 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3588
3589 /* Handle machine checks before interrupts are enabled */
3590 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY) ||
3591 (intr_info & INTR_INFO_VECTOR_MASK) == MC_VECTOR)
3592 kvm_machine_check();
3593
3594 /* We need to handle NMIs before interrupts are enabled */
3595 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3596 (intr_info & INTR_INFO_VALID_MASK)) {
3597 KVMTRACE_0D(NMI, vcpu, handler);
3598 asm("int $2");
3599 }
3600
3601 vmx_complete_interrupts(vmx);
3602 }
3603
3604 #undef R
3605 #undef Q
3606
3607 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3608 {
3609 struct vcpu_vmx *vmx = to_vmx(vcpu);
3610
3611 if (vmx->vmcs) {
3612 vcpu_clear(vmx);
3613 free_vmcs(vmx->vmcs);
3614 vmx->vmcs = NULL;
3615 }
3616 }
3617
3618 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3619 {
3620 struct vcpu_vmx *vmx = to_vmx(vcpu);
3621
3622 spin_lock(&vmx_vpid_lock);
3623 if (vmx->vpid != 0)
3624 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3625 spin_unlock(&vmx_vpid_lock);
3626 vmx_free_vmcs(vcpu);
3627 kfree(vmx->host_msrs);
3628 kfree(vmx->guest_msrs);
3629 kvm_vcpu_uninit(vcpu);
3630 kmem_cache_free(kvm_vcpu_cache, vmx);
3631 }
3632
3633 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3634 {
3635 int err;
3636 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3637 int cpu;
3638
3639 if (!vmx)
3640 return ERR_PTR(-ENOMEM);
3641
3642 allocate_vpid(vmx);
3643
3644 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3645 if (err)
3646 goto free_vcpu;
3647
3648 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3649 if (!vmx->guest_msrs) {
3650 err = -ENOMEM;
3651 goto uninit_vcpu;
3652 }
3653
3654 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3655 if (!vmx->host_msrs)
3656 goto free_guest_msrs;
3657
3658 vmx->vmcs = alloc_vmcs();
3659 if (!vmx->vmcs)
3660 goto free_msrs;
3661
3662 vmcs_clear(vmx->vmcs);
3663
3664 cpu = get_cpu();
3665 vmx_vcpu_load(&vmx->vcpu, cpu);
3666 err = vmx_vcpu_setup(vmx);
3667 vmx_vcpu_put(&vmx->vcpu);
3668 put_cpu();
3669 if (err)
3670 goto free_vmcs;
3671 if (vm_need_virtualize_apic_accesses(kvm))
3672 if (alloc_apic_access_page(kvm) != 0)
3673 goto free_vmcs;
3674
3675 if (vm_need_ept())
3676 if (alloc_identity_pagetable(kvm) != 0)
3677 goto free_vmcs;
3678
3679 return &vmx->vcpu;
3680
3681 free_vmcs:
3682 free_vmcs(vmx->vmcs);
3683 free_msrs:
3684 kfree(vmx->host_msrs);
3685 free_guest_msrs:
3686 kfree(vmx->guest_msrs);
3687 uninit_vcpu:
3688 kvm_vcpu_uninit(&vmx->vcpu);
3689 free_vcpu:
3690 kmem_cache_free(kvm_vcpu_cache, vmx);
3691 return ERR_PTR(err);
3692 }
3693
3694 static void __init vmx_check_processor_compat(void *rtn)
3695 {
3696 struct vmcs_config vmcs_conf;
3697
3698 *(int *)rtn = 0;
3699 if (setup_vmcs_config(&vmcs_conf) < 0)
3700 *(int *)rtn = -EIO;
3701 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3702 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3703 smp_processor_id());
3704 *(int *)rtn = -EIO;
3705 }
3706 }
3707
3708 static int get_ept_level(void)
3709 {
3710 return VMX_EPT_DEFAULT_GAW + 1;
3711 }
3712
3713 static int vmx_get_mt_mask_shift(void)
3714 {
3715 return VMX_EPT_MT_EPTE_SHIFT;
3716 }
3717
3718 static struct kvm_x86_ops vmx_x86_ops = {
3719 .cpu_has_kvm_support = cpu_has_kvm_support,
3720 .disabled_by_bios = vmx_disabled_by_bios,
3721 .hardware_setup = hardware_setup,
3722 .hardware_unsetup = hardware_unsetup,
3723 .check_processor_compatibility = vmx_check_processor_compat,
3724 .hardware_enable = hardware_enable,
3725 .hardware_disable = hardware_disable,
3726 .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
3727
3728 .vcpu_create = vmx_create_vcpu,
3729 .vcpu_free = vmx_free_vcpu,
3730 .vcpu_reset = vmx_vcpu_reset,
3731
3732 .prepare_guest_switch = vmx_save_host_state,
3733 .vcpu_load = vmx_vcpu_load,
3734 .vcpu_put = vmx_vcpu_put,
3735
3736 .set_guest_debug = set_guest_debug,
3737 .get_msr = vmx_get_msr,
3738 .set_msr = vmx_set_msr,
3739 .get_segment_base = vmx_get_segment_base,
3740 .get_segment = vmx_get_segment,
3741 .set_segment = vmx_set_segment,
3742 .get_cpl = vmx_get_cpl,
3743 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3744 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3745 .set_cr0 = vmx_set_cr0,
3746 .set_cr3 = vmx_set_cr3,
3747 .set_cr4 = vmx_set_cr4,
3748 .set_efer = vmx_set_efer,
3749 .get_idt = vmx_get_idt,
3750 .set_idt = vmx_set_idt,
3751 .get_gdt = vmx_get_gdt,
3752 .set_gdt = vmx_set_gdt,
3753 .cache_reg = vmx_cache_reg,
3754 .get_rflags = vmx_get_rflags,
3755 .set_rflags = vmx_set_rflags,
3756
3757 .tlb_flush = vmx_flush_tlb,
3758
3759 .run = vmx_vcpu_run,
3760 .handle_exit = kvm_handle_exit,
3761 .skip_emulated_instruction = skip_emulated_instruction,
3762 .set_interrupt_shadow = vmx_set_interrupt_shadow,
3763 .get_interrupt_shadow = vmx_get_interrupt_shadow,
3764 .patch_hypercall = vmx_patch_hypercall,
3765 .get_irq = vmx_get_irq,
3766 .set_irq = vmx_inject_irq,
3767 .queue_exception = vmx_queue_exception,
3768 .exception_injected = vmx_exception_injected,
3769 .inject_pending_irq = vmx_intr_assist,
3770 .inject_pending_vectors = do_interrupt_requests,
3771
3772 .set_tss_addr = vmx_set_tss_addr,
3773 .get_tdp_level = get_ept_level,
3774 .get_mt_mask_shift = vmx_get_mt_mask_shift,
3775 };
3776
3777 static int __init vmx_init(void)
3778 {
3779 void *va;
3780 int r;
3781
3782 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3783 if (!vmx_io_bitmap_a)
3784 return -ENOMEM;
3785
3786 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3787 if (!vmx_io_bitmap_b) {
3788 r = -ENOMEM;
3789 goto out;
3790 }
3791
3792 vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3793 if (!vmx_msr_bitmap) {
3794 r = -ENOMEM;
3795 goto out1;
3796 }
3797
3798 /*
3799 * Allow direct access to the PC debug port (it is often used for I/O
3800 * delays, but the vmexits simply slow things down).
3801 */
3802 va = kmap(vmx_io_bitmap_a);
3803 memset(va, 0xff, PAGE_SIZE);
3804 clear_bit(0x80, va);
3805 kunmap(vmx_io_bitmap_a);
3806
3807 va = kmap(vmx_io_bitmap_b);
3808 memset(va, 0xff, PAGE_SIZE);
3809 kunmap(vmx_io_bitmap_b);
3810
3811 va = kmap(vmx_msr_bitmap);
3812 memset(va, 0xff, PAGE_SIZE);
3813 kunmap(vmx_msr_bitmap);
3814
3815 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3816
3817 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
3818 if (r)
3819 goto out2;
3820
3821 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
3822 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
3823 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
3824 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
3825 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
3826
3827 if (vm_need_ept()) {
3828 bypass_guest_pf = 0;
3829 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3830 VMX_EPT_WRITABLE_MASK);
3831 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
3832 VMX_EPT_EXECUTABLE_MASK,
3833 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
3834 kvm_enable_tdp();
3835 } else
3836 kvm_disable_tdp();
3837
3838 if (bypass_guest_pf)
3839 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3840
3841 ept_sync_global();
3842
3843 return 0;
3844
3845 out2:
3846 __free_page(vmx_msr_bitmap);
3847 out1:
3848 __free_page(vmx_io_bitmap_b);
3849 out:
3850 __free_page(vmx_io_bitmap_a);
3851 return r;
3852 }
3853
3854 static void __exit vmx_exit(void)
3855 {
3856 __free_page(vmx_msr_bitmap);
3857 __free_page(vmx_io_bitmap_b);
3858 __free_page(vmx_io_bitmap_a);
3859
3860 kvm_exit();
3861 }
3862
3863 module_init(vmx_init)
3864 module_exit(vmx_exit)
Support for the Chinese Samsung S3C2440 based development boards