?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
drm/i915: Move flushing list cleanup from flush request retire to request emit.
[linux-2.6/mini2440.git] / drivers / gpu / drm / i915 / i915_gem.c
blob9fd28ebe0aa3739a489c41d4a26772a8d53b1a13
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #include "drmP.h"
29 #include "drm.h"
30 #include "i915_drm.h"
31 #include "i915_drv.h"
32 #include <linux/swap.h>
33
34 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
35
36 static int
37 i915_gem_object_set_domain(struct drm_gem_object *obj,
38 uint32_t read_domains,
39 uint32_t write_domain);
40 static int
41 i915_gem_object_set_domain_range(struct drm_gem_object *obj,
42 uint64_t offset,
43 uint64_t size,
44 uint32_t read_domains,
45 uint32_t write_domain);
46 static int
47 i915_gem_set_domain(struct drm_gem_object *obj,
48 struct drm_file *file_priv,
49 uint32_t read_domains,
50 uint32_t write_domain);
51 static int i915_gem_object_get_page_list(struct drm_gem_object *obj);
52 static void i915_gem_object_free_page_list(struct drm_gem_object *obj);
53 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
54
55 static void
56 i915_gem_cleanup_ringbuffer(struct drm_device *dev);
57
58 int
59 i915_gem_init_ioctl(struct drm_device *dev, void *data,
60 struct drm_file *file_priv)
61 {
62 drm_i915_private_t *dev_priv = dev->dev_private;
63 struct drm_i915_gem_init *args = data;
64
65 mutex_lock(&dev->struct_mutex);
66
67 if (args->gtt_start >= args->gtt_end ||
68 (args->gtt_start & (PAGE_SIZE - 1)) != 0 ||
69 (args->gtt_end & (PAGE_SIZE - 1)) != 0) {
70 mutex_unlock(&dev->struct_mutex);
71 return -EINVAL;
72 }
73
74 drm_mm_init(&dev_priv->mm.gtt_space, args->gtt_start,
75 args->gtt_end - args->gtt_start);
76
77 dev->gtt_total = (uint32_t) (args->gtt_end - args->gtt_start);
78
79 mutex_unlock(&dev->struct_mutex);
80
81 return 0;
82 }
83
84 int
85 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
86 struct drm_file *file_priv)
87 {
88 struct drm_i915_gem_get_aperture *args = data;
89
90 if (!(dev->driver->driver_features & DRIVER_GEM))
91 return -ENODEV;
92
93 args->aper_size = dev->gtt_total;
94 args->aper_available_size = (args->aper_size -
95 atomic_read(&dev->pin_memory));
96
97 return 0;
98 }
99
100
101 /**
102 * Creates a new mm object and returns a handle to it.
103 */
104 int
105 i915_gem_create_ioctl(struct drm_device *dev, void *data,
106 struct drm_file *file_priv)
107 {
108 struct drm_i915_gem_create *args = data;
109 struct drm_gem_object *obj;
110 int handle, ret;
111
112 args->size = roundup(args->size, PAGE_SIZE);
113
114 /* Allocate the new object */
115 obj = drm_gem_object_alloc(dev, args->size);
116 if (obj == NULL)
117 return -ENOMEM;
118
119 ret = drm_gem_handle_create(file_priv, obj, &handle);
120 mutex_lock(&dev->struct_mutex);
121 drm_gem_object_handle_unreference(obj);
122 mutex_unlock(&dev->struct_mutex);
123
124 if (ret)
125 return ret;
126
127 args->handle = handle;
128
129 return 0;
130 }
131
132 /**
133 * Reads data from the object referenced by handle.
134 *
135 * On error, the contents of *data are undefined.
136 */
137 int
138 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
139 struct drm_file *file_priv)
140 {
141 struct drm_i915_gem_pread *args = data;
142 struct drm_gem_object *obj;
143 struct drm_i915_gem_object *obj_priv;
144 ssize_t read;
145 loff_t offset;
146 int ret;
147
148 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
149 if (obj == NULL)
150 return -EBADF;
151 obj_priv = obj->driver_private;
152
153 /* Bounds check source.
154 *
155 * XXX: This could use review for overflow issues...
156 */
157 if (args->offset > obj->size || args->size > obj->size ||
158 args->offset + args->size > obj->size) {
159 drm_gem_object_unreference(obj);
160 return -EINVAL;
161 }
162
163 mutex_lock(&dev->struct_mutex);
164
165 ret = i915_gem_object_set_domain_range(obj, args->offset, args->size,
166 I915_GEM_DOMAIN_CPU, 0);
167 if (ret != 0) {
168 drm_gem_object_unreference(obj);
169 mutex_unlock(&dev->struct_mutex);
170 return ret;
171 }
172
173 offset = args->offset;
174
175 read = vfs_read(obj->filp, (char __user *)(uintptr_t)args->data_ptr,
176 args->size, &offset);
177 if (read != args->size) {
178 drm_gem_object_unreference(obj);
179 mutex_unlock(&dev->struct_mutex);
180 if (read < 0)
181 return read;
182 else
183 return -EINVAL;
184 }
185
186 drm_gem_object_unreference(obj);
187 mutex_unlock(&dev->struct_mutex);
188
189 return 0;
190 }
191
192 /* This is the fast write path which cannot handle
193 * page faults in the source data
194 */
195
196 static inline int
197 fast_user_write(struct io_mapping *mapping,
198 loff_t page_base, int page_offset,
199 char __user *user_data,
200 int length)
201 {
202 char *vaddr_atomic;
203 unsigned long unwritten;
204
205 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
206 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
207 user_data, length);
208 io_mapping_unmap_atomic(vaddr_atomic);
209 if (unwritten)
210 return -EFAULT;
211 return 0;
212 }
213
214 /* Here's the write path which can sleep for
215 * page faults
216 */
217
218 static inline int
219 slow_user_write(struct io_mapping *mapping,
220 loff_t page_base, int page_offset,
221 char __user *user_data,
222 int length)
223 {
224 char __iomem *vaddr;
225 unsigned long unwritten;
226
227 vaddr = io_mapping_map_wc(mapping, page_base);
228 if (vaddr == NULL)
229 return -EFAULT;
230 unwritten = __copy_from_user(vaddr + page_offset,
231 user_data, length);
232 io_mapping_unmap(vaddr);
233 if (unwritten)
234 return -EFAULT;
235 return 0;
236 }
237
238 static int
239 i915_gem_gtt_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
240 struct drm_i915_gem_pwrite *args,
241 struct drm_file *file_priv)
242 {
243 struct drm_i915_gem_object *obj_priv = obj->driver_private;
244 drm_i915_private_t *dev_priv = dev->dev_private;
245 ssize_t remain;
246 loff_t offset, page_base;
247 char __user *user_data;
248 int page_offset, page_length;
249 int ret;
250
251 user_data = (char __user *) (uintptr_t) args->data_ptr;
252 remain = args->size;
253 if (!access_ok(VERIFY_READ, user_data, remain))
254 return -EFAULT;
255
256
257 mutex_lock(&dev->struct_mutex);
258 ret = i915_gem_object_pin(obj, 0);
259 if (ret) {
260 mutex_unlock(&dev->struct_mutex);
261 return ret;
262 }
263 ret = i915_gem_set_domain(obj, file_priv,
264 I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
265 if (ret)
266 goto fail;
267
268 obj_priv = obj->driver_private;
269 offset = obj_priv->gtt_offset + args->offset;
270 obj_priv->dirty = 1;
271
272 while (remain > 0) {
273 /* Operation in this page
274 *
275 * page_base = page offset within aperture
276 * page_offset = offset within page
277 * page_length = bytes to copy for this page
278 */
279 page_base = (offset & ~(PAGE_SIZE-1));
280 page_offset = offset & (PAGE_SIZE-1);
281 page_length = remain;
282 if ((page_offset + remain) > PAGE_SIZE)
283 page_length = PAGE_SIZE - page_offset;
284
285 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
286 page_offset, user_data, page_length);
287
288 /* If we get a fault while copying data, then (presumably) our
289 * source page isn't available. In this case, use the
290 * non-atomic function
291 */
292 if (ret) {
293 ret = slow_user_write (dev_priv->mm.gtt_mapping,
294 page_base, page_offset,
295 user_data, page_length);
296 if (ret)
297 goto fail;
298 }
299
300 remain -= page_length;
301 user_data += page_length;
302 offset += page_length;
303 }
304
305 fail:
306 i915_gem_object_unpin(obj);
307 mutex_unlock(&dev->struct_mutex);
308
309 return ret;
310 }
311
312 static int
313 i915_gem_shmem_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
314 struct drm_i915_gem_pwrite *args,
315 struct drm_file *file_priv)
316 {
317 int ret;
318 loff_t offset;
319 ssize_t written;
320
321 mutex_lock(&dev->struct_mutex);
322
323 ret = i915_gem_set_domain(obj, file_priv,
324 I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
325 if (ret) {
326 mutex_unlock(&dev->struct_mutex);
327 return ret;
328 }
329
330 offset = args->offset;
331
332 written = vfs_write(obj->filp,
333 (char __user *)(uintptr_t) args->data_ptr,
334 args->size, &offset);
335 if (written != args->size) {
336 mutex_unlock(&dev->struct_mutex);
337 if (written < 0)
338 return written;
339 else
340 return -EINVAL;
341 }
342
343 mutex_unlock(&dev->struct_mutex);
344
345 return 0;
346 }
347
348 /**
349 * Writes data to the object referenced by handle.
350 *
351 * On error, the contents of the buffer that were to be modified are undefined.
352 */
353 int
354 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
355 struct drm_file *file_priv)
356 {
357 struct drm_i915_gem_pwrite *args = data;
358 struct drm_gem_object *obj;
359 struct drm_i915_gem_object *obj_priv;
360 int ret = 0;
361
362 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
363 if (obj == NULL)
364 return -EBADF;
365 obj_priv = obj->driver_private;
366
367 /* Bounds check destination.
368 *
369 * XXX: This could use review for overflow issues...
370 */
371 if (args->offset > obj->size || args->size > obj->size ||
372 args->offset + args->size > obj->size) {
373 drm_gem_object_unreference(obj);
374 return -EINVAL;
375 }
376
377 /* We can only do the GTT pwrite on untiled buffers, as otherwise
378 * it would end up going through the fenced access, and we'll get
379 * different detiling behavior between reading and writing.
380 * pread/pwrite currently are reading and writing from the CPU
381 * perspective, requiring manual detiling by the client.
382 */
383 if (obj_priv->tiling_mode == I915_TILING_NONE &&
384 dev->gtt_total != 0)
385 ret = i915_gem_gtt_pwrite(dev, obj, args, file_priv);
386 else
387 ret = i915_gem_shmem_pwrite(dev, obj, args, file_priv);
388
389 #if WATCH_PWRITE
390 if (ret)
391 DRM_INFO("pwrite failed %d\n", ret);
392 #endif
393
394 drm_gem_object_unreference(obj);
395
396 return ret;
397 }
398
399 /**
400 * Called when user space prepares to use an object
401 */
402 int
403 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
404 struct drm_file *file_priv)
405 {
406 struct drm_i915_gem_set_domain *args = data;
407 struct drm_gem_object *obj;
408 int ret;
409
410 if (!(dev->driver->driver_features & DRIVER_GEM))
411 return -ENODEV;
412
413 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
414 if (obj == NULL)
415 return -EBADF;
416
417 mutex_lock(&dev->struct_mutex);
418 #if WATCH_BUF
419 DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n",
420 obj, obj->size, args->read_domains, args->write_domain);
421 #endif
422 ret = i915_gem_set_domain(obj, file_priv,
423 args->read_domains, args->write_domain);
424 drm_gem_object_unreference(obj);
425 mutex_unlock(&dev->struct_mutex);
426 return ret;
427 }
428
429 /**
430 * Called when user space has done writes to this buffer
431 */
432 int
433 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
434 struct drm_file *file_priv)
435 {
436 struct drm_i915_gem_sw_finish *args = data;
437 struct drm_gem_object *obj;
438 struct drm_i915_gem_object *obj_priv;
439 int ret = 0;
440
441 if (!(dev->driver->driver_features & DRIVER_GEM))
442 return -ENODEV;
443
444 mutex_lock(&dev->struct_mutex);
445 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
446 if (obj == NULL) {
447 mutex_unlock(&dev->struct_mutex);
448 return -EBADF;
449 }
450
451 #if WATCH_BUF
452 DRM_INFO("%s: sw_finish %d (%p %d)\n",
453 __func__, args->handle, obj, obj->size);
454 #endif
455 obj_priv = obj->driver_private;
456
457 /* Pinned buffers may be scanout, so flush the cache */
458 if ((obj->write_domain & I915_GEM_DOMAIN_CPU) && obj_priv->pin_count) {
459 i915_gem_clflush_object(obj);
460 drm_agp_chipset_flush(dev);
461 }
462 drm_gem_object_unreference(obj);
463 mutex_unlock(&dev->struct_mutex);
464 return ret;
465 }
466
467 /**
468 * Maps the contents of an object, returning the address it is mapped
469 * into.
470 *
471 * While the mapping holds a reference on the contents of the object, it doesn't
472 * imply a ref on the object itself.
473 */
474 int
475 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
476 struct drm_file *file_priv)
477 {
478 struct drm_i915_gem_mmap *args = data;
479 struct drm_gem_object *obj;
480 loff_t offset;
481 unsigned long addr;
482
483 if (!(dev->driver->driver_features & DRIVER_GEM))
484 return -ENODEV;
485
486 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
487 if (obj == NULL)
488 return -EBADF;
489
490 offset = args->offset;
491
492 down_write(&current->mm->mmap_sem);
493 addr = do_mmap(obj->filp, 0, args->size,
494 PROT_READ | PROT_WRITE, MAP_SHARED,
495 args->offset);
496 up_write(&current->mm->mmap_sem);
497 mutex_lock(&dev->struct_mutex);
498 drm_gem_object_unreference(obj);
499 mutex_unlock(&dev->struct_mutex);
500 if (IS_ERR((void *)addr))
501 return addr;
502
503 args->addr_ptr = (uint64_t) addr;
504
505 return 0;
506 }
507
508 static void
509 i915_gem_object_free_page_list(struct drm_gem_object *obj)
510 {
511 struct drm_i915_gem_object *obj_priv = obj->driver_private;
512 int page_count = obj->size / PAGE_SIZE;
513 int i;
514
515 if (obj_priv->page_list == NULL)
516 return;
517
518
519 for (i = 0; i < page_count; i++)
520 if (obj_priv->page_list[i] != NULL) {
521 if (obj_priv->dirty)
522 set_page_dirty(obj_priv->page_list[i]);
523 mark_page_accessed(obj_priv->page_list[i]);
524 page_cache_release(obj_priv->page_list[i]);
525 }
526 obj_priv->dirty = 0;
527
528 drm_free(obj_priv->page_list,
529 page_count * sizeof(struct page *),
530 DRM_MEM_DRIVER);
531 obj_priv->page_list = NULL;
532 }
533
534 static void
535 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
536 {
537 struct drm_device *dev = obj->dev;
538 drm_i915_private_t *dev_priv = dev->dev_private;
539 struct drm_i915_gem_object *obj_priv = obj->driver_private;
540
541 /* Add a reference if we're newly entering the active list. */
542 if (!obj_priv->active) {
543 drm_gem_object_reference(obj);
544 obj_priv->active = 1;
545 }
546 /* Move from whatever list we were on to the tail of execution. */
547 list_move_tail(&obj_priv->list,
548 &dev_priv->mm.active_list);
549 obj_priv->last_rendering_seqno = seqno;
550 }
551
552 static void
553 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
554 {
555 struct drm_device *dev = obj->dev;
556 drm_i915_private_t *dev_priv = dev->dev_private;
557 struct drm_i915_gem_object *obj_priv = obj->driver_private;
558
559 BUG_ON(!obj_priv->active);
560 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
561 obj_priv->last_rendering_seqno = 0;
562 }
563
564 static void
565 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
566 {
567 struct drm_device *dev = obj->dev;
568 drm_i915_private_t *dev_priv = dev->dev_private;
569 struct drm_i915_gem_object *obj_priv = obj->driver_private;
570
571 i915_verify_inactive(dev, __FILE__, __LINE__);
572 if (obj_priv->pin_count != 0)
573 list_del_init(&obj_priv->list);
574 else
575 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
576
577 obj_priv->last_rendering_seqno = 0;
578 if (obj_priv->active) {
579 obj_priv->active = 0;
580 drm_gem_object_unreference(obj);
581 }
582 i915_verify_inactive(dev, __FILE__, __LINE__);
583 }
584
585 /**
586 * Creates a new sequence number, emitting a write of it to the status page
587 * plus an interrupt, which will trigger i915_user_interrupt_handler.
588 *
589 * Must be called with struct_lock held.
590 *
591 * Returned sequence numbers are nonzero on success.
592 */
593 static uint32_t
594 i915_add_request(struct drm_device *dev, uint32_t flush_domains)
595 {
596 drm_i915_private_t *dev_priv = dev->dev_private;
597 struct drm_i915_gem_request *request;
598 uint32_t seqno;
599 int was_empty;
600 RING_LOCALS;
601
602 request = drm_calloc(1, sizeof(*request), DRM_MEM_DRIVER);
603 if (request == NULL)
604 return 0;
605
606 /* Grab the seqno we're going to make this request be, and bump the
607 * next (skipping 0 so it can be the reserved no-seqno value).
608 */
609 seqno = dev_priv->mm.next_gem_seqno;
610 dev_priv->mm.next_gem_seqno++;
611 if (dev_priv->mm.next_gem_seqno == 0)
612 dev_priv->mm.next_gem_seqno++;
613
614 BEGIN_LP_RING(4);
615 OUT_RING(MI_STORE_DWORD_INDEX);
616 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
617 OUT_RING(seqno);
618
619 OUT_RING(MI_USER_INTERRUPT);
620 ADVANCE_LP_RING();
621
622 DRM_DEBUG("%d\n", seqno);
623
624 request->seqno = seqno;
625 request->emitted_jiffies = jiffies;
626 was_empty = list_empty(&dev_priv->mm.request_list);
627 list_add_tail(&request->list, &dev_priv->mm.request_list);
628
629 /* Associate any objects on the flushing list matching the write
630 * domain we're flushing with our flush.
631 */
632 if (flush_domains != 0) {
633 struct drm_i915_gem_object *obj_priv, *next;
634
635 list_for_each_entry_safe(obj_priv, next,
636 &dev_priv->mm.flushing_list, list) {
637 struct drm_gem_object *obj = obj_priv->obj;
638
639 if ((obj->write_domain & flush_domains) ==
640 obj->write_domain) {
641 obj->write_domain = 0;
642 i915_gem_object_move_to_active(obj, seqno);
643 }
644 }
645
646 }
647
648 if (was_empty && !dev_priv->mm.suspended)
649 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
650 return seqno;
651 }
652
653 /**
654 * Command execution barrier
655 *
656 * Ensures that all commands in the ring are finished
657 * before signalling the CPU
658 */
659 static uint32_t
660 i915_retire_commands(struct drm_device *dev)
661 {
662 drm_i915_private_t *dev_priv = dev->dev_private;
663 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
664 uint32_t flush_domains = 0;
665 RING_LOCALS;
666
667 /* The sampler always gets flushed on i965 (sigh) */
668 if (IS_I965G(dev))
669 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
670 BEGIN_LP_RING(2);
671 OUT_RING(cmd);
672 OUT_RING(0); /* noop */
673 ADVANCE_LP_RING();
674 return flush_domains;
675 }
676
677 /**
678 * Moves buffers associated only with the given active seqno from the active
679 * to inactive list, potentially freeing them.
680 */
681 static void
682 i915_gem_retire_request(struct drm_device *dev,
683 struct drm_i915_gem_request *request)
684 {
685 drm_i915_private_t *dev_priv = dev->dev_private;
686
687 /* Move any buffers on the active list that are no longer referenced
688 * by the ringbuffer to the flushing/inactive lists as appropriate.
689 */
690 while (!list_empty(&dev_priv->mm.active_list)) {
691 struct drm_gem_object *obj;
692 struct drm_i915_gem_object *obj_priv;
693
694 obj_priv = list_first_entry(&dev_priv->mm.active_list,
695 struct drm_i915_gem_object,
696 list);
697 obj = obj_priv->obj;
698
699 /* If the seqno being retired doesn't match the oldest in the
700 * list, then the oldest in the list must still be newer than
701 * this seqno.
702 */
703 if (obj_priv->last_rendering_seqno != request->seqno)
704 return;
705 #if WATCH_LRU
706 DRM_INFO("%s: retire %d moves to inactive list %p\n",
707 __func__, request->seqno, obj);
708 #endif
709
710 if (obj->write_domain != 0)
711 i915_gem_object_move_to_flushing(obj);
712 else
713 i915_gem_object_move_to_inactive(obj);
714 }
715 }
716
717 /**
718 * Returns true if seq1 is later than seq2.
719 */
720 static int
721 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
722 {
723 return (int32_t)(seq1 - seq2) >= 0;
724 }
725
726 uint32_t
727 i915_get_gem_seqno(struct drm_device *dev)
728 {
729 drm_i915_private_t *dev_priv = dev->dev_private;
730
731 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
732 }
733
734 /**
735 * This function clears the request list as sequence numbers are passed.
736 */
737 void
738 i915_gem_retire_requests(struct drm_device *dev)
739 {
740 drm_i915_private_t *dev_priv = dev->dev_private;
741 uint32_t seqno;
742
743 seqno = i915_get_gem_seqno(dev);
744
745 while (!list_empty(&dev_priv->mm.request_list)) {
746 struct drm_i915_gem_request *request;
747 uint32_t retiring_seqno;
748
749 request = list_first_entry(&dev_priv->mm.request_list,
750 struct drm_i915_gem_request,
751 list);
752 retiring_seqno = request->seqno;
753
754 if (i915_seqno_passed(seqno, retiring_seqno) ||
755 dev_priv->mm.wedged) {
756 i915_gem_retire_request(dev, request);
757
758 list_del(&request->list);
759 drm_free(request, sizeof(*request), DRM_MEM_DRIVER);
760 } else
761 break;
762 }
763 }
764
765 void
766 i915_gem_retire_work_handler(struct work_struct *work)
767 {
768 drm_i915_private_t *dev_priv;
769 struct drm_device *dev;
770
771 dev_priv = container_of(work, drm_i915_private_t,
772 mm.retire_work.work);
773 dev = dev_priv->dev;
774
775 mutex_lock(&dev->struct_mutex);
776 i915_gem_retire_requests(dev);
777 if (!dev_priv->mm.suspended &&
778 !list_empty(&dev_priv->mm.request_list))
779 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
780 mutex_unlock(&dev->struct_mutex);
781 }
782
783 /**
784 * Waits for a sequence number to be signaled, and cleans up the
785 * request and object lists appropriately for that event.
786 */
787 static int
788 i915_wait_request(struct drm_device *dev, uint32_t seqno)
789 {
790 drm_i915_private_t *dev_priv = dev->dev_private;
791 int ret = 0;
792
793 BUG_ON(seqno == 0);
794
795 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
796 dev_priv->mm.waiting_gem_seqno = seqno;
797 i915_user_irq_get(dev);
798 ret = wait_event_interruptible(dev_priv->irq_queue,
799 i915_seqno_passed(i915_get_gem_seqno(dev),
800 seqno) ||
801 dev_priv->mm.wedged);
802 i915_user_irq_put(dev);
803 dev_priv->mm.waiting_gem_seqno = 0;
804 }
805 if (dev_priv->mm.wedged)
806 ret = -EIO;
807
808 if (ret && ret != -ERESTARTSYS)
809 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
810 __func__, ret, seqno, i915_get_gem_seqno(dev));
811
812 /* Directly dispatch request retiring. While we have the work queue
813 * to handle this, the waiter on a request often wants an associated
814 * buffer to have made it to the inactive list, and we would need
815 * a separate wait queue to handle that.
816 */
817 if (ret == 0)
818 i915_gem_retire_requests(dev);
819
820 return ret;
821 }
822
823 static void
824 i915_gem_flush(struct drm_device *dev,
825 uint32_t invalidate_domains,
826 uint32_t flush_domains)
827 {
828 drm_i915_private_t *dev_priv = dev->dev_private;
829 uint32_t cmd;
830 RING_LOCALS;
831
832 #if WATCH_EXEC
833 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
834 invalidate_domains, flush_domains);
835 #endif
836
837 if (flush_domains & I915_GEM_DOMAIN_CPU)
838 drm_agp_chipset_flush(dev);
839
840 if ((invalidate_domains | flush_domains) & ~(I915_GEM_DOMAIN_CPU |
841 I915_GEM_DOMAIN_GTT)) {
842 /*
843 * read/write caches:
844 *
845 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
846 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
847 * also flushed at 2d versus 3d pipeline switches.
848 *
849 * read-only caches:
850 *
851 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
852 * MI_READ_FLUSH is set, and is always flushed on 965.
853 *
854 * I915_GEM_DOMAIN_COMMAND may not exist?
855 *
856 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
857 * invalidated when MI_EXE_FLUSH is set.
858 *
859 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
860 * invalidated with every MI_FLUSH.
861 *
862 * TLBs:
863 *
864 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
865 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
866 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
867 * are flushed at any MI_FLUSH.
868 */
869
870 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
871 if ((invalidate_domains|flush_domains) &
872 I915_GEM_DOMAIN_RENDER)
873 cmd &= ~MI_NO_WRITE_FLUSH;
874 if (!IS_I965G(dev)) {
875 /*
876 * On the 965, the sampler cache always gets flushed
877 * and this bit is reserved.
878 */
879 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
880 cmd |= MI_READ_FLUSH;
881 }
882 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
883 cmd |= MI_EXE_FLUSH;
884
885 #if WATCH_EXEC
886 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
887 #endif
888 BEGIN_LP_RING(2);
889 OUT_RING(cmd);
890 OUT_RING(0); /* noop */
891 ADVANCE_LP_RING();
892 }
893 }
894
895 /**
896 * Ensures that all rendering to the object has completed and the object is
897 * safe to unbind from the GTT or access from the CPU.
898 */
899 static int
900 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
901 {
902 struct drm_device *dev = obj->dev;
903 struct drm_i915_gem_object *obj_priv = obj->driver_private;
904 int ret;
905
906 /* If there are writes queued to the buffer, flush and
907 * create a new seqno to wait for.
908 */
909 if (obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)) {
910 uint32_t seqno, write_domain = obj->write_domain;
911 #if WATCH_BUF
912 DRM_INFO("%s: flushing object %p from write domain %08x\n",
913 __func__, obj, write_domain);
914 #endif
915 i915_gem_flush(dev, 0, write_domain);
916
917 seqno = i915_add_request(dev, write_domain);
918 i915_gem_object_move_to_active(obj, seqno);
919 #if WATCH_LRU
920 DRM_INFO("%s: flush moves to exec list %p\n", __func__, obj);
921 #endif
922 }
923
924 /* If there is rendering queued on the buffer being evicted, wait for
925 * it.
926 */
927 if (obj_priv->active) {
928 #if WATCH_BUF
929 DRM_INFO("%s: object %p wait for seqno %08x\n",
930 __func__, obj, obj_priv->last_rendering_seqno);
931 #endif
932 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
933 if (ret != 0)
934 return ret;
935 }
936
937 return 0;
938 }
939
940 /**
941 * Unbinds an object from the GTT aperture.
942 */
943 static int
944 i915_gem_object_unbind(struct drm_gem_object *obj)
945 {
946 struct drm_device *dev = obj->dev;
947 struct drm_i915_gem_object *obj_priv = obj->driver_private;
948 int ret = 0;
949
950 #if WATCH_BUF
951 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
952 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
953 #endif
954 if (obj_priv->gtt_space == NULL)
955 return 0;
956
957 if (obj_priv->pin_count != 0) {
958 DRM_ERROR("Attempting to unbind pinned buffer\n");
959 return -EINVAL;
960 }
961
962 /* Wait for any rendering to complete
963 */
964 ret = i915_gem_object_wait_rendering(obj);
965 if (ret) {
966 DRM_ERROR("wait_rendering failed: %d\n", ret);
967 return ret;
968 }
969
970 /* Move the object to the CPU domain to ensure that
971 * any possible CPU writes while it's not in the GTT
972 * are flushed when we go to remap it. This will
973 * also ensure that all pending GPU writes are finished
974 * before we unbind.
975 */
976 ret = i915_gem_object_set_domain(obj, I915_GEM_DOMAIN_CPU,
977 I915_GEM_DOMAIN_CPU);
978 if (ret) {
979 DRM_ERROR("set_domain failed: %d\n", ret);
980 return ret;
981 }
982
983 if (obj_priv->agp_mem != NULL) {
984 drm_unbind_agp(obj_priv->agp_mem);
985 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
986 obj_priv->agp_mem = NULL;
987 }
988
989 BUG_ON(obj_priv->active);
990
991 i915_gem_object_free_page_list(obj);
992
993 if (obj_priv->gtt_space) {
994 atomic_dec(&dev->gtt_count);
995 atomic_sub(obj->size, &dev->gtt_memory);
996
997 drm_mm_put_block(obj_priv->gtt_space);
998 obj_priv->gtt_space = NULL;
999 }
1000
1001 /* Remove ourselves from the LRU list if present. */
1002 if (!list_empty(&obj_priv->list))
1003 list_del_init(&obj_priv->list);
1004
1005 return 0;
1006 }
1007
1008 static int
1009 i915_gem_evict_something(struct drm_device *dev)
1010 {
1011 drm_i915_private_t *dev_priv = dev->dev_private;
1012 struct drm_gem_object *obj;
1013 struct drm_i915_gem_object *obj_priv;
1014 int ret = 0;
1015
1016 for (;;) {
1017 /* If there's an inactive buffer available now, grab it
1018 * and be done.
1019 */
1020 if (!list_empty(&dev_priv->mm.inactive_list)) {
1021 obj_priv = list_first_entry(&dev_priv->mm.inactive_list,
1022 struct drm_i915_gem_object,
1023 list);
1024 obj = obj_priv->obj;
1025 BUG_ON(obj_priv->pin_count != 0);
1026 #if WATCH_LRU
1027 DRM_INFO("%s: evicting %p\n", __func__, obj);
1028 #endif
1029 BUG_ON(obj_priv->active);
1030
1031 /* Wait on the rendering and unbind the buffer. */
1032 ret = i915_gem_object_unbind(obj);
1033 break;
1034 }
1035
1036 /* If we didn't get anything, but the ring is still processing
1037 * things, wait for one of those things to finish and hopefully
1038 * leave us a buffer to evict.
1039 */
1040 if (!list_empty(&dev_priv->mm.request_list)) {
1041 struct drm_i915_gem_request *request;
1042
1043 request = list_first_entry(&dev_priv->mm.request_list,
1044 struct drm_i915_gem_request,
1045 list);
1046
1047 ret = i915_wait_request(dev, request->seqno);
1048 if (ret)
1049 break;
1050
1051 /* if waiting caused an object to become inactive,
1052 * then loop around and wait for it. Otherwise, we
1053 * assume that waiting freed and unbound something,
1054 * so there should now be some space in the GTT
1055 */
1056 if (!list_empty(&dev_priv->mm.inactive_list))
1057 continue;
1058 break;
1059 }
1060
1061 /* If we didn't have anything on the request list but there
1062 * are buffers awaiting a flush, emit one and try again.
1063 * When we wait on it, those buffers waiting for that flush
1064 * will get moved to inactive.
1065 */
1066 if (!list_empty(&dev_priv->mm.flushing_list)) {
1067 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1068 struct drm_i915_gem_object,
1069 list);
1070 obj = obj_priv->obj;
1071
1072 i915_gem_flush(dev,
1073 obj->write_domain,
1074 obj->write_domain);
1075 i915_add_request(dev, obj->write_domain);
1076
1077 obj = NULL;
1078 continue;
1079 }
1080
1081 DRM_ERROR("inactive empty %d request empty %d "
1082 "flushing empty %d\n",
1083 list_empty(&dev_priv->mm.inactive_list),
1084 list_empty(&dev_priv->mm.request_list),
1085 list_empty(&dev_priv->mm.flushing_list));
1086 /* If we didn't do any of the above, there's nothing to be done
1087 * and we just can't fit it in.
1088 */
1089 return -ENOMEM;
1090 }
1091 return ret;
1092 }
1093
1094 static int
1095 i915_gem_object_get_page_list(struct drm_gem_object *obj)
1096 {
1097 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1098 int page_count, i;
1099 struct address_space *mapping;
1100 struct inode *inode;
1101 struct page *page;
1102 int ret;
1103
1104 if (obj_priv->page_list)
1105 return 0;
1106
1107 /* Get the list of pages out of our struct file. They'll be pinned
1108 * at this point until we release them.
1109 */
1110 page_count = obj->size / PAGE_SIZE;
1111 BUG_ON(obj_priv->page_list != NULL);
1112 obj_priv->page_list = drm_calloc(page_count, sizeof(struct page *),
1113 DRM_MEM_DRIVER);
1114 if (obj_priv->page_list == NULL) {
1115 DRM_ERROR("Faled to allocate page list\n");
1116 return -ENOMEM;
1117 }
1118
1119 inode = obj->filp->f_path.dentry->d_inode;
1120 mapping = inode->i_mapping;
1121 for (i = 0; i < page_count; i++) {
1122 page = read_mapping_page(mapping, i, NULL);
1123 if (IS_ERR(page)) {
1124 ret = PTR_ERR(page);
1125 DRM_ERROR("read_mapping_page failed: %d\n", ret);
1126 i915_gem_object_free_page_list(obj);
1127 return ret;
1128 }
1129 obj_priv->page_list[i] = page;
1130 }
1131 return 0;
1132 }
1133
1134 /**
1135 * Finds free space in the GTT aperture and binds the object there.
1136 */
1137 static int
1138 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
1139 {
1140 struct drm_device *dev = obj->dev;
1141 drm_i915_private_t *dev_priv = dev->dev_private;
1142 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1143 struct drm_mm_node *free_space;
1144 int page_count, ret;
1145
1146 if (alignment == 0)
1147 alignment = PAGE_SIZE;
1148 if (alignment & (PAGE_SIZE - 1)) {
1149 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
1150 return -EINVAL;
1151 }
1152
1153 search_free:
1154 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
1155 obj->size, alignment, 0);
1156 if (free_space != NULL) {
1157 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
1158 alignment);
1159 if (obj_priv->gtt_space != NULL) {
1160 obj_priv->gtt_space->private = obj;
1161 obj_priv->gtt_offset = obj_priv->gtt_space->start;
1162 }
1163 }
1164 if (obj_priv->gtt_space == NULL) {
1165 /* If the gtt is empty and we're still having trouble
1166 * fitting our object in, we're out of memory.
1167 */
1168 #if WATCH_LRU
1169 DRM_INFO("%s: GTT full, evicting something\n", __func__);
1170 #endif
1171 if (list_empty(&dev_priv->mm.inactive_list) &&
1172 list_empty(&dev_priv->mm.flushing_list) &&
1173 list_empty(&dev_priv->mm.active_list)) {
1174 DRM_ERROR("GTT full, but LRU list empty\n");
1175 return -ENOMEM;
1176 }
1177
1178 ret = i915_gem_evict_something(dev);
1179 if (ret != 0) {
1180 DRM_ERROR("Failed to evict a buffer %d\n", ret);
1181 return ret;
1182 }
1183 goto search_free;
1184 }
1185
1186 #if WATCH_BUF
1187 DRM_INFO("Binding object of size %d at 0x%08x\n",
1188 obj->size, obj_priv->gtt_offset);
1189 #endif
1190 ret = i915_gem_object_get_page_list(obj);
1191 if (ret) {
1192 drm_mm_put_block(obj_priv->gtt_space);
1193 obj_priv->gtt_space = NULL;
1194 return ret;
1195 }
1196
1197 page_count = obj->size / PAGE_SIZE;
1198 /* Create an AGP memory structure pointing at our pages, and bind it
1199 * into the GTT.
1200 */
1201 obj_priv->agp_mem = drm_agp_bind_pages(dev,
1202 obj_priv->page_list,
1203 page_count,
1204 obj_priv->gtt_offset,
1205 obj_priv->agp_type);
1206 if (obj_priv->agp_mem == NULL) {
1207 i915_gem_object_free_page_list(obj);
1208 drm_mm_put_block(obj_priv->gtt_space);
1209 obj_priv->gtt_space = NULL;
1210 return -ENOMEM;
1211 }
1212 atomic_inc(&dev->gtt_count);
1213 atomic_add(obj->size, &dev->gtt_memory);
1214
1215 /* Assert that the object is not currently in any GPU domain. As it
1216 * wasn't in the GTT, there shouldn't be any way it could have been in
1217 * a GPU cache
1218 */
1219 BUG_ON(obj->read_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1220 BUG_ON(obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1221
1222 return 0;
1223 }
1224
1225 void
1226 i915_gem_clflush_object(struct drm_gem_object *obj)
1227 {
1228 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1229
1230 /* If we don't have a page list set up, then we're not pinned
1231 * to GPU, and we can ignore the cache flush because it'll happen
1232 * again at bind time.
1233 */
1234 if (obj_priv->page_list == NULL)
1235 return;
1236
1237 drm_clflush_pages(obj_priv->page_list, obj->size / PAGE_SIZE);
1238 }
1239
1240 /*
1241 * Set the next domain for the specified object. This
1242 * may not actually perform the necessary flushing/invaliding though,
1243 * as that may want to be batched with other set_domain operations
1244 *
1245 * This is (we hope) the only really tricky part of gem. The goal
1246 * is fairly simple -- track which caches hold bits of the object
1247 * and make sure they remain coherent. A few concrete examples may
1248 * help to explain how it works. For shorthand, we use the notation
1249 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
1250 * a pair of read and write domain masks.
1251 *
1252 * Case 1: the batch buffer
1253 *
1254 * 1. Allocated
1255 * 2. Written by CPU
1256 * 3. Mapped to GTT
1257 * 4. Read by GPU
1258 * 5. Unmapped from GTT
1259 * 6. Freed
1260 *
1261 * Let's take these a step at a time
1262 *
1263 * 1. Allocated
1264 * Pages allocated from the kernel may still have
1265 * cache contents, so we set them to (CPU, CPU) always.
1266 * 2. Written by CPU (using pwrite)
1267 * The pwrite function calls set_domain (CPU, CPU) and
1268 * this function does nothing (as nothing changes)
1269 * 3. Mapped by GTT
1270 * This function asserts that the object is not
1271 * currently in any GPU-based read or write domains
1272 * 4. Read by GPU
1273 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
1274 * As write_domain is zero, this function adds in the
1275 * current read domains (CPU+COMMAND, 0).
1276 * flush_domains is set to CPU.
1277 * invalidate_domains is set to COMMAND
1278 * clflush is run to get data out of the CPU caches
1279 * then i915_dev_set_domain calls i915_gem_flush to
1280 * emit an MI_FLUSH and drm_agp_chipset_flush
1281 * 5. Unmapped from GTT
1282 * i915_gem_object_unbind calls set_domain (CPU, CPU)
1283 * flush_domains and invalidate_domains end up both zero
1284 * so no flushing/invalidating happens
1285 * 6. Freed
1286 * yay, done
1287 *
1288 * Case 2: The shared render buffer
1289 *
1290 * 1. Allocated
1291 * 2. Mapped to GTT
1292 * 3. Read/written by GPU
1293 * 4. set_domain to (CPU,CPU)
1294 * 5. Read/written by CPU
1295 * 6. Read/written by GPU
1296 *
1297 * 1. Allocated
1298 * Same as last example, (CPU, CPU)
1299 * 2. Mapped to GTT
1300 * Nothing changes (assertions find that it is not in the GPU)
1301 * 3. Read/written by GPU
1302 * execbuffer calls set_domain (RENDER, RENDER)
1303 * flush_domains gets CPU
1304 * invalidate_domains gets GPU
1305 * clflush (obj)
1306 * MI_FLUSH and drm_agp_chipset_flush
1307 * 4. set_domain (CPU, CPU)
1308 * flush_domains gets GPU
1309 * invalidate_domains gets CPU
1310 * wait_rendering (obj) to make sure all drawing is complete.
1311 * This will include an MI_FLUSH to get the data from GPU
1312 * to memory
1313 * clflush (obj) to invalidate the CPU cache
1314 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
1315 * 5. Read/written by CPU
1316 * cache lines are loaded and dirtied
1317 * 6. Read written by GPU
1318 * Same as last GPU access
1319 *
1320 * Case 3: The constant buffer
1321 *
1322 * 1. Allocated
1323 * 2. Written by CPU
1324 * 3. Read by GPU
1325 * 4. Updated (written) by CPU again
1326 * 5. Read by GPU
1327 *
1328 * 1. Allocated
1329 * (CPU, CPU)
1330 * 2. Written by CPU
1331 * (CPU, CPU)
1332 * 3. Read by GPU
1333 * (CPU+RENDER, 0)
1334 * flush_domains = CPU
1335 * invalidate_domains = RENDER
1336 * clflush (obj)
1337 * MI_FLUSH
1338 * drm_agp_chipset_flush
1339 * 4. Updated (written) by CPU again
1340 * (CPU, CPU)
1341 * flush_domains = 0 (no previous write domain)
1342 * invalidate_domains = 0 (no new read domains)
1343 * 5. Read by GPU
1344 * (CPU+RENDER, 0)
1345 * flush_domains = CPU
1346 * invalidate_domains = RENDER
1347 * clflush (obj)
1348 * MI_FLUSH
1349 * drm_agp_chipset_flush
1350 */
1351 static int
1352 i915_gem_object_set_domain(struct drm_gem_object *obj,
1353 uint32_t read_domains,
1354 uint32_t write_domain)
1355 {
1356 struct drm_device *dev = obj->dev;
1357 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1358 uint32_t invalidate_domains = 0;
1359 uint32_t flush_domains = 0;
1360 int ret;
1361
1362 #if WATCH_BUF
1363 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
1364 __func__, obj,
1365 obj->read_domains, read_domains,
1366 obj->write_domain, write_domain);
1367 #endif
1368 /*
1369 * If the object isn't moving to a new write domain,
1370 * let the object stay in multiple read domains
1371 */
1372 if (write_domain == 0)
1373 read_domains |= obj->read_domains;
1374 else
1375 obj_priv->dirty = 1;
1376
1377 /*
1378 * Flush the current write domain if
1379 * the new read domains don't match. Invalidate
1380 * any read domains which differ from the old
1381 * write domain
1382 */
1383 if (obj->write_domain && obj->write_domain != read_domains) {
1384 flush_domains |= obj->write_domain;
1385 invalidate_domains |= read_domains & ~obj->write_domain;
1386 }
1387 /*
1388 * Invalidate any read caches which may have
1389 * stale data. That is, any new read domains.
1390 */
1391 invalidate_domains |= read_domains & ~obj->read_domains;
1392 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
1393 #if WATCH_BUF
1394 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
1395 __func__, flush_domains, invalidate_domains);
1396 #endif
1397 /*
1398 * If we're invaliding the CPU cache and flushing a GPU cache,
1399 * then pause for rendering so that the GPU caches will be
1400 * flushed before the cpu cache is invalidated
1401 */
1402 if ((invalidate_domains & I915_GEM_DOMAIN_CPU) &&
1403 (flush_domains & ~(I915_GEM_DOMAIN_CPU |
1404 I915_GEM_DOMAIN_GTT))) {
1405 ret = i915_gem_object_wait_rendering(obj);
1406 if (ret)
1407 return ret;
1408 }
1409 i915_gem_clflush_object(obj);
1410 }
1411
1412 if ((write_domain | flush_domains) != 0)
1413 obj->write_domain = write_domain;
1414
1415 /* If we're invalidating the CPU domain, clear the per-page CPU
1416 * domain list as well.
1417 */
1418 if (obj_priv->page_cpu_valid != NULL &&
1419 (write_domain != 0 ||
1420 read_domains & I915_GEM_DOMAIN_CPU)) {
1421 drm_free(obj_priv->page_cpu_valid, obj->size / PAGE_SIZE,
1422 DRM_MEM_DRIVER);
1423 obj_priv->page_cpu_valid = NULL;
1424 }
1425 obj->read_domains = read_domains;
1426
1427 dev->invalidate_domains |= invalidate_domains;
1428 dev->flush_domains |= flush_domains;
1429 #if WATCH_BUF
1430 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
1431 __func__,
1432 obj->read_domains, obj->write_domain,
1433 dev->invalidate_domains, dev->flush_domains);
1434 #endif
1435 return 0;
1436 }
1437
1438 /**
1439 * Set the read/write domain on a range of the object.
1440 *
1441 * Currently only implemented for CPU reads, otherwise drops to normal
1442 * i915_gem_object_set_domain().
1443 */
1444 static int
1445 i915_gem_object_set_domain_range(struct drm_gem_object *obj,
1446 uint64_t offset,
1447 uint64_t size,
1448 uint32_t read_domains,
1449 uint32_t write_domain)
1450 {
1451 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1452 int ret, i;
1453
1454 if (obj->read_domains & I915_GEM_DOMAIN_CPU)
1455 return 0;
1456
1457 if (read_domains != I915_GEM_DOMAIN_CPU ||
1458 write_domain != 0)
1459 return i915_gem_object_set_domain(obj,
1460 read_domains, write_domain);
1461
1462 /* Wait on any GPU rendering to the object to be flushed. */
1463 ret = i915_gem_object_wait_rendering(obj);
1464 if (ret)
1465 return ret;
1466
1467 if (obj_priv->page_cpu_valid == NULL) {
1468 obj_priv->page_cpu_valid = drm_calloc(1, obj->size / PAGE_SIZE,
1469 DRM_MEM_DRIVER);
1470 }
1471
1472 /* Flush the cache on any pages that are still invalid from the CPU's
1473 * perspective.
1474 */
1475 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; i++) {
1476 if (obj_priv->page_cpu_valid[i])
1477 continue;
1478
1479 drm_clflush_pages(obj_priv->page_list + i, 1);
1480
1481 obj_priv->page_cpu_valid[i] = 1;
1482 }
1483
1484 return 0;
1485 }
1486
1487 /**
1488 * Once all of the objects have been set in the proper domain,
1489 * perform the necessary flush and invalidate operations.
1490 *
1491 * Returns the write domains flushed, for use in flush tracking.
1492 */
1493 static uint32_t
1494 i915_gem_dev_set_domain(struct drm_device *dev)
1495 {
1496 uint32_t flush_domains = dev->flush_domains;
1497
1498 /*
1499 * Now that all the buffers are synced to the proper domains,
1500 * flush and invalidate the collected domains
1501 */
1502 if (dev->invalidate_domains | dev->flush_domains) {
1503 #if WATCH_EXEC
1504 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
1505 __func__,
1506 dev->invalidate_domains,
1507 dev->flush_domains);
1508 #endif
1509 i915_gem_flush(dev,
1510 dev->invalidate_domains,
1511 dev->flush_domains);
1512 dev->invalidate_domains = 0;
1513 dev->flush_domains = 0;
1514 }
1515
1516 return flush_domains;
1517 }
1518
1519 /**
1520 * Pin an object to the GTT and evaluate the relocations landing in it.
1521 */
1522 static int
1523 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
1524 struct drm_file *file_priv,
1525 struct drm_i915_gem_exec_object *entry)
1526 {
1527 struct drm_device *dev = obj->dev;
1528 drm_i915_private_t *dev_priv = dev->dev_private;
1529 struct drm_i915_gem_relocation_entry reloc;
1530 struct drm_i915_gem_relocation_entry __user *relocs;
1531 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1532 int i, ret;
1533 void __iomem *reloc_page;
1534
1535 /* Choose the GTT offset for our buffer and put it there. */
1536 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
1537 if (ret)
1538 return ret;
1539
1540 entry->offset = obj_priv->gtt_offset;
1541
1542 relocs = (struct drm_i915_gem_relocation_entry __user *)
1543 (uintptr_t) entry->relocs_ptr;
1544 /* Apply the relocations, using the GTT aperture to avoid cache
1545 * flushing requirements.
1546 */
1547 for (i = 0; i < entry->relocation_count; i++) {
1548 struct drm_gem_object *target_obj;
1549 struct drm_i915_gem_object *target_obj_priv;
1550 uint32_t reloc_val, reloc_offset;
1551 uint32_t __iomem *reloc_entry;
1552
1553 ret = copy_from_user(&reloc, relocs + i, sizeof(reloc));
1554 if (ret != 0) {
1555 i915_gem_object_unpin(obj);
1556 return ret;
1557 }
1558
1559 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
1560 reloc.target_handle);
1561 if (target_obj == NULL) {
1562 i915_gem_object_unpin(obj);
1563 return -EBADF;
1564 }
1565 target_obj_priv = target_obj->driver_private;
1566
1567 /* The target buffer should have appeared before us in the
1568 * exec_object list, so it should have a GTT space bound by now.
1569 */
1570 if (target_obj_priv->gtt_space == NULL) {
1571 DRM_ERROR("No GTT space found for object %d\n",
1572 reloc.target_handle);
1573 drm_gem_object_unreference(target_obj);
1574 i915_gem_object_unpin(obj);
1575 return -EINVAL;
1576 }
1577
1578 if (reloc.offset > obj->size - 4) {
1579 DRM_ERROR("Relocation beyond object bounds: "
1580 "obj %p target %d offset %d size %d.\n",
1581 obj, reloc.target_handle,
1582 (int) reloc.offset, (int) obj->size);
1583 drm_gem_object_unreference(target_obj);
1584 i915_gem_object_unpin(obj);
1585 return -EINVAL;
1586 }
1587 if (reloc.offset & 3) {
1588 DRM_ERROR("Relocation not 4-byte aligned: "
1589 "obj %p target %d offset %d.\n",
1590 obj, reloc.target_handle,
1591 (int) reloc.offset);
1592 drm_gem_object_unreference(target_obj);
1593 i915_gem_object_unpin(obj);
1594 return -EINVAL;
1595 }
1596
1597 if (reloc.write_domain && target_obj->pending_write_domain &&
1598 reloc.write_domain != target_obj->pending_write_domain) {
1599 DRM_ERROR("Write domain conflict: "
1600 "obj %p target %d offset %d "
1601 "new %08x old %08x\n",
1602 obj, reloc.target_handle,
1603 (int) reloc.offset,
1604 reloc.write_domain,
1605 target_obj->pending_write_domain);
1606 drm_gem_object_unreference(target_obj);
1607 i915_gem_object_unpin(obj);
1608 return -EINVAL;
1609 }
1610
1611 #if WATCH_RELOC
1612 DRM_INFO("%s: obj %p offset %08x target %d "
1613 "read %08x write %08x gtt %08x "
1614 "presumed %08x delta %08x\n",
1615 __func__,
1616 obj,
1617 (int) reloc.offset,
1618 (int) reloc.target_handle,
1619 (int) reloc.read_domains,
1620 (int) reloc.write_domain,
1621 (int) target_obj_priv->gtt_offset,
1622 (int) reloc.presumed_offset,
1623 reloc.delta);
1624 #endif
1625
1626 target_obj->pending_read_domains |= reloc.read_domains;
1627 target_obj->pending_write_domain |= reloc.write_domain;
1628
1629 /* If the relocation already has the right value in it, no
1630 * more work needs to be done.
1631 */
1632 if (target_obj_priv->gtt_offset == reloc.presumed_offset) {
1633 drm_gem_object_unreference(target_obj);
1634 continue;
1635 }
1636
1637 /* Now that we're going to actually write some data in,
1638 * make sure that any rendering using this buffer's contents
1639 * is completed.
1640 */
1641 i915_gem_object_wait_rendering(obj);
1642
1643 /* As we're writing through the gtt, flush
1644 * any CPU writes before we write the relocations
1645 */
1646 if (obj->write_domain & I915_GEM_DOMAIN_CPU) {
1647 i915_gem_clflush_object(obj);
1648 drm_agp_chipset_flush(dev);
1649 obj->write_domain = 0;
1650 }
1651
1652 /* Map the page containing the relocation we're going to
1653 * perform.
1654 */
1655 reloc_offset = obj_priv->gtt_offset + reloc.offset;
1656 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
1657 (reloc_offset &
1658 ~(PAGE_SIZE - 1)));
1659 reloc_entry = (uint32_t __iomem *)(reloc_page +
1660 (reloc_offset & (PAGE_SIZE - 1)));
1661 reloc_val = target_obj_priv->gtt_offset + reloc.delta;
1662
1663 #if WATCH_BUF
1664 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
1665 obj, (unsigned int) reloc.offset,
1666 readl(reloc_entry), reloc_val);
1667 #endif
1668 writel(reloc_val, reloc_entry);
1669 io_mapping_unmap_atomic(reloc_page);
1670
1671 /* Write the updated presumed offset for this entry back out
1672 * to the user.
1673 */
1674 reloc.presumed_offset = target_obj_priv->gtt_offset;
1675 ret = copy_to_user(relocs + i, &reloc, sizeof(reloc));
1676 if (ret != 0) {
1677 drm_gem_object_unreference(target_obj);
1678 i915_gem_object_unpin(obj);
1679 return ret;
1680 }
1681
1682 drm_gem_object_unreference(target_obj);
1683 }
1684
1685 #if WATCH_BUF
1686 if (0)
1687 i915_gem_dump_object(obj, 128, __func__, ~0);
1688 #endif
1689 return 0;
1690 }
1691
1692 /** Dispatch a batchbuffer to the ring
1693 */
1694 static int
1695 i915_dispatch_gem_execbuffer(struct drm_device *dev,
1696 struct drm_i915_gem_execbuffer *exec,
1697 uint64_t exec_offset)
1698 {
1699 drm_i915_private_t *dev_priv = dev->dev_private;
1700 struct drm_clip_rect __user *boxes = (struct drm_clip_rect __user *)
1701 (uintptr_t) exec->cliprects_ptr;
1702 int nbox = exec->num_cliprects;
1703 int i = 0, count;
1704 uint32_t exec_start, exec_len;
1705 RING_LOCALS;
1706
1707 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
1708 exec_len = (uint32_t) exec->batch_len;
1709
1710 if ((exec_start | exec_len) & 0x7) {
1711 DRM_ERROR("alignment\n");
1712 return -EINVAL;
1713 }
1714
1715 if (!exec_start)
1716 return -EINVAL;
1717
1718 count = nbox ? nbox : 1;
1719
1720 for (i = 0; i < count; i++) {
1721 if (i < nbox) {
1722 int ret = i915_emit_box(dev, boxes, i,
1723 exec->DR1, exec->DR4);
1724 if (ret)
1725 return ret;
1726 }
1727
1728 if (IS_I830(dev) || IS_845G(dev)) {
1729 BEGIN_LP_RING(4);
1730 OUT_RING(MI_BATCH_BUFFER);
1731 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
1732 OUT_RING(exec_start + exec_len - 4);
1733 OUT_RING(0);
1734 ADVANCE_LP_RING();
1735 } else {
1736 BEGIN_LP_RING(2);
1737 if (IS_I965G(dev)) {
1738 OUT_RING(MI_BATCH_BUFFER_START |
1739 (2 << 6) |
1740 MI_BATCH_NON_SECURE_I965);
1741 OUT_RING(exec_start);
1742 } else {
1743 OUT_RING(MI_BATCH_BUFFER_START |
1744 (2 << 6));
1745 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
1746 }
1747 ADVANCE_LP_RING();
1748 }
1749 }
1750
1751 /* XXX breadcrumb */
1752 return 0;
1753 }
1754
1755 /* Throttle our rendering by waiting until the ring has completed our requests
1756 * emitted over 20 msec ago.
1757 *
1758 * This should get us reasonable parallelism between CPU and GPU but also
1759 * relatively low latency when blocking on a particular request to finish.
1760 */
1761 static int
1762 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
1763 {
1764 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1765 int ret = 0;
1766 uint32_t seqno;
1767
1768 mutex_lock(&dev->struct_mutex);
1769 seqno = i915_file_priv->mm.last_gem_throttle_seqno;
1770 i915_file_priv->mm.last_gem_throttle_seqno =
1771 i915_file_priv->mm.last_gem_seqno;
1772 if (seqno)
1773 ret = i915_wait_request(dev, seqno);
1774 mutex_unlock(&dev->struct_mutex);
1775 return ret;
1776 }
1777
1778 int
1779 i915_gem_execbuffer(struct drm_device *dev, void *data,
1780 struct drm_file *file_priv)
1781 {
1782 drm_i915_private_t *dev_priv = dev->dev_private;
1783 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1784 struct drm_i915_gem_execbuffer *args = data;
1785 struct drm_i915_gem_exec_object *exec_list = NULL;
1786 struct drm_gem_object **object_list = NULL;
1787 struct drm_gem_object *batch_obj;
1788 int ret, i, pinned = 0;
1789 uint64_t exec_offset;
1790 uint32_t seqno, flush_domains;
1791
1792 #if WATCH_EXEC
1793 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
1794 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
1795 #endif
1796
1797 if (args->buffer_count < 1) {
1798 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
1799 return -EINVAL;
1800 }
1801 /* Copy in the exec list from userland */
1802 exec_list = drm_calloc(sizeof(*exec_list), args->buffer_count,
1803 DRM_MEM_DRIVER);
1804 object_list = drm_calloc(sizeof(*object_list), args->buffer_count,
1805 DRM_MEM_DRIVER);
1806 if (exec_list == NULL || object_list == NULL) {
1807 DRM_ERROR("Failed to allocate exec or object list "
1808 "for %d buffers\n",
1809 args->buffer_count);
1810 ret = -ENOMEM;
1811 goto pre_mutex_err;
1812 }
1813 ret = copy_from_user(exec_list,
1814 (struct drm_i915_relocation_entry __user *)
1815 (uintptr_t) args->buffers_ptr,
1816 sizeof(*exec_list) * args->buffer_count);
1817 if (ret != 0) {
1818 DRM_ERROR("copy %d exec entries failed %d\n",
1819 args->buffer_count, ret);
1820 goto pre_mutex_err;
1821 }
1822
1823 mutex_lock(&dev->struct_mutex);
1824
1825 i915_verify_inactive(dev, __FILE__, __LINE__);
1826
1827 if (dev_priv->mm.wedged) {
1828 DRM_ERROR("Execbuf while wedged\n");
1829 mutex_unlock(&dev->struct_mutex);
1830 return -EIO;
1831 }
1832
1833 if (dev_priv->mm.suspended) {
1834 DRM_ERROR("Execbuf while VT-switched.\n");
1835 mutex_unlock(&dev->struct_mutex);
1836 return -EBUSY;
1837 }
1838
1839 /* Zero the gloabl flush/invalidate flags. These
1840 * will be modified as each object is bound to the
1841 * gtt
1842 */
1843 dev->invalidate_domains = 0;
1844 dev->flush_domains = 0;
1845
1846 /* Look up object handles and perform the relocations */
1847 for (i = 0; i < args->buffer_count; i++) {
1848 object_list[i] = drm_gem_object_lookup(dev, file_priv,
1849 exec_list[i].handle);
1850 if (object_list[i] == NULL) {
1851 DRM_ERROR("Invalid object handle %d at index %d\n",
1852 exec_list[i].handle, i);
1853 ret = -EBADF;
1854 goto err;
1855 }
1856
1857 object_list[i]->pending_read_domains = 0;
1858 object_list[i]->pending_write_domain = 0;
1859 ret = i915_gem_object_pin_and_relocate(object_list[i],
1860 file_priv,
1861 &exec_list[i]);
1862 if (ret) {
1863 DRM_ERROR("object bind and relocate failed %d\n", ret);
1864 goto err;
1865 }
1866 pinned = i + 1;
1867 }
1868
1869 /* Set the pending read domains for the batch buffer to COMMAND */
1870 batch_obj = object_list[args->buffer_count-1];
1871 batch_obj->pending_read_domains = I915_GEM_DOMAIN_COMMAND;
1872 batch_obj->pending_write_domain = 0;
1873
1874 i915_verify_inactive(dev, __FILE__, __LINE__);
1875
1876 for (i = 0; i < args->buffer_count; i++) {
1877 struct drm_gem_object *obj = object_list[i];
1878
1879 /* make sure all previous memory operations have passed */
1880 ret = i915_gem_object_set_domain(obj,
1881 obj->pending_read_domains,
1882 obj->pending_write_domain);
1883 if (ret)
1884 goto err;
1885 }
1886
1887 i915_verify_inactive(dev, __FILE__, __LINE__);
1888
1889 /* Flush/invalidate caches and chipset buffer */
1890 flush_domains = i915_gem_dev_set_domain(dev);
1891
1892 i915_verify_inactive(dev, __FILE__, __LINE__);
1893
1894 #if WATCH_COHERENCY
1895 for (i = 0; i < args->buffer_count; i++) {
1896 i915_gem_object_check_coherency(object_list[i],
1897 exec_list[i].handle);
1898 }
1899 #endif
1900
1901 exec_offset = exec_list[args->buffer_count - 1].offset;
1902
1903 #if WATCH_EXEC
1904 i915_gem_dump_object(object_list[args->buffer_count - 1],
1905 args->batch_len,
1906 __func__,
1907 ~0);
1908 #endif
1909
1910 (void)i915_add_request(dev, flush_domains);
1911
1912 /* Exec the batchbuffer */
1913 ret = i915_dispatch_gem_execbuffer(dev, args, exec_offset);
1914 if (ret) {
1915 DRM_ERROR("dispatch failed %d\n", ret);
1916 goto err;
1917 }
1918
1919 /*
1920 * Ensure that the commands in the batch buffer are
1921 * finished before the interrupt fires
1922 */
1923 flush_domains = i915_retire_commands(dev);
1924
1925 i915_verify_inactive(dev, __FILE__, __LINE__);
1926
1927 /*
1928 * Get a seqno representing the execution of the current buffer,
1929 * which we can wait on. We would like to mitigate these interrupts,
1930 * likely by only creating seqnos occasionally (so that we have
1931 * *some* interrupts representing completion of buffers that we can
1932 * wait on when trying to clear up gtt space).
1933 */
1934 seqno = i915_add_request(dev, flush_domains);
1935 BUG_ON(seqno == 0);
1936 i915_file_priv->mm.last_gem_seqno = seqno;
1937 for (i = 0; i < args->buffer_count; i++) {
1938 struct drm_gem_object *obj = object_list[i];
1939
1940 i915_gem_object_move_to_active(obj, seqno);
1941 #if WATCH_LRU
1942 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
1943 #endif
1944 }
1945 #if WATCH_LRU
1946 i915_dump_lru(dev, __func__);
1947 #endif
1948
1949 i915_verify_inactive(dev, __FILE__, __LINE__);
1950
1951 /* Copy the new buffer offsets back to the user's exec list. */
1952 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1953 (uintptr_t) args->buffers_ptr,
1954 exec_list,
1955 sizeof(*exec_list) * args->buffer_count);
1956 if (ret)
1957 DRM_ERROR("failed to copy %d exec entries "
1958 "back to user (%d)\n",
1959 args->buffer_count, ret);
1960 err:
1961 if (object_list != NULL) {
1962 for (i = 0; i < pinned; i++)
1963 i915_gem_object_unpin(object_list[i]);
1964
1965 for (i = 0; i < args->buffer_count; i++)
1966 drm_gem_object_unreference(object_list[i]);
1967 }
1968 mutex_unlock(&dev->struct_mutex);
1969
1970 pre_mutex_err:
1971 drm_free(object_list, sizeof(*object_list) * args->buffer_count,
1972 DRM_MEM_DRIVER);
1973 drm_free(exec_list, sizeof(*exec_list) * args->buffer_count,
1974 DRM_MEM_DRIVER);
1975
1976 return ret;
1977 }
1978
1979 int
1980 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
1981 {
1982 struct drm_device *dev = obj->dev;
1983 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1984 int ret;
1985
1986 i915_verify_inactive(dev, __FILE__, __LINE__);
1987 if (obj_priv->gtt_space == NULL) {
1988 ret = i915_gem_object_bind_to_gtt(obj, alignment);
1989 if (ret != 0) {
1990 DRM_ERROR("Failure to bind: %d", ret);
1991 return ret;
1992 }
1993 }
1994 obj_priv->pin_count++;
1995
1996 /* If the object is not active and not pending a flush,
1997 * remove it from the inactive list
1998 */
1999 if (obj_priv->pin_count == 1) {
2000 atomic_inc(&dev->pin_count);
2001 atomic_add(obj->size, &dev->pin_memory);
2002 if (!obj_priv->active &&
2003 (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
2004 I915_GEM_DOMAIN_GTT)) == 0 &&
2005 !list_empty(&obj_priv->list))
2006 list_del_init(&obj_priv->list);
2007 }
2008 i915_verify_inactive(dev, __FILE__, __LINE__);
2009
2010 return 0;
2011 }
2012
2013 void
2014 i915_gem_object_unpin(struct drm_gem_object *obj)
2015 {
2016 struct drm_device *dev = obj->dev;
2017 drm_i915_private_t *dev_priv = dev->dev_private;
2018 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2019
2020 i915_verify_inactive(dev, __FILE__, __LINE__);
2021 obj_priv->pin_count--;
2022 BUG_ON(obj_priv->pin_count < 0);
2023 BUG_ON(obj_priv->gtt_space == NULL);
2024
2025 /* If the object is no longer pinned, and is
2026 * neither active nor being flushed, then stick it on
2027 * the inactive list
2028 */
2029 if (obj_priv->pin_count == 0) {
2030 if (!obj_priv->active &&
2031 (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
2032 I915_GEM_DOMAIN_GTT)) == 0)
2033 list_move_tail(&obj_priv->list,
2034 &dev_priv->mm.inactive_list);
2035 atomic_dec(&dev->pin_count);
2036 atomic_sub(obj->size, &dev->pin_memory);
2037 }
2038 i915_verify_inactive(dev, __FILE__, __LINE__);
2039 }
2040
2041 int
2042 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2043 struct drm_file *file_priv)
2044 {
2045 struct drm_i915_gem_pin *args = data;
2046 struct drm_gem_object *obj;
2047 struct drm_i915_gem_object *obj_priv;
2048 int ret;
2049
2050 mutex_lock(&dev->struct_mutex);
2051
2052 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2053 if (obj == NULL) {
2054 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
2055 args->handle);
2056 mutex_unlock(&dev->struct_mutex);
2057 return -EBADF;
2058 }
2059 obj_priv = obj->driver_private;
2060
2061 ret = i915_gem_object_pin(obj, args->alignment);
2062 if (ret != 0) {
2063 drm_gem_object_unreference(obj);
2064 mutex_unlock(&dev->struct_mutex);
2065 return ret;
2066 }
2067
2068 /* XXX - flush the CPU caches for pinned objects
2069 * as the X server doesn't manage domains yet
2070 */
2071 if (obj->write_domain & I915_GEM_DOMAIN_CPU) {
2072 i915_gem_clflush_object(obj);
2073 drm_agp_chipset_flush(dev);
2074 obj->write_domain = 0;
2075 }
2076 args->offset = obj_priv->gtt_offset;
2077 drm_gem_object_unreference(obj);
2078 mutex_unlock(&dev->struct_mutex);
2079
2080 return 0;
2081 }
2082
2083 int
2084 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2085 struct drm_file *file_priv)
2086 {
2087 struct drm_i915_gem_pin *args = data;
2088 struct drm_gem_object *obj;
2089
2090 mutex_lock(&dev->struct_mutex);
2091
2092 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2093 if (obj == NULL) {
2094 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
2095 args->handle);
2096 mutex_unlock(&dev->struct_mutex);
2097 return -EBADF;
2098 }
2099
2100 i915_gem_object_unpin(obj);
2101
2102 drm_gem_object_unreference(obj);
2103 mutex_unlock(&dev->struct_mutex);
2104 return 0;
2105 }
2106
2107 int
2108 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2109 struct drm_file *file_priv)
2110 {
2111 struct drm_i915_gem_busy *args = data;
2112 struct drm_gem_object *obj;
2113 struct drm_i915_gem_object *obj_priv;
2114
2115 mutex_lock(&dev->struct_mutex);
2116 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2117 if (obj == NULL) {
2118 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
2119 args->handle);
2120 mutex_unlock(&dev->struct_mutex);
2121 return -EBADF;
2122 }
2123
2124 obj_priv = obj->driver_private;
2125 args->busy = obj_priv->active;
2126
2127 drm_gem_object_unreference(obj);
2128 mutex_unlock(&dev->struct_mutex);
2129 return 0;
2130 }
2131
2132 int
2133 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2134 struct drm_file *file_priv)
2135 {
2136 return i915_gem_ring_throttle(dev, file_priv);
2137 }
2138
2139 int i915_gem_init_object(struct drm_gem_object *obj)
2140 {
2141 struct drm_i915_gem_object *obj_priv;
2142
2143 obj_priv = drm_calloc(1, sizeof(*obj_priv), DRM_MEM_DRIVER);
2144 if (obj_priv == NULL)
2145 return -ENOMEM;
2146
2147 /*
2148 * We've just allocated pages from the kernel,
2149 * so they've just been written by the CPU with
2150 * zeros. They'll need to be clflushed before we
2151 * use them with the GPU.
2152 */
2153 obj->write_domain = I915_GEM_DOMAIN_CPU;
2154 obj->read_domains = I915_GEM_DOMAIN_CPU;
2155
2156 obj_priv->agp_type = AGP_USER_MEMORY;
2157
2158 obj->driver_private = obj_priv;
2159 obj_priv->obj = obj;
2160 INIT_LIST_HEAD(&obj_priv->list);
2161 return 0;
2162 }
2163
2164 void i915_gem_free_object(struct drm_gem_object *obj)
2165 {
2166 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2167
2168 while (obj_priv->pin_count > 0)
2169 i915_gem_object_unpin(obj);
2170
2171 i915_gem_object_unbind(obj);
2172
2173 drm_free(obj_priv->page_cpu_valid, 1, DRM_MEM_DRIVER);
2174 drm_free(obj->driver_private, 1, DRM_MEM_DRIVER);
2175 }
2176
2177 static int
2178 i915_gem_set_domain(struct drm_gem_object *obj,
2179 struct drm_file *file_priv,
2180 uint32_t read_domains,
2181 uint32_t write_domain)
2182 {
2183 struct drm_device *dev = obj->dev;
2184 int ret;
2185 uint32_t flush_domains;
2186
2187 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
2188
2189 ret = i915_gem_object_set_domain(obj, read_domains, write_domain);
2190 if (ret)
2191 return ret;
2192 flush_domains = i915_gem_dev_set_domain(obj->dev);
2193
2194 if (flush_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT))
2195 (void) i915_add_request(dev, flush_domains);
2196
2197 return 0;
2198 }
2199
2200 /** Unbinds all objects that are on the given buffer list. */
2201 static int
2202 i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
2203 {
2204 struct drm_gem_object *obj;
2205 struct drm_i915_gem_object *obj_priv;
2206 int ret;
2207
2208 while (!list_empty(head)) {
2209 obj_priv = list_first_entry(head,
2210 struct drm_i915_gem_object,
2211 list);
2212 obj = obj_priv->obj;
2213
2214 if (obj_priv->pin_count != 0) {
2215 DRM_ERROR("Pinned object in unbind list\n");
2216 mutex_unlock(&dev->struct_mutex);
2217 return -EINVAL;
2218 }
2219
2220 ret = i915_gem_object_unbind(obj);
2221 if (ret != 0) {
2222 DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
2223 ret);
2224 mutex_unlock(&dev->struct_mutex);
2225 return ret;
2226 }
2227 }
2228
2229
2230 return 0;
2231 }
2232
2233 static int
2234 i915_gem_idle(struct drm_device *dev)
2235 {
2236 drm_i915_private_t *dev_priv = dev->dev_private;
2237 uint32_t seqno, cur_seqno, last_seqno;
2238 int stuck, ret;
2239
2240 mutex_lock(&dev->struct_mutex);
2241
2242 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
2243 mutex_unlock(&dev->struct_mutex);
2244 return 0;
2245 }
2246
2247 /* Hack! Don't let anybody do execbuf while we don't control the chip.
2248 * We need to replace this with a semaphore, or something.
2249 */
2250 dev_priv->mm.suspended = 1;
2251
2252 /* Cancel the retire work handler, wait for it to finish if running
2253 */
2254 mutex_unlock(&dev->struct_mutex);
2255 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2256 mutex_lock(&dev->struct_mutex);
2257
2258 i915_kernel_lost_context(dev);
2259
2260 /* Flush the GPU along with all non-CPU write domains
2261 */
2262 i915_gem_flush(dev, ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT),
2263 ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
2264 seqno = i915_add_request(dev, ~(I915_GEM_DOMAIN_CPU |
2265 I915_GEM_DOMAIN_GTT));
2266
2267 if (seqno == 0) {
2268 mutex_unlock(&dev->struct_mutex);
2269 return -ENOMEM;
2270 }
2271
2272 dev_priv->mm.waiting_gem_seqno = seqno;
2273 last_seqno = 0;
2274 stuck = 0;
2275 for (;;) {
2276 cur_seqno = i915_get_gem_seqno(dev);
2277 if (i915_seqno_passed(cur_seqno, seqno))
2278 break;
2279 if (last_seqno == cur_seqno) {
2280 if (stuck++ > 100) {
2281 DRM_ERROR("hardware wedged\n");
2282 dev_priv->mm.wedged = 1;
2283 DRM_WAKEUP(&dev_priv->irq_queue);
2284 break;
2285 }
2286 }
2287 msleep(10);
2288 last_seqno = cur_seqno;
2289 }
2290 dev_priv->mm.waiting_gem_seqno = 0;
2291
2292 i915_gem_retire_requests(dev);
2293
2294 if (!dev_priv->mm.wedged) {
2295 /* Active and flushing should now be empty as we've
2296 * waited for a sequence higher than any pending execbuffer
2297 */
2298 WARN_ON(!list_empty(&dev_priv->mm.active_list));
2299 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
2300 /* Request should now be empty as we've also waited
2301 * for the last request in the list
2302 */
2303 WARN_ON(!list_empty(&dev_priv->mm.request_list));
2304 }
2305
2306 /* Empty the active and flushing lists to inactive. If there's
2307 * anything left at this point, it means that we're wedged and
2308 * nothing good's going to happen by leaving them there. So strip
2309 * the GPU domains and just stuff them onto inactive.
2310 */
2311 while (!list_empty(&dev_priv->mm.active_list)) {
2312 struct drm_i915_gem_object *obj_priv;
2313
2314 obj_priv = list_first_entry(&dev_priv->mm.active_list,
2315 struct drm_i915_gem_object,
2316 list);
2317 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
2318 i915_gem_object_move_to_inactive(obj_priv->obj);
2319 }
2320
2321 while (!list_empty(&dev_priv->mm.flushing_list)) {
2322 struct drm_i915_gem_object *obj_priv;
2323
2324 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
2325 struct drm_i915_gem_object,
2326 list);
2327 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
2328 i915_gem_object_move_to_inactive(obj_priv->obj);
2329 }
2330
2331
2332 /* Move all inactive buffers out of the GTT. */
2333 ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
2334 WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
2335 if (ret) {
2336 mutex_unlock(&dev->struct_mutex);
2337 return ret;
2338 }
2339
2340 i915_gem_cleanup_ringbuffer(dev);
2341 mutex_unlock(&dev->struct_mutex);
2342
2343 return 0;
2344 }
2345
2346 static int
2347 i915_gem_init_hws(struct drm_device *dev)
2348 {
2349 drm_i915_private_t *dev_priv = dev->dev_private;
2350 struct drm_gem_object *obj;
2351 struct drm_i915_gem_object *obj_priv;
2352 int ret;
2353
2354 /* If we need a physical address for the status page, it's already
2355 * initialized at driver load time.
2356 */
2357 if (!I915_NEED_GFX_HWS(dev))
2358 return 0;
2359
2360 obj = drm_gem_object_alloc(dev, 4096);
2361 if (obj == NULL) {
2362 DRM_ERROR("Failed to allocate status page\n");
2363 return -ENOMEM;
2364 }
2365 obj_priv = obj->driver_private;
2366 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
2367
2368 ret = i915_gem_object_pin(obj, 4096);
2369 if (ret != 0) {
2370 drm_gem_object_unreference(obj);
2371 return ret;
2372 }
2373
2374 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
2375
2376 dev_priv->hw_status_page = kmap(obj_priv->page_list[0]);
2377 if (dev_priv->hw_status_page == NULL) {
2378 DRM_ERROR("Failed to map status page.\n");
2379 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
2380 drm_gem_object_unreference(obj);
2381 return -EINVAL;
2382 }
2383 dev_priv->hws_obj = obj;
2384 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
2385 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
2386 I915_READ(HWS_PGA); /* posting read */
2387 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
2388
2389 return 0;
2390 }
2391
2392 static int
2393 i915_gem_init_ringbuffer(struct drm_device *dev)
2394 {
2395 drm_i915_private_t *dev_priv = dev->dev_private;
2396 struct drm_gem_object *obj;
2397 struct drm_i915_gem_object *obj_priv;
2398 int ret;
2399 u32 head;
2400
2401 ret = i915_gem_init_hws(dev);
2402 if (ret != 0)
2403 return ret;
2404
2405 obj = drm_gem_object_alloc(dev, 128 * 1024);
2406 if (obj == NULL) {
2407 DRM_ERROR("Failed to allocate ringbuffer\n");
2408 return -ENOMEM;
2409 }
2410 obj_priv = obj->driver_private;
2411
2412 ret = i915_gem_object_pin(obj, 4096);
2413 if (ret != 0) {
2414 drm_gem_object_unreference(obj);
2415 return ret;
2416 }
2417
2418 /* Set up the kernel mapping for the ring. */
2419 dev_priv->ring.Size = obj->size;
2420 dev_priv->ring.tail_mask = obj->size - 1;
2421
2422 dev_priv->ring.map.offset = dev->agp->base + obj_priv->gtt_offset;
2423 dev_priv->ring.map.size = obj->size;
2424 dev_priv->ring.map.type = 0;
2425 dev_priv->ring.map.flags = 0;
2426 dev_priv->ring.map.mtrr = 0;
2427
2428 drm_core_ioremap_wc(&dev_priv->ring.map, dev);
2429 if (dev_priv->ring.map.handle == NULL) {
2430 DRM_ERROR("Failed to map ringbuffer.\n");
2431 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
2432 drm_gem_object_unreference(obj);
2433 return -EINVAL;
2434 }
2435 dev_priv->ring.ring_obj = obj;
2436 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
2437
2438 /* Stop the ring if it's running. */
2439 I915_WRITE(PRB0_CTL, 0);
2440 I915_WRITE(PRB0_TAIL, 0);
2441 I915_WRITE(PRB0_HEAD, 0);
2442
2443 /* Initialize the ring. */
2444 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
2445 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
2446
2447 /* G45 ring initialization fails to reset head to zero */
2448 if (head != 0) {
2449 DRM_ERROR("Ring head not reset to zero "
2450 "ctl %08x head %08x tail %08x start %08x\n",
2451 I915_READ(PRB0_CTL),
2452 I915_READ(PRB0_HEAD),
2453 I915_READ(PRB0_TAIL),
2454 I915_READ(PRB0_START));
2455 I915_WRITE(PRB0_HEAD, 0);
2456
2457 DRM_ERROR("Ring head forced to zero "
2458 "ctl %08x head %08x tail %08x start %08x\n",
2459 I915_READ(PRB0_CTL),
2460 I915_READ(PRB0_HEAD),
2461 I915_READ(PRB0_TAIL),
2462 I915_READ(PRB0_START));
2463 }
2464
2465 I915_WRITE(PRB0_CTL,
2466 ((obj->size - 4096) & RING_NR_PAGES) |
2467 RING_NO_REPORT |
2468 RING_VALID);
2469
2470 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
2471
2472 /* If the head is still not zero, the ring is dead */
2473 if (head != 0) {
2474 DRM_ERROR("Ring initialization failed "
2475 "ctl %08x head %08x tail %08x start %08x\n",
2476 I915_READ(PRB0_CTL),
2477 I915_READ(PRB0_HEAD),
2478 I915_READ(PRB0_TAIL),
2479 I915_READ(PRB0_START));
2480 return -EIO;
2481 }
2482
2483 /* Update our cache of the ring state */
2484 i915_kernel_lost_context(dev);
2485
2486 return 0;
2487 }
2488
2489 static void
2490 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
2491 {
2492 drm_i915_private_t *dev_priv = dev->dev_private;
2493
2494 if (dev_priv->ring.ring_obj == NULL)
2495 return;
2496
2497 drm_core_ioremapfree(&dev_priv->ring.map, dev);
2498
2499 i915_gem_object_unpin(dev_priv->ring.ring_obj);
2500 drm_gem_object_unreference(dev_priv->ring.ring_obj);
2501 dev_priv->ring.ring_obj = NULL;
2502 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
2503
2504 if (dev_priv->hws_obj != NULL) {
2505 struct drm_gem_object *obj = dev_priv->hws_obj;
2506 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2507
2508 kunmap(obj_priv->page_list[0]);
2509 i915_gem_object_unpin(obj);
2510 drm_gem_object_unreference(obj);
2511 dev_priv->hws_obj = NULL;
2512 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
2513 dev_priv->hw_status_page = NULL;
2514
2515 /* Write high address into HWS_PGA when disabling. */
2516 I915_WRITE(HWS_PGA, 0x1ffff000);
2517 }
2518 }
2519
2520 int
2521 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2522 struct drm_file *file_priv)
2523 {
2524 drm_i915_private_t *dev_priv = dev->dev_private;
2525 int ret;
2526
2527 if (dev_priv->mm.wedged) {
2528 DRM_ERROR("Reenabling wedged hardware, good luck\n");
2529 dev_priv->mm.wedged = 0;
2530 }
2531
2532 ret = i915_gem_init_ringbuffer(dev);
2533 if (ret != 0)
2534 return ret;
2535
2536 dev_priv->mm.gtt_mapping = io_mapping_create_wc(dev->agp->base,
2537 dev->agp->agp_info.aper_size
2538 * 1024 * 1024);
2539
2540 mutex_lock(&dev->struct_mutex);
2541 BUG_ON(!list_empty(&dev_priv->mm.active_list));
2542 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2543 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
2544 BUG_ON(!list_empty(&dev_priv->mm.request_list));
2545 dev_priv->mm.suspended = 0;
2546 mutex_unlock(&dev->struct_mutex);
2547
2548 drm_irq_install(dev);
2549
2550 return 0;
2551 }
2552
2553 int
2554 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2555 struct drm_file *file_priv)
2556 {
2557 drm_i915_private_t *dev_priv = dev->dev_private;
2558 int ret;
2559
2560 ret = i915_gem_idle(dev);
2561 drm_irq_uninstall(dev);
2562
2563 io_mapping_free(dev_priv->mm.gtt_mapping);
2564 return ret;
2565 }
2566
2567 void
2568 i915_gem_lastclose(struct drm_device *dev)
2569 {
2570 int ret;
2571
2572 ret = i915_gem_idle(dev);
2573 if (ret)
2574 DRM_ERROR("failed to idle hardware: %d\n", ret);
2575 }
2576
2577 void
2578 i915_gem_load(struct drm_device *dev)
2579 {
2580 drm_i915_private_t *dev_priv = dev->dev_private;
2581
2582 INIT_LIST_HEAD(&dev_priv->mm.active_list);
2583 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
2584 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
2585 INIT_LIST_HEAD(&dev_priv->mm.request_list);
2586 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
2587 i915_gem_retire_work_handler);
2588 dev_priv->mm.next_gem_seqno = 1;
2589
2590 i915_gem_detect_bit_6_swizzle(dev);
2591 }
Support for the Chinese Samsung S3C2440 based development boards