2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/ratelimit.h>
14 #include <linux/kallsyms.h>
15 #include <linux/rcupdate.h>
16 #include <linux/kobject.h>
17 #include <linux/uaccess.h>
18 #include <linux/kdebug.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/string.h>
22 #include <linux/sysdev.h>
23 #include <linux/ctype.h>
24 #include <linux/sched.h>
25 #include <linux/sysfs.h>
26 #include <linux/types.h>
27 #include <linux/init.h>
28 #include <linux/kmod.h>
29 #include <linux/poll.h>
30 #include <linux/cpu.h>
31 #include <linux/smp.h>
34 #include <asm/processor.h>
41 /* Handle unconfigured int18 (should never happen) */
42 static void unexpected_machine_check(struct pt_regs
*regs
, long error_code
)
44 printk(KERN_ERR
"CPU#%d: Unexpected int18 (Machine Check).\n",
48 /* Call the installed machine check handler for this CPU setup. */
49 void (*machine_check_vector
)(struct pt_regs
*, long error_code
) =
50 unexpected_machine_check
;
54 #ifdef CONFIG_X86_NEW_MCE
56 #define MISC_MCELOG_MINOR 227
60 DEFINE_PER_CPU(unsigned, mce_exception_count
);
64 * 0: always panic on uncorrected errors, log corrected errors
65 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
66 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
67 * 3: never panic or SIGBUS, log all errors (for testing only)
69 static int tolerant
= 1;
72 static unsigned long notify_user
;
74 static int mce_bootlog
= -1;
76 static char trigger
[128];
77 static char *trigger_argv
[2] = { trigger
, NULL
};
79 static unsigned long dont_init_banks
;
81 static DECLARE_WAIT_QUEUE_HEAD(mce_wait
);
83 /* MCA banks polled by the period polling timer for corrected events */
84 DEFINE_PER_CPU(mce_banks_t
, mce_poll_banks
) = {
85 [0 ... BITS_TO_LONGS(MAX_NR_BANKS
)-1] = ~0UL
88 static inline int skip_bank_init(int i
)
90 return i
< BITS_PER_LONG
&& test_bit(i
, &dont_init_banks
);
93 /* Do initial initialization of a struct mce */
94 void mce_setup(struct mce
*m
)
96 memset(m
, 0, sizeof(struct mce
));
97 m
->cpu
= smp_processor_id();
101 DEFINE_PER_CPU(struct mce
, injectm
);
102 EXPORT_PER_CPU_SYMBOL_GPL(injectm
);
105 * Lockless MCE logging infrastructure.
106 * This avoids deadlocks on printk locks without having to break locks. Also
107 * separate MCEs from kernel messages to avoid bogus bug reports.
110 static struct mce_log mcelog
= {
115 void mce_log(struct mce
*mce
)
117 unsigned next
, entry
;
122 entry
= rcu_dereference(mcelog
.next
);
125 * When the buffer fills up discard new entries.
126 * Assume that the earlier errors are the more
129 if (entry
>= MCE_LOG_LEN
) {
130 set_bit(MCE_OVERFLOW
,
131 (unsigned long *)&mcelog
.flags
);
134 /* Old left over entry. Skip: */
135 if (mcelog
.entry
[entry
].finished
) {
143 if (cmpxchg(&mcelog
.next
, entry
, next
) == entry
)
146 memcpy(mcelog
.entry
+ entry
, mce
, sizeof(struct mce
));
148 mcelog
.entry
[entry
].finished
= 1;
151 set_bit(0, ¬ify_user
);
154 static void print_mce(struct mce
*m
)
156 printk(KERN_EMERG
"\n"
157 KERN_EMERG
"HARDWARE ERROR\n"
159 "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
160 m
->cpu
, m
->mcgstatus
, m
->bank
, m
->status
);
162 printk(KERN_EMERG
"RIP%s %02x:<%016Lx> ",
163 !(m
->mcgstatus
& MCG_STATUS_EIPV
) ? " !INEXACT!" : "",
165 if (m
->cs
== __KERNEL_CS
)
166 print_symbol("{%s}", m
->ip
);
169 printk(KERN_EMERG
"TSC %llx ", m
->tsc
);
171 printk("ADDR %llx ", m
->addr
);
173 printk("MISC %llx ", m
->misc
);
175 printk(KERN_EMERG
"This is not a software problem!\n");
176 printk(KERN_EMERG
"Run through mcelog --ascii to decode "
177 "and contact your hardware vendor\n");
180 static void mce_panic(char *msg
, struct mce
*backup
, u64 start
)
186 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
187 u64 tsc
= mcelog
.entry
[i
].tsc
;
189 if ((s64
)(tsc
- start
) < 0)
191 print_mce(&mcelog
.entry
[i
]);
192 if (backup
&& mcelog
.entry
[i
].tsc
== backup
->tsc
)
200 /* Support code for software error injection */
202 static int msr_to_offset(u32 msr
)
204 unsigned bank
= __get_cpu_var(injectm
.bank
);
206 return offsetof(struct mce
, ip
);
207 if (msr
== MSR_IA32_MC0_STATUS
+ bank
*4)
208 return offsetof(struct mce
, status
);
209 if (msr
== MSR_IA32_MC0_ADDR
+ bank
*4)
210 return offsetof(struct mce
, addr
);
211 if (msr
== MSR_IA32_MC0_MISC
+ bank
*4)
212 return offsetof(struct mce
, misc
);
213 if (msr
== MSR_IA32_MCG_STATUS
)
214 return offsetof(struct mce
, mcgstatus
);
218 /* MSR access wrappers used for error injection */
219 static u64
mce_rdmsrl(u32 msr
)
222 if (__get_cpu_var(injectm
).finished
) {
223 int offset
= msr_to_offset(msr
);
226 return *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
);
232 static void mce_wrmsrl(u32 msr
, u64 v
)
234 if (__get_cpu_var(injectm
).finished
) {
235 int offset
= msr_to_offset(msr
);
237 *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
) = v
;
243 int mce_available(struct cpuinfo_x86
*c
)
247 return cpu_has(c
, X86_FEATURE_MCE
) && cpu_has(c
, X86_FEATURE_MCA
);
250 static inline void mce_get_rip(struct mce
*m
, struct pt_regs
*regs
)
252 if (regs
&& (m
->mcgstatus
& MCG_STATUS_RIPV
)) {
260 /* Assume the RIP in the MSR is exact. Is this true? */
261 m
->mcgstatus
|= MCG_STATUS_EIPV
;
262 m
->ip
= mce_rdmsrl(rip_msr
);
267 DEFINE_PER_CPU(unsigned, mce_poll_count
);
270 * Poll for corrected events or events that happened before reset.
271 * Those are just logged through /dev/mcelog.
273 * This is executed in standard interrupt context.
275 void machine_check_poll(enum mcp_flags flags
, mce_banks_t
*b
)
280 __get_cpu_var(mce_poll_count
)++;
284 m
.mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
285 for (i
= 0; i
< banks
; i
++) {
286 if (!bank
[i
] || !test_bit(i
, *b
))
295 m
.status
= mce_rdmsrl(MSR_IA32_MC0_STATUS
+ i
*4);
296 if (!(m
.status
& MCI_STATUS_VAL
))
300 * Uncorrected events are handled by the exception handler
301 * when it is enabled. But when the exception is disabled log
304 * TBD do the same check for MCI_STATUS_EN here?
306 if ((m
.status
& MCI_STATUS_UC
) && !(flags
& MCP_UC
))
309 if (m
.status
& MCI_STATUS_MISCV
)
310 m
.misc
= mce_rdmsrl(MSR_IA32_MC0_MISC
+ i
*4);
311 if (m
.status
& MCI_STATUS_ADDRV
)
312 m
.addr
= mce_rdmsrl(MSR_IA32_MC0_ADDR
+ i
*4);
314 if (!(flags
& MCP_TIMESTAMP
))
317 * Don't get the IP here because it's unlikely to
318 * have anything to do with the actual error location.
320 if (!(flags
& MCP_DONTLOG
)) {
322 add_taint(TAINT_MACHINE_CHECK
);
326 * Clear state for this bank.
328 mce_wrmsrl(MSR_IA32_MC0_STATUS
+4*i
, 0);
332 * Don't clear MCG_STATUS here because it's only defined for
338 EXPORT_SYMBOL_GPL(machine_check_poll
);
341 * The actual machine check handler. This only handles real
342 * exceptions when something got corrupted coming in through int 18.
344 * This is executed in NMI context not subject to normal locking rules. This
345 * implies that most kernel services cannot be safely used. Don't even
346 * think about putting a printk in there!
348 void do_machine_check(struct pt_regs
*regs
, long error_code
)
350 struct mce m
, panicm
;
351 int panicm_found
= 0;
355 * If no_way_out gets set, there is no safe way to recover from this
356 * MCE. If tolerant is cranked up, we'll try anyway.
360 * If kill_it gets set, there might be a way to recover from this
364 DECLARE_BITMAP(toclear
, MAX_NR_BANKS
);
366 atomic_inc(&mce_entry
);
368 __get_cpu_var(mce_exception_count
)++;
370 if (notify_die(DIE_NMI
, "machine check", regs
, error_code
,
371 18, SIGKILL
) == NOTIFY_STOP
)
378 m
.mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
380 /* if the restart IP is not valid, we're done for */
381 if (!(m
.mcgstatus
& MCG_STATUS_RIPV
))
387 for (i
= 0; i
< banks
; i
++) {
388 __clear_bit(i
, toclear
);
396 m
.status
= mce_rdmsrl(MSR_IA32_MC0_STATUS
+ i
*4);
397 if ((m
.status
& MCI_STATUS_VAL
) == 0)
401 * Non uncorrected errors are handled by machine_check_poll
404 if ((m
.status
& MCI_STATUS_UC
) == 0)
408 * Set taint even when machine check was not enabled.
410 add_taint(TAINT_MACHINE_CHECK
);
412 __set_bit(i
, toclear
);
414 if (m
.status
& MCI_STATUS_EN
) {
415 /* if PCC was set, there's no way out */
416 no_way_out
|= !!(m
.status
& MCI_STATUS_PCC
);
418 * If this error was uncorrectable and there was
419 * an overflow, we're in trouble. If no overflow,
420 * we might get away with just killing a task.
422 if (m
.status
& MCI_STATUS_UC
) {
423 if (tolerant
< 1 || m
.status
& MCI_STATUS_OVER
)
429 * Machine check event was not enabled. Clear, but
435 if (m
.status
& MCI_STATUS_MISCV
)
436 m
.misc
= mce_rdmsrl(MSR_IA32_MC0_MISC
+ i
*4);
437 if (m
.status
& MCI_STATUS_ADDRV
)
438 m
.addr
= mce_rdmsrl(MSR_IA32_MC0_ADDR
+ i
*4);
440 mce_get_rip(&m
, regs
);
444 * Did this bank cause the exception?
446 * Assume that the bank with uncorrectable errors did it,
447 * and that there is only a single one:
449 if ((m
.status
& MCI_STATUS_UC
) &&
450 (m
.status
& MCI_STATUS_EN
)) {
457 * If we didn't find an uncorrectable error, pick
458 * the last one (shouldn't happen, just being safe).
464 * If we have decided that we just CAN'T continue, and the user
465 * has not set tolerant to an insane level, give up and die.
467 if (no_way_out
&& tolerant
< 3)
468 mce_panic("Machine check", &panicm
, mcestart
);
471 * If the error seems to be unrecoverable, something should be
472 * done. Try to kill as little as possible. If we can kill just
473 * one task, do that. If the user has set the tolerance very
474 * high, don't try to do anything at all.
476 if (kill_it
&& tolerant
< 3) {
480 * If the EIPV bit is set, it means the saved IP is the
481 * instruction which caused the MCE.
483 if (m
.mcgstatus
& MCG_STATUS_EIPV
)
484 user_space
= panicm
.ip
&& (panicm
.cs
& 3);
487 * If we know that the error was in user space, send a
488 * SIGBUS. Otherwise, panic if tolerance is low.
490 * force_sig() takes an awful lot of locks and has a slight
491 * risk of deadlocking.
494 force_sig(SIGBUS
, current
);
495 } else if (panic_on_oops
|| tolerant
< 2) {
496 mce_panic("Uncorrected machine check",
501 /* notify userspace ASAP */
502 set_thread_flag(TIF_MCE_NOTIFY
);
504 /* the last thing we do is clear state */
505 for (i
= 0; i
< banks
; i
++) {
506 if (test_bit(i
, toclear
))
507 mce_wrmsrl(MSR_IA32_MC0_STATUS
+4*i
, 0);
509 mce_wrmsrl(MSR_IA32_MCG_STATUS
, 0);
511 atomic_dec(&mce_entry
);
514 EXPORT_SYMBOL_GPL(do_machine_check
);
516 #ifdef CONFIG_X86_MCE_INTEL
518 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
519 * @cpu: The CPU on which the event occurred.
520 * @status: Event status information
522 * This function should be called by the thermal interrupt after the
523 * event has been processed and the decision was made to log the event
526 * The status parameter will be saved to the 'status' field of 'struct mce'
527 * and historically has been the register value of the
528 * MSR_IA32_THERMAL_STATUS (Intel) msr.
530 void mce_log_therm_throt_event(__u64 status
)
535 m
.bank
= MCE_THERMAL_BANK
;
539 #endif /* CONFIG_X86_MCE_INTEL */
542 * Periodic polling timer for "silent" machine check errors. If the
543 * poller finds an MCE, poll 2x faster. When the poller finds no more
544 * errors, poll 2x slower (up to check_interval seconds).
546 static int check_interval
= 5 * 60; /* 5 minutes */
548 static DEFINE_PER_CPU(int, next_interval
); /* in jiffies */
549 static DEFINE_PER_CPU(struct timer_list
, mce_timer
);
551 static void mcheck_timer(unsigned long data
)
553 struct timer_list
*t
= &per_cpu(mce_timer
, data
);
556 WARN_ON(smp_processor_id() != data
);
558 if (mce_available(¤t_cpu_data
)) {
559 machine_check_poll(MCP_TIMESTAMP
,
560 &__get_cpu_var(mce_poll_banks
));
564 * Alert userspace if needed. If we logged an MCE, reduce the
565 * polling interval, otherwise increase the polling interval.
567 n
= &__get_cpu_var(next_interval
);
568 if (mce_notify_user())
569 *n
= max(*n
/2, HZ
/100);
571 *n
= min(*n
*2, (int)round_jiffies_relative(check_interval
*HZ
));
573 t
->expires
= jiffies
+ *n
;
577 static void mce_do_trigger(struct work_struct
*work
)
579 call_usermodehelper(trigger
, trigger_argv
, NULL
, UMH_NO_WAIT
);
582 static DECLARE_WORK(mce_trigger_work
, mce_do_trigger
);
585 * Notify the user(s) about new machine check events.
586 * Can be called from interrupt context, but not from machine check/NMI
589 int mce_notify_user(void)
591 /* Not more than two messages every minute */
592 static DEFINE_RATELIMIT_STATE(ratelimit
, 60*HZ
, 2);
594 clear_thread_flag(TIF_MCE_NOTIFY
);
596 if (test_and_clear_bit(0, ¬ify_user
)) {
597 wake_up_interruptible(&mce_wait
);
600 * There is no risk of missing notifications because
601 * work_pending is always cleared before the function is
604 if (trigger
[0] && !work_pending(&mce_trigger_work
))
605 schedule_work(&mce_trigger_work
);
607 if (__ratelimit(&ratelimit
))
608 printk(KERN_INFO
"Machine check events logged\n");
614 EXPORT_SYMBOL_GPL(mce_notify_user
);
617 * Initialize Machine Checks for a CPU.
619 static int mce_cap_init(void)
624 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
626 b
= cap
& MCG_BANKCNT_MASK
;
627 printk(KERN_INFO
"mce: CPU supports %d MCE banks\n", b
);
629 if (b
> MAX_NR_BANKS
) {
631 "MCE: Using only %u machine check banks out of %u\n",
636 /* Don't support asymmetric configurations today */
637 WARN_ON(banks
!= 0 && b
!= banks
);
640 bank
= kmalloc(banks
* sizeof(u64
), GFP_KERNEL
);
643 memset(bank
, 0xff, banks
* sizeof(u64
));
646 /* Use accurate RIP reporting if available. */
647 if ((cap
& MCG_EXT_P
) && MCG_EXT_CNT(cap
) >= 9)
648 rip_msr
= MSR_IA32_MCG_EIP
;
653 static void mce_init(void)
655 mce_banks_t all_banks
;
660 * Log the machine checks left over from the previous reset.
662 bitmap_fill(all_banks
, MAX_NR_BANKS
);
663 machine_check_poll(MCP_UC
|(!mce_bootlog
? MCP_DONTLOG
: 0), &all_banks
);
665 set_in_cr4(X86_CR4_MCE
);
667 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
669 wrmsr(MSR_IA32_MCG_CTL
, 0xffffffff, 0xffffffff);
671 for (i
= 0; i
< banks
; i
++) {
672 if (skip_bank_init(i
))
674 wrmsrl(MSR_IA32_MC0_CTL
+4*i
, bank
[i
]);
675 wrmsrl(MSR_IA32_MC0_STATUS
+4*i
, 0);
679 /* Add per CPU specific workarounds here */
680 static void mce_cpu_quirks(struct cpuinfo_x86
*c
)
682 /* This should be disabled by the BIOS, but isn't always */
683 if (c
->x86_vendor
== X86_VENDOR_AMD
) {
684 if (c
->x86
== 15 && banks
> 4) {
686 * disable GART TBL walk error reporting, which
687 * trips off incorrectly with the IOMMU & 3ware
690 clear_bit(10, (unsigned long *)&bank
[4]);
692 if (c
->x86
<= 17 && mce_bootlog
< 0) {
694 * Lots of broken BIOS around that don't clear them
695 * by default and leave crap in there. Don't log:
700 * Various K7s with broken bank 0 around. Always disable
707 if (c
->x86_vendor
== X86_VENDOR_INTEL
) {
709 * SDM documents that on family 6 bank 0 should not be written
710 * because it aliases to another special BIOS controlled
712 * But it's not aliased anymore on model 0x1a+
713 * Don't ignore bank 0 completely because there could be a
714 * valid event later, merely don't write CTL0.
717 if (c
->x86
== 6 && c
->x86_model
< 0x1A)
718 __set_bit(0, &dont_init_banks
);
722 static void __cpuinit
mce_ancient_init(struct cpuinfo_x86
*c
)
726 switch (c
->x86_vendor
) {
727 case X86_VENDOR_INTEL
:
728 if (mce_p5_enabled())
729 intel_p5_mcheck_init(c
);
731 case X86_VENDOR_CENTAUR
:
732 winchip_mcheck_init(c
);
737 static void mce_cpu_features(struct cpuinfo_x86
*c
)
739 switch (c
->x86_vendor
) {
740 case X86_VENDOR_INTEL
:
741 mce_intel_feature_init(c
);
744 mce_amd_feature_init(c
);
751 static void mce_init_timer(void)
753 struct timer_list
*t
= &__get_cpu_var(mce_timer
);
754 int *n
= &__get_cpu_var(next_interval
);
756 *n
= check_interval
* HZ
;
759 setup_timer(t
, mcheck_timer
, smp_processor_id());
760 t
->expires
= round_jiffies(jiffies
+ *n
);
765 * Called for each booted CPU to set up machine checks.
766 * Must be called with preempt off:
768 void __cpuinit
mcheck_init(struct cpuinfo_x86
*c
)
775 if (!mce_available(c
))
778 if (mce_cap_init() < 0) {
784 machine_check_vector
= do_machine_check
;
792 * Character device to read and clear the MCE log.
795 static DEFINE_SPINLOCK(mce_state_lock
);
796 static int open_count
; /* #times opened */
797 static int open_exclu
; /* already open exclusive? */
799 static int mce_open(struct inode
*inode
, struct file
*file
)
801 spin_lock(&mce_state_lock
);
803 if (open_exclu
|| (open_count
&& (file
->f_flags
& O_EXCL
))) {
804 spin_unlock(&mce_state_lock
);
809 if (file
->f_flags
& O_EXCL
)
813 spin_unlock(&mce_state_lock
);
815 return nonseekable_open(inode
, file
);
818 static int mce_release(struct inode
*inode
, struct file
*file
)
820 spin_lock(&mce_state_lock
);
825 spin_unlock(&mce_state_lock
);
830 static void collect_tscs(void *data
)
832 unsigned long *cpu_tsc
= (unsigned long *)data
;
834 rdtscll(cpu_tsc
[smp_processor_id()]);
837 static DEFINE_MUTEX(mce_read_mutex
);
839 static ssize_t
mce_read(struct file
*filp
, char __user
*ubuf
, size_t usize
,
842 char __user
*buf
= ubuf
;
843 unsigned long *cpu_tsc
;
847 cpu_tsc
= kmalloc(nr_cpu_ids
* sizeof(long), GFP_KERNEL
);
851 mutex_lock(&mce_read_mutex
);
852 next
= rcu_dereference(mcelog
.next
);
854 /* Only supports full reads right now */
855 if (*off
!= 0 || usize
< MCE_LOG_LEN
*sizeof(struct mce
)) {
856 mutex_unlock(&mce_read_mutex
);
865 for (i
= prev
; i
< next
; i
++) {
866 unsigned long start
= jiffies
;
868 while (!mcelog
.entry
[i
].finished
) {
869 if (time_after_eq(jiffies
, start
+ 2)) {
870 memset(mcelog
.entry
+ i
, 0,
877 err
|= copy_to_user(buf
, mcelog
.entry
+ i
,
879 buf
+= sizeof(struct mce
);
884 memset(mcelog
.entry
+ prev
, 0,
885 (next
- prev
) * sizeof(struct mce
));
887 next
= cmpxchg(&mcelog
.next
, prev
, 0);
888 } while (next
!= prev
);
893 * Collect entries that were still getting written before the
896 on_each_cpu(collect_tscs
, cpu_tsc
, 1);
898 for (i
= next
; i
< MCE_LOG_LEN
; i
++) {
899 if (mcelog
.entry
[i
].finished
&&
900 mcelog
.entry
[i
].tsc
< cpu_tsc
[mcelog
.entry
[i
].cpu
]) {
901 err
|= copy_to_user(buf
, mcelog
.entry
+i
,
904 buf
+= sizeof(struct mce
);
905 memset(&mcelog
.entry
[i
], 0, sizeof(struct mce
));
908 mutex_unlock(&mce_read_mutex
);
911 return err
? -EFAULT
: buf
- ubuf
;
914 static unsigned int mce_poll(struct file
*file
, poll_table
*wait
)
916 poll_wait(file
, &mce_wait
, wait
);
917 if (rcu_dereference(mcelog
.next
))
918 return POLLIN
| POLLRDNORM
;
922 static long mce_ioctl(struct file
*f
, unsigned int cmd
, unsigned long arg
)
924 int __user
*p
= (int __user
*)arg
;
926 if (!capable(CAP_SYS_ADMIN
))
930 case MCE_GET_RECORD_LEN
:
931 return put_user(sizeof(struct mce
), p
);
932 case MCE_GET_LOG_LEN
:
933 return put_user(MCE_LOG_LEN
, p
);
934 case MCE_GETCLEAR_FLAGS
: {
938 flags
= mcelog
.flags
;
939 } while (cmpxchg(&mcelog
.flags
, flags
, 0) != flags
);
941 return put_user(flags
, p
);
948 /* Modified in mce-inject.c, so not static or const */
949 struct file_operations mce_chrdev_ops
= {
951 .release
= mce_release
,
954 .unlocked_ioctl
= mce_ioctl
,
956 EXPORT_SYMBOL_GPL(mce_chrdev_ops
);
958 static struct miscdevice mce_log_device
= {
965 * mce=off disables machine check
966 * mce=TOLERANCELEVEL (number, see above)
967 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
968 * mce=nobootlog Don't log MCEs from before booting.
970 static int __init
mcheck_enable(char *str
)
976 if (!strcmp(str
, "off"))
978 else if (!strcmp(str
, "bootlog") || !strcmp(str
, "nobootlog"))
979 mce_bootlog
= (str
[0] == 'b');
980 else if (isdigit(str
[0]))
981 get_option(&str
, &tolerant
);
983 printk(KERN_INFO
"mce argument %s ignored. Please use /sys\n",
989 __setup("mce", mcheck_enable
);
996 * Disable machine checks on suspend and shutdown. We can't really handle
999 static int mce_disable(void)
1003 for (i
= 0; i
< banks
; i
++) {
1004 if (!skip_bank_init(i
))
1005 wrmsrl(MSR_IA32_MC0_CTL
+ i
*4, 0);
1010 static int mce_suspend(struct sys_device
*dev
, pm_message_t state
)
1012 return mce_disable();
1015 static int mce_shutdown(struct sys_device
*dev
)
1017 return mce_disable();
1021 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1022 * Only one CPU is active at this time, the others get re-added later using
1025 static int mce_resume(struct sys_device
*dev
)
1028 mce_cpu_features(¤t_cpu_data
);
1033 static void mce_cpu_restart(void *data
)
1035 del_timer_sync(&__get_cpu_var(mce_timer
));
1036 if (mce_available(¤t_cpu_data
))
1041 /* Reinit MCEs after user configuration changes */
1042 static void mce_restart(void)
1044 on_each_cpu(mce_cpu_restart
, NULL
, 1);
1047 static struct sysdev_class mce_sysclass
= {
1048 .suspend
= mce_suspend
,
1049 .shutdown
= mce_shutdown
,
1050 .resume
= mce_resume
,
1051 .name
= "machinecheck",
1054 DEFINE_PER_CPU(struct sys_device
, mce_dev
);
1057 void (*threshold_cpu_callback
)(unsigned long action
, unsigned int cpu
);
1059 static struct sysdev_attribute
*bank_attrs
;
1061 static ssize_t
show_bank(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1064 u64 b
= bank
[attr
- bank_attrs
];
1066 return sprintf(buf
, "%llx\n", b
);
1069 static ssize_t
set_bank(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1070 const char *buf
, size_t size
)
1074 if (strict_strtoull(buf
, 0, &new) < 0)
1077 bank
[attr
- bank_attrs
] = new;
1084 show_trigger(struct sys_device
*s
, struct sysdev_attribute
*attr
, char *buf
)
1086 strcpy(buf
, trigger
);
1088 return strlen(trigger
) + 1;
1091 static ssize_t
set_trigger(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1092 const char *buf
, size_t siz
)
1097 strncpy(trigger
, buf
, sizeof(trigger
));
1098 trigger
[sizeof(trigger
)-1] = 0;
1099 len
= strlen(trigger
);
1100 p
= strchr(trigger
, '\n');
1108 static ssize_t
store_int_with_restart(struct sys_device
*s
,
1109 struct sysdev_attribute
*attr
,
1110 const char *buf
, size_t size
)
1112 ssize_t ret
= sysdev_store_int(s
, attr
, buf
, size
);
1117 static SYSDEV_ATTR(trigger
, 0644, show_trigger
, set_trigger
);
1118 static SYSDEV_INT_ATTR(tolerant
, 0644, tolerant
);
1120 static struct sysdev_ext_attribute attr_check_interval
= {
1121 _SYSDEV_ATTR(check_interval
, 0644, sysdev_show_int
,
1122 store_int_with_restart
),
1126 static struct sysdev_attribute
*mce_attrs
[] = {
1127 &attr_tolerant
.attr
, &attr_check_interval
.attr
, &attr_trigger
,
1131 static cpumask_var_t mce_dev_initialized
;
1133 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1134 static __cpuinit
int mce_create_device(unsigned int cpu
)
1139 if (!mce_available(&boot_cpu_data
))
1142 memset(&per_cpu(mce_dev
, cpu
).kobj
, 0, sizeof(struct kobject
));
1143 per_cpu(mce_dev
, cpu
).id
= cpu
;
1144 per_cpu(mce_dev
, cpu
).cls
= &mce_sysclass
;
1146 err
= sysdev_register(&per_cpu(mce_dev
, cpu
));
1150 for (i
= 0; mce_attrs
[i
]; i
++) {
1151 err
= sysdev_create_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
1155 for (i
= 0; i
< banks
; i
++) {
1156 err
= sysdev_create_file(&per_cpu(mce_dev
, cpu
),
1161 cpumask_set_cpu(cpu
, mce_dev_initialized
);
1166 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), &bank_attrs
[i
]);
1169 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
1171 sysdev_unregister(&per_cpu(mce_dev
, cpu
));
1176 static __cpuinit
void mce_remove_device(unsigned int cpu
)
1180 if (!cpumask_test_cpu(cpu
, mce_dev_initialized
))
1183 for (i
= 0; mce_attrs
[i
]; i
++)
1184 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
1186 for (i
= 0; i
< banks
; i
++)
1187 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), &bank_attrs
[i
]);
1189 sysdev_unregister(&per_cpu(mce_dev
, cpu
));
1190 cpumask_clear_cpu(cpu
, mce_dev_initialized
);
1193 /* Make sure there are no machine checks on offlined CPUs. */
1194 static void mce_disable_cpu(void *h
)
1196 unsigned long action
= *(unsigned long *)h
;
1199 if (!mce_available(¤t_cpu_data
))
1201 if (!(action
& CPU_TASKS_FROZEN
))
1203 for (i
= 0; i
< banks
; i
++) {
1204 if (!skip_bank_init(i
))
1205 wrmsrl(MSR_IA32_MC0_CTL
+ i
*4, 0);
1209 static void mce_reenable_cpu(void *h
)
1211 unsigned long action
= *(unsigned long *)h
;
1214 if (!mce_available(¤t_cpu_data
))
1217 if (!(action
& CPU_TASKS_FROZEN
))
1219 for (i
= 0; i
< banks
; i
++) {
1220 if (!skip_bank_init(i
))
1221 wrmsrl(MSR_IA32_MC0_CTL
+ i
*4, bank
[i
]);
1225 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
1226 static int __cpuinit
1227 mce_cpu_callback(struct notifier_block
*nfb
, unsigned long action
, void *hcpu
)
1229 unsigned int cpu
= (unsigned long)hcpu
;
1230 struct timer_list
*t
= &per_cpu(mce_timer
, cpu
);
1234 case CPU_ONLINE_FROZEN
:
1235 mce_create_device(cpu
);
1236 if (threshold_cpu_callback
)
1237 threshold_cpu_callback(action
, cpu
);
1240 case CPU_DEAD_FROZEN
:
1241 if (threshold_cpu_callback
)
1242 threshold_cpu_callback(action
, cpu
);
1243 mce_remove_device(cpu
);
1245 case CPU_DOWN_PREPARE
:
1246 case CPU_DOWN_PREPARE_FROZEN
:
1248 smp_call_function_single(cpu
, mce_disable_cpu
, &action
, 1);
1250 case CPU_DOWN_FAILED
:
1251 case CPU_DOWN_FAILED_FROZEN
:
1252 t
->expires
= round_jiffies(jiffies
+
1253 __get_cpu_var(next_interval
));
1254 add_timer_on(t
, cpu
);
1255 smp_call_function_single(cpu
, mce_reenable_cpu
, &action
, 1);
1258 /* intentionally ignoring frozen here */
1259 cmci_rediscover(cpu
);
1265 static struct notifier_block mce_cpu_notifier __cpuinitdata
= {
1266 .notifier_call
= mce_cpu_callback
,
1269 static __init
int mce_init_banks(void)
1273 bank_attrs
= kzalloc(sizeof(struct sysdev_attribute
) * banks
,
1278 for (i
= 0; i
< banks
; i
++) {
1279 struct sysdev_attribute
*a
= &bank_attrs
[i
];
1281 a
->attr
.name
= kasprintf(GFP_KERNEL
, "bank%d", i
);
1285 a
->attr
.mode
= 0644;
1286 a
->show
= show_bank
;
1287 a
->store
= set_bank
;
1293 kfree(bank_attrs
[i
].attr
.name
);
1300 static __init
int mce_init_device(void)
1305 if (!mce_available(&boot_cpu_data
))
1308 alloc_cpumask_var(&mce_dev_initialized
, GFP_KERNEL
);
1310 err
= mce_init_banks();
1314 err
= sysdev_class_register(&mce_sysclass
);
1318 for_each_online_cpu(i
) {
1319 err
= mce_create_device(i
);
1324 register_hotcpu_notifier(&mce_cpu_notifier
);
1325 misc_register(&mce_log_device
);
1330 device_initcall(mce_init_device
);
1332 #else /* CONFIG_X86_OLD_MCE: */
1335 EXPORT_SYMBOL_GPL(nr_mce_banks
); /* non-fatal.o */
1337 /* This has to be run for each processor */
1338 void mcheck_init(struct cpuinfo_x86
*c
)
1340 if (mce_disabled
== 1)
1343 switch (c
->x86_vendor
) {
1344 case X86_VENDOR_AMD
:
1348 case X86_VENDOR_INTEL
:
1350 intel_p5_mcheck_init(c
);
1352 intel_p6_mcheck_init(c
);
1354 intel_p4_mcheck_init(c
);
1357 case X86_VENDOR_CENTAUR
:
1359 winchip_mcheck_init(c
);
1365 printk(KERN_INFO
"mce: CPU supports %d MCE banks\n", nr_mce_banks
);
1368 static int __init
mcheck_enable(char *str
)
1374 __setup("mce", mcheck_enable
);
1376 #endif /* CONFIG_X86_OLD_MCE */
1379 * Old style boot options parsing. Only for compatibility.
1381 static int __init
mcheck_disable(char *str
)
1386 __setup("nomce", mcheck_disable
);