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drm/radeon/kms: fix legacy crtc2 dpms
[linux-2.6/mini2440.git] / drivers / gpu / drm / radeon / radeon_legacy_crtc.c
blobff9c18d07925d79c7c9e6004b8154db7fae1c35d
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include "radeon_fixed.h"
30 #include "radeon.h"
31
32 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
33 struct drm_display_mode *mode,
34 struct drm_display_mode *adjusted_mode)
35 {
36 struct drm_device *dev = crtc->dev;
37 struct radeon_device *rdev = dev->dev_private;
38 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
39 int xres = mode->hdisplay;
40 int yres = mode->vdisplay;
41 bool hscale = true, vscale = true;
42 int hsync_wid;
43 int vsync_wid;
44 int hsync_start;
45 int blank_width;
46 u32 scale, inc, crtc_more_cntl;
47 u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
48 u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
49 u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
50 struct radeon_native_mode *native_mode = &radeon_crtc->native_mode;
51
52 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
53 (RADEON_VERT_STRETCH_RESERVED |
54 RADEON_VERT_AUTO_RATIO_INC);
55 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
56 (RADEON_HORZ_FP_LOOP_STRETCH |
57 RADEON_HORZ_AUTO_RATIO_INC);
58
59 crtc_more_cntl = 0;
60 if ((rdev->family == CHIP_RS100) ||
61 (rdev->family == CHIP_RS200)) {
62 /* This is to workaround the asic bug for RMX, some versions
63 of BIOS dosen't have this register initialized correctly. */
64 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
65 }
66
67
68 fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
69 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
70
71 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
72 if (!hsync_wid)
73 hsync_wid = 1;
74 hsync_start = mode->crtc_hsync_start - 8;
75
76 fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
77 | ((hsync_wid & 0x3f) << 16)
78 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
79 ? RADEON_CRTC_H_SYNC_POL
80 : 0));
81
82 fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
83 | ((mode->crtc_vdisplay - 1) << 16));
84
85 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
86 if (!vsync_wid)
87 vsync_wid = 1;
88
89 fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
90 | ((vsync_wid & 0x1f) << 16)
91 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
92 ? RADEON_CRTC_V_SYNC_POL
93 : 0));
94
95 fp_horz_vert_active = 0;
96
97 if (native_mode->panel_xres == 0 ||
98 native_mode->panel_yres == 0) {
99 hscale = false;
100 vscale = false;
101 } else {
102 if (xres > native_mode->panel_xres)
103 xres = native_mode->panel_xres;
104 if (yres > native_mode->panel_yres)
105 yres = native_mode->panel_yres;
106
107 if (xres == native_mode->panel_xres)
108 hscale = false;
109 if (yres == native_mode->panel_yres)
110 vscale = false;
111 }
112
113 switch (radeon_crtc->rmx_type) {
114 case RMX_FULL:
115 case RMX_ASPECT:
116 if (!hscale)
117 fp_horz_stretch |= ((xres/8-1) << 16);
118 else {
119 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
120 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
121 / native_mode->panel_xres + 1;
122 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
123 RADEON_HORZ_STRETCH_BLEND |
124 RADEON_HORZ_STRETCH_ENABLE |
125 ((native_mode->panel_xres/8-1) << 16));
126 }
127
128 if (!vscale)
129 fp_vert_stretch |= ((yres-1) << 12);
130 else {
131 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
132 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
133 / native_mode->panel_yres + 1;
134 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
135 RADEON_VERT_STRETCH_ENABLE |
136 RADEON_VERT_STRETCH_BLEND |
137 ((native_mode->panel_yres-1) << 12));
138 }
139 break;
140 case RMX_CENTER:
141 fp_horz_stretch |= ((xres/8-1) << 16);
142 fp_vert_stretch |= ((yres-1) << 12);
143
144 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
145 RADEON_CRTC_AUTO_VERT_CENTER_EN);
146
147 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
148 if (blank_width > 110)
149 blank_width = 110;
150
151 fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
152 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
153
154 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
155 if (!hsync_wid)
156 hsync_wid = 1;
157
158 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
159 | ((hsync_wid & 0x3f) << 16)
160 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
161 ? RADEON_CRTC_H_SYNC_POL
162 : 0));
163
164 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
165 | ((mode->crtc_vdisplay - 1) << 16));
166
167 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
168 if (!vsync_wid)
169 vsync_wid = 1;
170
171 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
172 | ((vsync_wid & 0x1f) << 16)
173 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
174 ? RADEON_CRTC_V_SYNC_POL
175 : 0)));
176
177 fp_horz_vert_active = (((native_mode->panel_yres) & 0xfff) |
178 (((native_mode->panel_xres / 8) & 0x1ff) << 16));
179 break;
180 case RMX_OFF:
181 default:
182 fp_horz_stretch |= ((xres/8-1) << 16);
183 fp_vert_stretch |= ((yres-1) << 12);
184 break;
185 }
186
187 WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch);
188 WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch);
189 WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl);
190 WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active);
191 WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid);
192 WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid);
193 WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
194 WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
195 }
196
197 void radeon_restore_common_regs(struct drm_device *dev)
198 {
199 /* don't need this yet */
200 }
201
202 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
203 {
204 struct radeon_device *rdev = dev->dev_private;
205 int i = 0;
206
207 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
208 the cause yet, but this workaround will mask the problem for now.
209 Other chips usually will pass at the very first test, so the
210 workaround shouldn't have any effect on them. */
211 for (i = 0;
212 (i < 10000 &&
213 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
214 i++);
215 }
216
217 static void radeon_pll_write_update(struct drm_device *dev)
218 {
219 struct radeon_device *rdev = dev->dev_private;
220
221 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
222
223 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
224 RADEON_PPLL_ATOMIC_UPDATE_W,
225 ~(RADEON_PPLL_ATOMIC_UPDATE_W));
226 }
227
228 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
229 {
230 struct radeon_device *rdev = dev->dev_private;
231 int i = 0;
232
233
234 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
235 the cause yet, but this workaround will mask the problem for now.
236 Other chips usually will pass at the very first test, so the
237 workaround shouldn't have any effect on them. */
238 for (i = 0;
239 (i < 10000 &&
240 RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
241 i++);
242 }
243
244 static void radeon_pll2_write_update(struct drm_device *dev)
245 {
246 struct radeon_device *rdev = dev->dev_private;
247
248 while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
249
250 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
251 RADEON_P2PLL_ATOMIC_UPDATE_W,
252 ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
253 }
254
255 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
256 uint16_t fb_div)
257 {
258 unsigned int vcoFreq;
259
260 if (!ref_div)
261 return 1;
262
263 vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div;
264
265 /*
266 * This is horribly crude: the VCO frequency range is divided into
267 * 3 parts, each part having a fixed PLL gain value.
268 */
269 if (vcoFreq >= 30000)
270 /*
271 * [300..max] MHz : 7
272 */
273 return 7;
274 else if (vcoFreq >= 18000)
275 /*
276 * [180..300) MHz : 4
277 */
278 return 4;
279 else
280 /*
281 * [0..180) MHz : 1
282 */
283 return 1;
284 }
285
286 void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
287 {
288 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
289 struct drm_device *dev = crtc->dev;
290 struct radeon_device *rdev = dev->dev_private;
291 uint32_t mask;
292
293 if (radeon_crtc->crtc_id)
294 mask = (RADEON_CRTC2_DISP_DIS |
295 RADEON_CRTC2_VSYNC_DIS |
296 RADEON_CRTC2_HSYNC_DIS |
297 RADEON_CRTC2_DISP_REQ_EN_B);
298 else
299 mask = (RADEON_CRTC_DISPLAY_DIS |
300 RADEON_CRTC_VSYNC_DIS |
301 RADEON_CRTC_HSYNC_DIS);
302
303 switch (mode) {
304 case DRM_MODE_DPMS_ON:
305 if (radeon_crtc->crtc_id)
306 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
307 else {
308 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
309 RADEON_CRTC_DISP_REQ_EN_B));
310 WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
311 }
312 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
313 radeon_crtc_load_lut(crtc);
314 break;
315 case DRM_MODE_DPMS_STANDBY:
316 case DRM_MODE_DPMS_SUSPEND:
317 case DRM_MODE_DPMS_OFF:
318 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
319 if (radeon_crtc->crtc_id)
320 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
321 else {
322 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
323 RADEON_CRTC_DISP_REQ_EN_B));
324 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
325 }
326 break;
327 }
328 }
329
330 /* properly set crtc bpp when using atombios */
331 void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)
332 {
333 struct drm_device *dev = crtc->dev;
334 struct radeon_device *rdev = dev->dev_private;
335 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
336 int format;
337 uint32_t crtc_gen_cntl;
338 uint32_t disp_merge_cntl;
339 uint32_t crtc_pitch;
340
341 switch (crtc->fb->bits_per_pixel) {
342 case 15: /* 555 */
343 format = 3;
344 break;
345 case 16: /* 565 */
346 format = 4;
347 break;
348 case 24: /* RGB */
349 format = 5;
350 break;
351 case 32: /* xRGB */
352 format = 6;
353 break;
354 default:
355 return;
356 }
357
358 crtc_pitch = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
359 ((crtc->fb->bits_per_pixel * 8) - 1)) /
360 (crtc->fb->bits_per_pixel * 8));
361 crtc_pitch |= crtc_pitch << 16;
362
363 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
364
365 switch (radeon_crtc->crtc_id) {
366 case 0:
367 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
368 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
369 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
370
371 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff;
372 crtc_gen_cntl |= (format << 8);
373 crtc_gen_cntl |= RADEON_CRTC_EXT_DISP_EN;
374 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
375 break;
376 case 1:
377 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
378 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
379 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
380
381 crtc_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff;
382 crtc_gen_cntl |= (format << 8);
383 WREG32(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl);
384 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
385 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
386 break;
387 }
388 }
389
390 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
391 struct drm_framebuffer *old_fb)
392 {
393 struct drm_device *dev = crtc->dev;
394 struct radeon_device *rdev = dev->dev_private;
395 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
396 struct radeon_framebuffer *radeon_fb;
397 struct drm_gem_object *obj;
398 uint64_t base;
399 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
400 uint32_t crtc_pitch, pitch_pixels;
401 uint32_t tiling_flags;
402
403 DRM_DEBUG("\n");
404
405 radeon_fb = to_radeon_framebuffer(crtc->fb);
406
407 obj = radeon_fb->obj;
408 if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) {
409 return -EINVAL;
410 }
411 /* if scanout was in GTT this really wouldn't work */
412 /* crtc offset is from display base addr not FB location */
413 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location;
414
415 base -= radeon_crtc->legacy_display_base_addr;
416
417 crtc_offset_cntl = 0;
418
419 pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
420 crtc_pitch = (((pitch_pixels * crtc->fb->bits_per_pixel) +
421 ((crtc->fb->bits_per_pixel * 8) - 1)) /
422 (crtc->fb->bits_per_pixel * 8));
423 crtc_pitch |= crtc_pitch << 16;
424
425 radeon_object_get_tiling_flags(obj->driver_private,
426 &tiling_flags, NULL);
427 if (tiling_flags & RADEON_TILING_MICRO)
428 DRM_ERROR("trying to scanout microtiled buffer\n");
429
430 if (tiling_flags & RADEON_TILING_MACRO) {
431 if (ASIC_IS_R300(rdev))
432 crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
433 R300_CRTC_MICRO_TILE_BUFFER_DIS |
434 R300_CRTC_MACRO_TILE_EN);
435 else
436 crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
437 } else {
438 if (ASIC_IS_R300(rdev))
439 crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
440 R300_CRTC_MICRO_TILE_BUFFER_DIS |
441 R300_CRTC_MACRO_TILE_EN);
442 else
443 crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
444 }
445
446 if (tiling_flags & RADEON_TILING_MACRO) {
447 if (ASIC_IS_R300(rdev)) {
448 crtc_tile_x0_y0 = x | (y << 16);
449 base &= ~0x7ff;
450 } else {
451 int byteshift = crtc->fb->bits_per_pixel >> 4;
452 int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11;
453 base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
454 crtc_offset_cntl |= (y % 16);
455 }
456 } else {
457 int offset = y * pitch_pixels + x;
458 switch (crtc->fb->bits_per_pixel) {
459 case 15:
460 case 16:
461 offset *= 2;
462 break;
463 case 24:
464 offset *= 3;
465 break;
466 case 32:
467 offset *= 4;
468 break;
469 default:
470 return false;
471 }
472 base += offset;
473 }
474
475 base &= ~7;
476
477 crtc_offset = (u32)base;
478
479 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
480
481 if (ASIC_IS_R300(rdev)) {
482 if (radeon_crtc->crtc_id)
483 WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
484 else
485 WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
486 }
487 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
488 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
489 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
490
491 if (old_fb && old_fb != crtc->fb) {
492 radeon_fb = to_radeon_framebuffer(old_fb);
493 radeon_gem_object_unpin(radeon_fb->obj);
494 }
495 return 0;
496 }
497
498 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
499 {
500 struct drm_device *dev = crtc->dev;
501 struct radeon_device *rdev = dev->dev_private;
502 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
503 int format;
504 int hsync_start;
505 int hsync_wid;
506 int vsync_wid;
507 uint32_t crtc_h_total_disp;
508 uint32_t crtc_h_sync_strt_wid;
509 uint32_t crtc_v_total_disp;
510 uint32_t crtc_v_sync_strt_wid;
511
512 DRM_DEBUG("\n");
513
514 switch (crtc->fb->bits_per_pixel) {
515 case 15: /* 555 */
516 format = 3;
517 break;
518 case 16: /* 565 */
519 format = 4;
520 break;
521 case 24: /* RGB */
522 format = 5;
523 break;
524 case 32: /* xRGB */
525 format = 6;
526 break;
527 default:
528 return false;
529 }
530
531 crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
532 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
533
534 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
535 if (!hsync_wid)
536 hsync_wid = 1;
537 hsync_start = mode->crtc_hsync_start - 8;
538
539 crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
540 | ((hsync_wid & 0x3f) << 16)
541 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
542 ? RADEON_CRTC_H_SYNC_POL
543 : 0));
544
545 /* This works for double scan mode. */
546 crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
547 | ((mode->crtc_vdisplay - 1) << 16));
548
549 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
550 if (!vsync_wid)
551 vsync_wid = 1;
552
553 crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
554 | ((vsync_wid & 0x1f) << 16)
555 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
556 ? RADEON_CRTC_V_SYNC_POL
557 : 0));
558
559 /* TODO -> Dell Server */
560 if (0) {
561 uint32_t disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
562 uint32_t tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
563 uint32_t dac2_cntl = RREG32(RADEON_DAC_CNTL2);
564 uint32_t crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
565
566 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
567 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
568
569 /* For CRT on DAC2, don't turn it on if BIOS didn't
570 enable it, even it's detected.
571 */
572 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
573 tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
574 tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
575
576 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
577 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
578 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
579 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
580 }
581
582 if (radeon_crtc->crtc_id) {
583 uint32_t crtc2_gen_cntl;
584 uint32_t disp2_merge_cntl;
585
586 /* check to see if TV DAC is enabled for another crtc and keep it enabled */
587 if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_CRT2_ON)
588 crtc2_gen_cntl = RADEON_CRTC2_CRT2_ON;
589 else
590 crtc2_gen_cntl = 0;
591
592 crtc2_gen_cntl |= ((format << 8)
593 | RADEON_CRTC2_VSYNC_DIS
594 | RADEON_CRTC2_HSYNC_DIS
595 | RADEON_CRTC2_DISP_DIS
596 | RADEON_CRTC2_DISP_REQ_EN_B
597 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
598 ? RADEON_CRTC2_DBL_SCAN_EN
599 : 0)
600 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
601 ? RADEON_CRTC2_CSYNC_EN
602 : 0)
603 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
604 ? RADEON_CRTC2_INTERLACE_EN
605 : 0));
606
607 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
608 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
609
610 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
611 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
612 } else {
613 uint32_t crtc_gen_cntl;
614 uint32_t crtc_ext_cntl;
615 uint32_t disp_merge_cntl;
616
617 crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN
618 | (format << 8)
619 | RADEON_CRTC_DISP_REQ_EN_B
620 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
621 ? RADEON_CRTC_DBL_SCAN_EN
622 : 0)
623 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
624 ? RADEON_CRTC_CSYNC_EN
625 : 0)
626 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
627 ? RADEON_CRTC_INTERLACE_EN
628 : 0));
629
630 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
631 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
632 RADEON_CRTC_VSYNC_DIS |
633 RADEON_CRTC_HSYNC_DIS |
634 RADEON_CRTC_DISPLAY_DIS);
635
636 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
637 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
638
639 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
640 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
641 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
642 }
643
644 WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
645 WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
646 WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
647 WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
648
649 return true;
650 }
651
652 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
653 {
654 struct drm_device *dev = crtc->dev;
655 struct radeon_device *rdev = dev->dev_private;
656 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
657 struct drm_encoder *encoder;
658 uint32_t feedback_div = 0;
659 uint32_t frac_fb_div = 0;
660 uint32_t reference_div = 0;
661 uint32_t post_divider = 0;
662 uint32_t freq = 0;
663 uint8_t pll_gain;
664 int pll_flags = RADEON_PLL_LEGACY;
665 bool use_bios_divs = false;
666 /* PLL registers */
667 uint32_t pll_ref_div = 0;
668 uint32_t pll_fb_post_div = 0;
669 uint32_t htotal_cntl = 0;
670
671 struct radeon_pll *pll;
672
673 struct {
674 int divider;
675 int bitvalue;
676 } *post_div, post_divs[] = {
677 /* From RAGE 128 VR/RAGE 128 GL Register
678 * Reference Manual (Technical Reference
679 * Manual P/N RRG-G04100-C Rev. 0.04), page
680 * 3-17 (PLL_DIV_[3:0]).
681 */
682 { 1, 0 }, /* VCLK_SRC */
683 { 2, 1 }, /* VCLK_SRC/2 */
684 { 4, 2 }, /* VCLK_SRC/4 */
685 { 8, 3 }, /* VCLK_SRC/8 */
686 { 3, 4 }, /* VCLK_SRC/3 */
687 { 16, 5 }, /* VCLK_SRC/16 */
688 { 6, 6 }, /* VCLK_SRC/6 */
689 { 12, 7 }, /* VCLK_SRC/12 */
690 { 0, 0 }
691 };
692
693 if (radeon_crtc->crtc_id)
694 pll = &rdev->clock.p2pll;
695 else
696 pll = &rdev->clock.p1pll;
697
698 if (mode->clock > 200000) /* range limits??? */
699 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
700 else
701 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
702
703 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
704 if (encoder->crtc == crtc) {
705 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
706 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
707 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
708 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
709 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
710 if (lvds) {
711 if (lvds->use_bios_dividers) {
712 pll_ref_div = lvds->panel_ref_divider;
713 pll_fb_post_div = (lvds->panel_fb_divider |
714 (lvds->panel_post_divider << 16));
715 htotal_cntl = 0;
716 use_bios_divs = true;
717 }
718 }
719 pll_flags |= RADEON_PLL_USE_REF_DIV;
720 }
721 }
722 }
723
724 DRM_DEBUG("\n");
725
726 if (!use_bios_divs) {
727 radeon_compute_pll(pll, mode->clock,
728 &freq, &feedback_div, &frac_fb_div,
729 &reference_div, &post_divider,
730 pll_flags);
731
732 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
733 if (post_div->divider == post_divider)
734 break;
735 }
736
737 if (!post_div->divider)
738 post_div = &post_divs[0];
739
740 DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
741 (unsigned)freq,
742 feedback_div,
743 reference_div,
744 post_divider);
745
746 pll_ref_div = reference_div;
747 #if defined(__powerpc__) && (0) /* TODO */
748 /* apparently programming this otherwise causes a hang??? */
749 if (info->MacModel == RADEON_MAC_IBOOK)
750 pll_fb_post_div = 0x000600ad;
751 else
752 #endif
753 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16));
754
755 htotal_cntl = mode->htotal & 0x7;
756
757 }
758
759 pll_gain = radeon_compute_pll_gain(pll->reference_freq,
760 pll_ref_div & 0x3ff,
761 pll_fb_post_div & 0x7ff);
762
763 if (radeon_crtc->crtc_id) {
764 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
765 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
766 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
767
768 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
769 RADEON_PIX2CLK_SRC_SEL_CPUCLK,
770 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
771
772 WREG32_PLL_P(RADEON_P2PLL_CNTL,
773 RADEON_P2PLL_RESET
774 | RADEON_P2PLL_ATOMIC_UPDATE_EN
775 | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
776 ~(RADEON_P2PLL_RESET
777 | RADEON_P2PLL_ATOMIC_UPDATE_EN
778 | RADEON_P2PLL_PVG_MASK));
779
780 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
781 pll_ref_div,
782 ~RADEON_P2PLL_REF_DIV_MASK);
783
784 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
785 pll_fb_post_div,
786 ~RADEON_P2PLL_FB0_DIV_MASK);
787
788 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
789 pll_fb_post_div,
790 ~RADEON_P2PLL_POST0_DIV_MASK);
791
792 radeon_pll2_write_update(dev);
793 radeon_pll2_wait_for_read_update_complete(dev);
794
795 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
796
797 WREG32_PLL_P(RADEON_P2PLL_CNTL,
798 0,
799 ~(RADEON_P2PLL_RESET
800 | RADEON_P2PLL_SLEEP
801 | RADEON_P2PLL_ATOMIC_UPDATE_EN));
802
803 DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
804 (unsigned)pll_ref_div,
805 (unsigned)pll_fb_post_div,
806 (unsigned)htotal_cntl,
807 RREG32_PLL(RADEON_P2PLL_CNTL));
808 DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n",
809 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
810 (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
811 (unsigned)((pll_fb_post_div &
812 RADEON_P2PLL_POST0_DIV_MASK) >> 16));
813
814 mdelay(50); /* Let the clock to lock */
815
816 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
817 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
818 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
819
820 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
821 } else {
822 if (rdev->flags & RADEON_IS_MOBILITY) {
823 /* A temporal workaround for the occational blanking on certain laptop panels.
824 This appears to related to the PLL divider registers (fail to lock?).
825 It occurs even when all dividers are the same with their old settings.
826 In this case we really don't need to fiddle with PLL registers.
827 By doing this we can avoid the blanking problem with some panels.
828 */
829 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
830 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
831 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
832 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
833 RADEON_PLL_DIV_SEL,
834 ~(RADEON_PLL_DIV_SEL));
835 r100_pll_errata_after_index(rdev);
836 return;
837 }
838 }
839
840 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
841 RADEON_VCLK_SRC_SEL_CPUCLK,
842 ~(RADEON_VCLK_SRC_SEL_MASK));
843 WREG32_PLL_P(RADEON_PPLL_CNTL,
844 RADEON_PPLL_RESET
845 | RADEON_PPLL_ATOMIC_UPDATE_EN
846 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
847 | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
848 ~(RADEON_PPLL_RESET
849 | RADEON_PPLL_ATOMIC_UPDATE_EN
850 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
851 | RADEON_PPLL_PVG_MASK));
852
853 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
854 RADEON_PLL_DIV_SEL,
855 ~(RADEON_PLL_DIV_SEL));
856 r100_pll_errata_after_index(rdev);
857
858 if (ASIC_IS_R300(rdev) ||
859 (rdev->family == CHIP_RS300) ||
860 (rdev->family == CHIP_RS400) ||
861 (rdev->family == CHIP_RS480)) {
862 if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
863 /* When restoring console mode, use saved PPLL_REF_DIV
864 * setting.
865 */
866 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
867 pll_ref_div,
868 0);
869 } else {
870 /* R300 uses ref_div_acc field as real ref divider */
871 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
872 (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
873 ~R300_PPLL_REF_DIV_ACC_MASK);
874 }
875 } else
876 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
877 pll_ref_div,
878 ~RADEON_PPLL_REF_DIV_MASK);
879
880 WREG32_PLL_P(RADEON_PPLL_DIV_3,
881 pll_fb_post_div,
882 ~RADEON_PPLL_FB3_DIV_MASK);
883
884 WREG32_PLL_P(RADEON_PPLL_DIV_3,
885 pll_fb_post_div,
886 ~RADEON_PPLL_POST3_DIV_MASK);
887
888 radeon_pll_write_update(dev);
889 radeon_pll_wait_for_read_update_complete(dev);
890
891 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
892
893 WREG32_PLL_P(RADEON_PPLL_CNTL,
894 0,
895 ~(RADEON_PPLL_RESET
896 | RADEON_PPLL_SLEEP
897 | RADEON_PPLL_ATOMIC_UPDATE_EN
898 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
899
900 DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
901 pll_ref_div,
902 pll_fb_post_div,
903 (unsigned)htotal_cntl,
904 RREG32_PLL(RADEON_PPLL_CNTL));
905 DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n",
906 pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
907 pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
908 (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
909
910 mdelay(50); /* Let the clock to lock */
911
912 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
913 RADEON_VCLK_SRC_SEL_PPLLCLK,
914 ~(RADEON_VCLK_SRC_SEL_MASK));
915
916 }
917 }
918
919 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
920 struct drm_display_mode *mode,
921 struct drm_display_mode *adjusted_mode)
922 {
923 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
924 return false;
925 return true;
926 }
927
928 static int radeon_crtc_mode_set(struct drm_crtc *crtc,
929 struct drm_display_mode *mode,
930 struct drm_display_mode *adjusted_mode,
931 int x, int y, struct drm_framebuffer *old_fb)
932 {
933 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
934 struct drm_device *dev = crtc->dev;
935 struct radeon_device *rdev = dev->dev_private;
936
937 /* TODO TV */
938 radeon_crtc_set_base(crtc, x, y, old_fb);
939 radeon_set_crtc_timing(crtc, adjusted_mode);
940 radeon_set_pll(crtc, adjusted_mode);
941 radeon_bandwidth_update(rdev);
942 if (radeon_crtc->crtc_id == 0) {
943 radeon_legacy_rmx_mode_set(crtc, mode, adjusted_mode);
944 } else {
945 if (radeon_crtc->rmx_type != RMX_OFF) {
946 /* FIXME: only first crtc has rmx what should we
947 * do ?
948 */
949 DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
950 }
951 }
952 return 0;
953 }
954
955 static void radeon_crtc_prepare(struct drm_crtc *crtc)
956 {
957 radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
958 }
959
960 static void radeon_crtc_commit(struct drm_crtc *crtc)
961 {
962 radeon_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
963 }
964
965 static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
966 .dpms = radeon_crtc_dpms,
967 .mode_fixup = radeon_crtc_mode_fixup,
968 .mode_set = radeon_crtc_mode_set,
969 .mode_set_base = radeon_crtc_set_base,
970 .prepare = radeon_crtc_prepare,
971 .commit = radeon_crtc_commit,
972 };
973
974
975 void radeon_legacy_init_crtc(struct drm_device *dev,
976 struct radeon_crtc *radeon_crtc)
977 {
978 if (radeon_crtc->crtc_id == 1)
979 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
980 drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
981 }
Support for the Chinese Samsung S3C2440 based development boards