2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/ratelimit.h>
14 #include <linux/kallsyms.h>
15 #include <linux/rcupdate.h>
16 #include <linux/kobject.h>
17 #include <linux/uaccess.h>
18 #include <linux/kdebug.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/string.h>
22 #include <linux/sysdev.h>
23 #include <linux/ctype.h>
24 #include <linux/sched.h>
25 #include <linux/sysfs.h>
26 #include <linux/types.h>
27 #include <linux/init.h>
28 #include <linux/kmod.h>
29 #include <linux/poll.h>
30 #include <linux/cpu.h>
31 #include <linux/smp.h>
34 #include <asm/processor.h>
39 #include "mce-internal.h"
42 /* Handle unconfigured int18 (should never happen) */
43 static void unexpected_machine_check(struct pt_regs
*regs
, long error_code
)
45 printk(KERN_ERR
"CPU#%d: Unexpected int18 (Machine Check).\n",
49 /* Call the installed machine check handler for this CPU setup. */
50 void (*machine_check_vector
)(struct pt_regs
*, long error_code
) =
51 unexpected_machine_check
;
55 #ifdef CONFIG_X86_NEW_MCE
57 #define MISC_MCELOG_MINOR 227
61 DEFINE_PER_CPU(unsigned, mce_exception_count
);
65 * 0: always panic on uncorrected errors, log corrected errors
66 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
67 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
68 * 3: never panic or SIGBUS, log all errors (for testing only)
70 static int tolerant
= 1;
73 static unsigned long notify_user
;
75 static int mce_bootlog
= -1;
77 static char trigger
[128];
78 static char *trigger_argv
[2] = { trigger
, NULL
};
80 static unsigned long dont_init_banks
;
82 static DECLARE_WAIT_QUEUE_HEAD(mce_wait
);
84 /* MCA banks polled by the period polling timer for corrected events */
85 DEFINE_PER_CPU(mce_banks_t
, mce_poll_banks
) = {
86 [0 ... BITS_TO_LONGS(MAX_NR_BANKS
)-1] = ~0UL
89 static inline int skip_bank_init(int i
)
91 return i
< BITS_PER_LONG
&& test_bit(i
, &dont_init_banks
);
94 /* Do initial initialization of a struct mce */
95 void mce_setup(struct mce
*m
)
97 memset(m
, 0, sizeof(struct mce
));
98 m
->cpu
= m
->extcpu
= smp_processor_id();
100 /* We hope get_seconds stays lockless */
101 m
->time
= get_seconds();
102 m
->cpuvendor
= boot_cpu_data
.x86_vendor
;
103 m
->cpuid
= cpuid_eax(1);
105 m
->socketid
= cpu_data(m
->extcpu
).phys_proc_id
;
107 m
->apicid
= cpu_data(m
->extcpu
).initial_apicid
;
108 rdmsrl(MSR_IA32_MCG_CAP
, m
->mcgcap
);
111 DEFINE_PER_CPU(struct mce
, injectm
);
112 EXPORT_PER_CPU_SYMBOL_GPL(injectm
);
115 * Lockless MCE logging infrastructure.
116 * This avoids deadlocks on printk locks without having to break locks. Also
117 * separate MCEs from kernel messages to avoid bogus bug reports.
120 static struct mce_log mcelog
= {
121 .signature
= MCE_LOG_SIGNATURE
,
123 .recordlen
= sizeof(struct mce
),
126 void mce_log(struct mce
*mce
)
128 unsigned next
, entry
;
133 entry
= rcu_dereference(mcelog
.next
);
136 * When the buffer fills up discard new entries.
137 * Assume that the earlier errors are the more
140 if (entry
>= MCE_LOG_LEN
) {
141 set_bit(MCE_OVERFLOW
,
142 (unsigned long *)&mcelog
.flags
);
145 /* Old left over entry. Skip: */
146 if (mcelog
.entry
[entry
].finished
) {
154 if (cmpxchg(&mcelog
.next
, entry
, next
) == entry
)
157 memcpy(mcelog
.entry
+ entry
, mce
, sizeof(struct mce
));
159 mcelog
.entry
[entry
].finished
= 1;
163 set_bit(0, ¬ify_user
);
166 static void print_mce(struct mce
*m
)
168 printk(KERN_EMERG
"\n"
169 KERN_EMERG
"HARDWARE ERROR\n"
171 "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
172 m
->extcpu
, m
->mcgstatus
, m
->bank
, m
->status
);
174 printk(KERN_EMERG
"RIP%s %02x:<%016Lx> ",
175 !(m
->mcgstatus
& MCG_STATUS_EIPV
) ? " !INEXACT!" : "",
177 if (m
->cs
== __KERNEL_CS
)
178 print_symbol("{%s}", m
->ip
);
181 printk(KERN_EMERG
"TSC %llx ", m
->tsc
);
183 printk("ADDR %llx ", m
->addr
);
185 printk("MISC %llx ", m
->misc
);
187 printk(KERN_EMERG
"PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
188 m
->cpuvendor
, m
->cpuid
, m
->time
, m
->socketid
,
190 printk(KERN_EMERG
"This is not a software problem!\n");
191 printk(KERN_EMERG
"Run through mcelog --ascii to decode "
192 "and contact your hardware vendor\n");
195 static void mce_panic(char *msg
, struct mce
*final
, char *exp
)
201 /* First print corrected ones that are still unlogged */
202 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
203 struct mce
*m
= &mcelog
.entry
[i
];
204 if ((m
->status
& MCI_STATUS_VAL
) &&
205 !(m
->status
& MCI_STATUS_UC
))
208 /* Now print uncorrected but with the final one last */
209 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
210 struct mce
*m
= &mcelog
.entry
[i
];
211 if (!(m
->status
& MCI_STATUS_VAL
))
213 if (!final
|| memcmp(m
, final
, sizeof(struct mce
)))
219 printk(KERN_EMERG
"Machine check: %s\n", exp
);
223 /* Support code for software error injection */
225 static int msr_to_offset(u32 msr
)
227 unsigned bank
= __get_cpu_var(injectm
.bank
);
229 return offsetof(struct mce
, ip
);
230 if (msr
== MSR_IA32_MC0_STATUS
+ bank
*4)
231 return offsetof(struct mce
, status
);
232 if (msr
== MSR_IA32_MC0_ADDR
+ bank
*4)
233 return offsetof(struct mce
, addr
);
234 if (msr
== MSR_IA32_MC0_MISC
+ bank
*4)
235 return offsetof(struct mce
, misc
);
236 if (msr
== MSR_IA32_MCG_STATUS
)
237 return offsetof(struct mce
, mcgstatus
);
241 /* MSR access wrappers used for error injection */
242 static u64
mce_rdmsrl(u32 msr
)
245 if (__get_cpu_var(injectm
).finished
) {
246 int offset
= msr_to_offset(msr
);
249 return *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
);
255 static void mce_wrmsrl(u32 msr
, u64 v
)
257 if (__get_cpu_var(injectm
).finished
) {
258 int offset
= msr_to_offset(msr
);
260 *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
) = v
;
266 int mce_available(struct cpuinfo_x86
*c
)
270 return cpu_has(c
, X86_FEATURE_MCE
) && cpu_has(c
, X86_FEATURE_MCA
);
273 static inline void mce_get_rip(struct mce
*m
, struct pt_regs
*regs
)
275 if (regs
&& (m
->mcgstatus
& MCG_STATUS_RIPV
)) {
283 /* Assume the RIP in the MSR is exact. Is this true? */
284 m
->mcgstatus
|= MCG_STATUS_EIPV
;
285 m
->ip
= mce_rdmsrl(rip_msr
);
290 DEFINE_PER_CPU(unsigned, mce_poll_count
);
293 * Poll for corrected events or events that happened before reset.
294 * Those are just logged through /dev/mcelog.
296 * This is executed in standard interrupt context.
298 void machine_check_poll(enum mcp_flags flags
, mce_banks_t
*b
)
303 __get_cpu_var(mce_poll_count
)++;
307 m
.mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
308 for (i
= 0; i
< banks
; i
++) {
309 if (!bank
[i
] || !test_bit(i
, *b
))
318 m
.status
= mce_rdmsrl(MSR_IA32_MC0_STATUS
+ i
*4);
319 if (!(m
.status
& MCI_STATUS_VAL
))
323 * Uncorrected events are handled by the exception handler
324 * when it is enabled. But when the exception is disabled log
327 * TBD do the same check for MCI_STATUS_EN here?
329 if ((m
.status
& MCI_STATUS_UC
) && !(flags
& MCP_UC
))
332 if (m
.status
& MCI_STATUS_MISCV
)
333 m
.misc
= mce_rdmsrl(MSR_IA32_MC0_MISC
+ i
*4);
334 if (m
.status
& MCI_STATUS_ADDRV
)
335 m
.addr
= mce_rdmsrl(MSR_IA32_MC0_ADDR
+ i
*4);
337 if (!(flags
& MCP_TIMESTAMP
))
340 * Don't get the IP here because it's unlikely to
341 * have anything to do with the actual error location.
343 if (!(flags
& MCP_DONTLOG
)) {
345 add_taint(TAINT_MACHINE_CHECK
);
349 * Clear state for this bank.
351 mce_wrmsrl(MSR_IA32_MC0_STATUS
+4*i
, 0);
355 * Don't clear MCG_STATUS here because it's only defined for
361 EXPORT_SYMBOL_GPL(machine_check_poll
);
364 * Do a quick check if any of the events requires a panic.
365 * This decides if we keep the events around or clear them.
367 static int mce_no_way_out(struct mce
*m
, char **msg
)
371 for (i
= 0; i
< banks
; i
++) {
372 m
->status
= mce_rdmsrl(MSR_IA32_MC0_STATUS
+ i
*4);
373 if (mce_severity(m
, tolerant
, msg
) >= MCE_PANIC_SEVERITY
)
380 * The actual machine check handler. This only handles real
381 * exceptions when something got corrupted coming in through int 18.
383 * This is executed in NMI context not subject to normal locking rules. This
384 * implies that most kernel services cannot be safely used. Don't even
385 * think about putting a printk in there!
387 void do_machine_check(struct pt_regs
*regs
, long error_code
)
389 struct mce m
, panicm
;
390 int panicm_found
= 0;
393 * If no_way_out gets set, there is no safe way to recover from this
394 * MCE. If tolerant is cranked up, we'll try anyway.
398 * If kill_it gets set, there might be a way to recover from this
402 DECLARE_BITMAP(toclear
, MAX_NR_BANKS
);
403 char *msg
= "Unknown";
405 atomic_inc(&mce_entry
);
407 __get_cpu_var(mce_exception_count
)++;
409 if (notify_die(DIE_NMI
, "machine check", regs
, error_code
,
410 18, SIGKILL
) == NOTIFY_STOP
)
417 m
.mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
418 no_way_out
= mce_no_way_out(&m
, &msg
);
422 for (i
= 0; i
< banks
; i
++) {
423 __clear_bit(i
, toclear
);
431 m
.status
= mce_rdmsrl(MSR_IA32_MC0_STATUS
+ i
*4);
432 if ((m
.status
& MCI_STATUS_VAL
) == 0)
436 * Non uncorrected errors are handled by machine_check_poll
437 * Leave them alone, unless this panics.
439 if ((m
.status
& MCI_STATUS_UC
) == 0 && !no_way_out
)
443 * Set taint even when machine check was not enabled.
445 add_taint(TAINT_MACHINE_CHECK
);
447 __set_bit(i
, toclear
);
449 if (m
.status
& MCI_STATUS_EN
) {
451 * If this error was uncorrectable and there was
452 * an overflow, we're in trouble. If no overflow,
453 * we might get away with just killing a task.
455 if (m
.status
& MCI_STATUS_UC
)
459 * Machine check event was not enabled. Clear, but
465 if (m
.status
& MCI_STATUS_MISCV
)
466 m
.misc
= mce_rdmsrl(MSR_IA32_MC0_MISC
+ i
*4);
467 if (m
.status
& MCI_STATUS_ADDRV
)
468 m
.addr
= mce_rdmsrl(MSR_IA32_MC0_ADDR
+ i
*4);
470 mce_get_rip(&m
, regs
);
474 * Did this bank cause the exception?
476 * Assume that the bank with uncorrectable errors did it,
477 * and that there is only a single one:
479 if ((m
.status
& MCI_STATUS_UC
) &&
480 (m
.status
& MCI_STATUS_EN
)) {
487 * If we didn't find an uncorrectable error, pick
488 * the last one (shouldn't happen, just being safe).
494 * If we have decided that we just CAN'T continue, and the user
495 * has not set tolerant to an insane level, give up and die.
497 if (no_way_out
&& tolerant
< 3)
498 mce_panic("Machine check", &panicm
, msg
);
501 * If the error seems to be unrecoverable, something should be
502 * done. Try to kill as little as possible. If we can kill just
503 * one task, do that. If the user has set the tolerance very
504 * high, don't try to do anything at all.
506 if (kill_it
&& tolerant
< 3) {
510 * If the EIPV bit is set, it means the saved IP is the
511 * instruction which caused the MCE.
513 if (m
.mcgstatus
& MCG_STATUS_EIPV
)
514 user_space
= panicm
.ip
&& (panicm
.cs
& 3);
517 * If we know that the error was in user space, send a
518 * SIGBUS. Otherwise, panic if tolerance is low.
520 * force_sig() takes an awful lot of locks and has a slight
521 * risk of deadlocking.
524 force_sig(SIGBUS
, current
);
525 } else if (panic_on_oops
|| tolerant
< 2) {
526 mce_panic("Uncorrected machine check", &panicm
, msg
);
530 /* notify userspace ASAP */
531 set_thread_flag(TIF_MCE_NOTIFY
);
533 /* the last thing we do is clear state */
534 for (i
= 0; i
< banks
; i
++) {
535 if (test_bit(i
, toclear
))
536 mce_wrmsrl(MSR_IA32_MC0_STATUS
+4*i
, 0);
538 mce_wrmsrl(MSR_IA32_MCG_STATUS
, 0);
540 atomic_dec(&mce_entry
);
543 EXPORT_SYMBOL_GPL(do_machine_check
);
545 #ifdef CONFIG_X86_MCE_INTEL
547 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
548 * @cpu: The CPU on which the event occurred.
549 * @status: Event status information
551 * This function should be called by the thermal interrupt after the
552 * event has been processed and the decision was made to log the event
555 * The status parameter will be saved to the 'status' field of 'struct mce'
556 * and historically has been the register value of the
557 * MSR_IA32_THERMAL_STATUS (Intel) msr.
559 void mce_log_therm_throt_event(__u64 status
)
564 m
.bank
= MCE_THERMAL_BANK
;
568 #endif /* CONFIG_X86_MCE_INTEL */
571 * Periodic polling timer for "silent" machine check errors. If the
572 * poller finds an MCE, poll 2x faster. When the poller finds no more
573 * errors, poll 2x slower (up to check_interval seconds).
575 static int check_interval
= 5 * 60; /* 5 minutes */
577 static DEFINE_PER_CPU(int, next_interval
); /* in jiffies */
578 static DEFINE_PER_CPU(struct timer_list
, mce_timer
);
580 static void mcheck_timer(unsigned long data
)
582 struct timer_list
*t
= &per_cpu(mce_timer
, data
);
585 WARN_ON(smp_processor_id() != data
);
587 if (mce_available(¤t_cpu_data
)) {
588 machine_check_poll(MCP_TIMESTAMP
,
589 &__get_cpu_var(mce_poll_banks
));
593 * Alert userspace if needed. If we logged an MCE, reduce the
594 * polling interval, otherwise increase the polling interval.
596 n
= &__get_cpu_var(next_interval
);
597 if (mce_notify_user())
598 *n
= max(*n
/2, HZ
/100);
600 *n
= min(*n
*2, (int)round_jiffies_relative(check_interval
*HZ
));
602 t
->expires
= jiffies
+ *n
;
606 static void mce_do_trigger(struct work_struct
*work
)
608 call_usermodehelper(trigger
, trigger_argv
, NULL
, UMH_NO_WAIT
);
611 static DECLARE_WORK(mce_trigger_work
, mce_do_trigger
);
614 * Notify the user(s) about new machine check events.
615 * Can be called from interrupt context, but not from machine check/NMI
618 int mce_notify_user(void)
620 /* Not more than two messages every minute */
621 static DEFINE_RATELIMIT_STATE(ratelimit
, 60*HZ
, 2);
623 clear_thread_flag(TIF_MCE_NOTIFY
);
625 if (test_and_clear_bit(0, ¬ify_user
)) {
626 wake_up_interruptible(&mce_wait
);
629 * There is no risk of missing notifications because
630 * work_pending is always cleared before the function is
633 if (trigger
[0] && !work_pending(&mce_trigger_work
))
634 schedule_work(&mce_trigger_work
);
636 if (__ratelimit(&ratelimit
))
637 printk(KERN_INFO
"Machine check events logged\n");
643 EXPORT_SYMBOL_GPL(mce_notify_user
);
646 * Initialize Machine Checks for a CPU.
648 static int mce_cap_init(void)
653 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
655 b
= cap
& MCG_BANKCNT_MASK
;
656 printk(KERN_INFO
"mce: CPU supports %d MCE banks\n", b
);
658 if (b
> MAX_NR_BANKS
) {
660 "MCE: Using only %u machine check banks out of %u\n",
665 /* Don't support asymmetric configurations today */
666 WARN_ON(banks
!= 0 && b
!= banks
);
669 bank
= kmalloc(banks
* sizeof(u64
), GFP_KERNEL
);
672 memset(bank
, 0xff, banks
* sizeof(u64
));
675 /* Use accurate RIP reporting if available. */
676 if ((cap
& MCG_EXT_P
) && MCG_EXT_CNT(cap
) >= 9)
677 rip_msr
= MSR_IA32_MCG_EIP
;
682 static void mce_init(void)
684 mce_banks_t all_banks
;
689 * Log the machine checks left over from the previous reset.
691 bitmap_fill(all_banks
, MAX_NR_BANKS
);
692 machine_check_poll(MCP_UC
|(!mce_bootlog
? MCP_DONTLOG
: 0), &all_banks
);
694 set_in_cr4(X86_CR4_MCE
);
696 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
698 wrmsr(MSR_IA32_MCG_CTL
, 0xffffffff, 0xffffffff);
700 for (i
= 0; i
< banks
; i
++) {
701 if (skip_bank_init(i
))
703 wrmsrl(MSR_IA32_MC0_CTL
+4*i
, bank
[i
]);
704 wrmsrl(MSR_IA32_MC0_STATUS
+4*i
, 0);
708 /* Add per CPU specific workarounds here */
709 static void mce_cpu_quirks(struct cpuinfo_x86
*c
)
711 /* This should be disabled by the BIOS, but isn't always */
712 if (c
->x86_vendor
== X86_VENDOR_AMD
) {
713 if (c
->x86
== 15 && banks
> 4) {
715 * disable GART TBL walk error reporting, which
716 * trips off incorrectly with the IOMMU & 3ware
719 clear_bit(10, (unsigned long *)&bank
[4]);
721 if (c
->x86
<= 17 && mce_bootlog
< 0) {
723 * Lots of broken BIOS around that don't clear them
724 * by default and leave crap in there. Don't log:
729 * Various K7s with broken bank 0 around. Always disable
736 if (c
->x86_vendor
== X86_VENDOR_INTEL
) {
738 * SDM documents that on family 6 bank 0 should not be written
739 * because it aliases to another special BIOS controlled
741 * But it's not aliased anymore on model 0x1a+
742 * Don't ignore bank 0 completely because there could be a
743 * valid event later, merely don't write CTL0.
746 if (c
->x86
== 6 && c
->x86_model
< 0x1A)
747 __set_bit(0, &dont_init_banks
);
751 static void __cpuinit
mce_ancient_init(struct cpuinfo_x86
*c
)
755 switch (c
->x86_vendor
) {
756 case X86_VENDOR_INTEL
:
757 if (mce_p5_enabled())
758 intel_p5_mcheck_init(c
);
760 case X86_VENDOR_CENTAUR
:
761 winchip_mcheck_init(c
);
766 static void mce_cpu_features(struct cpuinfo_x86
*c
)
768 switch (c
->x86_vendor
) {
769 case X86_VENDOR_INTEL
:
770 mce_intel_feature_init(c
);
773 mce_amd_feature_init(c
);
780 static void mce_init_timer(void)
782 struct timer_list
*t
= &__get_cpu_var(mce_timer
);
783 int *n
= &__get_cpu_var(next_interval
);
785 *n
= check_interval
* HZ
;
788 setup_timer(t
, mcheck_timer
, smp_processor_id());
789 t
->expires
= round_jiffies(jiffies
+ *n
);
794 * Called for each booted CPU to set up machine checks.
795 * Must be called with preempt off:
797 void __cpuinit
mcheck_init(struct cpuinfo_x86
*c
)
804 if (!mce_available(c
))
807 if (mce_cap_init() < 0) {
813 machine_check_vector
= do_machine_check
;
821 * Character device to read and clear the MCE log.
824 static DEFINE_SPINLOCK(mce_state_lock
);
825 static int open_count
; /* #times opened */
826 static int open_exclu
; /* already open exclusive? */
828 static int mce_open(struct inode
*inode
, struct file
*file
)
830 spin_lock(&mce_state_lock
);
832 if (open_exclu
|| (open_count
&& (file
->f_flags
& O_EXCL
))) {
833 spin_unlock(&mce_state_lock
);
838 if (file
->f_flags
& O_EXCL
)
842 spin_unlock(&mce_state_lock
);
844 return nonseekable_open(inode
, file
);
847 static int mce_release(struct inode
*inode
, struct file
*file
)
849 spin_lock(&mce_state_lock
);
854 spin_unlock(&mce_state_lock
);
859 static void collect_tscs(void *data
)
861 unsigned long *cpu_tsc
= (unsigned long *)data
;
863 rdtscll(cpu_tsc
[smp_processor_id()]);
866 static DEFINE_MUTEX(mce_read_mutex
);
868 static ssize_t
mce_read(struct file
*filp
, char __user
*ubuf
, size_t usize
,
871 char __user
*buf
= ubuf
;
872 unsigned long *cpu_tsc
;
876 cpu_tsc
= kmalloc(nr_cpu_ids
* sizeof(long), GFP_KERNEL
);
880 mutex_lock(&mce_read_mutex
);
881 next
= rcu_dereference(mcelog
.next
);
883 /* Only supports full reads right now */
884 if (*off
!= 0 || usize
< MCE_LOG_LEN
*sizeof(struct mce
)) {
885 mutex_unlock(&mce_read_mutex
);
894 for (i
= prev
; i
< next
; i
++) {
895 unsigned long start
= jiffies
;
897 while (!mcelog
.entry
[i
].finished
) {
898 if (time_after_eq(jiffies
, start
+ 2)) {
899 memset(mcelog
.entry
+ i
, 0,
906 err
|= copy_to_user(buf
, mcelog
.entry
+ i
,
908 buf
+= sizeof(struct mce
);
913 memset(mcelog
.entry
+ prev
, 0,
914 (next
- prev
) * sizeof(struct mce
));
916 next
= cmpxchg(&mcelog
.next
, prev
, 0);
917 } while (next
!= prev
);
922 * Collect entries that were still getting written before the
925 on_each_cpu(collect_tscs
, cpu_tsc
, 1);
927 for (i
= next
; i
< MCE_LOG_LEN
; i
++) {
928 if (mcelog
.entry
[i
].finished
&&
929 mcelog
.entry
[i
].tsc
< cpu_tsc
[mcelog
.entry
[i
].cpu
]) {
930 err
|= copy_to_user(buf
, mcelog
.entry
+i
,
933 buf
+= sizeof(struct mce
);
934 memset(&mcelog
.entry
[i
], 0, sizeof(struct mce
));
937 mutex_unlock(&mce_read_mutex
);
940 return err
? -EFAULT
: buf
- ubuf
;
943 static unsigned int mce_poll(struct file
*file
, poll_table
*wait
)
945 poll_wait(file
, &mce_wait
, wait
);
946 if (rcu_dereference(mcelog
.next
))
947 return POLLIN
| POLLRDNORM
;
951 static long mce_ioctl(struct file
*f
, unsigned int cmd
, unsigned long arg
)
953 int __user
*p
= (int __user
*)arg
;
955 if (!capable(CAP_SYS_ADMIN
))
959 case MCE_GET_RECORD_LEN
:
960 return put_user(sizeof(struct mce
), p
);
961 case MCE_GET_LOG_LEN
:
962 return put_user(MCE_LOG_LEN
, p
);
963 case MCE_GETCLEAR_FLAGS
: {
967 flags
= mcelog
.flags
;
968 } while (cmpxchg(&mcelog
.flags
, flags
, 0) != flags
);
970 return put_user(flags
, p
);
977 /* Modified in mce-inject.c, so not static or const */
978 struct file_operations mce_chrdev_ops
= {
980 .release
= mce_release
,
983 .unlocked_ioctl
= mce_ioctl
,
985 EXPORT_SYMBOL_GPL(mce_chrdev_ops
);
987 static struct miscdevice mce_log_device
= {
994 * mce=off disables machine check
995 * mce=TOLERANCELEVEL (number, see above)
996 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
997 * mce=nobootlog Don't log MCEs from before booting.
999 static int __init
mcheck_enable(char *str
)
1005 if (!strcmp(str
, "off"))
1007 else if (!strcmp(str
, "bootlog") || !strcmp(str
, "nobootlog"))
1008 mce_bootlog
= (str
[0] == 'b');
1009 else if (isdigit(str
[0]))
1010 get_option(&str
, &tolerant
);
1012 printk(KERN_INFO
"mce argument %s ignored. Please use /sys\n",
1018 __setup("mce", mcheck_enable
);
1025 * Disable machine checks on suspend and shutdown. We can't really handle
1028 static int mce_disable(void)
1032 for (i
= 0; i
< banks
; i
++) {
1033 if (!skip_bank_init(i
))
1034 wrmsrl(MSR_IA32_MC0_CTL
+ i
*4, 0);
1039 static int mce_suspend(struct sys_device
*dev
, pm_message_t state
)
1041 return mce_disable();
1044 static int mce_shutdown(struct sys_device
*dev
)
1046 return mce_disable();
1050 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1051 * Only one CPU is active at this time, the others get re-added later using
1054 static int mce_resume(struct sys_device
*dev
)
1057 mce_cpu_features(¤t_cpu_data
);
1062 static void mce_cpu_restart(void *data
)
1064 del_timer_sync(&__get_cpu_var(mce_timer
));
1065 if (mce_available(¤t_cpu_data
))
1070 /* Reinit MCEs after user configuration changes */
1071 static void mce_restart(void)
1073 on_each_cpu(mce_cpu_restart
, NULL
, 1);
1076 static struct sysdev_class mce_sysclass
= {
1077 .suspend
= mce_suspend
,
1078 .shutdown
= mce_shutdown
,
1079 .resume
= mce_resume
,
1080 .name
= "machinecheck",
1083 DEFINE_PER_CPU(struct sys_device
, mce_dev
);
1086 void (*threshold_cpu_callback
)(unsigned long action
, unsigned int cpu
);
1088 static struct sysdev_attribute
*bank_attrs
;
1090 static ssize_t
show_bank(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1093 u64 b
= bank
[attr
- bank_attrs
];
1095 return sprintf(buf
, "%llx\n", b
);
1098 static ssize_t
set_bank(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1099 const char *buf
, size_t size
)
1103 if (strict_strtoull(buf
, 0, &new) < 0)
1106 bank
[attr
- bank_attrs
] = new;
1113 show_trigger(struct sys_device
*s
, struct sysdev_attribute
*attr
, char *buf
)
1115 strcpy(buf
, trigger
);
1117 return strlen(trigger
) + 1;
1120 static ssize_t
set_trigger(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1121 const char *buf
, size_t siz
)
1126 strncpy(trigger
, buf
, sizeof(trigger
));
1127 trigger
[sizeof(trigger
)-1] = 0;
1128 len
= strlen(trigger
);
1129 p
= strchr(trigger
, '\n');
1137 static ssize_t
store_int_with_restart(struct sys_device
*s
,
1138 struct sysdev_attribute
*attr
,
1139 const char *buf
, size_t size
)
1141 ssize_t ret
= sysdev_store_int(s
, attr
, buf
, size
);
1146 static SYSDEV_ATTR(trigger
, 0644, show_trigger
, set_trigger
);
1147 static SYSDEV_INT_ATTR(tolerant
, 0644, tolerant
);
1149 static struct sysdev_ext_attribute attr_check_interval
= {
1150 _SYSDEV_ATTR(check_interval
, 0644, sysdev_show_int
,
1151 store_int_with_restart
),
1155 static struct sysdev_attribute
*mce_attrs
[] = {
1156 &attr_tolerant
.attr
, &attr_check_interval
.attr
, &attr_trigger
,
1160 static cpumask_var_t mce_dev_initialized
;
1162 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1163 static __cpuinit
int mce_create_device(unsigned int cpu
)
1168 if (!mce_available(&boot_cpu_data
))
1171 memset(&per_cpu(mce_dev
, cpu
).kobj
, 0, sizeof(struct kobject
));
1172 per_cpu(mce_dev
, cpu
).id
= cpu
;
1173 per_cpu(mce_dev
, cpu
).cls
= &mce_sysclass
;
1175 err
= sysdev_register(&per_cpu(mce_dev
, cpu
));
1179 for (i
= 0; mce_attrs
[i
]; i
++) {
1180 err
= sysdev_create_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
1184 for (i
= 0; i
< banks
; i
++) {
1185 err
= sysdev_create_file(&per_cpu(mce_dev
, cpu
),
1190 cpumask_set_cpu(cpu
, mce_dev_initialized
);
1195 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), &bank_attrs
[i
]);
1198 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
1200 sysdev_unregister(&per_cpu(mce_dev
, cpu
));
1205 static __cpuinit
void mce_remove_device(unsigned int cpu
)
1209 if (!cpumask_test_cpu(cpu
, mce_dev_initialized
))
1212 for (i
= 0; mce_attrs
[i
]; i
++)
1213 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
1215 for (i
= 0; i
< banks
; i
++)
1216 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), &bank_attrs
[i
]);
1218 sysdev_unregister(&per_cpu(mce_dev
, cpu
));
1219 cpumask_clear_cpu(cpu
, mce_dev_initialized
);
1222 /* Make sure there are no machine checks on offlined CPUs. */
1223 static void mce_disable_cpu(void *h
)
1225 unsigned long action
= *(unsigned long *)h
;
1228 if (!mce_available(¤t_cpu_data
))
1230 if (!(action
& CPU_TASKS_FROZEN
))
1232 for (i
= 0; i
< banks
; i
++) {
1233 if (!skip_bank_init(i
))
1234 wrmsrl(MSR_IA32_MC0_CTL
+ i
*4, 0);
1238 static void mce_reenable_cpu(void *h
)
1240 unsigned long action
= *(unsigned long *)h
;
1243 if (!mce_available(¤t_cpu_data
))
1246 if (!(action
& CPU_TASKS_FROZEN
))
1248 for (i
= 0; i
< banks
; i
++) {
1249 if (!skip_bank_init(i
))
1250 wrmsrl(MSR_IA32_MC0_CTL
+ i
*4, bank
[i
]);
1254 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
1255 static int __cpuinit
1256 mce_cpu_callback(struct notifier_block
*nfb
, unsigned long action
, void *hcpu
)
1258 unsigned int cpu
= (unsigned long)hcpu
;
1259 struct timer_list
*t
= &per_cpu(mce_timer
, cpu
);
1263 case CPU_ONLINE_FROZEN
:
1264 mce_create_device(cpu
);
1265 if (threshold_cpu_callback
)
1266 threshold_cpu_callback(action
, cpu
);
1269 case CPU_DEAD_FROZEN
:
1270 if (threshold_cpu_callback
)
1271 threshold_cpu_callback(action
, cpu
);
1272 mce_remove_device(cpu
);
1274 case CPU_DOWN_PREPARE
:
1275 case CPU_DOWN_PREPARE_FROZEN
:
1277 smp_call_function_single(cpu
, mce_disable_cpu
, &action
, 1);
1279 case CPU_DOWN_FAILED
:
1280 case CPU_DOWN_FAILED_FROZEN
:
1281 t
->expires
= round_jiffies(jiffies
+
1282 __get_cpu_var(next_interval
));
1283 add_timer_on(t
, cpu
);
1284 smp_call_function_single(cpu
, mce_reenable_cpu
, &action
, 1);
1287 /* intentionally ignoring frozen here */
1288 cmci_rediscover(cpu
);
1294 static struct notifier_block mce_cpu_notifier __cpuinitdata
= {
1295 .notifier_call
= mce_cpu_callback
,
1298 static __init
int mce_init_banks(void)
1302 bank_attrs
= kzalloc(sizeof(struct sysdev_attribute
) * banks
,
1307 for (i
= 0; i
< banks
; i
++) {
1308 struct sysdev_attribute
*a
= &bank_attrs
[i
];
1310 a
->attr
.name
= kasprintf(GFP_KERNEL
, "bank%d", i
);
1314 a
->attr
.mode
= 0644;
1315 a
->show
= show_bank
;
1316 a
->store
= set_bank
;
1322 kfree(bank_attrs
[i
].attr
.name
);
1329 static __init
int mce_init_device(void)
1334 if (!mce_available(&boot_cpu_data
))
1337 alloc_cpumask_var(&mce_dev_initialized
, GFP_KERNEL
);
1339 err
= mce_init_banks();
1343 err
= sysdev_class_register(&mce_sysclass
);
1347 for_each_online_cpu(i
) {
1348 err
= mce_create_device(i
);
1353 register_hotcpu_notifier(&mce_cpu_notifier
);
1354 misc_register(&mce_log_device
);
1359 device_initcall(mce_init_device
);
1361 #else /* CONFIG_X86_OLD_MCE: */
1364 EXPORT_SYMBOL_GPL(nr_mce_banks
); /* non-fatal.o */
1366 /* This has to be run for each processor */
1367 void mcheck_init(struct cpuinfo_x86
*c
)
1369 if (mce_disabled
== 1)
1372 switch (c
->x86_vendor
) {
1373 case X86_VENDOR_AMD
:
1377 case X86_VENDOR_INTEL
:
1379 intel_p5_mcheck_init(c
);
1381 intel_p6_mcheck_init(c
);
1383 intel_p4_mcheck_init(c
);
1386 case X86_VENDOR_CENTAUR
:
1388 winchip_mcheck_init(c
);
1394 printk(KERN_INFO
"mce: CPU supports %d MCE banks\n", nr_mce_banks
);
1397 static int __init
mcheck_enable(char *str
)
1403 __setup("mce", mcheck_enable
);
1405 #endif /* CONFIG_X86_OLD_MCE */
1408 * Old style boot options parsing. Only for compatibility.
1410 static int __init
mcheck_disable(char *str
)
1415 __setup("nomce", mcheck_disable
);