arch/arm/mach-at91/clock.c

   1 /*
   2  * linux/arch/arm/mach-at91/clock.c
   3  *
   4  * Copyright (C) 2005 David Brownell
   5  * Copyright (C) 2005 Ivan Kokshaysky
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/fs.h>
  17 #include <linux/debugfs.h>
  18 #include <linux/seq_file.h>
  19 #include <linux/list.h>
  20 #include <linux/errno.h>
  21 #include <linux/err.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/delay.h>
  24 #include <linux/clk.h>
  25
  26 #include <asm/io.h>
  27 #include <asm/mach-types.h>
  28
  29 #include <asm/hardware.h>
  30 #include <asm/arch/at91_pmc.h>
  31 #include <asm/arch/cpu.h>
  32
  33 #include "clock.h"
  34
  35
  36 /*
  37  * There's a lot more which can be done with clocks, including cpufreq
  38  * integration, slow clock mode support (for system suspend), letting
  39  * PLLB be used at other rates (on boards that don't need USB), etc.
  40  */
  41
  42 #define clk_is_primary(x)       ((x)->type & CLK_TYPE_PRIMARY)
  43 #define clk_is_programmable(x)  ((x)->type & CLK_TYPE_PROGRAMMABLE)
  44 #define clk_is_peripheral(x)    ((x)->type & CLK_TYPE_PERIPHERAL)
  45 #define clk_is_sys(x)           ((x)->type & CLK_TYPE_SYSTEM)
  46
  47
  48 static LIST_HEAD(clocks);
  49 static DEFINE_SPINLOCK(clk_lock);
  50
  51 static u32 at91_pllb_usb_init;
  52
  53 /*
  54  * Four primary clock sources:  two crystal oscillators (32K, main), and
  55  * two PLLs.  PLLA usually runs the master clock; and PLLB must run at
  56  * 48 MHz (unless no USB function clocks are needed).  The main clock and
  57  * both PLLs are turned off to run in "slow clock mode" (system suspend).
  58  */
  59 static struct clk clk32k = {
  60         .name           = "clk32k",
  61         .rate_hz        = AT91_SLOW_CLOCK,
  62         .users          = 1,            /* always on */
  63         .id             = 0,
  64         .type           = CLK_TYPE_PRIMARY,
  65 };
  66 static struct clk main_clk = {
  67         .name           = "main",
  68         .pmc_mask       = AT91_PMC_MOSCS,       /* in PMC_SR */
  69         .id             = 1,
  70         .type           = CLK_TYPE_PRIMARY,
  71 };
  72 static struct clk plla = {
  73         .name           = "plla",
  74         .parent         = &main_clk,
  75         .pmc_mask       = AT91_PMC_LOCKA,       /* in PMC_SR */
  76         .id             = 2,
  77         .type           = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
  78 };
  79
  80 static void pllb_mode(struct clk *clk, int is_on)
  81 {
  82         u32     value;
  83
  84         if (is_on) {
  85                 is_on = AT91_PMC_LOCKB;
  86                 value = at91_pllb_usb_init;
  87         } else
  88                 value = 0;
  89
  90         // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
  91         at91_sys_write(AT91_CKGR_PLLBR, value);
  92
  93         do {
  94                 cpu_relax();
  95         } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
  96 }
  97
  98 static struct clk pllb = {
  99         .name           = "pllb",
 100         .parent         = &main_clk,
 101         .pmc_mask       = AT91_PMC_LOCKB,       /* in PMC_SR */
 102         .mode           = pllb_mode,
 103         .id             = 3,
 104         .type           = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
 105 };
 106
 107 static void pmc_sys_mode(struct clk *clk, int is_on)
 108 {
 109         if (is_on)
 110                 at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
 111         else
 112                 at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
 113 }
 114
 115 static void pmc_uckr_mode(struct clk *clk, int is_on)
 116 {
 117         unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
 118
 119         if (is_on) {
 120                 is_on = AT91_PMC_LOCKU;
 121                 at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
 122         } else
 123                 at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
 124
 125         do {
 126                 cpu_relax();
 127         } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
 128 }
 129
 130 /* USB function clocks (PLLB must be 48 MHz) */
 131 static struct clk udpck = {
 132         .name           = "udpck",
 133         .parent         = &pllb,
 134         .mode           = pmc_sys_mode,
 135 };
 136 static struct clk utmi_clk = {
 137         .name           = "utmi_clk",
 138         .parent         = &main_clk,
 139         .pmc_mask       = AT91_PMC_UPLLEN,      /* in CKGR_UCKR */
 140         .mode           = pmc_uckr_mode,
 141         .type           = CLK_TYPE_PLL,
 142 };
 143 static struct clk uhpck = {
 144         .name           = "uhpck",
 145         .parent         = &pllb,
 146         .mode           = pmc_sys_mode,
 147 };
 148
 149
 150 /*
 151  * The master clock is divided from the CPU clock (by 1-4).  It's used for
 152  * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
 153  * (e.g baud rate generation).  It's sourced from one of the primary clocks.
 154  */
 155 static struct clk mck = {
 156         .name           = "mck",
 157         .pmc_mask       = AT91_PMC_MCKRDY,      /* in PMC_SR */
 158 };
 159
 160 static void pmc_periph_mode(struct clk *clk, int is_on)
 161 {
 162         if (is_on)
 163                 at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
 164         else
 165                 at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
 166 }
 167
 168 static struct clk __init *at91_css_to_clk(unsigned long css)
 169 {
 170         switch (css) {
 171                 case AT91_PMC_CSS_SLOW:
 172                         return &clk32k;
 173                 case AT91_PMC_CSS_MAIN:
 174                         return &main_clk;
 175                 case AT91_PMC_CSS_PLLA:
 176                         return &plla;
 177                 case AT91_PMC_CSS_PLLB:
 178                         return &pllb;
 179         }
 180
 181         return NULL;
 182 }
 183
 184 /*
 185  * Associate a particular clock with a function (eg, "uart") and device.
 186  * The drivers can then request the same 'function' with several different
 187  * devices and not care about which clock name to use.
 188  */
 189 void __init at91_clock_associate(const char *id, struct device *dev, const char *func)
 190 {
 191         struct clk *clk = clk_get(NULL, id);
 192
 193         if (!dev || !clk || !IS_ERR(clk_get(dev, func)))
 194                 return;
 195
 196         clk->function = func;
 197         clk->dev = dev;
 198 }
 199
 200 /* clocks cannot be de-registered no refcounting necessary */
 201 struct clk *clk_get(struct device *dev, const char *id)
 202 {
 203         struct clk *clk;
 204
 205         list_for_each_entry(clk, &clocks, node) {
 206                 if (strcmp(id, clk->name) == 0)
 207                         return clk;
 208                 if (clk->function && (dev == clk->dev) && strcmp(id, clk->function) == 0)
 209                         return clk;
 210         }
 211
 212         return ERR_PTR(-ENOENT);
 213 }
 214 EXPORT_SYMBOL(clk_get);
 215
 216 void clk_put(struct clk *clk)
 217 {
 218 }
 219 EXPORT_SYMBOL(clk_put);
 220
 221 static void __clk_enable(struct clk *clk)
 222 {
 223         if (clk->parent)
 224                 __clk_enable(clk->parent);
 225         if (clk->users++ == 0 && clk->mode)
 226                 clk->mode(clk, 1);
 227 }
 228
 229 int clk_enable(struct clk *clk)
 230 {
 231         unsigned long   flags;
 232
 233         spin_lock_irqsave(&clk_lock, flags);
 234         __clk_enable(clk);
 235         spin_unlock_irqrestore(&clk_lock, flags);
 236         return 0;
 237 }
 238 EXPORT_SYMBOL(clk_enable);
 239
 240 static void __clk_disable(struct clk *clk)
 241 {
 242         BUG_ON(clk->users == 0);
 243         if (--clk->users == 0 && clk->mode)
 244                 clk->mode(clk, 0);
 245         if (clk->parent)
 246                 __clk_disable(clk->parent);
 247 }
 248
 249 void clk_disable(struct clk *clk)
 250 {
 251         unsigned long   flags;
 252
 253         spin_lock_irqsave(&clk_lock, flags);
 254         __clk_disable(clk);
 255         spin_unlock_irqrestore(&clk_lock, flags);
 256 }
 257 EXPORT_SYMBOL(clk_disable);
 258
 259 unsigned long clk_get_rate(struct clk *clk)
 260 {
 261         unsigned long   flags;
 262         unsigned long   rate;
 263
 264         spin_lock_irqsave(&clk_lock, flags);
 265         for (;;) {
 266                 rate = clk->rate_hz;
 267                 if (rate || !clk->parent)
 268                         break;
 269                 clk = clk->parent;
 270         }
 271         spin_unlock_irqrestore(&clk_lock, flags);
 272         return rate;
 273 }
 274 EXPORT_SYMBOL(clk_get_rate);
 275
 276 /*------------------------------------------------------------------------*/
 277
 278 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
 279
 280 /*
 281  * For now, only the programmable clocks support reparenting (MCK could
 282  * do this too, with care) or rate changing (the PLLs could do this too,
 283  * ditto MCK but that's more for cpufreq).  Drivers may reparent to get
 284  * a better rate match; we don't.
 285  */
 286
 287 long clk_round_rate(struct clk *clk, unsigned long rate)
 288 {
 289         unsigned long   flags;
 290         unsigned        prescale;
 291         unsigned long   actual;
 292
 293         if (!clk_is_programmable(clk))
 294                 return -EINVAL;
 295         spin_lock_irqsave(&clk_lock, flags);
 296
 297         actual = clk->parent->rate_hz;
 298         for (prescale = 0; prescale < 7; prescale++) {
 299                 if (actual && actual <= rate)
 300                         break;
 301                 actual >>= 1;
 302         }
 303
 304         spin_unlock_irqrestore(&clk_lock, flags);
 305         return (prescale < 7) ? actual : -ENOENT;
 306 }
 307 EXPORT_SYMBOL(clk_round_rate);
 308
 309 int clk_set_rate(struct clk *clk, unsigned long rate)
 310 {
 311         unsigned long   flags;
 312         unsigned        prescale;
 313         unsigned long   actual;
 314
 315         if (!clk_is_programmable(clk))
 316                 return -EINVAL;
 317         if (clk->users)
 318                 return -EBUSY;
 319         spin_lock_irqsave(&clk_lock, flags);
 320
 321         actual = clk->parent->rate_hz;
 322         for (prescale = 0; prescale < 7; prescale++) {
 323                 if (actual && actual <= rate) {
 324                         u32     pckr;
 325
 326                         pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
 327                         pckr &= AT91_PMC_CSS_PLLB;      /* clock selection */
 328                         pckr |= prescale << 2;
 329                         at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
 330                         clk->rate_hz = actual;
 331                         break;
 332                 }
 333                 actual >>= 1;
 334         }
 335
 336         spin_unlock_irqrestore(&clk_lock, flags);
 337         return (prescale < 7) ? actual : -ENOENT;
 338 }
 339 EXPORT_SYMBOL(clk_set_rate);
 340
 341 struct clk *clk_get_parent(struct clk *clk)
 342 {
 343         return clk->parent;
 344 }
 345 EXPORT_SYMBOL(clk_get_parent);
 346
 347 int clk_set_parent(struct clk *clk, struct clk *parent)
 348 {
 349         unsigned long   flags;
 350
 351         if (clk->users)
 352                 return -EBUSY;
 353         if (!clk_is_primary(parent) || !clk_is_programmable(clk))
 354                 return -EINVAL;
 355         spin_lock_irqsave(&clk_lock, flags);
 356
 357         clk->rate_hz = parent->rate_hz;
 358         clk->parent = parent;
 359         at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);
 360
 361         spin_unlock_irqrestore(&clk_lock, flags);
 362         return 0;
 363 }
 364 EXPORT_SYMBOL(clk_set_parent);
 365
 366 /* establish PCK0..PCK3 parentage and rate */
 367 static void __init init_programmable_clock(struct clk *clk)
 368 {
 369         struct clk      *parent;
 370         u32             pckr;
 371
 372         pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
 373         parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
 374         clk->parent = parent;
 375         clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2));
 376 }
 377
 378 #endif  /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
 379
 380 /*------------------------------------------------------------------------*/
 381
 382 #ifdef CONFIG_DEBUG_FS
 383
 384 static int at91_clk_show(struct seq_file *s, void *unused)
 385 {
 386         u32             scsr, pcsr, uckr = 0, sr;
 387         struct clk      *clk;
 388
 389         seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
 390         seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));
 391         seq_printf(s, "MOR  = %8x\n", at91_sys_read(AT91_CKGR_MOR));
 392         seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
 393         seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
 394         if (!cpu_is_at91sam9rl())
 395                 seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
 396         if (cpu_is_at91cap9() || cpu_is_at91sam9rl())
 397                 seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR));
 398         seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
 399         seq_printf(s, "SR   = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
 400
 401         seq_printf(s, "\n");
 402
 403         list_for_each_entry(clk, &clocks, node) {
 404                 char    *state;
 405
 406                 if (clk->mode == pmc_sys_mode)
 407                         state = (scsr & clk->pmc_mask) ? "on" : "off";
 408                 else if (clk->mode == pmc_periph_mode)
 409                         state = (pcsr & clk->pmc_mask) ? "on" : "off";
 410                 else if (clk->mode == pmc_uckr_mode)
 411                         state = (uckr & clk->pmc_mask) ? "on" : "off";
 412                 else if (clk->pmc_mask)
 413                         state = (sr & clk->pmc_mask) ? "on" : "off";
 414                 else if (clk == &clk32k || clk == &main_clk)
 415                         state = "on";
 416                 else
 417                         state = "";
 418
 419                 seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n",
 420                         clk->name, clk->users, state, clk_get_rate(clk),
 421                         clk->parent ? clk->parent->name : "");
 422         }
 423         return 0;
 424 }
 425
 426 static int at91_clk_open(struct inode *inode, struct file *file)
 427 {
 428         return single_open(file, at91_clk_show, NULL);
 429 }
 430
 431 static const struct file_operations at91_clk_operations = {
 432         .open           = at91_clk_open,
 433         .read           = seq_read,
 434         .llseek         = seq_lseek,
 435         .release        = single_release,
 436 };
 437
 438 static int __init at91_clk_debugfs_init(void)
 439 {
 440         /* /sys/kernel/debug/at91_clk */
 441         (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
 442
 443         return 0;
 444 }
 445 postcore_initcall(at91_clk_debugfs_init);
 446
 447 #endif
 448
 449 /*------------------------------------------------------------------------*/
 450
 451 /* Register a new clock */
 452 int __init clk_register(struct clk *clk)
 453 {
 454         if (clk_is_peripheral(clk)) {
 455                 clk->parent = &mck;
 456                 clk->mode = pmc_periph_mode;
 457                 list_add_tail(&clk->node, &clocks);
 458         }
 459         else if (clk_is_sys(clk)) {
 460                 clk->parent = &mck;
 461                 clk->mode = pmc_sys_mode;
 462
 463                 list_add_tail(&clk->node, &clocks);
 464         }
 465 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
 466         else if (clk_is_programmable(clk)) {
 467                 clk->mode = pmc_sys_mode;
 468                 init_programmable_clock(clk);
 469                 list_add_tail(&clk->node, &clocks);
 470         }
 471 #endif
 472
 473         return 0;
 474 }
 475
 476
 477 /*------------------------------------------------------------------------*/
 478
 479 static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
 480 {
 481         unsigned mul, div;
 482
 483         div = reg & 0xff;
 484         mul = (reg >> 16) & 0x7ff;
 485         if (div && mul) {
 486                 freq /= div;
 487                 freq *= mul + 1;
 488         } else
 489                 freq = 0;
 490
 491         return freq;
 492 }
 493
 494 static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
 495 {
 496         if (pll == &pllb && (reg & AT91_PMC_USB96M))
 497                 return freq / 2;
 498         else
 499                 return freq;
 500 }
 501
 502 static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
 503 {
 504         unsigned i, div = 0, mul = 0, diff = 1 << 30;
 505         unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
 506
 507         /* PLL output max 240 MHz (or 180 MHz per errata) */
 508         if (out_freq > 240000000)
 509                 goto fail;
 510
 511         for (i = 1; i < 256; i++) {
 512                 int diff1;
 513                 unsigned input, mul1;
 514
 515                 /*
 516                  * PLL input between 1MHz and 32MHz per spec, but lower
 517                  * frequences seem necessary in some cases so allow 100K.
 518                  */
 519                 input = main_freq / i;
 520                 if (input < 100000)
 521                         continue;
 522                 if (input > 32000000)
 523                         continue;
 524
 525                 mul1 = out_freq / input;
 526                 if (mul1 > 2048)
 527                         continue;
 528                 if (mul1 < 2)
 529                         goto fail;
 530
 531                 diff1 = out_freq - input * mul1;
 532                 if (diff1 < 0)
 533                         diff1 = -diff1;
 534                 if (diff > diff1) {
 535                         diff = diff1;
 536                         div = i;
 537                         mul = mul1;
 538                         if (diff == 0)
 539                                 break;
 540                 }
 541         }
 542         if (i == 256 && diff > (out_freq >> 5))
 543                 goto fail;
 544         return ret | ((mul - 1) << 16) | div;
 545 fail:
 546         return 0;
 547 }
 548
 549 static struct clk *const standard_pmc_clocks[] __initdata = {
 550         /* four primary clocks */
 551         &clk32k,
 552         &main_clk,
 553         &plla,
 554         &pllb,
 555
 556         /* PLLB children (USB) */
 557         &udpck,
 558         &uhpck,
 559
 560         /* MCK */
 561         &mck
 562 };
 563
 564 int __init at91_clock_init(unsigned long main_clock)
 565 {
 566         unsigned tmp, freq, mckr;
 567         int i;
 568
 569         /*
 570          * When the bootloader initialized the main oscillator correctly,
 571          * there's no problem using the cycle counter.  But if it didn't,
 572          * or when using oscillator bypass mode, we must be told the speed
 573          * of the main clock.
 574          */
 575         if (!main_clock) {
 576                 do {
 577                         tmp = at91_sys_read(AT91_CKGR_MCFR);
 578                 } while (!(tmp & AT91_PMC_MAINRDY));
 579                 main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
 580         }
 581         main_clk.rate_hz = main_clock;
 582
 583         /* report if PLLA is more than mildly overclocked */
 584         plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
 585         if (plla.rate_hz > 209000000)
 586                 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
 587
 588         /*
 589          * USB clock init:  choose 48 MHz PLLB value,
 590          * disable 48MHz clock during usb peripheral suspend.
 591          *
 592          * REVISIT:  assumes MCK doesn't derive from PLLB!
 593          */
 594         at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
 595         pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
 596         if (cpu_is_at91rm9200()) {
 597                 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
 598                 udpck.pmc_mask = AT91RM9200_PMC_UDP;
 599                 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
 600         } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263()) {
 601                 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
 602                 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
 603         } else if (cpu_is_at91cap9()) {
 604                 uhpck.pmc_mask = AT91CAP9_PMC_UHP;
 605         }
 606         at91_sys_write(AT91_CKGR_PLLBR, 0);
 607
 608         udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
 609         uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
 610
 611         /*
 612          * USB HS clock init
 613          */
 614         if (cpu_is_at91cap9() || cpu_is_at91sam9rl()) {
 615                 /*
 616                  * multiplier is hard-wired to 40
 617                  * (obtain the USB High Speed 480 MHz when input is 12 MHz)
 618                  */
 619                 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
 620         }
 621
 622         /*
 623          * MCK and CPU derive from one of those primary clocks.
 624          * For now, assume this parentage won't change.
 625          */
 626         mckr = at91_sys_read(AT91_PMC_MCKR);
 627         mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
 628         freq = mck.parent->rate_hz;
 629         freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));                           /* prescale */
 630         if (cpu_is_at91rm9200())
 631                 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8));       /* mdiv */
 632         else
 633                 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      /* mdiv */
 634
 635         /* Register the PMC's standard clocks */
 636         for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
 637                 list_add_tail(&standard_pmc_clocks[i]->node, &clocks);
 638
 639         if (cpu_is_at91cap9() || cpu_is_at91sam9rl())
 640                 list_add_tail(&utmi_clk.node, &clocks);
 641
 642         /* MCK and CPU clock are "always on" */
 643         clk_enable(&mck);
 644
 645         printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
 646                 freq / 1000000, (unsigned) mck.rate_hz / 1000000,
 647                 (unsigned) main_clock / 1000000,
 648                 ((unsigned) main_clock % 1000000) / 1000);
 649
 650         return 0;
 651 }
 652
 653 /*
 654  * Several unused clocks may be active.  Turn them off.
 655  */
 656 static int __init at91_clock_reset(void)
 657 {
 658         unsigned long pcdr = 0;
 659         unsigned long scdr = 0;
 660         struct clk *clk;
 661
 662         list_for_each_entry(clk, &clocks, node) {
 663                 if (clk->users > 0)
 664                         continue;
 665
 666                 if (clk->mode == pmc_periph_mode)
 667                         pcdr |= clk->pmc_mask;
 668
 669                 if (clk->mode == pmc_sys_mode)
 670                         scdr |= clk->pmc_mask;
 671
 672                 pr_debug("Clocks: disable unused %s\n", clk->name);
 673         }
 674
 675         at91_sys_write(AT91_PMC_PCDR, pcdr);
 676         at91_sys_write(AT91_PMC_SCDR, scdr);
 677
 678         return 0;
 679 }
 680 late_initcall(at91_clock_reset);